JPS6089192A - Recording and reproducing device of video signal - Google Patents

Abstract

PURPOSE:To reproduce a broad band luminance signal and a high quality chrominance signal without deterioration of band width of a luminance signal by giving 1H delay to the luminance signal of broad band and adding a high frequency component of a delay signal to a luminance signal of narrow band. CONSTITUTION:As S waveform at transmission is reproduced to an output of a dynamic de-emphasis circuit 31 and inputted to D/A converters 47-50 via an A/D converter 57, time axis restoration RAMs 40-43, and 1H delay circuits 44- 46. A broad band luminance signal at each other line as shown in Yw is obtained at an output of the A/D 47 and a luminance signal with different band width is obtained at each line as shown in YNW is obtained in an output of an A/D 48. An HPF51 and an adder circuit 52 add the signal to the high frequency component YNW of the YW to obtain a luminance signal Y' unchanged with the band width at each line from the YNW and the YW. An output signal of the circuit 52 is incomplete for the horizontal synchronizing signal, a synchronism addition circuit 53 adds a fH signal from a PLL so as to obtain the signal Y'.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to equipment for recording and reproducing video signals, and more particularly to a device suitable for time-division multiplexing and recording and reproducing luminance signals and chroma signals in video signals. [Background of the Invention] Timeplex is a conventional technology for recording and reproducing a luminance signal and a chroma signal by time division multiplexing.

Timeplex is a method in which the luminance signal is time-compressed into 415 signals, the chroma signal is time-compressed into 115 signals, and then these signals are time-division multiplexed.

The disadvantage of the time-plex method is that it is difficult to secure the bandwidth of the luminance signal. In the Timeplex method, 5
Since the time is expanded by /4 times, the bandwidth is 80% compared to a method that does not perform time compression and expansion.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to eliminate the drawbacks of the prior art and to provide a video signal recording and reproducing device that time-division multiplexes a luminance signal and a chroma signal and records and reproduces them without degrading the reproduction bandwidth of the luminance signal. .

[Summary of the invention]

In the present invention, a signal in which a luminance signal that is not time-compressed and a luminance signal that is time-compressed are switched for each line is recorded on a recording medium and reproduced. In addition, in order to simplify the software, the signal arrangement is changed to a luminance signal that is not time-compressed, a horizontal synchronization signal, a chroma zero level, a first color difference signal that is compressed by 11 hours, and a luminance signal that is time-compressed. , the time-compressed second
chrominance signal, luminance signal that is not time compressed,...
The order shall be... In the reproducing device, if the signal is only demodulated once, a wideband luminance signal and a narrowband luminance signal will be generated alternately for each line. To compensate for this, the wideband luminance signal is delayed by 1H, and the high frequency component of the delayed signal is added to the narrowband luminance signal.

[Embodiments of the invention]

Hereinafter, one practical example of the present invention will be explained using FIGS. 1 to 5. FIG. 1 is a block diagram showing -fflJ of a recording circuit when the present invention is used in a video tape recorder, and FIG. 2 is a diagram showing the waveforms of each part of FIG. 1 and the operation of the RAM.

In FIG. 1, reference numeral 1 denotes a video signal generator, which outputs Y, [J, and V shown in FIG. 2.

2 is a switch circuit, and U and V are human power and tL.

U and Y appear alternately on each line in the output.

6.4 is an AD converter that converts an analog signal into a digital signal, 5 is a synchronization separation circuit, 6 is a phase comparison circuit, and 7 is a 5120fHV CO (fH: a clock that constitutes a horizontal synchronization circuit and whose phase is synchronized with the horizontal synchronization signal. signal, 1024
Generate 1 fH, , 256fH. 11 is a - frequency divider and outputs 12B0fH. 12, 13.

14 and 15 are RAMs for time axis conversion, and RAM1 and RAM2 are time compression circuits for color difference signals that compress the time axis to T with a write clock of 256fH and a read clock of 128Of)I. RAM3 has a write clock of 1o24fH and a read clock of 128O
f) A time compression circuit for luminance signals that compresses the time axis as I. RAM'4 is a 1H delay circuit for luminance signals in which both the write clock and the read clock are 1024 fH. (IH is one horizontal scanning period) A, B, C, and D in FIG. 2 are RAM1.

The operating states of 2.3.4 are shown below.) A LOW period indicates a read period, and a LOW period indicates a write period.

In Fig. 1, 16 is a signal synthesis circuit that synthesizes the outputs of RAM1, 2.5.4, and 17 is a DA controller I (-) that returns the digital signal to an analog signal, and the waveform shown in Fig. 2 S is output. As can be seen from the figure, the characteristics of the waveform of S are a luminance signal that is not time-compressed (Y * Yn...)
n-25 luminance signal time-compressed into and- (Yn-s t Yn-s +...)
appear alternately on each line. The two time-compressed color difference signals U and V are arranged adjacently before and after the time-compressed luminance signal. The horizontal synchronizing signal is arranged every other line, and a 50% IRE signal is added between the horizontal synchronizing signal and the U signal, and this is used to determine the zero level of the color difference signal.

By using the signal format as described above, the following length B can be obtained.

(1) Only four RAMs are required for time axis conversion. (2) The delay time associated with time axis conversion can be set to 1H, making it easy to stop time axis compression during vertical blanking IA. (5) Y, U, and V delay times of 11 are uniform and color shift is less likely to occur.

18 to 25 are signal processing circuits similar to conventional video tape recorders; 18 is a circuit for clamping the synchronization tip;
19 is a dynamic emphasis circuit that increases the amount of emphasis as the input signal level becomes smaller, 20 is a clip circuit that limits overshoot caused by emphasis, 21 is a frequency modulation circuit, 22 is a write amplifier, 23 is a two-channel rotary transformer, and 24 is a Two video heads, 25 are video tapes.

FIG. 3 is a block diagram showing an example of a playback circuit when the present invention is used in a video tape recorder, FIG. 4 is a waveform diagram of each part in FIG. 3, and FIG. 5 is an operation of RAMs 5, 6, 7, and 8. It is a figure showing a state.

In FIG. 6, 23 to 31 are playback circuits of a conventional video tape recorder, 26 is a two-channel head amplifier, 27 is a de-switch circuit, 28 is an FM equalization circuit, 29 is a limiter, and 30 is a The FM demodulation circuit 61 is a dynamic de-emphasis circuit.

The output of the dynamic de-emphasis circuit 61 has a fourth
The waveform shown in FIG. S is reproduced I7, and a horizontal synchronization signal having a lower frequency is extracted by the synchronization separation circuit H32. 53 to 38 constitute the PLL, and 36 is 7
Frequency divider, 37 is T frequency divider, 68 is 7 frequency divider, sq ha 51
20fH Nov CO.

57 is an AD converter that converts the analog signal S into a digital signal. 40 to 45 are RAMs for restoring the time axis, to which a clock signal is supplied from the PLL circuit. RAM
5 is 1024f for both 1-input clock and readout clock.
This is a 1H delay circuit whose HL, write, and read timings are shown in FIG. 5E. RAM6 has a write clock of 12
This is a 1x time axis push and hold circuit in which the 80 fHs read clock is set to 1024 fH, and the read timing is set to E in FIG. RAIVI7. RAM8 has a write clock of 1280fn and a read clock of 256fH.
The write and read timings are shown in FIG. 5G.

This is a five-fold time axis expansion circuit. 44, 45, 46 are 1H delay circuits, and 47, 48, 49, 50 are DA converters for converting digital signals back to analog signals.

At the output of 47, a wideband luminance signal of every other line shown as YW in FIG. 4 is obtained, and at the output of 48, a luminance signal having a different bandwidth for each line shown as YNW of FIG. 4 is obtained.

The HPF 51 and the adder circuit 52 add the high frequency component of YW to YNW in order to obtain a signal Y' whose bandwidth does not change from line to line from YNW and YW.

The output signal of 52 is an incomplete horizontal synchronization signal, and the synchronization addition circuit 55 does not add the fH times signal from PLL 9.
'becomes a signal. 54, 55, and 56 are signal output terminals.

〔Effect of the invention〕

According to the present invention, there is no bandwidth deterioration of the luminance signal, which is a drawback of the conventional split-division multiplexing method, and it is possible to simultaneously reproduce a wideband luminance signal and a high-quality ROMA signal.

[Brief explanation of the drawing]

Fig. 1 is a diagram showing an example of the recording circuit of the present invention, Fig. 2 is a diagram showing the waveforms of each part of Fig. 1 and the operation of the RAM, and Fig. 3 is a diagram showing an example of the reproducing circuit of the invention. Block diagram, 4th
The figure shows the waveforms of each part in Fig. 3, and Fig. 5 shows the R of Fig. 3.
It is a figure which shows operation|movement of AM. 12, 13, 14, 15...RA for time axis compression
M. 3.4.57...AD converter, 17.47.48,49.50・DA:ff converter,
40, 41, 42, 45...RA for time axis expansion
Continuation of M0 page 1 @ Inventor Kenji Fuse 29 Asaji, Yoshida-cho, Totsuka-ku, Yokohama City, Hitachi, Ltd. Home Appliance Research Laboratory

Claims (1)

[Claims] In an Eirin signal recording and reproducing device that records and reproduces at least a luminance signal and two color difference signals on a recording medium, means for generating a time-compressed luminance signal and time-compressed first and second color difference signals; The luminance signal becomes time-compressed,
a time-compressed first color difference signal, a time-compressed luminance,
A video signal recording and reproducing device characterized by having means for arranging signals in the order of a time-compressed second color difference signal, a time [41, an uncompressed luminance signal, and so on]. .