JPH0522891B2 - - Google Patents

Description

[Detailed description of the invention] The present invention relates to a display device for flash photography.

When using a series-controlled auto-flash speedlight, the speedlight can re-flash in a short time when the amount of light emitted is relatively small, making it possible to emit continuous flashes at a rate of several frames per second, which is stored in the main capacitor. It is possible to shoot several frames using only energy. During continuous flash photography, an indication was displayed each time the flash photography was performed to supply energy to the flash discharge tube until the reflected light from the subject reached a predetermined value, and the display was then reset. This had the disadvantage that it was difficult for the photographer to observe.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned drawbacks and provide a display device for flash photography that can display how many times a proper light control operation has been performed and which number of light control operations have failed during continuous flash photography. .

Hereinafter, the present invention will be explained based on examples. FIG. 1 is a block diagram showing an embodiment of the present invention.
When power switch S ₁ is on, DC/DC converter 1 boosts the voltage of power supply E and connects it to the high-voltage power supply line.
Supplied between V _CM and GND. Further, the voltage of the low voltage power supply E is supplied between the power supply V _CC and GND. The main capacitor C _M stores the output voltage of the DC/DC converter 1 as energy for flashlight emission.

Turn on/off synchro contact S _x built into camera 2
The off signal is applied to the input terminal g of the control circuit 3. The on/off signal of the MD tuning switch _S2 is applied to the input terminal h of the control circuit 3. The switch S ₂
is turned on when the motor drive device is attached to the camera and continuous shooting is performed.For example, it is turned on by an operation member (not shown) placed on the speedlight side, or by an operation member (not shown) placed on the camera body or motor drive device. (not shown). In the latter case, the switch _S2 itself is provided in the camera body or motor drive device, and electrically connected to the speedlight side. The control circuit 3 outputs the output terminals c and d in synchronization with the turning on of the synchro contact S _x .
Trigger pulses sig-1 and sig-2 are generated.
Further, when the switch _S2 is on, the control circuit 3 generates the first control pulse sig-3 at the terminal e after a fixed time _γ1 after the synchro contact _Sx is turned on.
This fixed time is variable depending on the frame speed of the motor drive device. Further, the control circuit 3 generates a photometric pulse sig-4 at the terminal f for a certain period of time γ ₂ corresponding to the maximum light emission time during continuous light emission of the speedlight in synchronization with the turning on of the synchro contact _S x.

Resistor R ₁ , capacitor C ₁ , transformer L and the first
Thyristor T ₁ constitutes the trigger circuit of the flash discharge tube FT. The second thyristor _T2 opens and closes the main discharge loop between the discharge tube FT and the main capacitor _CM . Commutation capacitor C ₂ is normally charged via resistors R ₂ and R ₃ with the polarity shown. The third thyristor T ₃ opens and closes the commutation loop for connecting the commutation capacitor C ₂ in a reverse bias state with respect to the second thyristor T ₂ . Photodiode DP and capacitor _C3 constitute a light amount integration circuit. The transistor Tr ₁ is turned off while the photometric pulse sig-4 is applied from the control circuit 3 to enable charging of the capacitor C ₃ .
Comparator CP is resistor _R5 and Zener diode
The second control pulse sig-5 is generated when the reference voltage determined by Dz ₁ and the charging voltage of the capacitor C ₃ reach a predetermined relationship. The third thyristor _T3 is OR
When the first or second control pulse is applied through the gate _G1 , it turns on and closes the commutation loop.

The detection circuit 5 detects the possible number of times the flash can be emitted from the charging voltage of the main capacitor _CM , and outputs a number of pulses corresponding to the number of times to the terminal a. Resistor R ₆ and capacitor C ₄ constitute a differentiating circuit and generate an output at connection point P ₁ . Display selection switch _S3 is a capacitor
It is connected in parallel with _C4 , and is off when the flash is in the possible number of flash firing display mode, and is turned on prior to flash photography. NAND gate G ₂ , G ₃
The latch circuit consisting of the above inputs the on/off signal of the synchro contact S _x and the output signal of the connection point P ₁ . A differentiator circuit consisting of resistor R ₇ and capacitors C ₅ and C ₆ connects the output of NAND gate G ₂ and NAND gate G ₃
The input is the Q output of , and an output signal is generated at the connection point _P2 .

AND gate _G4 is connected to the output of terminal a of detection circuit 5.
The output of NAND gate _G2 is used as input.
AND gate _G5 is the output of terminal f of control circuit 3 (sig
-4) and the Q output of NAND gate _G2 are input. The Q output of the NAND gate _G3 is applied to the terminal b of the detection circuit 5, and prevents the output from being generated at the terminal a of the detection circuit 5 when the Q output is "H". The output of the connection point _P2 is applied to the reset terminal R of the shift register SR via the OR gate _G3 .
When switch _S4 is on, shift register SR
is reset by the output of connection point _P2 , and when switch _S4 is off, the shift register SR is reset accordingly.

The output of the OR gate G6, which receives the output of the AND gate _G4 and the output of _the AND gate _G5 , is applied to the clock input terminal of the shift register SR. AND
The output of OR gate G ₃ whose inputs are the output of gate G ₄ and the output of comparator CP is a shift register.
Applied to data input terminal D of SR. The shift register SR outputs "L" to output terminals ₁ to _o according to the count value. Each of the light emitting diodes _D1 to _D0 lights up when the corresponding output terminal is "L". The relay circuit 4 transmits the outputs of the output terminals Q ₁ to Q _o of the shift register SR to the light emitting diodes D' ₁ to D' _o on the camera body side. Light emitting diode D ₁ and
D′ ₁ , D ₂ and D′ ₂ ...D _o and D′ _o light up at the same time. Light emitting diodes _D1 to _D0 : D' ₁ to _D0 ' may be arranged on the speedlight side and/or camera side as necessary.

Next, the operation will be explained.

(1) Operation when using the motor drive device;
In a scene where flash photography is performed continuously using a motor drive device, the subject conditions are considered to be approximately constant. Therefore, while keeping the subject distance and aperture value constant, the amount of light emitted by the speedlight (i.e., the light emission time) is set to a predetermined value.
If you limit it to GN _L and adjust the correspondence between the piece speed of the motor drive device and the light emission time,
It is possible to take several consecutive flash shots. In other words, since the frame speed represents the number of shots per unit time,
If the light emission amount is set to end at a predetermined value GNL for each photographing, continuous flash photography becomes possible, although the subject may be limited. Specifically, after the synchro contact S _x is turned on by turning on the switch S ₂ , the first control pulse is generated.
The time _r1 until sig-3 occurs is made to correspond to the piece speed.

Now, when power switch S ₁ is turned on, DC/DC
Main capacitor C _M by comparator 1,
Capacitors C ₁ and C ₂ start charging. It is assumed that the switch _S4 is turned on at this time.
At the same time, since connection point P ₁ outputs “L” when the power is turned on (switch S ₃ is off at this time), NAND
The output of gate _G2 becomes "H", and the Q output of NAND gate _G3 becomes "L". Therefore, the connection point _P2 momentarily becomes “H” and the shift register SR
Reset the contents. On the other hand, the detection circuit 5
Since the Q output of NAND gate _G3 is "L", the number of "H" level pulses corresponding to the number of times that flash light can be emitted is sent to terminal a from the charging voltage of main capacitor C _M.
occurs in The output of NAND gate _G2 is “H”
Therefore, the pulse output from terminal a is an AND gate.
It is transmitted to OR gates G ₆ and G ₇ via G ₄ . Here, it is assumed that the shift register SR sequentially reads the input of the terminal D when the terminal CK is at "H". Then, the pulses from the terminal a are simultaneously applied to the input terminals CK and D of the shift register SR via the OR gates G ₆ and G ₇ , respectively.
Shift register SR counts the number of output pulses at terminal a. Therefore, the count value corresponds to the number of times that flash light can be emitted. When the number of times the flash can be emitted is one, the terminal ₁ is set to "L", when the number of times the flash can be emitted is twice, the terminals ₁ and ₂ are set to "L", and when the number of times the flash can be emitted is n, terminals ₁ to _o are set to "L". Accordingly, the light emitting diodes D ₁ to _{D o} are also turned on, and the number of light emitting diodes that are turned on indicates the number of times that flash light can be emitted. This number of times is also displayed on the camera body 2 side via the relay circuit 4, for example, in the viewfinder.

Here, the calculation of the possible number of times the flash can be emitted will be explained. The charging voltage of the main capacitor _CM is set to V ₀ before firing, V ₁ after the first firing, V ₂ after the second firing, and _Vo after the nth firing.
If the energy required for the predetermined amount of light emission GNL is α, the following relationship holds true. That is, the energy required for the first light emission is 1/2C _M V ₀ ² -1/2C _M V ₁ ² = α The energy required for the second light emission is 1/2C _M V ₁ ² -1/2C _M V ₂ ² = α 〓 Since the energy required for the nth light emission can be expressed as 1/2C _M V _o-1 ² -1/2C _M V _o ² = α (where, C _M is the capacitance of the main capacitor), the nth The terminal voltage of the main capacitor _CM at the time of the second flash emission can be expressed as _Vo ² =V ₀ ² -2nα/ _CM .

From this, the possible number of flash emissions N can be calculated as N=C _M (V ₀ ² −V _o ² )/2α (1). N pulses obtained from this calculation result are output from terminal a.

After confirming the possible number of flashes from the number of light-emitting diodes D ₁ to D _o and D ₁ ′ to D _o ′ lit, the photographer operates the camera release (the fact that these light-emitting diodes are lit means that the main It also means that the capacitor has been charged to a voltage that allows it to emit light.)
Then, the synchro contact S _x turns on, so
NAND gate _G3 outputs "H" to the Q output, and NAND gate _G2 outputs "L" to the output.
Therefore, an "H" pulse is momentarily generated at the connection point _P2 , resetting the contents of the shift register SR.
Furthermore, the AND gate _G4 is closed, and the detection circuit 5 is prevented from generating a pulse output to the terminal a. Conversely, the gate of AND gate _G5 is opened.

Now, when synchro contact S _x turns on at time t ₁ ,
The control circuit 3 has trigger pulses sig-1,
Generates sig-2. As a result, the first thyristor T ₁ and the second thyristor T ₂ are turned on, so that the discharge tube FT emits light. At the same time, the control circuit 3
A photometric pulse sig-4 is generated in the transistor Tr _1.
Turn off. Therefore, the capacitor _C3 is charged by the photocurrent of the photodiode DP according to the reflected light from the object. When the charging voltage of capacitor _C3 reaches a predetermined relationship with the reference voltage at time _t2 , comparator CP is inverted and outputs the second control pulse sig-5.
occurs. The third thyristor _T3 , which is applied with the second control pulse via the OR gate _G1 , turns on,
Closes the commutation loop. As a result, the second thyristor _T2 is turned off, and the discharge tube FT stops emitting light.

If the time interval between times t ₁ and t ₂ is shorter than the constant time γ ₁ , the above-mentioned operation is performed. However, if this time interval is longer than the fixed time γ ₁ , the first control pulse (sig-3) is generated at the arrival time t ₃ of the fixed time γ ₁ .
is applied to the third thyristor _T3 from the terminal e of the control circuit 3 via the OR gate _G1 , and the flash light emission is stopped.

In this manner, the flash light emission is automatically completed within a certain time _γ1 by the first and second control pulses, so that the frame speed of the motor drive device and the flash light emission can be synchronized. In order to ensure proper exposure by continuous flash emission, it is preferable to select the aperture value and subject distance in advance according to the predetermined light emission amount GNL.

The amount of flash light emission is controlled in the above manner,
The dimming display is performed as follows. Since the output of the terminal f of the control circuit 3 is “L” for a certain period of time γ ₂ ,
During this time, OR gate _G6 outputs "H". Therefore, the shift register SR receives the second control pulse (sig-5) inputted to the input terminal D for each flash emission.
Load. In other words, when the first flash is emitted, the second
₁ of the shift register when the control pulse of
When the output becomes "L", the light emitting diodes D ₁ and D ₁ ' light up, and when the second control pulse is generated the second time, the outputs ₁ and ₂ of the shift register become "L" and the light emitting diode D ₁ lights up. , D ₁ ′; D ₂ , D ₂ ′ are lit.
On the other hand, if the flash emission is stopped by the first control pulse without generating the second control pulse in the third time, _{the 1} output of the shift register will be "H", ₂ ,
Since the Q ₃ output is “L”, the light emitting diode D ₂ ,
D ₂ ′; D ₃ and D ₃ ′ will light up. In this way, the number of light-emitting diodes that are lit corresponds to the number of successfully dimmed lights, and the number of light-emitting diodes that are lit or turned off in the direction in which the light-emitting diodes are arranged corresponds to the number of frames during continuous flash photography that are dimmed. If successful, it will display how many frames the dimming failed.

Now, when this flash photography is completed and the switch _S3 is turned on, the output of the NAND gate _G2 becomes "H" and the Q output of the NAND gate _G3 becomes "L".
Therefore, the shift register SR is reset by a momentary "H" pulse at the connection point _P2 , and enters the display mode for the number of possible flash emissions described above. Furthermore, the switch
If you turn off _S4 , the above display operations will not occur.
Further, the constant time γ ₁ and the maximum light emission time γ ₂ match, and the transistor Tr ₁ is turned on after γ ₁ (γ ₂ ) has elapsed from the time when the synchro contact S _x is turned on, and the charge in the capacitor C ₂ is to prepare for the next flash photography.

(2) Operation when the motor drive device is not used: At this time, switch _S2 is turned off and the first control pulse sig-3 is not generated, so the dimming operation is performed using only the second control pulse sig-5. will be held. By applying "H" to terminal R of shift register SR when switch _S2 is off, the display of the possible number of flashes can be erased.

Next, the detection circuit 5 will be explained. In Figure 2
A ₁ to _{A 6} are operational amplifiers (hereinafter referred to as op amplifiers).
CP ₁ to CP _o are comparators. ZD ₁ to ZD ₂ are Zener diodes. D _2-1 , D _2-2 , and D _2-3 are diodes. Tr ₁ to Tr ₄ are transistors. r ₁ ~ _{r 13} and r _2-1 ~ _{r 2-o} are resistances, especially
r ₁ is a positor. C _2-1 to _{C 2-o} are capacitors. I _p and I _p are constant current sources that generate currents proportional to absolute temperature. _IQ is a constant current source. Note that the symbols of the resistors and constant current sources represent their values.

Now, let the voltage at the connection point P ₃ of resistors r ₁ and r ₂ be e ₀ , the Zener voltage of Zener diode ZD ₁ be e ₁ , and the emitter current of transistor Tr ₂ connected to the output terminal of OP amplifier A ₂ I _E , collector current
If I _C , then I _E =e ₀ −e ₁ /r ₆ , but if h _FE of transistor Tr ₂ is sufficiently large, I _C ≈I _E may be satisfied. _{Therefore , the output voltage V X of the OP amplifier A4 is V _} (2) (However, I _s is reverse saturation current, q is electronic charge,
(T is the absolute temperature, K is the Boltzmann constant,) Next, find the output voltage V _Y of the OP amplifier _A3 .

The current I _D1 flowing through the diode D _2-1 is the op amp A ₃
Since the non-inverting input terminal of is grounded, it can be expressed as I _D1 = e ₀ /r ₄ +e ₁ / _rs . Therefore _, V _Y =-KT/qlnI _D1 / _Is =-KT/qln( _e0 / _Isr4 + _e1 / _Isr4 )...( ₃ ).

Since OP amplifier _A5 performs differential amplification, r ₃ = r ₁₀
When the resistance values are set so that = _r9 = _r11 , the output voltage _V5 of the OP amplifier _A5 can be expressed as _V2 = _VX - _VY . Here, from equations (2) and (3), V _Z = r ₇ I _O +KT/qlne ₀ −e ₁ /I _s r ₆ +KT/qln (e ₀ /I _s r ₄ +e ₁ /I _s r ₅ ) ...(4) becomes. Next, between the base-emitter voltage V _BE of transistor Tr ₃ and the collector current I _C3 , V _BE =
There is a relationship of KT/qlnI _C3 /I _s . Here, V _BE is the output voltage V _Z of OP amplifier A ₅ minus the forward voltage of diode D _2-3 , so V _BE = V _Z −V _D3 = r ₇ I ₀ +KT/qlne ₀ −e ₁ /I _s r ₆ +KT/q
lne ₀ ／I ₃ r ₄ ＋e ₁ ／I _s r ₅ −KT ／qlnI _P ／I _s If we select the resistance value so that r ₆ = r ₄ = r ₅ = R, we get the following equation. The formula holds true.

That is, V _BE = r ₇ I _O +KT/qlne ₀ −e ₁ /I _s R+ KT/qlne ₀ +e ₁ /RI _s −KT/qlnI _P /I _s =KT/qlnI _C3 /I _s ……(5) becomes.

Rearranging equation (5), r ₇ I _O +KT/qlne ₀ −e ₁ /RI _P・e ₀ +e ₁ /RI _C3 = 0 By the way, since the constant current I _O is a current proportional to the absolute temperature T, r ₇ It can be expressed as I _O =KT/qlnQ (6) (where Q is a proportionality constant). Therefore, KT/qln(e ₀ −e ₁ /RI _P・e ₀ +e ₁ /RI _C3 )・Q=0 ∴e ₀ −e ₁ /RI _P・e ₀ +e ₁ /RI _c3・Q=1 ∴ I _c3 = Q / R ² I _P (e ₀ ² −e ₁ ) ² ...(7) By the way, e ₀ = r ₂ / r ₁ + r ₂ V _cM e ₁ = r ₂ / r ₁ + r ₂ V _o . If r ₁ , r ₂ , and V _z D ₁ are selected so that

I _c3 = Q/R ² I _P (r ₁ / r ₁ + r ₂ ) ² (V _cM ² −V _o ² ) ...(8) Comparing equations (1) and (8), the constant term C _M /2α and Q/R ² I _P (r ₁ /r ₁ + r ₂ ) ² are selected so that they have a constant proportional relationship, then the voltage across resistor r ₁₂ connected to the collector of transistor Tr ₃ is V ₁₂ =
r ₁₂ · I _c3 is proportional to the number of flashes possible (N). That is,
The voltage at the connection point _P4 decreases as N increases.
On the other hand, the non-inverting inputs of comparators CP ₁ to CPn (reference voltage determined by resistors r _2-1 to _{r 2-o} and constant current _IQ )
Since comparator CP ₁ has the highest value and then decreases in order, when the voltage at connection point P ₄ decreases as main capacitor _CM is charged, first the output of comparator CP ₁ reverses from “L” to “H”. do.
Thereafter, the comparators CP ₂ , CP ₃ , etc. are inverted. A differentiating circuit consisting of capacitors C _2-1 to C _2-o and resistor r ₁₃ generates a differential pulse every time the comparators CP ₁ to CPn invert. The waveform shaping circuit _A7 shapes this differential pulse and applies it to terminal a.

On the other hand, when the terminal b becomes "H" due to the Q output of the NAND gate _G3 , the transistor _Tr4 is turned on and the voltage at the connection point _P3 is lowered to the ground potential. Therefore, the voltage at the connection point _P4 rises almost to the potential of the power supply line _Vcc , and the outputs of the comparators _CP1 to CPn are never inverted from "L" to "H".

Further, the hogistor _r1 is arranged near the flash discharge tube FT, and changes its resistance value depending on the temperature of the flash discharge tube FT itself or its surrounding temperature. In other words, as the temperature of the discharge tube FT rises (for example _, the discharge energy during flash light emission is a factor), the voltage at which flash light can be emitted tends to rise. increase and decrease the voltage e ₀ at the connection point p ₃ . From equation (7), voltage e ₀
If the current _Ic3 decreases, the current Ic3 also decreases, and as a result, the number of pulses generated at the terminal a decreases.

FIG. 3 is a circuit diagram showing a modification of the detection circuit. Components having the same functions as those in FIG. 2 are given the same reference numerals. In this embodiment, when the outputs of the comparators CP ₁ to CPn are inverted from "L" to "H", the corresponding light emitting diode among the light emitting diodes D _3-1 to _{D 3-o} lights up, and the number of possible flashes is increased. is displayed.

FIG _. 4 is an example circuit of the control circuit 3. In the figure, when _the synchro contact _S
The first one-shot multivibrator consisting of capacitor C ₂₀ and resistor R ₂₀ is activated, and inverter G ₂₁
The output of is “L” for a certain period of time γ ₃ . This output is transmitted to terminal C via inverter G ₂₂ and to terminal d via inverter G ₂₃ . The time _r3 during which this inverter _G21 is at "L" is the first,
This is sufficient time for the second thyristors T ₁ and T ₂ to turn on.

The second one-shot multivibrator consisting of NAND gate G ₂₄ , inverter G ₂₅ , capacitor C ₂₁ , and resistor R ₂₁ is activated when the output of inverter G ₂₁ becomes “L”, and the output of inverter G ₂₅ remains γ ₁ for a certain period of time. It becomes “L” during this period. If the resistance R ₂₁ is made variable according to the piece speed, γ ₁ changes. Inverter G ₂₆ ,
The third one-shot multivibrator, which consists of a capacitor C ₂₂ and a resistor R ₂₂ , starts operating when the output of the inverter G ₂₅ changes from "L" to "H" after the elapse of γ ₁ , and remains "H" for a certain period of time γ ₃ . Output.

When the synchro contact Sx is turned on when the switch _S2 is turned on and the output of the inverter _G27 is "H", the terminal f is connected to a signal _γ1 for a certain period of time via the AND gate _G29 and the OR gate _G30 . "L" is output during this period. Similarly, AND gate G ₂₆ is an inverter
After the output of _G25 becomes "H", "H" is output to terminal e for a certain period of time _γ3 . In other words, when switch _S2 is on (during continuous flash photography), the first control output
sig-3 and photometric pulse sig-4 are “L” for the same time
It is becoming.

Next, when the switch _S2 is turned off, the NAND gate _G31 outputs "H" only when the synchro contact Sx is turned on. The fourth one-shot multivibrator consisting of NAND gate G ₃₂ , inverter G ₃₃ , capacitor C ₂₃ , and resistor R ₂₃ starts operating, and inverter G ₃₃ keeps the output “L” for a certain period of time γ ₄ . At this time, since the output of the AND gate _G29 is "L", the terminal f becomes "L" for a certain period of time _γ4 . This time r ₄ is the time required for the speedlight to emit maximum light when not continuously emitting light.

FIG. 5 is a block diagram showing another embodiment of the MD tuning switch. A switch _S5 on the camera body side connected in series with the switch _S2 is configured such that the terminal h cannot be set to "L" unless the motor drive device MD is attached to the camera or the power is turned on. In this way, continuous flash photography is prevented inadvertently.

According to the present invention, it is possible to display the number of correct flash control operations and the number of failed flash control operations during continuous flash photography, so that the photographer can check the result of the flash control operation after continuous flash photography. It has various uses, such as being used as a reference for the next continuous flash photography, and has the effect of being a useful display for continuous flash photography.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention;
2 is a circuit diagram showing an example of a specific configuration of the detection circuit 5 in FIG. 1, FIG. 3 is a circuit diagram showing another example of the detection circuit, and FIG. 4 is another example of the MD tuning device. It is a diagram. FIG. 5 is a diagram showing another example of the MD tuning switch. Explanation of symbols of main parts, _CM ...Main capacitor, 3...Control circuit, _G1 ...OR gate, _T3 ...
...Third thyristor, DP...Photodiode,
C ₃ ... Capacitor, Tr ₁ ... Transistor, R ₅ ...
...Resistor, Dz ₁ ... Zener diode, C _P ... Comparator, 5 ... Detection circuit, SR ... Shift register, {D ₁ ... Dn, D' ₁ ... Dn'} ... Light emitting diode.

Claims (1)

[Scope of Claims] 1. A display device for flash photography used in a flash photography device capable of continuous photography, comprising: a detection means for detecting whether light reflected from a subject due to light emission from a flash discharge tube reaches a predetermined value; , a display unit having a plurality of display elements, in which the plurality of display elements are arranged regularly, and displaying the detection result of the detection means by the display element, which differs for each shooting in the continuous shooting; When the means detects that the reflected light from the subject has reached a predetermined value, it generates a first control signal to control the display element to a first display state, and Therefore, when it is detected that the reflected light from the subject does not reach a predetermined value, a second control signal is generated to control the display element to enter the second display state, and the detection means A display device for flash photography, comprising display control means for outputting the first or second control signal corresponding to the detection result to different display elements of the display section.