JPH05227148A - Frame pattern detection circuit - Google Patents

Abstract

PURPOSE:To detect the frame pattern of each channel without complicating a circuit scale and control even when the number of channels multiplexed on a frame is increased. CONSTITUTION:An input part 11 fetches data A1, B1, C1,... of each channel multiplexed on the frame of an input data signal Di corresponding to a timing signal C1 from a timing signal generating part 15, and sends it out to a storage part 13. The storage part 13 stores the data of each channel classified by each channel sequentially. and accumulates a prescribed number of frames at each channel. A pattern detecting part 12 compares the data of prescribed number of frames read out at each channel from the storage part 13 with reference frame pattern data set in advance, and sends out pattern detection information D1 representing whether or not coincidence between them can be obtained to an output part 14. The output part 14 holds the pattern detection information at each channel, and outputs them as pattern detection information D2a-D2c.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frame pattern detecting circuit, and more particularly to a frame pattern detecting circuit for detecting a frame pattern of a multi-frame data signal transmitted via a satellite line.

[0002]

2. Description of the Related Art FIG. 3 is a block diagram showing an example of a conventional frame pattern detection circuit, and FIG. 4 is a timing chart for explaining the operation. The case where the input data signal Di of the multi-frame structure in which the data of a plurality of channels (A, B, C) are time-division multiplexed in the frame is received and the frame pattern of the data of each channel is detected is shown.

By the way, the frame pattern detection circuit is
Input sections 1A, 1B and 1C provided corresponding to the respective channels A, B and C, and pattern detection sections 2A, 2B,
2C, output sections 3A, 3B and 3C, and a timing signal generating section 4. Here, the timing signal generator 4 generates a timing signal to be supplied to each part in synchronization with the reference clock Cs.

The input sections 1A, 1B and 1C have the data A1, B1, C1, A2 of each channel multiplexed in each frame of the input data signal Di according to the timing signals C1a, C1b and C1c, respectively. B2, C2 ...
Respectively, and the pattern detection units 2A, 2B, 2C
To each.

The pattern detectors 2A, 2B and 2C sequentially store the data taken in by the input units 1A, 1B and 1C for a predetermined number of frames, respectively, and generate a timing signal C.
2a, C2b, C2c are respectively compared with preset reference frame pattern data, and pattern detection information D1a, D1b, D1c indicating whether or not they match are sent to the output units 3A, 3B, 3C, respectively.

The output sections 3A, 3B and 3C respectively receive and hold the pattern detection information D1a, D1b and D1c according to the timing signals C3a, C3b and C3c and output them as pattern detection information D2a, D2b and D2c.

[0007]

In the conventional frame pattern detection circuit described above, it is necessary to provide an input section, a pattern detection section, and an output section for each channel multiplexed in a frame. Since the timing signal generator needs to generate a large number of timing signals to be supplied to the input section, the pattern detection section, and the output section,
When the number of channels multiplexed in a frame increases, the circuit scale increases and control becomes complicated.

An object of the present invention is to provide a frame pattern detection circuit capable of detecting the frame pattern of each channel without complicating the circuit scale and control even if the number of channels multiplexed in a frame increases. is there.

[0009]

A frame pattern detection circuit of the present invention receives a data signal of a multi-frame structure in which a plurality of channels are time-division multiplexed in each frame and detects a frame pattern of data of each channel. In the frame pattern detection circuit, means for extracting the data of each channel from the data signal, and data for each channel extracted by the extracting means are sequentially stored for each channel and a predetermined number of frames are accumulated for each channel. Storage means and the predetermined number of frames of data stored in the storage means are read out for each channel and compared with preset reference frame pattern data, and detection information indicating match or mismatch is sent out for each channel. Detection means,
Output means for receiving and transmitting the detection information for each channel is received.

[0010]

The present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a timing chart for explaining the operation. Multiple channels (A,
(B, C) shows a case where the input data signal Di having a multi-frame structure in which time division multiplexing is performed is received and the frame pattern of the data of each channel is detected.

Here, the frame pattern detection circuit includes an input unit 11, a pattern detection unit 12, a storage unit 13, an output unit 14, and a timing signal generation unit 15. The timing signal generator 15 generates a timing signal to be supplied to each part in synchronization with the reference clock Cs.

Next, the operation will be described with reference to FIG.

The input section 11 receives the data A1, B1, C1, A2, B2, C2 of each channel multiplexed in the frame of the input data signal Di according to the timing signal C1.
.. is taken in and sent to the storage unit 13. The storage unit 13 sequentially stores the data of each channel for each channel according to the timing signal C3, accumulates a predetermined number of frames of data for each channel, and reads the accumulated predetermined number of frames of data for each channel. It is sent to the pattern detection unit 12.

The pattern detection unit 12 compares the predetermined number of frames of data read from the storage unit 13 for each channel with preset reference frame pattern data according to the timing signal C2, and determines whether they match. Is transmitted to the output unit 14 for each channel.

The output unit 14 holds the pattern detection information D1 for each channel according to the timing signal C4 and outputs it as pattern detection information D2a, D2b, D2c.

As described above, the same circuit is used to temporally divide the processing to detect the frame pattern.

[0018]

As described above, according to the present invention, if the frame pattern detection processing time can be secured within each frame period in accordance with the number of channels multiplexed in each frame, the storage section is provided. , The data of each channel can be sequentially stored for each channel, and a predetermined number of frames of data can be accumulated and read for each channel.
The data processing of a plurality of channels can be temporally divided and independently executed by the input section, the pattern detection section, and the output section of the set. Therefore, the circuit scale is minimized regardless of the number of channels to be processed, and the operation control only repeats the same operation, so that the circuit and control can be simplified.

Although the frame pattern detection is described in the present embodiment, the present invention is not limited to the frame pattern detection and can be used for other similar signal detection processing.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a timing chart for explaining the present embodiment.

FIG. 3 is a block diagram showing an example of a conventional frame pattern detection circuit.

FIG. 4 is a timing chart for explaining the operation of the conventional frame pattern detection circuit shown in FIG.

[Explanation of symbols]

 11 Input Section 12 Pattern Detection Section 13 Storage Section 14 Output Section 15 Timing Signal Generation Section C1 to C4 Timing Signal Di Input Data Signal D1, D2a to D2c Pattern Detection Information

Claims (1)

[Claims] 1. A frame pattern detection circuit that receives a data signal of a multi-frame structure in which a plurality of channels are time-division multiplexed in each frame and detects a frame pattern of data of each channel, Means for extracting data of each channel, storage means for sequentially storing the data of each channel extracted by the extraction means for each channel and accumulating a predetermined number of frames for each channel, and the storage means stored in the storage means Data for a predetermined number of frames is read out for each channel and compared with preset reference frame pattern data, and detection means for sending out detection information indicating whether they match or not for each channel, and for each channel receiving the detection information. A frame pattern detection circuit, comprising: output means for holding and transmitting each.