JPH05227121A - Synchronous type spread spectrum modem - Google Patents

Abstract

PURPOSE:To provide a synchronous type spread spectrum (SS) modem un-requiring a synchronism holding function such as a delayed locked loop(DLL) or an AGC circuit, etc. CONSTITUTION:A means 52 which performs the angle modulation of information, a means 25 which obtains a clock signal by frequency-dividing an angle modulated wave into 1/N1, a means 48 which generates a spread code based on the clock signal, and a means 10 which outputs an SS modulated wave by performing the spread modulation of the angle modulated wave by the spread code are provided on a modulator side. A means 33 which performs the reverse spread of the SS modulated wave by a spread code for demodulation, means 4. 24, and 22 which perform the angle demodulation of reverse spread output by a phase locked loop, a means 34 which performs SS synchronism detection by detecting the presence/absence of a noise from phase comparison output in the phase locked loop via a BPF 16, and means 26, 27, and 35 and a Sw which set by selecting either both frequency-dividing output by an SS synchronism detection signal as the clock signal for spread code generator for demodulation by obtaining the output in which VC022 output in the phase locked loop is frequency-divided into 1/N1 and the output frequency-divided into 1/N2 are provided on a demodulator side.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronous spread spectrum modulation / demodulation device, and more particularly to a delay locked loop (DLL).
The present invention relates to a synchronization-type spread spectrum (hereinafter also abbreviated as "SS") modulation / demodulation device that does not require a synchronization holding function such as AGC circuit.

[0002]

TECHNICAL BACKGROUND Recently, in SS communication, mobile communication using the multiple access method by SS technology has reached a practical range. As is well known, since radio resources are limited, it is necessary to effectively use frequencies. In that respect, the SS signal can contribute to the improvement of frequency utilization efficiency in principle. Because,
Since the SS signal is spread over a wide frequency band and the power spectrum density of the modulated wave is very small, it has little effect on other conventional communication radio waves, etc., and can be mixed in existing communication frequency bands. The effect in that respect is also great. For the above reasons, wireless communication by SS is becoming familiar, and in the future, such as mobile-to-mobile communication applications mounted on vehicles, etc.
It is hoped for its future potential and development potential.

[0003]

2. Description of the Related Art In SS communication, synchronization acquisition and synchronization holding in reception are basically necessary, and various synchronization acquisition and holding methods have been proposed and put to practical use. Among them, PSK (Pha (Pha
se Shift Keying) Carrier for modulation and S that is secondary modulation
The synchronous SS modulation and demodulation method, in which the SS modulation is performed in a synchronous relationship with the spread code clock signal used for the S modulation, is also known as a method in which the circuit configuration can be somewhat simplified in the reception demodulation.

A conventional technique of the SS modulation and demodulation system will be described with reference to FIGS. FIG. 1 is a block configuration diagram of a conventional SS modulation device (transmission unit) capable of implementing a synchronous SS modulation system, FIG. 2 is a block configuration diagram of a conventional synchronization SS demodulation device (reception unit), and FIG. 3 is a DLL ( (Delay lock loop) type block diagram of a signal processing circuit, which is the main part of the sync hold circuit, FIG. 4 is a sync hold characteristic diagram in the DLL sync hold circuit, and FIG. 5 is a correlation characteristic showing a sliding correlation type sync acquisition operation. It is a figure.

First, the SS modulator shown in FIG. 1 will be described. Information signal d such as data from the input terminal In1
(t) is the carrier cos for PSK modulation from the oscillator 19.
ωt is supplied to the multiplier 9 for PSK modulation, and the PSK modulation of the information d (t) is performed here, and the PSK modulated wave d (t) cosωt is obtained. Furthermore, the oscillator output is divided by the frequency divider 2
A clock signal is generated by supplying it to 5 and dividing it by 1 / N _{1. Based} on this, a spread code generator (PNG) 48 generates a spread code P (t). Therefore, the spreading code P (t) that is output is kept in synchronization with the carrier cosωt. The spread code P (t) is supplied to the multiplier 10 for spread modulation, where SS (spread spectrum) modulation is performed to generate an SS modulated wave P (t) * d (t) cosωt,
It is output from an output terminal Out1 via a BPF (bandpass filter) 11.

Next, the operation of the SS demodulator will be described with reference to FIG. The SS modulated wave received by the antenna (not shown) is supplied to the BPF 12 via the input terminal In2, where the frequency components other than the main lobe of the spread modulation signal are removed, and the AGC (automatic gain control) circuit. 2 is output. If the level of the received SS modulated wave is too low, the synchronization acquisition operation described later will be hindered. Therefore, the AGC circuit 2 automatically amplifies the signal appropriately, and then the sliding correlation and despreading in the subsequent stage are performed. It is supplied to the demodulator / multiplier 3 and the DLL-type synchronization holding signal processing circuit (hereinafter simply referred to as “DLL signal processing circuit”) 36.

The SS modulated wave supplied to the multiplier 3 is despread by being multiplied with the spreading code generated by the PNG (spreading code generator) 47, and is used for generating this despreading code. The clock signal of
It is set by the VCO (voltage controlled oscillator) 21 a little higher than that at the time of holding the synchronization. Therefore, the sliding correlation and the despread demodulation are performed in time series.

The operation leading to synchronization acquisition (establishment) will now be described. The input SS modulated wave P (t) * d (t) cosωt from which unnecessary frequency band components have been attenuated or removed by the BPF 12 is used by the spread code P from the spread code generator 47 in the multiplier 3.
Correlation is performed by multiplication with (t). This spreading code P
(t) is actually P (t-τ) having a delay of time τ compared to the spreading code P (t) generated by the PNG 48 of the SS modulator (transmission side), and this is P (t). On the letter P of
Although notated with (hat), it will be expressed as "ρ (t)" here because of the restrictions on the characters that can be used in electronic applications. Therefore, the multiplication output from the multiplier 3 is P (t) * ρ
(t) * d (t) cosωt.

The multiplication output is supplied to the multipliers 4 and 5, and the multiplier 4 reproduces the carrier carrier cos (ω) from the VCO 22.
Synchronous detection is performed by multiplication with t-φ). Therefore, from the multiplier 4, (1/2) P (t) * ρ (t) * d (t) * {cosφ + cos (2ω
t-φ)} is output, and the LPF (low-pass filter) 17 at the next stage removes the P (t) * ρ (t) * d (t) cos (2ωt-φ) / 2 component. , P (t) * ρ (t) * d (t) cosφ. If the value of φ is close to 0, LPF17 output P (t) * ρ (t) * d
The level of (t) cosφ is about 1/2. On the other hand, in the multiplier 5, the reproduction carrier cos (ωt-φ) from the VCO 22 is
si whose phase has been shifted by π / 2 in the π / 2 phase shift circuit 23
A carrier of n (ωt-φ) is supplied.

Therefore, the output of the multiplier 5 is (-1/2) P (t) *.
ρ (t) * d (t) * {sinφ + sin (2ωt-φ)} and LPF16
Outputs -P (t) * ρ (t) sinφ, but the actual level is close to zero. The outputs of the LPF 17 and the LPF 16 are both supplied to the multiplier 6, where both outputs are multiplied and the output is P ² (t) ρ ² (t) * d ² (t) * (-1/2 )
It is obtained as an error signal of sin2φ. The error signal is further filtered by the loop filter 2 which determines the response time constant of the loop.
After being converted into an error signal of -Ksin2φ in 4, the VCO
22 is supplied as a control signal. The carrier reproducing circuit 50 including such a loop of phase locked loop can simultaneously perform PSK demodulation in synchronization with the input carrier.

It is this carrier regeneration circuit 50 that first starts to work after the power supply of the SS demodulator (reception unit) is turned on. Therefore, after carrier regeneration, the correlation output P (t) * ρ (t) obtained from the LPF 17 is obtained. ), That is, 3 around the point t ₀ in FIG.
The output based on the angular output characteristic is supplied to a threshold level detection circuit (synchronization determination circuit) 34 for synchronous acquisition of sliding correlation, and after the synchronization acquisition point SHL is detected here, an output (waveform) shaping circuit 35 is further provided. , And a constant DC output is obtained from the time of synchronization acquisition. This DC output is supplied to the adder circuit 42, where it is added to the correlation output from the DLL signal processing circuit 36 and then supplied to the VCO 21. The VCO 21 is controlled by the obtained addition output, and the controlled voltage-controlled oscillation output becomes a clock signal for generating the spread code at the time of normal synchronization holding.

Next, the synchronization holding operation will be described. The input SS modulated wave is supplied to the DLL signal processing circuit 36 via the BPF 12. Here, a specific circuit example of the DLL signal processing circuit 36 is shown in FIG. The SS modulated wave is input from the input terminal In3 to the multipliers 7 and 8
Is supplied to. On the other hand, the multiplier 3 is connected to the input terminal In4.
The spread code (a) having a phase Δt earlier than that of the regular spread code P (t) supplied to the terminal (a) and the spread code (b) having a phase Δt slower than P (t + Δt) at the input terminal In5. , PNG47
More supplied respectively.

In the SS system, Δt is a time corresponding to one bit of the spread code, that is, one chip time. Therefore, the output of the multiplier 7 is a PSK modulated wave which is a despread output during normal operation and can be transmitted. It is supplied to the absolute value circuit (or envelope detection circuit) 38 through the narrow band characteristic BPF 13. Similarly, the output of the multiplier 8 is also supplied to the absolute value circuit 39 via the BPF 14. Therefore, the absolute value circuit 3
The output of 8 is approximately P to the component of twice the carrier frequency.
It becomes a signal multiplied by (t) * P (t−Δt), and the absolute value circuit 3
Similarly, for 9 outputs, P (t) * P is added to the component twice the carrier frequency.
It is obtained as a signal multiplied by (t + Δt).

Both output signals are supplied to a subtraction circuit 40 to be subtracted and calculated, and the characteristics thereof are inverse S-shaped correlation characteristics as schematically shown in FIG. It should be noted that point (C) in FIG. 4 is a synchronization holding point. The correlation output thus obtained is
It is output from the output terminal Out3 to the adder circuit 42 of FIG. 2 via the loop filter 28 for processing this into a control signal, and is added to the output of the waveform shaping circuit 35 here and then supplied to the VCO 21 for synchronization. It is held.

[0015]

The conventional receiving and demodulating device in SS communication requires synchronization holding, an AGC circuit, etc., the circuit is complicated and the cost increases, and each circuit does not always follow the theory. Since it doesn't work, there were problems such as an increase in errors. In particular, it has been desired to simplify the SS synchronization circuit and realize a reception / demodulation device that does not require the AGC circuit 2. Also, V for carrier reproduction
An oscillator is required for both the CO 22 and the VCO 21 for clock generation, and a synchronization holding circuit must also be used together, so that it is difficult to operate the device stably due to complication of the device and increase in circuit scale. There was a problem of becoming.

[0016]

In the synchronous spread spectrum modulation / demodulation device of the present invention, an angle modulation means for angle-modulating information and a first frequency division number of the obtained angle-modulated wave are provided on the modulation device side. First dividing means for obtaining a clock signal by dividing by
The demodulation device side is provided with a spread code generating means for generating a spread code based on the clock signal, and a spread modulating means for spread modulating the angle modulated wave with the spread code to output an SS modulated wave.
The despreading means for despreading the S-modulated wave by the demodulation spreading code, the angle demodulating means for obtaining the demodulated output by performing the angle demodulation of the despreading output by the phase locked loop circuit, and the band from the phase comparison output in the phase locked loop. Sync detection means for detecting SS sync by detecting the presence or absence of noise through a filter, and an output obtained by dividing the output of the voltage controlled oscillator in the phase locked loop by the first division number and a second division. A clock signal generating means for obtaining a frequency-divided output and selecting either of the frequency-divided outputs by the SS synchronization detection signal as a clock signal for the demodulation spreading code generator is configured. This is a solution to the above problem.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the synchronous spread spectrum modulation / demodulation device of the present invention will be described with reference to FIG. Figure 6
Is a block system diagram of the synchronous SS modulation and demodulation device of the present invention. FIG. 1A shows the transmitting side (synchronous SS demodulation device).
(B) indicates the receiving side (synchronous SS modulator), and in FIG. 6, the same components as those of the conventional SS modulator and demodulator shown in FIGS. 1 and 2 are designated by the same reference numerals. , Its detailed description is omitted. In FIG. 6, 52 is an angle modulator, 43 is an amplitude limiting amplifier, and 26 and 27 are frequency dividers for dividing the input signal frequency into 1 / N ₁ and 1 / N ₂ , respectively.

The operation of the device of the present invention will be described with reference to FIGS. 6 (A) and 6 (B).
Will be explained together. First, on the transmitting side, the information S (t) is supplied from the input terminal In1 to the angle modulator 52, and angle modulation (frequency modulation and phase modulation) is performed. The obtained angle modulated wave fm (t) is supplied to the multiplier 10 for spread modulation, and
The signal is branched and supplied to the frequency divider 25, where the spread code generator clock signal C ₀ (t) divided by N ₁ is obtained,
This is supplied to the spread code generator 48 to obtain the spread code P (t). The obtained spread code P (t) is supplied to the multiplier 10, and the spectrum modulation wave P (t) * fm (t) is obtained by multiplication with the angle modulation wave fm (t), and the antenna is transmitted via the BPF 11. It is output from A ₁ .

Next, the operation of the synchronous SS demodulator (reception side) will be described with reference to FIG. The transmitted spectrum-modulated wave is received by the receiving antenna A ₂ , and the BPF 1
The unnecessary frequency component outside the main lobe band is removed by 2 and then supplied to the despreading multiplier 3. The received SS modulated wave is P (t) * fm (t) + n (t) in which noise n (t) is mixed. In the multiplier 3, multiplication with the spread code ρ (t) output from the spread code generator 47 is performed, and the multiplication output P
(t) * ρ (t) * fm (t) + n (t) * ρ (t) is obtained.

The multiplication output is transmitted through the BPF 15 having the pass characteristic of the frequency bandwidth of the angle modulation wave, the angle modulation wave component and a part of the other diffusion component, and the amplitude limiting amplifier (L
After the amplitude is limited by the IM) 43, it is supplied to the phase comparator (multiplier) 4 for the phase locked loop (PLL).
The phase comparator 4 performs a phase comparison with the VCO output fm ′ (t) from the voltage controlled oscillator (VCO) 22 and outputs a phase comparison signal E (t). The phase comparison signal E (t) is supplied to the VCO 22 via the loop filter 24 so that the phase control signal E (t) is controlled as a PLL so that the VCO output synchronously follows the angle modulated wave. On the other hand, the VCO output is also supplied to the spread code generator 47 as the clock signal C ₁ (t) via the frequency divider 27 and the switch circuit Sw to generate the spread code ρ (t). In the phase comparison signal from the phase comparator 4, the noise frequency component slightly higher than the information frequency is BPF16.
Is supplied to the synchronization detection circuit 34 via.

By the way, the synchronization detection circuit 34 also identifies the presence or absence of noise. That is, since the angle-modulated wave (carrier) is maximum and the noise is minimal at the synchronization point due to the sliding correlation, the synchronization point can be detected. When the noise is large in the synchronization detection signal output, the synchronization is not established. That is, the angle-modulated wave is in a diffused state, and other noise also becomes diffused noise,
It is the smallest C / N. Therefore, the demodulation noise in the angle demodulation becomes maximum, and in that case, the shaping circuit 3
At the output of 5, a high level signal as a binary signal is obtained.

Similarly, when the noise is small, it means that the synchronization is established, and the binary signal of the shaping circuit 35 in that case is obtained as a low level signal. Therefore, the shaping circuit 35
When the output of is a low level signal, the switch circuit Sw is switched to the frequency divider 26. Since the frequency division number of the frequency divider 26 is N ₁ , a clock signal C ₀ (t) which is equal to the clock frequency at the time of modulation and coincides in time (phase) is obtained and supplied to the spread code generator 47. The spreading code P (t) is obtained and the despreading is performed in the multiplier 3.

Therefore, the despread output is P ² (t) * fm (t) + P
(t) * n (t) and P ² (t) is 1 (DC),
The despread output is fm (t) + P (t) * n (t), and BPF15
Fm (t) + n ′ (t) is supplied to the amplitude limiting amplifier 43 via In this way, the SS synchronization is established and the normal SS demodulation operation is started, and the PLL angle demodulation can be performed by the PLL circuit including the phase comparator 4, the loop filter 24, and the VCO 22. The demodulation information output S '(t) containing only diffused noise is output from the output terminal Out2 via the LPF 19.

[0024]

As described above, the device of the present invention can synchronize the carrier frequency and the spread code by dividing the modulated wave of the angle modulation circuit to obtain the spread code clock signal. With this, by using the PLL demodulation, the VCO output in the PLL demodulation can be divided to be a spread code clock signal for demodulation.
The delay lock loop type sync holding circuit used conventionally is not required, and the demodulation circuit is simplified. Further, although an AGC (automatic gain control) circuit is required for the receiving section in SS communication, in the present invention, since the amplitude limiting amplifier can be used for the input section for angle demodulation, the AGC circuit can be omitted. it can.

Therefore, no problem arises in angle demodulation, and the AGC circuit is required for the sliding correlation type synchronization acquisition circuit. In the present invention, it is possible to detect whether SS synchronization is in an asynchronous state or a synchronous state. Since the angle demodulation noise level is identified and the synchronization is acquired, the AGC circuit conventionally used is no longer necessary.
If the characteristics are not ideal characteristics, the problem of synchronization detection error at the time of synchronization acquisition that basically occurs does not occur. Further, by setting the frequency division number N ₂ to be slightly smaller, there are excellent features such as a certain effect in shortening the synchronization acquisition time.

[Brief description of drawings]

FIG. 1 is a block diagram of a conventional synchronous SS modulator.

FIG. 2 is a block configuration diagram of a conventional synchronous SS demodulation device.

FIG. 3 is a specific configuration diagram of a DLL-type synchronization holding signal processing circuit which is a main part of a conventional device.

FIG. 4 is a characteristic diagram showing a sync holding characteristic in a DLL-type sync holding signal processing circuit.

FIG. 5 is a correlation characteristic diagram for explaining a sliding correlation type synchronous capturing operation.

FIG. 6 is a block diagram showing an embodiment of a synchronous spread spectrum modulation / demodulation device of the present invention.

[Explanation of symbols]

1 ... Synchronous spread spectrum modulation / demodulation device, 3-10 ... Multiplier, 11-16 ... BPF (Band filter), 17-19
... LPF (low-pass filter) 21, 22 ... VCO (voltage controlled oscillator), 24 ... Loop filter, 25-27 ... Frequency divider, 34 ... Synchronization determination circuit (threshold level detection circuit), 35 ... Shaping circuit , 43 ... Amplitude limiting amplifier, 4
7, 48 ... PNG (spreading code generator), 50 ... Carrier reproducing circuit, 52 ... Angle modulator, Sw ... Switch circuit.

Claims (1)

[Claims] 1. A modulator, on the side of the modulator, angle modulating means for angle-modulating information, and first frequency dividing means for dividing the obtained angle-modulated wave by a first frequency division number to obtain a clock signal. A demodulation device comprising: spread code generating means for generating a spread code based on the clock signal; and spread modulating means for spread modulating the angle modulated wave with the spread code to output a spread spectrum (SS) modulated wave. On the side, despreading means for despreading the SS modulated wave by a spreading code for demodulation, angle demodulation means for performing angle demodulation on the despread output by a phase locked loop circuit to obtain demodulated output, and inside the phase locked loop The synchronization detection means for detecting the presence or absence of noise from the phase comparison output of the above through the bandpass filter and the output of the voltage controlled oscillator in the phase locked loop are divided by the first division number. Divided by the output and the second division number And a clock signal generating means for selecting either of the divided outputs according to the SS synchronization detection signal as a clock signal for a demodulation spreading code generator, and a synchronous spread spectrum Modulation and demodulation device.