JPH05226621A - Solid-state image pick-up element and its manufacture - Google Patents

Solid-state image pick-up element and its manufacture

Info

Publication number
JPH05226621A
JPH05226621A JP4061349A JP6134992A JPH05226621A JP H05226621 A JPH05226621 A JP H05226621A JP 4061349 A JP4061349 A JP 4061349A JP 6134992 A JP6134992 A JP 6134992A JP H05226621 A JPH05226621 A JP H05226621A
Authority
JP
Japan
Prior art keywords
solid
frame
frame body
light
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4061349A
Other languages
Japanese (ja)
Inventor
Hikari Kawashima
光 川島
Yasutaka Nishioka
康隆 西岡
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP4061349A priority Critical patent/JPH05226621A/en
Publication of JPH05226621A publication Critical patent/JPH05226621A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To achieve a solid-stage image pick-up element without any detection of a solid pattern by performing patterning so that a plurality of layers may remain as an annular wall which separates a light-reception part from a peripheral circuit part and then forming a frame body part around a picture-element part. CONSTITUTION:Polysilicon is laminated on a silicon substrate 1 through an insulation interlayer film 3, a resist is coated, and exposure and patterning are made for eliminating etching and obtaining an electrode pattern 4 but a pattern surrounding a periphery of a picture-element part 31 is left at the time of exposure, and a frame-shaped pattern according to the polysilicon layer 4 is formed in reference to pads 32. Also, patterning is made similarly when forming a second polysilicon electrode layer 6 and an alumina layer 8 for screening light and wiring for leaving a frame-shaped pattern so that the picture-element part 31 may be surrounded, thus forming the frame-body part 1. Then, when a resist for patterning a light-screening film and the alumina 8 for wiring is rotated and coated, it spreads from the center part of a wafer toward outside and then a film thickness of the resist within the picture-element part 31 is regulated by the frame body part 1, thus achieving a light-screening pattern for reducing coating nonuniformity.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】この発明は固体撮像素子の構造お
よびその製造方法に関し、特に遮光膜形成時の加工精度
を向上させるための方法及び構造に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a solid-state image pickup device and a method of manufacturing the same, and more particularly to a method and a structure for improving processing accuracy when forming a light shielding film.

【0002】[0002]

【従来の技術】図3は従来の固体撮像素子を示すチップ
の全体図であり、図において、31は光電変換を行なう
画素部であり、複数の受光素子がマトリクス状に配列さ
れ、受光領域に開口を有する遮光膜によりそれぞれ区画
されている。32はチップ外部との信号のやりとりを行
なうためのパッド部、33はパッド部32と画素部31
内の図示しないCCD電極とを接続するための配線橋渡
し部、34はウエハより各チップを切り出す際のダイシ
ングライン部、35は遮光膜(図示せず)を形成する際
に生じたレジストの塗布むらのラインを示す。また図4
は図3のA−A′線部分における断面図であり、基板2
上に層間絶縁膜3,第1の電極用ポリシリコン層4,層
間絶縁膜5,第2の電極用ポリシリコン層6,層間絶縁
膜7,遮光及び配線用アルミ8が順次形成されている。
2. Description of the Related Art FIG. 3 is an overall view of a chip showing a conventional solid-state image pickup device. In the figure, 31 is a pixel portion for performing photoelectric conversion, in which a plurality of light receiving elements are arranged in a matrix and a light receiving area is formed. Each is divided by a light shielding film having an opening. 32 is a pad section for exchanging signals with the outside of the chip, 33 is a pad section 32 and a pixel section 31.
A wiring bridging portion for connecting to a CCD electrode (not shown) inside, a dicing line portion 34 for cutting out each chip from the wafer, and a resist coating unevenness caused when forming a light shielding film (not shown). Shows the line. See also FIG.
3 is a cross-sectional view taken along the line AA ′ of FIG.
An interlayer insulating film 3, a first electrode polysilicon layer 4, an interlayer insulating film 5, a second electrode polysilicon layer 6, an interlayer insulating film 7, a light-shielding and wiring aluminum 8 are sequentially formed thereon.

【0003】次に製造方法、特に遮光膜形成工程につい
て説明する。遮光膜形成工程前では図3に示したように
パッド部32を構成する第1の電極用ポリシリコン層4
や橋渡し電極(配線をまたぐ電極)33、および画素部
31内のCCD電極となる第2の電極用ポリシリコン層
6、さらにはダイシングライン34等が形成されてお
り、これら構成部材によってウエハ表面に凹凸が生じて
いる。
Next, a manufacturing method, especially a light-shielding film forming step will be described. Before the light-shielding film forming step, as shown in FIG. 3, the first electrode polysilicon layer 4 forming the pad portion 32 is formed.
And a bridging electrode (an electrode that straddles the wiring) 33, a second electrode polysilicon layer 6 serving as a CCD electrode in the pixel portion 31, and a dicing line 34 are formed. There are irregularities.

【0004】図5に遮光膜形成工程の概略フローを示
す。まず、遮光膜形成前工程までの処理が終わった基板
51上に、Al等の遮光膜材料52をスパッタ法等によ
り積層し、続いてレジスト53をスピン塗布法により塗
布する(図5(a) )。
FIG. 5 shows a schematic flow of the light-shielding film forming process. First, a light shielding film material 52 such as Al is laminated by a sputtering method or the like on the substrate 51 which has been processed up to the step of forming the light shielding film, and then a resist 53 is applied by a spin coating method (FIG. 5 (a)). ).

【0005】次に、所望のマスクを用いて露光,現像
し、レジストパターン53aを形成する(図5(b) )。
Next, exposure and development are performed using a desired mask to form a resist pattern 53a (FIG. 5 (b)).

【0006】その後、上記レジストパターン53aをマ
スクにして遮光膜材料52をエッチングし、所望のAl
パターン52aを得る(図5(c) )。
After that, the light shielding film material 52 is etched by using the resist pattern 53a as a mask, and a desired Al is formed.
A pattern 52a is obtained (FIG. 5 (c)).

【0007】最後にレジストを除去し、基板51の所望
の部分を遮光するAlパターン52aとする(図5(d)
)。
Finally, the resist is removed to form an Al pattern 52a which shields a desired portion of the substrate 51 from light (FIG. 5 (d)).
).

【0008】[0008]

【発明が解決しようとする課題】従来の固体撮像素子の
製造方法では以上のようなプロセスにより遮光膜のパタ
ーニングを行なっているが、下地に凹凸があるところに
遮光膜材料を形成し、スピン塗布法によりレジストパタ
ーンを形成するため、図3中の破線で示すような、レジ
ストスピン塗布時の塗布むらが生じ、膜厚むらが発生す
る。そしてこの膜厚むらがレジストパターンの寸法むら
に反映するため、画素部における遮光パターンの開口む
らとなり、撮像時に画素部における開口むらが固定パタ
ーンとして検知されるなどの問題点があった。
In the conventional method for manufacturing a solid-state image pickup device, the light-shielding film is patterned by the above-mentioned process. However, the light-shielding film material is formed on the uneven surface of the base and spin coating is performed. Since the resist pattern is formed by the method, uneven coating occurs during resist spin coating, as indicated by the broken line in FIG. 3, and uneven film thickness occurs. Since the unevenness of the film thickness is reflected on the unevenness of the size of the resist pattern, there is a problem in that the unevenness of the opening of the light-shielding pattern in the pixel portion is detected, and the unevenness of the opening in the pixel portion is detected as a fixed pattern during imaging.

【0009】そして上述のような問題点を解決するため
に、例えば特開昭62−145770号公報に示される
ように、画素部及び周辺回路部よりも高い分離部を画素
部を囲むようにして形成し、この状態でレジストを回転
塗布することでレジストの塗布むらを低減するようにし
たものがあるが、この場合、分離部を作成するための新
たな製造フローを追加しなければならず、製造工程の増
大を招くものであった。
In order to solve the above problems, for example, as shown in Japanese Patent Laid-Open No. 62-145770, a separation portion higher than the pixel portion and the peripheral circuit portion is formed so as to surround the pixel portion. However, there is a method in which resist unevenness is reduced by spin-coating the resist in this state, but in this case, a new manufacturing flow for creating the separation part must be added, and the manufacturing process Was caused to increase.

【0010】この発明は、上記のような問題点を解消す
るためになされたもので、製造工程の増大を招くことな
く画素部における塗布むらを軽減し、撮像時の遮光パタ
ーンの開口むらによる固定パターンの検知のない固体撮
像素子の製造方法及び構造を提供することを目的とす
る。
The present invention has been made to solve the above-mentioned problems, and reduces coating unevenness in the pixel portion without increasing the number of manufacturing steps, and fixes the light-shielding pattern at the time of image pickup by the unevenness of the opening. An object of the present invention is to provide a method and a structure for manufacturing a solid-state image sensor without detecting a pattern.

【0011】[0011]

【課題を解決するための手段】この発明に係る固定撮像
素子及びその製造方法は、基板上での素子形成用の複数
の層のパターニングを行なう際に、上記複数の層が、受
光部と周辺回路部とを分離する環状の壁として残るよう
に行ない、画素部周囲に枠体部を形成するようにしたも
のである。
In a fixed image pickup device and a method of manufacturing the same according to the present invention, when patterning a plurality of layers for forming a device on a substrate, the plurality of layers form a light receiving portion and a peripheral portion. This is performed so as to remain as an annular wall that separates from the circuit portion, and a frame body portion is formed around the pixel portion.

【0012】また、上記枠体部を越えて上記受光部と周
辺回路部とを配線層により電気的に接続する場合には、
上記枠体と上記配線層との交差部において、上記配線層
に上記枠体の幅を維持するための枠体に対し平行な張り
出し部を設けるようにしたものである。
When the light receiving section and the peripheral circuit section are electrically connected by a wiring layer beyond the frame section,
At the intersection of the frame and the wiring layer, the wiring layer is provided with an overhanging portion parallel to the frame for maintaining the width of the frame.

【0013】また上記枠体部を構成する半導体層構造
を、その上部ほど幅が小さくなるように形成するように
したものである。
Further, the semiconductor layer structure forming the frame portion is formed such that the width becomes smaller toward the upper portion thereof.

【0014】[0014]

【作用】この発明においては、基板上での素子形成用の
複数の層のパターニングを行なう際に、上記複数の層
が、受光部と周辺回路部とを分離する環状の壁として残
るように行ない、画素部周囲に枠体を形成するようにし
たので、製造工程の増大を招くことなく、レジストスピ
ン塗布時の塗布むらを軽減することができる。
According to the present invention, when patterning a plurality of layers for forming elements on the substrate, the plurality of layers are left as annular walls separating the light receiving portion and the peripheral circuit portion. Since the frame is formed around the pixel portion, it is possible to reduce coating unevenness during resist spin coating without increasing the number of manufacturing steps.

【0015】また、上記枠体と上記配線層との交差部に
おいて、上記配線層に枠体に対し平行な張り出し部を設
け、上記枠体の幅を維持するようにしたので、上記枠体
を越えて上記受光部と周辺回路部とを配線層により電気
的に接続してもレジストの塗布むらが生じない。
At the intersection of the frame and the wiring layer, an overhanging portion parallel to the frame is provided in the wiring layer to maintain the width of the frame. Even if the light receiving portion and the peripheral circuit portion are electrically connected to each other by the wiring layer, uneven coating of the resist does not occur.

【0016】また、上記枠体部を構成する半導体層構造
は、その上部ほど幅が小さくなるように形成されている
ため、回転塗布時のレジストの流れがスムーズになる。
Further, since the semiconductor layer structure forming the frame portion is formed so that the width becomes smaller toward the upper portion thereof, the flow of the resist during spin coating becomes smooth.

【0017】[0017]

【実施例】以下、この発明の一実施例による固体撮像素
子を図について説明する。図1において、図3と同一符
号は同一または相当部分を示し、図1(a) はチップの全
体図であり、図1(b) は図1(a) のA−A′線部分の断
面図であり、1は画素部31の周囲部に形成された枠体
部、2は画素部31等がその表面に形成されたSi基
板、3,5,7は絶縁層間膜、4は枠体部1に相当する
箇所に形成された第1の電極用ポリシリコン、6は絶縁
層間膜5を介して第1の電極用ポリシリコン4の上方に
形成された第2の電極用ポリシリコン、8は遮光および
配線用アルミを示す。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A solid-state image sensor according to an embodiment of the present invention will be described below with reference to the drawings. 1, the same reference numerals as those in FIG. 3 indicate the same or corresponding portions, FIG. 1 (a) is an overall view of the chip, and FIG. 1 (b) is a cross section taken along the line AA ′ of FIG. 1 (a). 1 is a frame portion formed around the pixel portion 31, 2 is a Si substrate on which the pixel portion 31 and the like are formed, 3, 5 and 7 are insulating interlayer films, and 4 is a frame body. A first electrode polysilicon formed at a portion corresponding to the portion 1, 6 is a second electrode polysilicon formed above the first electrode polysilicon 4 via an insulating interlayer film 5, 8 Indicates light shielding and wiring aluminum.

【0018】次に製造方法について説明する。2層の電
極用ポリシリコン,1層の遮光及び配線用アルミで構成
される固体撮像素子において、例えば第1の電極用ポリ
シリコン4を形成する場合、従来の遮光膜形成フローと
同様にポリシリコンをスパッタ法等によりシリコン基板
1上に絶縁層間膜3を介して積層し、続いてレジストを
塗布し、露光,現像によりレジストをパターニングした
後、ポリシリコンをエッチングし、レジストを除去して
所望の電極パターン4を得る。
Next, the manufacturing method will be described. In a solid-state imaging device composed of two layers of polysilicon for electrodes and one layer of light-shielding and wiring aluminum, for example, when the first electrode polysilicon 4 is formed, the same polysilicon as the conventional light-shielding film formation flow is used. Are laminated on the silicon substrate 1 via the insulating interlayer film 3 by a sputtering method or the like, a resist is subsequently applied, the resist is patterned by exposure and development, and then the polysilicon is etched to remove the desired resist. The electrode pattern 4 is obtained.

【0019】上記レジストを露光する際、同時に画素部
31の周辺を囲むパターンを残すように露光し、画素部
31とパッド部32間に第1のポリシリコン層4による
枠状のパターンを形成する。以下同様にして、全面除去
される膜を除き、第2のポリシリコン電極層6,遮光及
び配線用アルミ層8形成時にも同様にパターニングして
画素部31を囲むような枠状のパターンを残し、枠体部
1を形成する。
At the time of exposing the resist, at the same time, the resist is exposed so as to leave a pattern surrounding the periphery of the pixel portion 31, and a frame-shaped pattern of the first polysilicon layer 4 is formed between the pixel portion 31 and the pad portion 32. .. Similarly, except for the film to be removed over the entire surface, patterning is similarly performed when the second polysilicon electrode layer 6, the light shielding and wiring aluminum layer 8 is formed, and a frame-shaped pattern surrounding the pixel portion 31 is left. The frame body portion 1 is formed.

【0020】そしてこの状態で、遮光膜及び配線用のア
ルミ8をパターニングするためのレジストを回転塗布す
ると、レジストは遠心力によりウエハ中心部から外側に
広がり、例えば図1(a) の画素部31からパッド部32
が形成された周辺部へ向かって(A′−A線方向)、枠
体部1を乗り越え画素部31からパッド部32が形成さ
れた周辺回路部へと流れ、画素部31内のレジストの膜
厚は枠体部1により規制されることとなる。このため画
素部31内ではパッド部32や配線橋渡し部33等の段
差による塗布むらは生じることなくその膜厚は均一とな
り、設計通りの遮光パターンが得られる。
In this state, when a resist for patterning the light-shielding film and the aluminum 8 for wiring is spin-coated, the resist spreads from the central portion of the wafer to the outside by centrifugal force, and for example, the pixel portion 31 of FIG. To pad 32
Toward the peripheral portion where the pad portion 32 is formed (the direction of the line A′-A), the frame portion 1 is passed over, and the pixel portion 31 flows to the peripheral circuit portion where the pad portion 32 is formed. The thickness is regulated by the frame body portion 1. Therefore, in the pixel portion 31, the coating thickness is uniform without causing coating unevenness due to the steps of the pad portion 32, the wiring bridging portion 33, and the like, and the light shielding pattern as designed can be obtained.

【0021】このように本実施例によれば、固体撮像素
子の画素及び配線等を製造する工程において、半導体
層,絶縁層,配線層等の積層される層をパターニングす
る際に、これらを画素部31を囲むように残して枠体部
1を形成するようにしたから、製造工程を増大すること
なく、レジスト回転塗布時の画素部31内における塗布
むらを低減することができ、設計通りの開口を有する遮
光パターンを得ることができる。
As described above, according to this embodiment, when patterning layers to be laminated such as a semiconductor layer, an insulating layer, and a wiring layer in a process of manufacturing pixels and wirings of a solid-state image pickup device, these are pixel Since the frame portion 1 is formed so as to surround the portion 31, the coating unevenness in the pixel portion 31 at the time of resist rotation coating can be reduced without increasing the number of manufacturing steps, and as designed. A light-shielding pattern having an opening can be obtained.

【0022】また、上記枠体部1を形成する際に、第2
の電極用ポリシリコン6を第1の電極用ポリシリコン4
よりも幅が小さくなるようにパターニングしているた
め、枠体部1の側面は階段状に形成されており、回転塗
布時のレジストの流れがスムーズになり、塗布むら低減
効果を高めるものとなっている。
In forming the frame body 1, the second
The electrode polysilicon 6 is replaced with the first electrode polysilicon 4
Since the patterning is performed so that the width is smaller than that of the frame body 1, the side surface of the frame body portion 1 is formed in a stepped shape, the flow of the resist during the spin coating becomes smooth, and the effect of reducing coating unevenness is enhanced. ing.

【0023】ところで、画素部31と周辺回路部とを接
続する場合に、枠体部1と配線層が交差することとなる
が、この場合、図2(a) に示すように、枠体部1を構成
するアルミ8の一部をパターニングして取り除き、枠体
部1と交差するアルミ8aを形成するようにしてもよ
く、この場合、これら配線層8,8aの凹凸により塗布
むらの影響が生じないようにアルミ8と8a間の間隔は
約50μm以下とするのが好ましい。
By the way, when the pixel portion 31 and the peripheral circuit portion are connected, the frame body portion 1 and the wiring layer intersect with each other. In this case, as shown in FIG. A part of the aluminum 8 constituting 1 may be patterned and removed to form the aluminum 8a intersecting the frame portion 1. In this case, the unevenness of the wiring layers 8 and 8a may cause uneven coating. The distance between the aluminum 8 and 8a is preferably about 50 μm or less so as not to occur.

【0024】また、図2(b) に示すように、枠体部1と
交差するアルミ8bに、枠体部1を構成するアルミ8と
平行な張り出し部80を形成し、アルミ8の幅を確保す
ることで、アルミ8と8b間のスペースによる枠体部1
の凹凸を低減することもできる。
Further, as shown in FIG. 2 (b), the aluminum 8b intersecting with the frame body 1 is formed with a projecting portion 80 parallel to the aluminum 8 constituting the frame body 1 so that the width of the aluminum 8 can be reduced. By securing it, the frame body part 1 by the space between the aluminum 8 and 8b
It is also possible to reduce the unevenness.

【0025】なお上記実施例では、固体撮像素子のSi
プロセス中におけるレジストの塗布むらを低減する場合
について示したが、以降の工程でオンチップカラーフィ
ルタ,オンチップマイクロレンズ等を形成するフローに
おいても同様に適用でき、上記実施例と同様の効果を奏
する。
In the above embodiment, the Si of the solid-state image pickup device is
Although the case of reducing the coating unevenness of the resist during the process is shown, it can be similarly applied to the flow of forming the on-chip color filter, the on-chip microlens and the like in the subsequent steps, and the same effect as the above-described embodiment is obtained. ..

【0026】また上記実施例では、画素部周囲の枠体部
を1つ形成したものを示したが、枠体部は2重,3重で
あってもよく、上記実施例と同様の効果を奏する。
Further, in the above-mentioned embodiment, one frame body portion around the pixel portion is formed, but the frame body portion may be double or triplet, and the same effect as that of the above-mentioned embodiment is obtained. Play.

【0027】[0027]

【発明の効果】以上のように、この発明によれば、基板
上での素子形成用の複数の層のパターニングを行なう際
に、上記複数の層が、受光部と周辺回路部とを分離する
環状の壁として残るように行ない、画素部周囲に枠体を
形成するようにしたので、製造工程の増大を招くことな
く、レジストスピン塗布時の塗布むらを軽減することが
でき、撮像時の固定パターンをなくすことができるとい
う効果がある。
As described above, according to the present invention, when patterning a plurality of layers for forming elements on a substrate, the plurality of layers separate the light receiving portion and the peripheral circuit portion. Since the frame is formed so as to remain as an annular wall around the pixel portion, uneven coating during resist spin coating can be reduced without increasing the manufacturing process, and fixing during imaging The effect is that the pattern can be eliminated.

【0028】また、上記枠体と上記配線層との交差部に
おいて、上記配線層に枠体に対し平行な張り出し部を設
け、上記枠体の幅を維持するようにしたので、レジスト
の塗布むらを招くことなく上記枠体を越えて上記受光部
と周辺回路部とを配線層により電気的に接続することが
できるという効果がある。
Further, at the intersection of the frame and the wiring layer, the wiring layer is provided with a protrusion parallel to the frame so that the width of the frame is maintained. There is an effect that the light receiving portion and the peripheral circuit portion can be electrically connected to each other by the wiring layer over the frame body without inviting.

【0029】また、上記枠体部を構成する半導体層構造
は、その上部ほど幅が小さくなるように形成されている
ため、回転塗布時のレジストの流れがスムーズになり、
塗布むら低減効果を高めることができるという効果があ
る。
Further, since the semiconductor layer structure forming the frame portion is formed so that the width becomes smaller toward the upper portion thereof, the flow of the resist during spin coating becomes smooth,
There is an effect that the effect of reducing coating unevenness can be enhanced.

【図面の簡単な説明】[Brief description of drawings]

【図1】この発明の一実施例による固体撮像素子のチッ
プ平面図と一部断面図。
FIG. 1 is a plan view and a partial sectional view of a chip of a solid-state image sensor according to an embodiment of the present invention.

【図2】この発明の一実施例による固体撮像素子の枠体
部の一部の拡大図。
FIG. 2 is an enlarged view of a part of a frame body portion of a solid-state image sensor according to an embodiment of the present invention.

【図3】従来の固体撮像素子のチップ平面図である。FIG. 3 is a plan view of a chip of a conventional solid-state image sensor.

【図4】従来の固体撮像素子の一部断面図である。FIG. 4 is a partial cross-sectional view of a conventional solid-state image sensor.

【図5】従来例の固体撮像素子の遮光膜及び配線層の製
造工程を示す断面図。
FIG. 5 is a cross-sectional view showing a manufacturing process of a light-shielding film and a wiring layer of a conventional solid-state imaging device.

【符号の説明】[Explanation of symbols]

1 画素部周囲の枠 8 遮光及び配線用アルミ 8a 配線用アルミ 8b 配線用アルミ 80 張り出し部 31 画素部 32 パッド部 33 橋渡し電極部 1 Frame around pixel part 8 Light-shielding and wiring aluminum 8a Wiring aluminum 8b Wiring aluminum 80 Overhang part 31 Pixel part 32 Pad part 33 Bridging electrode part

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】 受光部と、該受光部からの信号を処理す
る周辺回路部と、上記受光部と周辺回路部との間に設け
られた枠体部とを備えた固体撮像素子において、 上記枠体部を、前記受光部及び周辺回路部を構成する半
導体層構造を用いて形成したことを特徴とする固体撮像
素子。
1. A solid-state imaging device comprising: a light receiving section; a peripheral circuit section for processing a signal from the light receiving section; and a frame section provided between the light receiving section and the peripheral circuit section. A solid-state imaging device, wherein the frame body portion is formed by using a semiconductor layer structure forming the light receiving portion and the peripheral circuit portion.
【請求項2】 請求項1記載の固体撮像素子において、 上記枠体を構成する半導体層構造の一部は、上記受光部
と周辺回路部とを電気的に接続する配線層を含み、 上記枠体と上記配線層との交差部において、上記枠体部
はその幅が減少しており、上記配線層は上記交差部にお
ける枠体部の幅を維持するための、枠体部に対し平行な
張り出し部を有することを特徴とする固体撮像素子。
2. The solid-state image pickup device according to claim 1, wherein a part of a semiconductor layer structure forming the frame body includes a wiring layer electrically connecting the light receiving part and a peripheral circuit part, At the intersection between the body and the wiring layer, the width of the frame body portion is reduced, and the wiring layer is parallel to the frame body portion for maintaining the width of the frame body portion at the intersection portion. A solid-state image sensor having an overhang portion.
【請求項3】 請求項1記載の固体撮像素子において、 上記枠体部を構成する半導体層構造は、その上部ほど幅
が小さくなるように形成されていることを特徴とする固
体撮像素子。
3. The solid-state image pickup device according to claim 1, wherein the semiconductor layer structure forming the frame body portion is formed so that the width becomes smaller toward the upper part thereof.
【請求項4】 基板上での素子形成用の複数の層の形成
及びパターニングを行って、受光部及び周辺回路部を形
成して固体撮像素子を製造する方法において、 上記素子形成用の複数の層のパターニングは、 上記複数の層が、上記受光部と周辺回路部とを分離する
環状の壁として残るように行うことを特徴とする固体撮
像素子の製造方法。
4. A method for manufacturing a solid-state imaging device by forming and patterning a plurality of layers for forming an element on a substrate to form a light receiving part and a peripheral circuit part, wherein a plurality of the device forming elements are formed. The method for manufacturing a solid-state imaging device, wherein the patterning of the layers is performed such that the plurality of layers remain as an annular wall that separates the light receiving unit and the peripheral circuit unit.
JP4061349A 1992-02-13 1992-02-13 Solid-state image pick-up element and its manufacture Pending JPH05226621A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4061349A JPH05226621A (en) 1992-02-13 1992-02-13 Solid-state image pick-up element and its manufacture

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4061349A JPH05226621A (en) 1992-02-13 1992-02-13 Solid-state image pick-up element and its manufacture

Publications (1)

Publication Number Publication Date
JPH05226621A true JPH05226621A (en) 1993-09-03

Family

ID=13168576

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4061349A Pending JPH05226621A (en) 1992-02-13 1992-02-13 Solid-state image pick-up element and its manufacture

Country Status (1)

Country Link
JP (1) JPH05226621A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5530278A (en) * 1995-04-24 1996-06-25 Xerox Corporation Semiconductor chip having a dam to prevent contamination of photosensitive structures thereon

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5530278A (en) * 1995-04-24 1996-06-25 Xerox Corporation Semiconductor chip having a dam to prevent contamination of photosensitive structures thereon

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