JPH05226578A - Manufacture of three-dimensional integrated circuit device - Google Patents

Abstract

PURPOSE:To integrate the circuit device three dimensionally with high accuracy by a method wherein an alignment operation is performed by using an alignment mark which has been formed on a first-layer semiconductor substrate. CONSTITUTION:When a first-layer integrated circuit is formed, an alignment mark 5 composed of polycrystalline silicon is formed in a scribing-line region together with gate electrodes 4 on an active region in a p-silicon substrate 1. The surface of an n-type silicon semiconductor substrate 11 as a second silicon semiconductor substrate is etched; a groove 11A whose shape is the same as the scribing-line region in the p-silicon semiconductor substrate 1 is formed. SiO2 films 10, 12 in the p-silicon semiconductor substrate 1 and the n-silicon semiconductor substrate 11 are faced with each other; both are brought into close contact in such a way that scribing-line regions are overlapped; both are heated and pasted. The scribing-line regions take a role as alignment marks. Since their width is about 80mum, they can be aligned easily. In order to laminate three or more layers, the formation process of a second layer is repeated simply.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is directed to an integrated circuit formed on a semiconductor substrate without damaging the integrated circuit by high temperature heat treatment.
The present invention relates to a method for manufacturing a highly integrated three-dimensional integrated circuit device by forming an integrated circuit having good electrical characteristics on the integrated circuit with high alignment accuracy.

Until now, many means have been proposed to improve the degree of integration in a two-dimensional integrated circuit device. However, since the two-dimensional high-integration technology will reach a dead end sooner or later, the debate that the technology for three-dimensional integration must be developed has started, and the related technology has been proposed. Although it has been a long time since those technologies, they can be used at the laboratory stage, but they are scarcely applicable to mass production of integrated circuit devices in line. Therefore, most of the integrated circuit devices that are currently in practical use are still two-dimensionally integrated, but in any case, a practical technique for manufacturing a three-dimensional integrated circuit device has been developed. There must be.

[0003]

2. Description of the Related Art In recent years, a static random access memory (st
atic random access memory
y: SRAM) and the like, a three-dimensional integrated circuit device has been proposed in which a transistor integrated circuit is formed on a transistor integrated circuit formed on a silicon substrate via an interlayer insulating film (if necessary, Y. Inoue et al. 5 Symp.
VLSI Tech. , Tech. Dig. , P. Three
9, 1989 "4 PMOS/2NMOS Verti
cally Stacked CMOS-SRAM w
ith 0.6 μm Design Rule ”). In this proposed technique, a polycrystalline silicon film deposited on a bulk in which transistors are integrated via an interlayer insulating film is melted by an energy beam such as a laser beam, recrystallized, and then recrystallized. A three-dimensional integrated circuit device is obtained by forming a transistor in a crystal layer.

Further, an electrical connection is established by joining an Au / In pool filled with an Au / In alloy to the tungsten (W) bump formed on one substrate and the hole of the polyimide film formed on the other substrate. However, the idea of forming a three-dimensional integrated circuit device by bonding together semiconductor substrates on which integrated circuits are formed has also been proposed (in short, "Semiconductor World by Hayashi et al.
September issue, p. 58, 1990 ").

[0005]

Among the conventional techniques described above, the technique of melting a polycrystalline silicon film with an energy beam and then recrystallizing the polycrystalline silicon film is

It takes a lot of time to melt and recrystallize the polycrystalline silicon film by scanning with an energy beam, and for example, a diameter of about 10 [cm] (4
It takes about 3 [hours] to process the whole surface of [inch]. As the number of stacked recrystallized layers increases, the crystallinity of the recrystallized layer decreases. The heat of melting and recrystallization of the upper layer deteriorates the characteristics of the integrated circuit formed in the lower layer. There are problems such as.

Similarly, among the conventional techniques described above, the technique of bonding semiconductor substrates to each other does not cause the problem as in the technique of melting and recrystallization described above, but the technique of electrical W bump and Au to make connection
The position of the Au / In pool must be adjusted, but since the position cannot be adjusted with high precision, the size of the Au / In pool is set to, for example, 8 × 8 [μm.
² ] It is necessary to increase the size to a sufficient level to allow a sufficient margin, and thus the integration degree is sacrificed.

According to the present invention, when realizing the three-dimensionalization of the integrated circuit, the alignment of the integrated circuit or the elements can be realized with high accuracy to improve the degree of integration, and also the three-dimensionalization can be applied to the substrate. Similar to the matching technique, it can be performed in a short time, and the crystallinity of the crystal layer forming the integrated circuit and the characteristics of the integrated circuit itself are not sacrificed.

[0009]

In the method of manufacturing a three-dimensional integrated circuit device according to the present invention, (1) an integrated circuit device is built and used in a space between element groups in the integrated circuit device. Ordinary insulating film (eg SiO
The first semiconductor substrate (for example, p-) having the alignment mark (for example, the alignment mark 5) made of a material (for example, polycrystalline silicon) different from that of the ₂ film, the Si ₃ N ₄ film, the PSG film, the BPSG film, etc. A step of depositing an insulating film (for example, the PSG film 8 and the SiO ₂ film 10) on the silicon semiconductor substrate 1 and planarizing the same, and then forming a recess such as a groove (for example, a groove) at a position corresponding to the void on the surface. A second semiconductor substrate (for example, an n-silicon semiconductor substrate 11) in which a groove 11A) is formed and filled with an insulating film (for example, a SiO ₂ film 12) and then the insulating film is planarized, and the first semiconductor substrate. Each insulating film (eg, SiO ₂ film 12 and SiO ₂
A step of closely adhering so that the films 10) face each other,
Next, a step of performing thinning from the back surface of the second semiconductor substrate and stopping when the insulating film embedded in the recess is exposed, and then detecting the alignment mark Or a step of aligning with the integrated circuit device formed on the semiconductor substrate and then forming the integrated circuit device on the thinned second semiconductor substrate,
Alternatively,

(2) In the above (1), the second semiconductor substrate is thinned, and then each insulating film laminated to cover the void is selectively removed to obtain an alignment mark. Is characterized by including a step of expressing
Alternatively,

(3) On a first semiconductor substrate in which an integrated circuit device is formed and alignment marks made of a material different from a usual insulating film used in the integrated circuit device are formed in the space between the element groups. A step of depositing an insulating film and then planarizing,
Next, a flat insulating film (for example, a SiO ₂ film 21) having a buried oxide layer (for example, a buried oxide layer 20 formed by the SIMOX method) on the surface of a required depth from the surface and on the surface.
And a step of adhering each of the second semiconductor substrate and the first semiconductor substrate in close contact with each other so that the insulating films face each other, and then thinning from the back surface of the second semiconductor substrate to perform the embedding. Stopping at the stage where the oxide layer is exposed, then removing the buried oxide layer to expose the thinned second semiconductor substrate, and then detecting the alignment mark Aligning with the integrated circuit device formed on the first semiconductor substrate and then forming the integrated circuit device on the thinned second semiconductor substrate. Or

(4) In the above (2), the second semiconductor substrate is thinned, and then each insulating film and the second semiconductor substrate laminated to cover the void are selectively formed. Or a step of exposing the alignment mark to expose the alignment mark, or

(5) In (1), (2), (3), or (4), the element group is a block in which a plurality of required elements are formed, and the vacant space is formed in each block. Or a step of depositing an insulating film on the first semiconductor substrate, which is a line region to be independently isolated, and then planarizing the insulating film; or

(6) In the above (1), (2), (3), or (4), a scribe line in which the element group constitutes one chip and the void separates each chip independently. The method is characterized by including a step of depositing an insulating film on the first semiconductor substrate which is a region and then planarizing the insulating film.

[0015]

According to the present invention, regardless of the number of stacked semiconductor substrates, when an integrated circuit device is formed on a second or more semiconductor substrate, the integrated circuit device is always formed on the first semiconductor substrate. Since the alignment can be performed using the alignment mark formed at that time, the alignment accuracy is exactly the same as that in the normal integrated circuit device manufacturing process. As described above, a large alignment margin is unnecessary, and since the semiconductor substrate of the second layer or more can be formed to have the minimum thickness for forming an element, the etching amount during patterning is small, and the step Because of the small size, it is possible to highly finely and three-dimensionally integrate fine elements, electrodes and wirings.

Further, the alignment mark formed on the semiconductor substrate of the first layer can be accurately detected regardless of whether it is exposed or not, and is therefore commonly used in integrated circuit devices. Even if it is covered with an insulating film, it can be detected. Furthermore, even if the number of stacked semiconductor substrates is increased, there is no possibility that the crystallinity of the semiconductor will be deteriorated, and the productivity is higher than that of annealing using an energy beam. You can enjoy many similar benefits.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIGS. 1 to 7 are side sectional views of an essential part of an integrated circuit device in a process step for explaining a first embodiment of the present invention, which will be referred to below. The details will be described.

Referring to FIG. 1 1- (1) By applying a standard technique, an ordinary MIS (metal insulator) is formed on the first silicon semiconductor substrate.
A field effect transistor is formed to form an integrated circuit device.

In order to form the illustrated first layer integrated circuit device, any technique may be used as long as it is not a special technique. The point is that a MIS field effect transistor may be formed. The manufacturing process from the formation of the gate electrode and the source and drain regions will not be described in detail. Therefore, here, a part of the configuration of the integrated circuit device will be described together with the symbols.

In the figure, 1 is a p-silicon semiconductor substrate, and 2 is a silicon nitride (Si ₃ N ₄ ) film laminated on an extremely thin silicon dioxide (SiO ₂ ) film, for example, as an oxidation resistant mask film. Thermal oxidation (local oxida)
of SiO ₂ having a thickness of, for example, 600 [nm] formed by applying the ION of silicon (LOCOS) method.
The field insulating film 3 made of Si is formed on the active region of the p-silicon semiconductor substrate 1 by removing the oxidation resistant mask film and exposed, and has a thickness of, for example, 25 [nm] Si.
A gate insulating film made of O ₂ is a gate electrode made of polycrystalline silicon formed on the gate insulating film 3, and 5 is an alignment mark made of polycrystalline silicon formed at the same time as the gate electrode 4 in the scribe line region. , 6 are n ⁺ -source regions formed by the self-alignment method using the gate electrode 4 as a mask, and 7 are n ⁺ -drain regions formed by the self-alignment method using the gate electrode 4 as a mask.

1- (2) Chemical vapor deposition
position: CVD (phosphorus silicate glass) having a thickness of, for example, 300 [nm] by applying a CVD method.
A spo-silicate glass (PSG) film 8 is formed. 1- (3) Reactive ion etching using a resist process and etching gas of CF ₄ / CHF _{3 in} ordinary lithography technology
(Hing: RIE) method is applied to selectively etch the PSG film 8 and the gate insulating film 3 to n ^+.
Forming an electrode contact hole on the source region 6;

1- (4) By applying the CVD method, the thickness is, for example, 300 [n
m] W polycide film is formed. Before forming the W polycide film, the PSG film 8 may be reflowed as necessary to smooth the surface. 1- (5) Patterning of the W polycide film is performed to form the inter-element wiring 9 by applying the resist process in the ordinary lithography technique and the RIE method using CCl ₄ / O ₂ as the etching gas. To do.

1- (6) By applying the CVD method, the thickness is, for example, 600.
A [nm] SiO ₂ film 10 is formed. 1- (7) SiO ₂ film 1 by applying the etch back method
After performing the flattening of 0, the flatness on the surface of the SiO ₂ film 10 is further improved by applying the mirror polishing method. Through this step, the average thickness of the SiO ₂ film 10 is reduced to, for example, about 300 [nm].

See FIG. 2 2- (1) By applying a resist process in the lithography technique and an RIE method using CCl ₄ / O ₂ as an etching gas, an n-type second silicon semiconductor substrate is formed. The surface of the silicon semiconductor substrate 11 is selectively etched,
A groove 11A having the same shape as the scribe line region in the p-silicon semiconductor substrate 1 which is the first silicon semiconductor substrate and having a depth of 0.5 [μm] is formed. 2- (2) By applying the CVD method, the thickness is, for example, 1 [μ
m] SiO ₂ film 12 is formed.

2- (3) The SiO ₂ film 1 is formed by applying the etch back method.
After performing the flattening of No. 2, the flatness on the surface of the SiO ₂ film 12 is further improved by applying the mirror polishing method. By going through this process, the SiO ₂ film 12 becomes
The thickness of the portion corresponding to 1 A is, for example, about 700 [nm]. It should be noted that it is arbitrary which of the p-silicon semiconductor substrate 1 and the n-silicon semiconductor substrate 11 is processed first, and of course, they can be simultaneously processed.

See FIG. 3 3- (1) SiO ₂ film 10 on p-silicon semiconductor substrate 1 and SiO ₂ film 12 on n-silicon semiconductor substrate 11
Are opposed to each other, and they are adhered to each other so that their scribe line regions overlap with each other, and they are bonded by heating in a nitrogen (N ₂ ) atmosphere at a temperature of 900 ° C., for example.

By the way, p-silicon semiconductor substrate 1 and n
-When performing alignment with the silicon semiconductor substrate 11, a target of the p-silicon semiconductor substrate 1 cannot be seen through the n-silicon semiconductor substrate 11 by using a visible light microscope.

Therefore, the p-silicon semiconductor substrate 1 is viewed by using an infrared microscope. The positioning accuracy by the infrared microscope is at most 2 to 2 due to the wavelength of infrared rays.
It is about 4 [μm], which is very difficult with a fine alignment mark, but in this embodiment, the scribe line region plays the role of the alignment mark in this case, and the width thereof is actually Since the size is about 80 [μm], the alignment can be easily performed, which is one of the great advantages in the present invention.

See FIG. 4 4- (1) For example, by applying a selective polishing method using colloidal silica as an etchant, the n-silicon semiconductor substrate 11 is thinned from the back surface side. Here, the colloidal silica used as the etchant etches silicon, but SiO ₂ is difficult to etch. Therefore, the thinning of the n-silicon semiconductor substrate 11 progresses and the SiO ₂ embedded in the groove 11A. When the film 12 is exposed, the selective polishing is substantially stopped.

After this step, an island-shaped silicon film is formed on the integrated circuit device built in the p-silicon semiconductor substrate 1 via the insulating film such as the SiO ₂ film 10 and the SiO ₂ film 12. It will be. However, for simplification, the island-shaped silicon film thus obtained is also referred to as an n-silicon semiconductor substrate 11.

See FIG. 5 5- (1) By applying the RIE method using CF ₄ / CHF ₃ as the etching gas, the SiO ₂ film 12, the SiO ₂ film 10 and the PSG in the scribe line region are applied. The film 8 and the gate insulating film 3 are removed by anisotropic etching to expose the alignment mark 5 made of polycrystalline silicon. When performing this etching, since the exposed SiO ₂ film is only in the scribe line region, there is no need to apply a resist process to form a mask made of a resist film. is there.

5- (2) By applying the resist process in the lithography technique and the RIE method using CCl ₄ / O ₂ as the etching gas, the island-shaped n-silicon semiconductor substrate 11 is formed into a mesa. Etching is performed for insulation separation. 5- (3) A gate insulating film 13 made of SiO ₂ and having a thickness of 25 nm is formed by applying a thermal oxidation method at a temperature of 900 ° C., for example. In this case, the same insulating film as the gate insulating film 13 is formed on the p-silicon semiconductor substrate 1 and the alignment mark 5 made of polycrystalline silicon exposed in the scribe line region. In No. 5, since its shape has already appeared, even if it is covered with the SiO ₂ film, there is no influence on the detection by visible light.

See FIG. 6 6- (1) By applying the resist process in the lithography technique and the RIE method using CF ₄ / CHF ₃ as an etching gas, the SiO ₂ film 12, the SiO ₂ film 10,
The PSG film 8 and the gate insulating film 3 are anisotropically etched to form an electrode contact hole corresponding to the n ⁺ -drain region 7. 6- (2) By applying the CVD method, the thickness is, for example, 300 [n
m] W polycide film is formed.

6- (3) The W polycide film formed in the step 6- (2) is obtained by applying the resist process in the lithography technique and the RIE method using CCl ₄ / O ₂ as an etching gas. performing patterning, n ⁺ formed in the gate electrode 14 and the p- silicon semiconductor substrate 1 - p ⁺ is formed on the n- silicon semiconductor substrate 11 after the drain region 7 - an interlayer wiring 15 which connects the drain region Form. 6- (4) By applying the ion implantation method, the dose amount is set to, for example, 1 × 10 ¹⁵ [cm ⁻² ], and the ion acceleration energy is set to 15 [keV] to implant B ⁺ and p ⁺ Form the source region 16 and the p ⁺ -drain region 17.

See FIG. 7 7- (1) By applying the CVD method, the thickness is, for example, 600 [n
m] PSG film 18 is formed. 7- (2) The temperature is 900 [° C.] and the time is 30 in N ₂ atmosphere.
Annealing for [minutes] is performed to smooth the PSG film 18.

7- (3) The PSG film 18 is selectively etched by applying a resist process in the lithography technique and an RIE method using CF ₄ / CHF ₃ as an etching gas to perform n-silicon etching. An electrode contact hole corresponding to the p ⁺ − source region 16 formed in the semiconductor substrate 11 is formed. 7- (4) By applying the sputtering method, the thickness, for example, 1
An Al film of [μm] is formed, and then a resist process and etching gas in the lithographic technique are changed to C
By applying the RIE method with l ₂ / BCl ₃
The wiring 19 is formed by patterning the Al film.

In the three-dimensional integrated circuit device manufactured by the steps described above, the n-channel transistor is formed in the p-silicon semiconductor substrate 1 which is the first silicon semiconductor substrate, and the second channel is formed. The n-silicon semiconductor substrate 11, which is a silicon semiconductor substrate, has a structure in which a p-channel transistor is formed. As is clear from the structure of the electrodes and wiring, the p-channel transistor is formed in the p-silicon semiconductor substrate 1. n ^{+ in} n-channel transistor
The source region 6, and therefore the inter-element wiring 9 to the ground side power supply level (= V _SS ) supply line, and the p ⁺ -source region 16 in the p-channel transistor formed in the n-silicon semiconductor substrate 11. Therefore, the wiring 19 is connected to the positive power supply level (= V _CC ) supply line, and the gate electrode 4 in the n-channel transistor and the gate electrode 14 in the p-channel transistor are paired respectively. Transfer gate connected to the bit line and the word line by connecting and cross-connecting the gate electrode and the inter-layer wiring 15 connected as such.
By connecting the transistor and the interlayer wiring 15, it can be operated as a CMOS type memory in SRAM.

In the above-described embodiment, the p-silicon semiconductor substrate 1 which is the first silicon semiconductor substrate and the n-silicon semiconductor substrate which is the second silicon semiconductor substrate in which the integrated circuit device is built. When performing various processes in the process after bonding 11 and 11, since the alignment marks 5 formed on the p-silicon semiconductor substrate 1 which is the first silicon semiconductor substrate are all detected by visible light, n
-The elements formed on the silicon semiconductor substrate 11 can be aligned with high accuracy as in the case where the elements are formed on the p-silicon semiconductor substrate 1, and therefore, the fine elements can be formed on the n-silicon semiconductor substrate 11. Can be easily formed.

Further, in the case of stacking three or more layers, it is realized by simply repeating the above-mentioned second layer forming step, and in that case also, as described above, the alignment during the various processes is performed. In addition, high accuracy can be realized by using the alignment mark 5 formed on the p-silicon semiconductor substrate 1.

By the way, in the embodiment described above, the SiO ₂ film 1 existing in the scribe line region is used.
1, the SiO ₂ film 10, the PSG film 8 and the like are anisotropically etched to expose the alignment mark 5, but there is a case where such a step may not be necessary.

The reason is that an insulating film used in a usual integrated circuit device, for example, a SiO ₂ film, a Si ₃ N ₄ film,
If the PSG film or the like is used, the alignment mark 5 can be detected through them. For that purpose, the material of the alignment mark 5 is made different from that of a general insulating film in an integrated circuit device, and in particular, in the case of a translucent substance, the refractive index is different so that its shape is changed. It is preferable that it can be easily detected. Here, in addition to the alignment mark, when manufacturing a three-dimensional integrated circuit device, the integrated circuit device of the first layer is manufactured as the alignment mark regardless of the number of stacked semiconductor substrates. It is indispensable for forming a fine element that the one provided at that time is used to the end.
Therefore, if the alignment mark is formed in the scribe line region as in the above embodiment, the detection is always easy, but it is not essential to form the alignment mark in the scribe line region. If it is an integrated circuit device having a plurality of blocks in which a required number of elements are put together in a chip, it may be formed in a space between the element blocks. In that case, in order to apply the technique of the above-mentioned embodiment, a recess such as a groove or a void is formed at a position where the alignment mark can be seen in the semiconductor substrate which is bonded and serves as an upper layer. , The one in which the recess is filled with an insulating film made of a material different from that of the alignment mark is used, or the insulating film which covers the alignment mark can be selectively and easily removed. preferable.

As described above, in order to form a fine element with high accuracy, even if the integrated circuit device of the second layer or the integrated circuit device of more layers is formed, the first layer is formed. Alignment marks made for the integrated circuit device of the eye must be used. Therefore, it is impossible to implement the technique of attaching two semiconductor substrates, then making an integrated circuit device on the semiconductor substrate on one side, and then making an integrated circuit device on the semiconductor substrate on the other side. Is. The reason is that the alignment mark formed when the integrated circuit device is formed on the semiconductor substrate on one side cannot be detected through the semiconductor substrate on the other side.

In each of the first embodiment and its various modifications, a recess such as a groove is formed in the second silicon semiconductor substrate to be bonded to the first silicon semiconductor substrate, and the recess is formed. Although the material used for the alignment mark is filled with an insulating material different from that of the alignment mark, a silicon semiconductor substrate having no such a recess may be used, which will be described below.

FIGS. 8 to 13 are sectional side views of an essential part of an integrated circuit device in the process steps for explaining the second embodiment of the present invention. Hereinafter, these figures will be referred to. While explaining in detail. The same symbols as those used in FIGS. 1 to 7 represent the same parts or have the same meanings. Also in this embodiment, the first silicon semiconductor substrate in which the integrated circuit device is built is the same as that shown in FIG. 1 explained in the first embodiment, and therefore its explanation is omitted.

See FIG. 8- (1) SIMOX (separation by impla)
n-silicon semiconductor, which is a second silicon semiconductor substrate with O ⁺ at a dose of 1 × 10 ¹⁷ [cm ⁻² ] and an ion acceleration energy of 40 [keV]. It is injected into the substrate 11. In this step, if necessary, the dose amount of O ⁺ is set to 1 ×.
In the range of 10 ¹⁷ [cm ⁻² ] to 1 × 10 ¹⁸ [cm ⁻² ], and the ion acceleration energy is 80 [keV] to 200.
Each can be selected within the range of [keV].

8- (2) Heat treatment is performed in an Ar atmosphere at a temperature of 1300 [° C.] and a time of 6 [hours]. Depending on this process,
A buried oxide layer 20 having a thickness of 100 nm is formed at a depth of 50 nm from the surface. 8- (3) By applying the thermal oxidation method, the SiO ₂ film 2 having a thickness of, for example, 30 [nm] is formed on the surface of the n-silicon semiconductor substrate 11.
1 is formed.

See FIG. 9 9- (1) SiO ₂ film 10 on p-silicon semiconductor substrate 1 and SiO ₂ film 21 on n-silicon semiconductor substrate 11
Are opposed to each other and adhered to each other, and the substrates are bonded by heating in a nitrogen (N ₂ ) atmosphere at a temperature of 900 ° C., for example. In this case, p-silicon semiconductor substrate 1 and n
-Regarding the alignment with the silicon semiconductor substrate 11, a rough alignment of the facets is sufficient.

See FIG. 10 10- (1) For example, by applying a selective polishing method using colloidal silica as an etchant, the n-silicon semiconductor substrate 11 is thinned from the back surface side. Here, as the thinning of the n-silicon semiconductor substrate 11 progresses, the buried oxide layer 20 is formed.
Is displayed, the selective polishing is substantially stopped.

10- (2) The buried oxide layer 20 is formed by applying a chemical wet etching method using hydrofluoric acid as an etchant.
Is removed by etching. Here, the hydrofluoric acid used as the etchant etches SiO ₂ , but it is difficult to etch silicon.
When the silicon semiconductor substrate 11 is exposed, the etching is almost stopped.

After this step, a thickness of 35 [nm] is formed on the integrated circuit device built in the p-silicon semiconductor substrate 1 through the insulating film such as the SiO ₂ film 10 and the SiO ₂ film 21.
The silicon film of No. 1 is formed, which will also be referred to as n-silicon semiconductor substrate 11.

See FIG. 11 11- (1) The resist process in the lithography technique and the etching gas are CCl ₄ / O ₂ (for silicon) and C
RIE with F ₄ / CHF ₃ (for SiO ₂ and PSG)
By applying the method, the n-silicon semiconductor substrate 11, the SiO ₂ film 21 and the S in the scribe line region are formed.
The iO ₂ film 10, the PSG film 8 and the gate insulating film 3 are anisotropically etched and removed to expose the alignment mark 5 made of polycrystalline silicon.

As for the alignment of patterning in the resist process when performing this etching, rough alignment using infrared rays is sufficient because the width of the scribe line region is 80 [μm]. Needless to say, visible light may be used for alignment in the subsequent steps.

11- (2) By applying the resist process in the lithography technique and the RIE method in which the etching gas is CCl ₄ / O ₂ , the thinned n-silicon semiconductor substrate 11 is mesa-shaped. Etching is performed to separate the insulation. 11- (3) A gate insulating film 13 made of SiO ₂ and having a thickness of 25 nm is formed by applying a thermal oxidation method with a temperature of 900 ° C., for example.

See FIG. 12 12- (1) By applying the resist process in the lithography technique and the RIE method using CF ₄ / CHF ₃ as an etching gas, the SiO ₂ film 21, the SiO ₂ film 10,
The PSG film 8 and the gate insulating film 3 are anisotropically etched to form an electrode contact hole corresponding to the n ⁺ -drain region 7. 12- (2) By applying the CVD method, the thickness is, for example, 300 [n
m] W polycide film is formed.

12- (3) The W polycide film formed in step 12- (2) above is applied by applying the resist process in the lithography technique and the RIE method in which the etching gas is CCl ₄ / O _2. Patterning is performed to form an interlayer wiring 15 that connects the gate electrode 14 and the n ⁺ -drain region 7 formed on the p-silicon semiconductor substrate 1 to the p ⁺ -drain region formed on the n-silicon semiconductor substrate 11 later. Form. 12- (4) By applying the ion implantation method, the dose amount is set to, for example, 1 × 10 ¹⁵ [cm ⁻² ], and the ion acceleration energy is set to 15 [keV] to implant B ⁺ and p ⁺ Form the source region 16 and the p ⁺ -drain region 17.

See FIG. 13 13- (1) By applying the CVD method, the thickness is, for example, 600 [n
m] PSG film 18 is formed. 13- (2) 900 [° C.] and 30 hours in N ₂ atmosphere
Annealing for [minutes] is performed to smooth the PSG film 18. 13- (3) The n-silicon semiconductor substrate 11 is selectively etched by applying the resist process in the lithography technique and the RIE method using CF ₄ / CHF ₃ as the etching gas to selectively etch the PSG film 18. Then, an electrode contact hole corresponding to the p ⁺ − source region 16 formed in step 1 is formed.

13- (4) By applying the sputtering method, the thickness, for example, 1
An Al film of [μm] is formed, and then a resist process and etching gas in the lithographic technique are changed to C
By applying the RIE method with l ₂ / BCl ₃
The wiring 19 is formed by patterning the Al film. Also in the second embodiment described above, in order to stack three or more layers, the formation process of the second layer may be repeated. Although silicon is used as the semiconductor material in any of the above-described embodiments, the present invention can be implemented when other semiconductor materials are used.

[0058]

In the method for manufacturing a three-dimensional integrated circuit device according to the present invention, the alignment mark made of a material different from the usual insulating film is formed in the space between the element groups in which the integrated circuit device is formed. An insulating film is deposited on the formed first semiconductor substrate and then flattened, and the second semiconductor substrate having a flat insulating film on the surface and the first semiconductor substrate are adhered so that the insulating films face each other. Bonding, stopping at the stage where the insulating film is exposed by thinning from the back surface of the second semiconductor substrate, detecting the alignment mark and aligning with the integrated circuit device formed on the first semiconductor substrate. The integrated circuit device is built into the thinned second semiconductor substrate.

According to the above configuration, when an integrated circuit device is built on a semiconductor substrate of a second layer or more, the integrated circuit device is always built on the semiconductor substrate of the first layer regardless of the number of stacked semiconductor substrates. Since the alignment can be performed using the alignment mark formed at that time, the alignment accuracy is exactly the same as that in the normal integrated circuit device manufacturing process. As described above, a large alignment margin is unnecessary, and since the semiconductor substrate of the second layer or more can be formed to have the minimum thickness for forming an element, the etching amount in patterning is small and the step difference is formed. Due to their small size, fine elements, electrodes, wirings, etc. can be highly three-dimensionally highly integrated.

Further, the alignment mark formed on the semiconductor substrate of the first layer can be accurately detected regardless of whether it is exposed or not, and is therefore commonly used in integrated circuit devices. Even if it is covered with an insulating film, it can be detected. Furthermore, even if the number of stacked semiconductor substrates is increased, there is no possibility that the crystallinity of the semiconductor will be deteriorated, and the productivity is higher than that of annealing using an energy beam. You can enjoy many similar benefits.

[Brief description of drawings]

FIG. 1 is a side sectional view of an essential part of an integrated circuit device in a process key point for explaining a first embodiment.

FIG. 2 is a side sectional view of a main part of an integrated circuit device at a process key point for explaining a first embodiment.

FIG. 3 is a side sectional view of a main part of an integrated circuit device in a process key part for explaining a first embodiment.

FIG. 4 is a side sectional view of a main part of an integrated circuit device at a process key point for explaining a first embodiment.

FIG. 5 is a side sectional view of a main part of an integrated circuit device at a process key point for explaining a first embodiment.

FIG. 6 is a side sectional view of an essential part of the integrated circuit device in a process key point for explaining the first embodiment.

FIG. 7 is a side sectional view of a main part of an integrated circuit device in a process main part for explaining a first embodiment.

FIG. 8 is a cutaway side view of an essential part of an integrated circuit device at a process key point for explaining a second embodiment.

FIG. 9 is a sectional side view of a main part of an integrated circuit device at a process key point for explaining a second embodiment.

FIG. 10 is a cutaway side view of a main part of an integrated circuit device in a process main part for explaining a second embodiment.

FIG. 11 is a cutaway side view of an essential part of the integrated circuit device at a process key point for explaining the second embodiment.

FIG. 12 is a side sectional view of a main part of an integrated circuit device in a process main part for explaining a second embodiment.

FIG. 13 is a side sectional view of a main part of an integrated circuit device in a process main part for explaining a second embodiment.

[Explanation of symbols]

1 p-silicon semiconductor substrate 2 field insulating film 3 gate insulating film 4 gate electrode 5 alignment mark 6 n ⁺ -source region 7 n ⁺ -drain region 8 PSG film 9 inter-element wiring 10 SiO ₂ film 11 n-silicon semiconductor substrate 11A groove 12 SiO ₂ film 13 gate insulating film 14 gate electrode 15 interlayer wiring 16 p ⁺ − source region 17 p ⁺ − drain region 18 PSG film 19 wiring 20 embedded oxide layer 21 SiO ₂ film

Claims (6)

[Claims] 1. An insulating film is formed on a first semiconductor substrate in which an integrated circuit device is formed and alignment marks made of a material different from a normal insulating film used in the integrated circuit device are formed in a space between element groups. A step of depositing a film and then flattening it, and then forming a recess such as a groove in the surface at a position corresponding to the void and filling it with an insulating film, and then flattening the insulating film A step of closely bonding the substrate and the first semiconductor substrate so that the respective insulating films face each other, and then insulating the second semiconductor substrate from the back surface by thinning it to fill the recesses. A step of stopping when the film is exposed, and then detecting the alignment mark to align with the integrated circuit device formed on the first semiconductor substrate, and then the second thinned film Integrated circuit device on the semiconductor substrate Method for producing a three-dimensional integrated circuit device characterized by comprising contains the steps to fabricate a. 2. A step of exposing the alignment mark by selectively removing each insulating film laminated covering the void after thinning the second semiconductor substrate. The method for manufacturing a three-dimensional integrated circuit device according to claim 1, wherein 3. An insulating film is formed on a first semiconductor substrate in which an integrated circuit device is formed, and alignment marks made of a material different from a normal insulating film used in the integrated circuit device are formed in a space between element groups. A step of depositing a film and then planarizing it, and a second semiconductor substrate having a buried insulating layer on a surface of a required depth from the surface and having a flat insulating film on the surface, and the first semiconductor substrate. A step of adhering each of them so that their respective insulating films are opposed to each other, and a step of performing thinning from the back surface of the second semiconductor substrate and stopping when the embedded oxide layer is exposed; A step of exposing the thinned second semiconductor substrate by removing the buried oxide layer, and a step of detecting the alignment mark and an integrated circuit device formed on the first semiconductor substrate. Position And then forming an integrated circuit device on the thinned second semiconductor substrate. 4. The alignment mark is exposed by thinning the second semiconductor substrate and then selectively removing each insulating film and the second semiconductor substrate laminated to cover the void. 4. The method according to claim 3, characterized in that the step of causing is included.
A method for manufacturing the three-dimensional integrated circuit device described. 5. An insulating film is deposited on a first semiconductor substrate, wherein the element group is a block in which a plurality of required elements are formed, and the void is a line region for separating each block independently. The method for manufacturing a three-dimensional integrated circuit device according to claim 1, 2, 3 or 4, further comprising a step of flattening. 6. A step of depositing an insulating film on a first semiconductor substrate, which is a scribe line region in which the element group constitutes one chip and the cavities independently separate each chip, and then planarizes. The method for manufacturing a three-dimensional integrated circuit device according to claim 1, 2, 3, or 4, further comprising: