JPH05225358A - Input/output circuit for microcomputer - Google Patents

Abstract

PURPOSE:To effectively utilize a memory area in a memory by switching the same address signal by a switching means and controlling the 1st or 2nd control storage means. CONSTITUTION:A direction register 3 to be the 1st control storage means and a pull-up resistor control register 4 to be the 2nd control storage means are set up so as to be controlled by the same address signal. Namely a two-input AND circuit 11 is activated when the output, inverted Q, of a toggle circuit 10 is '1' and sends an address signal sent from a CPU through an address bus to the register 4. A two-input AND circuit 12 is activated when the output Q of the circuit 10 is '1' and sends the address signal to the register 3. Outputs from the circuits 11, 12 are delayed by a delay circuit 13, a trigger signal is sent to the circuit 10, and when an output signal from the circuit 13 is inputted to the input T of the circuit 10, the circuit 10 inverts its output.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an input / output circuit of a one-chip microcomputer, and more particularly to an input / output circuit of a microcomputer capable of effectively utilizing an address space.

[0002]

2. Description of the Related Art FIG. 3 is a circuit diagram of an input / output circuit of a conventional microcomputer. In the figure, 1 is a data bus, 2 is an address signal An + 1, and
To the output latch for storing the content of the data from the data bus 1, the direction register for storing the content of the data from the data bus 1 by the address signal An + 1, and the pull register 4 for storing the content of the data from the data bus 1 by the address signal Nn. An up resistance control register, 5 is an output buffer that outputs the data latched in the output latch 2 to the input / output terminal 6 in accordance with the input / output mode signal from the direction register 3, and 7 is an input / output mode signal from the direction register 3. An input buffer for transferring the data of the input / output terminal 6 to the data bus 1, 8 is a resistor connected to the input / output terminal 6 and the P-channel transistor 9, and 9 is an output of the pull-up resistor control register 4, and the resistor 8 is supplied to the power source. P-channel transistor to be connected.

FIG. 4 is a diagram showing a memory layout of addresses corresponding to the output latch 2, the direction register 3, and the pull-up resistance control register 4 in the input / output circuit of FIG. The memory arrangement in the figure is such that the address signal of the port P0 pull-up resistance control register is address An, the address signal of the port P0 direction register is An + 1, the address signal of the port P0 output latch is An + 2, and the address signal of the port P1 pull-up resistance control register. Is placed at An + 3, the address signal of the port P1 direction register is placed at An + 4, and the address signal of the port P1 output latch is placed at address An + 5, and these addresses are all non-overlapping.

Next, the operation will be described. Whether the input / output circuit of the microcomputer is used as the input mode or the output mode is determined by the input / output signal latched in the direction register 3. The input / output circuit of the port P0 will be described. Direction register 3
In order to write the data of the input / output mode signal to the central processing unit (not shown), the central processing unit (not shown) sends the address signal An + 1 of the port P0 direction register shown in FIG. 4 to the address bus (not shown).
To the direction register 3 by sending an input / output mode signal specifying the input / output mode via the data bus 1. At this time, when the content of the input / output mode signal of the direction register 3 is "0", it is in the input mode, and when the content of the input mode signal is "1", it is in the output mode. That is, when the content of the direction register 3 is “0”, the input buffer 7 becomes active and the data from the input / output terminal 6 is transferred to the data bus 1. Next, in the output mode, that is, when the content of the direction register 3 is "1", the output buffer 5 becomes active. At this time, the central processing unit sends the address An + 2 of the port P0 output latch shown in FIG. 4 to the output latch 2 via the address bus, sends the data to the data bus 1 and stores the data in the output latch 2. The data stored in the output latch 2 is transferred to the input / output terminal 6 via the output buffer 5.

Next, the pull-up resistor control register 4 controls whether or not the pull-up resistor is connected to the input terminal 6.
Is determined by the pull-up resistance control signal stored in. In order to write the data of the pull-up resistance control signal to the pull-up resistance control register 4, the central processing unit sends the address signal An of the address of the port P0 pull-up resistance control register shown in FIG. A pull-up resistance control signal for designating the presence / absence of a pull-up resistance is sent via it to write it in the pull-up resistance control register 4. At this time, when the content of the pull-up resistance control signal of the pull-up resistance control register 4 is "0", there is a pull-up resistance, and when it is "1", there is no pull-up resistance. When the pull-up resistor is present, that is, when the content of the pull-up resistor control register 4 is "0", the P-channel transistor 9 is turned on, and the resistor 8 is connected to the power supply via the P-channel transistor 9. Also, there is no pull-up resistor, that is,
When the content of the pull-up resistance control register 4 is “1”,
The P-channel transistor 9 is turned off and the resistor 8 is not connected to the power supply.

[0006]

Since the input / output circuit of the conventional microcomputer is constructed as described above, in the system to which the microcomputer is applied, the input / output is frequently switched and the presence / absence of the pull-up resistor is switched. Despite being rarely used, at least two memory areas for direction register 3, pull-up resistance control register 4 and output latch 2 were needed to control one port. Also, since the I / O control register, RAM, etc. are frequently accessed, it is necessary to place them in a special address area that can be accessed in a short execution cycle. Due to the increased number of I / O ports and higher functionality, the I / O control register, etc. Therefore, there is a problem that the RAM area arranged in the same memory area is limited.

The present invention has been made in order to solve the above-mentioned problems, and it is possible to efficiently utilize the limited accessible space in a short execution cycle of the entire address space and to reduce the number of input / output control registers and the like. The purpose is to obtain an input / output circuit of a microcomputer capable of controlling many ports in a memory area of a memory.

[0008]

An input / output circuit of a microcomputer according to the present invention comprises an input buffer for transferring data from a data bus to an input / output terminal under the control of a central processing unit, and an input / output terminal for inputting / outputting data from the data bus. An output buffer for transferring data, a first control storage means controlled by an address signal, latching an input / output signal from a data bus and controlling the input buffer or the output buffer according to an input / output mode signal, and the same as the address signal Second control storage means for controlling the resistance connected between the input / output terminal and the power supply by controlling the address signal of the central processing unit, and receiving the address signal from the central processing unit. The first control storage means or the second
And switching means for sending and controlling to the control means.

[0009]

Since the input / output circuit of the microcomputer according to the present invention controls the first or second control storage means by switching the same address signal by the switching means, the memory to which the address of the address signal is assigned. The memory area of can be used effectively.

[0010]

【Example】

Example 1. Embodiment 1 of the present invention will be described below with reference to the drawings. In FIG. 1, 1 to 9 are the same as the conventional ones, and thus the description thereof is omitted. 10 is a toggle circuit which is reset by a reset signal and whose output is inverted by the signal of the delay circuit 13, 11 is a 2-input AND circuit which inputs the address signal and the output of the toggle circuit 10, and 12 is the address signal and the output of the toggle circuit 10. 2-input AND circuit for input, 13 is 2-input AND circuit 11, 12
The delay circuit delays the (address signal An). The switching means 20 is configured by the above 10 to 13. The output of the 2-input AND circuit 11 is the pull-up control register 4 and the delay circuit.
The input T of the toggle circuit 10 is connected through 13, one end of the input of the two-input AND circuit 11 is connected to the output Q (inversion) of the toggle circuit 10, and the other end of this circuit is connected to the address bus. .. The output of the 2-input AND circuit 12 is connected to the output T of the toggle circuit 10 via the output latch 3 and the delay circuit 13, and one end of the 2-input AND circuit 12 has an output Q of the toggle circuit 10.
The other end of this circuit is connected to the address bus together with the other end of the 2-input AND circuit 11. A reset signal is connected to the input R of the toggle circuit 10.

The direction register 3 as the first control storage means has the same function as the conventional one, and activates the output buffer 5 and the input buffer 7 in accordance with the input mode signal.
The pull-up resistance control register 4 as the second control storage means has a function similar to that of the conventional one, and the resistance 8 connected to the input / output terminal 6 is connected to the pull-up resistance control signal in accordance with the pull-up resistance control signal.
It controls the channel transistor 9 and controls whether or not the resistor 8 is connected to the power supply via the P-channel transistor 9. Direction register 3 and pull-up resistance control register 4
Are controlled by the same address signal. The direction register 3 and the pull-up resistance control register 4 are set to be controlled by the same address signal. 2-input AND circuit 11
Is active when the output Q (inversion) of the toggle circuit 10 is "1" and sends the address signal sent from the central processing unit via the address bus to the pull-up control register 4. The 2-input AND circuit 12 becomes active when the output Q of the toggle circuit 10 is "1", and sends an address signal to the direction register 3. The delay circuit 13 delays the outputs of the two-input AND circuits 11 and 12 for a predetermined time and
Send a trigger signal to 10. When the reset signal is input to the input R, the toggle circuit 10 sets the output Q to "0" and the output Q.
(Inversion) is set to "1" and the output signal from the delay circuit 13 is
When it is input to the input T, the output is inverted.

In the memory arrangement of FIG. 2, the pull-up resistance control register and the direction register of the port P0 are designated by one address An, and the pull-up resistance control register and the direction register of the port P1 are designated by one address An. Is shown.

Next, the operation will be described. When the microcomputer is reset, the reset signal is input to the input R of the toggle circuit 10 by the reset signal, the output Q (inversion) of the toggle circuit 10 becomes "1", and the output Q becomes "0". The input of the input AND circuit 11 becomes active. The central processing unit executes a mode setting program for setting the presence or absence of a pull-up resistor. For example, when the port P0 has a pull-up resistor, the address An of the pull-up resistor control register of the port P0 is set to 2 from the address bus. The pull-up resistance control register 4 is supplied via the input AND circuit 11 to store the pull-up resistance control signal (for example, "0") sent via the data bus 1. The pull-up resistance control register 4 turns on the P-channel transistor 9 according to the pull-up resistance control signal “0”, and connects the resistor 8 to the power supply via the P-channel transistor 0. The signal of the address given to the pull-up resistance control register 4 is delayed by the delay circuit 13 for a predetermined time, input to the input T of the toggle circuit 10, and the toggle circuit 13 is inverted. As a result, the output Q (inversion) of the toggle circuit 10 becomes "0", the output Q becomes "1", and the input of the 2-input AND circuit 12 becomes active this time.

Next, the central processing unit executes a program for setting the input mode. For example, when the port P0 is set to the input mode, the address signal An of the direction register of the port P0 (identical to the pull-up resistance control register). 2) AND circuit 12 from the address bus)
The input mode signal (for example, "0") sent to the direction register 3 via the data bus 1 is latched. The direction register 3 activates the input buffer 7 according to the input mode signal “0” and transfers data from the input / output terminal 6 to the data bus 1. The signal of the address given to the direction register 3 is delayed by the delay circuit 13 for a predetermined time, input to the input T of the toggle circuit 10, and the output of the toggle circuit 10 is inverted. As a result, the output Q (inversion) of the toggle circuit 10 becomes "1", the output Q becomes "0", and the 2-input AND circuit 11 becomes active again. In this way
Two-input AND circuit even though the address of the direction register 3 and the pull-up resistance control register 4 are the same.
Since the 11 and 2 input AND circuits 12 are alternately activated, there is no fear of confusion, and the address signals of the direction register 3 and the pull-up resistance control register 4 can be shared as one address in the memory area.

[0015]

As described above, according to the present invention, an input buffer for transferring data from the data bus to the input / output terminal under the control of the central processing unit, and an output buffer for transferring data from the data bus to the input / output terminal. A first control storage means for controlling an input buffer or an output buffer according to an input / output mode signal by latching an input / output signal from a data bus controlled by an address signal, and controlled by the same address signal as the address signal, Second control storage means for latching data from the data bus to control a resistor connected between the input / output terminal and the power supply; and an address signal when the address signal is received from the central processing unit. Alternatively, since the switching means for sending and controlling to the second control means is provided, the access can be performed in a short execution cycle assigned to the control storage means. Kill the memory space of the memory can be utilized efficiently, the memory area of the memory, such as a small output resistance control register, there is an effect that it is possible to control the number of ports.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an input / output circuit according to a first embodiment of the present invention.

FIG. 2 is a memory layout diagram of addresses according to the first embodiment of the present invention.

FIG. 3 is a circuit diagram showing a conventional input / output circuit.

FIG. 4 is a memory layout diagram of addresses of a conventional input / output circuit.

[Explanation of symbols]

 1 data bus 2 output latch 3 direction register 4 pull-up resistance control register 5 output buffer 6 input terminal 7 input buffer 8 resistance 9 P-channel transistor 10 toggle circuit 11 2 input AND circuit 12 2 input AND circuit 13 delay circuit 20 switching means

Claims (1)

[Claims] 1. An input buffer for transferring data from a data bus to an input / output terminal under the control of a central processing unit, an output buffer for transferring data from the data bus to the input / output terminal, and a data bus controlled by an address signal Of the input / output signal of (1) to control the input buffer or the output buffer according to the input / output mode signal, and the data from the data bus controlled by the same address signal as the address signal. Second control storage means for latching and controlling a resistor connected between the input / output terminal and the power supply; and an address signal received from the central processing unit, the address signal is stored in the first control storage means or the first control storage means. An input / output circuit of a microcomputer, comprising: a switching means for sending and controlling the second control storage means.