JPH052239B2 - - Google Patents

Description

[Detailed description of the invention]

"Industrial Application Field" The present invention relates to a display controller used in a color display device or the like controlled by a CPU (Central Processing Unit). "Prior Art" Generally, when displaying images on a CPU-controlled color display device,
A color code is stored in VRAM (video RAM) corresponding to the display dot, and this color code is read out and determined by a color lookup table (hereinafter referred to as LUT) to display R (red), G (green), and B. (blue) color data, and further converts this color data into R, G, B color signals (analog signals) and sends them to the CRT along with the synchronization signal.
Output to color display device. ``Problem to be solved by the invention'' By the way, conventional color display devices of this type simply change the VRAM color code to R, G,
It only converts to a B color signal and displays it, so the degree of display freedom is low, and the CPU has to rewrite the data in VRAM every time the image is changed, so it has the disadvantage of placing a heavy burden on the CPU. It was hot. This invention has been made in view of the above-mentioned circumstances, and an object of the present invention is to provide a display controller that can display a wider variety of images than ever before, and can also reduce the CPU load compared to before. "Means for Solving the Problem" A display controller according to the present invention includes a storage means in which color data and display modification data corresponding to display dots are stored, and a storage means that synchronizes the color data and display modification data from the storage means with a dot clock. a readout means for sequentially reading out color data read by the readout means when the display modification data read by the readout means is specific data; a modifying means for performing arithmetic processing using the color data of a dot to be displayed one dot clock timing before the dot that has been displayed, and outputting the result of the arithmetic processing as display-modified color data; It is characterized by comprising a digital/analog converter that converts the color data to be output into an analog signal and outputs the signal to a color display device. "Embodiment" Hereinafter, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the configuration of a color display device with dot display using a display controller 1 according to an embodiment of the present invention. This display device will be described in detail below. (1) General configuration In Fig. 1, 2 is a CPU, 3 is a memory consisting of a ROM that stores programs used by the CPU 2, and a RAM for data storage, 4 is a video display processor (hereinafter referred to as VDP), 5 is VRAM. VDP4 is CPU2
The color code supplied via the bus line 6 is written into the VRAM5, the written color code is read out, and the dot data DD7-
It is sequentially output to the display controller 1 as 0 (8 bits). In addition, this VDP4 has a synchronization signal
It outputs SYN.I, blanking signal BLANK, display timing signal DTMG, page select signal PG-SEL and dot clock DCLK to the display controller 1, respectively. Here, the synchronization signal SYN・I is a signal for synchronizing the display on the CRT display device, and a blanking signal.
BLANK is a signal that is "1" during the screen display period and "0" during other periods, and the display timing signal DTMG is a signal that is "1" during the image display period and "0" during other periods. Note that the screen display period and the image display period are different. That is, the display screen is divided into an image display area and a border area, the image is displayed only in the image display area, and the border area is displayed in one color. The image display period is a period during which the image display area is scanned, and the screen display period is a period during which the screen (image display area and border area) is scanned. In addition, the page select signal PG-SEL is a signal that repeats "1" for 0.5 seconds and "0" for 0.5 seconds, for example.
The dot clock DCLK is a signal indicating the timing of displaying each dot on the display screen. The interface circuit 7 is a circuit for connecting the CPU 2 and the display controller 1. The display controller 1 receives dot data DD7 supplied from the VDP4.
-0 into R, G, B color data, and then convert these color data into red color signals RS,
Green color signal GS, blue color signal BS
(both are analog signals) and output to the CRT display device 8. Also, this display controller 1
outputs the signal YS and the synchronizing signals SYN and O to the CRT display device 8. Note that in this controller 1, the terminal T1 is directly connected to the data bus of the CPU 2. The CRT display device 8 is a color display device that has the function of a television receiver, and the CRT display device 8 is a color display device that has the function of a television receiver.
When is “1”, the red color signal RS, green color signal GS,
Color display is performed based on the blue color signal BS and synchronization signals SYN/O, and when the signal YS is "0", display is performed using the television signal. (2) Detailed configuration of display controller 1 FIGS. 2 to 4 are circuit diagrams each showing a detailed configuration of display controller 1. This display controller 1 can be roughly divided into a control section shown in FIG.
It is divided into a RAM address forming section shown in FIG. 3, and a dual port RAM 11 and color data conversion circuits 12r, 12g, and 12b shown in FIG. The configuration of each part will be explained below. Note that the operation of each part will be explained in detail later. (2-1) Control unit; FIG. 2 This control unit is a circuit that mainly controls data exchange between the CPU 2 and the display controller 1. In the figure, 17 is a 3-bit register, which reads input data based on the dot clock DCLK supplied to its load terminal L, and outputs it from its output terminal. This register 17 is a register for synchronization. That is, the clock pulse of the CPU 2 and the dot clock DCLK output from the VDP 4 are not synchronized. Therefore, for signals and data synchronized with the clock pulse of CPU2, the dot clock DCLK
signals and data that are synchronized with Register 17 is provided for this purpose. Also, shown below the same register 17
A DFF (D-type flip-flop) 18 is also provided for this purpose. pointer counter 19
is a 4-bit up counter that counts up the signal supplied to its up terminal UP,
Also, when a signal is supplied to the load terminal L, the data
Load WD3-0. In addition, data WD3-0
are the lower 4 outputs of the register 60 shown at the bottom of the figure.
It's bit. The write decoder 20 decodes the output of the pointer counter 19, becomes enabled only when the write strobe WRST is supplied to its enable terminal EN, and outputs the decoding result as strobe signals $MW, . . . Similarly, the read decoder 21 decodes the output of the pointer counter 19 and outputs the decoded result as a strobe signal $MR only when the read strobe RDST is supplied. 21,
22 is a buffer, and “1” is sent to its control terminal C.
When a signal is supplied, the input data is output as is from the output terminal, and when a "0" signal is supplied, the output terminal becomes a high impedance state. Also,
The line connecting buffer 27 and terminal T1 is 8.
This is a bit-directional bus. When the signal CS is supplied to the load terminal L of the register 60, the register 60 reads data obtained from the terminal T1, that is, the data bus of the CPU 2, and outputs the data to the register 24. Register 24 is a light strobe
When WRST is supplied, the output data of the register 23 is read and output as data WDB7-0. The mode register 25 is a 6-bit register that reads data WDB5-0 (lower 6 bits of data WDB7-0) when the strobe signal $MD is supplied. (2-2) RAM address forming unit: Figure 3 This RAM address forming unit includes a block B1 that converts dot data (color code) DD7-0 to new dot data DDa7-0,
Address data RWA7-0 (8 bits) and
Block B2 forming BA1-0 (2 bits)
Each data is divided into dual ports.
Address terminals AT2, AT of RAM11 (Figure 4)
1. In block B1, 30 and 31 are each 4-bit page registers, and 32 is a multiplexer. This multiplexer 32 outputs the data at the input terminal <1> when a "1" signal is supplied to its control terminal C, and when a "0" signal is supplied,
Outputs the data at input terminal <0>. 33 is a synchronization register, 34 is a 4-bit page mass register, 35 is a synchronization register, and 36 to 39 are multiplexers. Also, in block B2,
41 is a synchronization register, 42 is a multiplexer,
43 is a word counter, and 44 is a byte counter. These counters 43 and 44 each output data WDB7- when a signal is supplied to the load terminal L.
0, WDB1-0 is read, and when a “1” signal is supplied to the enable terminal EN,
Counts up the signal of the up terminal UP. In addition, the carryout signal of the byte counter 44
CO is supplied to the input end of OR gate 45. (2-3) Dual port RAM 11; Figure 4 This dual port RAM 11 is a LUT that converts color codes into color data, and is 1024
It consists of a byte RAM 11a and peripheral circuits. FIG. 5 is a diagram showing the configuration of the RAM 11a, and addresses 0 to 3 of this RAM 11a each have
R, G, B color data and attribute bits (8 bits each) corresponding to color code "0" are stored, and R, G, B colors corresponding to each color code "1" are stored in addresses 4 to 7. Data and attribute bits are stored, ..., 1020 ~
At address 1023, R, G, and B color data and attribute bits each corresponding to the color code "255" are stored. Then, based on the dot data DDa7-0 (color code) supplied to the address terminal AT2 of the dual port RAM 11, the corresponding R, G, B color data and attribute bits are read out, and the R, G, B
Color data is output as color data RD7-0, GD7-0, BD7-0 from output terminals Q2 to Q4, respectively, and attribute bits are output from output terminal Q5. In this case, the seventh and sixth attribute bits are output as attribute data AD7 and AD6. In addition,
Bits 5 to 0 of the attribute bits are not used in this embodiment. Further, the function of the attribute bit will be explained later. In this way, the dual port shown in Figure 4
When dot data DDa7-0 is applied to the address terminal AT2, the RAM11 responds to R, G,
B color data and attribute bits are read out, but completely independent of this readout,
Writing/reading of the RAM 11a can be performed in byte units. That is, by applying address data (10 bits) to the address terminal AT1 of this dual port RAM 11, applying 8-bit data to the data terminal WDT, and applying a pulse signal to the write terminal WT, writing to the RAM 11a can be performed. done,
Furthermore, by applying address data to the address terminal AT1 and applying a pulse signal to the read terminal RT, data within the address indicated by the address data is read out and output from the output terminal Q1. Address data RWA7-0 and
BA1-0 is data that specifies the address for reading/writing as described above, and address data RWA7-0 is the upper 8 of the address terminal AT1.
Address data BA1-0 is applied to the lower two bits, respectively. (2-4) Color data modification circuit 12r, 12g,
12b; FIG. 4 These color data modification circuits 12r to 12b have the same configuration, and color data RD7
-0, GD7-0, BD7-0 are modified according to the attribute signal AS, then this modification data is converted to an analog signal, and the color signals RS,
Output as GS, BGS. The attribute bit signal AS is the attribute data AD.
7 is delayed by one dot clock timing (hereinafter simply referred to as timing) by the register 46. Next, in the color data modification circuit 12r,
47r is a register that outputs color data RD7-0 with one timing delay, and 48r is the above signal.
Multiplexer controlled by AS, 49r
is an adder circuit, and 50r is a border register into which color data for determining the color of the border area is written. 51r is a multiplexer, 52r is a register that delays the output of the multiplexer 51r by one timing, 53r is a buffer, and 54 is a gate circuit. This gate circuit 54r has a control terminal C
When a "1" signal is applied to the gate, the gate is open, and when a "0" signal is applied, the gate is closed. 55r is a DAC (digital/analog converter), and this DAC
55r is output as a color signal RS via an amplifier 56r. (3) Operation of display controller 1 (3-1) Operation during writing by CPU 2 Prior to display processing, CPU 2 controls each register and dual port in display controller 1.
Write data to RAM11. During this writing, a strobe signal is output from the write decoder 20 (FIG. 2). Further, a register number is assigned to each register. The relationship between the register number, the strobe signal, the register to which writing is performed, etc. is as follows. 0 $MW...Dual port RAM 11 1 $MD...Mode register 25 (Fig. 2) 2 $WA...Word counter 43 (Fig. 3) 3 $BA...Byte counter 44 (Fig. 3) 4 $WA ...Bage mass register 34 (3rd
(Figure) 5 $P0...Page register 30 (Figure 3) 6 $P1...Page register 31 (Figure 3) 7 $BR...Border register 50r (Figure 4) 8 $BG...Border register 50g (Figure) (Fig. 4) 9 $BB...Border register 50b (Fig. 4) Next, the operation at the time of writing will be explained. Note that two addresses are assigned to the interface 7 (FIG. 1) as port addresses. below,
These addresses are used as port addresses PA0 and PA1
shall be. (i) Register individual write operation This operation is performed by registers 25, 43,...
This is an operation when writing data to any one of the 50b. In this case, the CPU 2 first outputs the port address PA0 to the bus, then outputs the register number to the data bus, and then outputs a write pulse (hereinafter referred to as the first process). When port address PA0 is output, interface 7 detects this and outputs “0” as signal AO.
Output. Next, when the write pulse is output, the interface 7 outputs the read/write signal.
It outputs "1" as WR and also outputs a pulse signal CS at the same timing as the write pulse.
When the pulse signal CS is output from the interface 7, this signal CS is sent to the register 60 (Fig. 2).
As a result, the register number on the data bus is read into the register 60 and supplied to the input terminal of the pointer counter 19. On the other hand, when the signal AO becomes "0" and the signal WR becomes "1", the AND gate 61 (FIG. 2) becomes open, and the pulse signal CS passes through the AND gate 61 and the synchronization register 17 to the pointer counter 19. is applied to the load terminal L of. This results in
The register number read into the register 60 is read into the pointer counter 19 and output to the write decoder 20. Next, the CPU 2 outputs the port register PA1 to the address bus, then outputs write data to the data bus, and then outputs a write pulse (hereinafter referred to as second processing). Interface 7 receives port address PA1 and outputs signal AO.
In response to a write pulse, it outputs "1" as a read/write signal WR and outputs a pulse signal CS. When the pulse signal CS is output, data on the data bus is read into the register 60. Also, the signal
When AO and WR become “1”, AND gate 62
is in the open state, and the signal CS is the AND gate 62,
Write strobe via register 17
Output as WRST. This write strobe WRST causes the data in the register 60 to be read into the register 24, and this read data is supplied to the registers 25, 43, . . . . Also, when the write strobe WRST is output,
While this strobe WRST is being output, the write decoder 20 is enabled, and the strobe signal $MW corresponding to the output of the pointer counter 19 is output from the write decoder 20. As a result, the data in the register 24 is read into the registers 25, 43, . . . to which the same strobe signal is applied. (ii) Register continuous write operation This operation is an operation when data is continuously written into a plurality of registers 25, 43, . . . . In this case, the CPU 2 first stores the first value in the mode register 25 (FIG. 2) by the process described in (i) above.
Write data that makes the bit “1”. As a result, the signal AUT output from the same register 25
-INC becomes "1", this "1" signal is supplied to the AND gate 63 (upper left in FIG. 2), and the AND gate 63 becomes open. Next, for example, each register 34, 30 with register numbers "4" to "9"...
When writing data to 50b, the CPU 2 writes the data into the register 34 with register number "4" by performing the process (i) above. When this writing is completed, the register number "4" is held in the pointer counter 19. Next, CPU2
The second process in the process (i) above, that is, output of port address PA1, register number "5"
It outputs data to be written to the register 30 and outputs a write pulse. As a result, "1" is output from the interface 7 as the signals AO and WR, and the pulse signal CS is output.
The above data is sent to register 6 by pulse signal CS.
Reads to 0. Then light strobe
WRST is output and this light strobe
The data in register 60 is read into register 24 by WRST. Also, the write strobe WRST is sent to the pointer counter 1 via the OR gate 64, the AND gate 63, and the register 17.
As a result, the pointer counter 19 is incremented, its count output becomes "5", and this count output "5" is supplied to the write decoder 20. As a result, the strobe signal $P0 is output from the write decoder 20 at the timing of the write strobe WRST, and the data in the register 24 is transferred to the register 30 (FIG. 2) by this strobe signal $P0.
loaded within. Similarly, when the CPU 2 sequentially outputs data to be written into the registers 31, 50r, 50g, and 50b by the second process, these data are sequentially written into each register. (iii) RAM individual write operation This operation is for writing data only into any one address of the RAM 11a.
In this case, the CPU 2 first writes "0" to the fifth bit of the mode register 25. As a result, the signal DIR-RD becomes "0". When the signal DIR-RD becomes “0”, the multiplexer 42 (Fig. 3)
The data at the input terminal <0>, that is, the output data WA7-0 of the word counter 43 is output from the multiplexer 42 as data RWA7-0, and is supplied to the dual port RAM 11. Next, the CPU 2 writes the lower two bits of the address at which data is to be written in the RAM 11a to the byte counter 44, and then writes the upper eight bits to the word counter 43. As a result, the same address is set to address terminal AT of dual port RAM11.
1. Next, the CPU 2 writes "0" to the pointer counter 19 (the first process),
Next, write data is output (second process). This data is temporarily stored in the register 24 (Fig. 2).
Then, it is written into the corresponding address of RAM 11a by the strobe signal $MW. (iv) RAM write operation When writing data continuously into the dual port RAM 11, the CPU 2 first sets the 0th, 1st, and 5th bits of the mode register 25 to “0”.
Write. This allows the signal FIX−BA,AUT
-INC and DIR-RD become "0". Signal FIX−
When BA becomes “0”, inverter 66 (third
(Figure) becomes “1” and the byte counter 44
is enabled, and OR gate 45 is enabled.
is in a through state. As a result, the two counters 44 and 43 are configured into one 10-bit up counter. Further, when the signal DIR-RD becomes "0", the data at the input terminal <0> of the multiplexer 42 (FIG. 3) is output from the multiplexer 42. Next, the CPU 2 writes the lower two bits of the start address to the byte counter 44, and
Then, the upper 8 bits are written into the word counter 43. For example, when writing data to the entire area (1024 bytes) of the RAM 11a (this case will be explained below), data "0" is written to each of the counters 44 and 43. Next, the CPU 2 writes "0" to the pointer counter 19, and then writes "0" to the pointer counter 19, and then
The data to be written to address 0 of 11a is output. This data is temporarily stored in the register 24 (Fig. 1).
Then, it is written to address 0 of the RAM 11a by the stroke signal $MW. Further, the strobe signal $MW is supplied to each up terminal UP of the registers 44 and 43 via an OR gate 67 (FIG. 3). As a result, the counter 44,
43 is incremented. Below, CPU2 is RAM11
The data to be written to the first address, second address, etc. of a is sequentially outputted by the second process described above.
As a result, data is sequentially written into each address of the RAM 11a, and the above-mentioned 10-bit counter is sequentially incremented. (3-2) Operation when reading by CPU2 CPU2 has registers and dual ports.
Data in the RAM 11 can be read out at any time regardless of image display. At the time of this reading, a strobe signal $MR... is output from the read decoder 21 (FIG. 2). Furthermore, data numbers are assigned in advance to readable data. The relationship among this data number, strobe signal, and read data is as follows. 0 $MR...Data 1 in dual port RAM 11 $ST...Status data 2 $RR...Border register 52r (Figure 4)
Data 3 in $RG...Border register 52g (Figure 4)
Data 4 in $RB……Border register 52b (Figure 4)
Here, the status data refers to the signal DTMG
(Figure 2 bottom), PG-SEL (Figure 3 left),
This is data indicating each state of BLANK3 (lower part of Figure 4), and these signals are buffer 22 (Figure 2).
is applied to the input terminal of Next, the operation at the time of reading will be explained. (i) Data individual read operation This operation is for reading any one of the data numbers "1" to "4". In this case, the CPU 2 first writes the data number into the pointer counter 19 by the first process described above. Next, after outputting the port address PA1 to the address bus, a read pulse is output (hereinafter referred to as the third process). port address
When PA1 is output, the interface 7 outputs "1" as the signal AO, and when the read pulse is output, the interface 7 outputs the signal AO.
It outputs "0" as WR and also outputs a pulse signal CS at the same timing as the read pulse.
When the signal AO becomes "1" and the signal WR becomes "0", the AND gate 69 shown in FIG. 2 becomes open, and the pulse signal CS is outputted through the AND gate 69. This causes the buffer 27 to enter the through state. Further, the pulse signal that has passed through the AND gate 69 is outputted as a read strobe RDST via the synchronization DFF 18 and applied to the read decoder 21 . As a result, a strobe signal corresponding to the data number in the pointer counter 19 is output from the read decoder 21. For example, when the strobe signal $ST is output, the buffer 22 becomes a through state, and the status data is passed through the buffers 22 and 21 to the CPU.
It is output to the second data bus. For example, when the strobe signal $RR is output, the buffer 53r in FIG. 4 becomes a through state, and the register 5
The data (R color data) in 2r is output to the data bus of the CPU 2 via the buffer 53r and the buffer 27. The data output to the data bus of the CPU 2 is read into the CPU 2 at a predetermined timing. (ii) Continuous data read operation In this operation, CPU2 reads data number “1”
This is an operation when a plurality of data out of "4" data are read out consecutively. This operation is almost the same as the register continuous write operation described above,
Therefore, detailed explanation will be omitted. in this case,
The CPU 2 first writes "1" to the first bit of the mode register 25, then writes the first data number to the pointer counter 19, and thereafter repeats the third process described above. As a result, each piece of data is sequentially output to the data bus of the CPU 2. (iii) RAM data individual read operation When reading one of the data in the dual port RAM 11, the CPU 2 first writes “0” to the fifth bit of the mode register 25, and then reads the word counter 43. , writes the address of the RAM 11a into the byte counter 44 (FIG. 3). Next, data number "0" is written in the pointer counter 19, and then the third process is performed. With this third process, the read decoder 2
The strobe signal $MR is output from 1 (Fig. 2), and the lead terminal RT of dual port RAM 11 is output.
supplied to As a result, registers 73 and 44
Data within the address indicated by the output is read out and output from the output terminal Q1, and this output data is sent to the data bus of the CPU 2 via the buffer 27. (iv) RAM data continuous read operation In this case, the CPU 2 first writes “0” to the 0th, 1st, and 5th bits of the mode register 25, as in the case of the “RAM continuous write operation” described above. Next, the lower two bits of the start address are written into the byte counter 44, and the upper eight bits are written into the word counter 43. Next, write the data number "0" to the pointer counter 19, and from then on,
Repeat the third process. By repeating this third process, the strobe signal $MR is repeatedly output, and a 10-bit counter consisting of registers 43 and 44 is successively incremented by this strobe signal $MR. As a result, the data in the dual port RAM 11 is sequentially read out in byte units and output to the data bus of the CPU 2 via the buffer 27. (v) RAM data selection read operation This operation is performed by selecting the R in the RAM 11a shown in FIG.
Color data only or G color data only,
Alternatively, this operation is performed when only B color data or only attribute bits are read out continuously. In this case, the CPU 2 first sets "1" to the 0th, 1st, and 5th bits of the mode register 25, respectively.
Write “1” and “0”. This allows the signal FIX
-BA and AUT-INC become "1", and signal DIR-RD becomes "0". When the signal FIX-BA becomes “1”,
The output of the inverter 66 (FIG. 3) becomes a "0" signal, and this "0" signal is supplied to the enable terminal EN of the byte counter 44. As a result, even if a pulse signal is thereafter supplied to the up terminal of the byte counter 44, the up-counting of the byte counter 44 is not performed, and the output of the byte counter 44 is maintained at a constant value. Also, when the signal FIX-BA becomes a “0” signal, the OR gate 45 (Fig. 3)
The output becomes a "1" signal, and this "1" signal is output to the enable terminal EN of the word counter 43. Thereby, the word counter 43 independently operates as an 8-bit counter and counts up the pulse signal supplied to its up terminal UP. Further, when the signal AUT-INC becomes "1", the AND gate 63 (FIG. 2) becomes open, and when the signal DIR-RD becomes "0", the output of the word counter 43 is
Figure) is output. Next, the CPU 2 writes a numerical value corresponding to the type of data to be read into the byte counter 44. In other words, when reading R color data, set "0", and when reading G color data, set "1".
, "2" to read B color data,
When reading the attribute bits, write "3" to each (see FIG. 5). Next, the CPU 2 writes the start address into the word counter 43, and then writes "0" into the pointer counter 19. Thereafter, the third process described above is repeated. By repeating this third process, the word counter 43 is sequentially incremented, and the output of the byte counter 44 (address data BA-1-
0) are sequentially read out from the RAM 11a. (vi) RAM read operation based on external address data When “1” is written to the 5th bit of the mode register 25, the signal DIR-RD becomes a “1” signal,
Data at the input terminal <1> of the multiplexer 42 is output from the multiplexer 42. Therefore, in this case, terminal T7 (Fig. 1, Fig. 3)
When address data is supplied to the synchronization register 41 and multiplexer 42
The data is supplied to the dual port RAM 11 via the dual port RAM 11. In other words, it becomes possible to read data based on external address data. (3-3) Basic display operation The most basic operation of the display controller 1 is as follows.
Dot data output from VDP4 (Figure 1)
Convert DD7-0 to R, G, B color data,
Next, these color data are converted into analog color signals RS, GS, BS and output to the CRT display device 8. The operation in this case will be explained below. In this case, CPU2 first registers mode register 2.
Write “1” to the second bit of 5. As a result, the signal DISP-ENB becomes a "1" signal, and the AND gate 71 (FIG. 2) becomes open. Next, 4-bit data "0" is written into the page mass register 34 (FIG. 3). As a result, a "0" signal is supplied to each control terminal C of the multiplexers 36-39, and the output of the synchronization register 33 is outputted through the multiplexers 36-39. That is,
In this case, the dot data DD7-0 is transferred to the dot data DDa7 via the synchronization registers 33 and 35.
-0 is applied to the address terminal AT2 of the dual port RAM 11. Next, R, G, and B color data are written in the dual port RAM 11, and "0...0" (8 bits) is written as each attribute bit. Next, border registers 50r, 50g, 50b (Figure 4)
Color data specifying the color of each border area is written in each. Next, CPU2 uses VDP4 to
Write dot data (color code) into VRAM5 and output a start command to VDP4. VDP4 receives this start command,
Thereafter, dot data is read from the VRAM 5, and the read dot data is sequentially output to the terminal T2 of the display controller 1 as dot data DD7-0. In addition, in parallel with the output of this dot data DD7-0, a synchronization signal SYN/I, a blanking signal BLANK, a display timing signal
DTMG and dot clock DCLK are output to terminals T3, T4, T5, and T17 of the display controller 1, respectively. The dot data DD7-0 supplied to the terminal T2 of the display controller 1 is sent to the registers 33 and 35.
(Fig. 3) and multiplexers 36 to 39 (upper 4 bits), the dot data DDa7-
It is applied as 0 to the address terminal AT2 of the dual port RAM 11. As a result, from the output terminals Q2 to Q4 of the dual port RAM 11,
R, G, B corresponding to dot data DDa7-0
Color data RD7-0, GD7-0, BD7-0
And attribute data AD7, AD6 (both "0") are output. And color data
RD7-0 is register 4 for one timing delay.
It is applied to one input terminal of the adder circuit 49r via the adder circuit 7r. At this time, the attribute signal AS "0" is applied to the control terminal C of the multiplexer 48r.
Data "0" of its input terminal <0> is output from r. As a result, the output of the adder circuit 49r becomes the same color data as the output of the register 47r, and this color data is transferred to the multiplexer 51.
It is supplied to the input terminal <1> of r. This multiplexer 51r outputs the color data for image display output from the adder circuit 49r during the image display period, and outputs the color data for the border color in the border register 50r during other periods. . That is,
The display timing signal DTMG (signal indicating the image display period) output from VDP4 is DFF
72 (lower part of Figure 2)
It is synchronized with DCLK, delayed by one timing by DFF 73, and supplied to control terminal C of multiplexer 51r via AND gate 71.
As a result, during the image display period, the addition circuit 4
During the other periods, the color data in the register 50r is outputted from the multiplexer 51r and supplied to the register 52r. The register 52r converts the color data output from the multiplexer 51r into 1
The timing is delayed and the signal is supplied to the gate circuit 54r. The gate circuit 54r is a circuit whose opening/closing is controlled by the signal BLANK3. Here, the signal
BLANK3 is VDP as shown in the lower part of Figure 4.
This signal is obtained by synchronizing the blanking signal BLANK (signal indicating the screen display period) outputted from 4 with the dot clock DCLK by the synchronization register 75 and delaying it by 2 timings by the delay registers 46 and 76. Then, the gate circuit 54r
is open during the screen display period, and register 5
Output the color data within 2r to DA55r.
In terms of timing, the dot data DD7-0 is synchronized by the registers 33 and 35 in FIG. 3, is delayed by two timings by the registers 47r and 52r in FIG. 4, and is sent to the gate circuit 54r. applied. Therefore, dot data DD7-
0 is converted into color data and sent to the gate circuit 54r.
The timing and blanking signal applied to
This is the same timing as when BLANK is output as signal BLANK3. The color data that has passed through the gate circuit 54r is converted into an analog color signal by the DAC 55r, and output to the CRT display device 8 as a color signal RS via the amplifier 56r. The above is how color data RD7-0 is a color signal.
This is the process of being converted to RS. Color data GD7
-0 and BD7-0 are also converted into color signals GS and BS through the same process. On the other hand, the synchronization signal SYN・
I is synchronized by register 75 (lower part of FIG. 4), delayed by two timings by registers 46 and 76, and outputted as a synchronizing signal via amplifier 78.
It is output to the CRT display device 8 as SYN・O.
Then, the CRT display device 8
Image display is performed in . (3-4) Blink display operation This operation is for blinking the displayed image based on the basic display operation described above. In this case, the CPU 2 writes the first and second data (4 bits each) to the page registers 30 and 31 (FIG. 3), respectively, and then writes "1" to the fourth bit of the mode register 25. , then data "1, 1," is stored in the page mass register 34.
1, 1” is written. The fourth value of the mode register 25
When “1” is written to the bit, the signal PG-
ENB becomes a "1" signal, and this "1" signal is supplied to the first input terminal of the AND gate 75 (left side in FIG. 3). The signal PG-SEL output from VDP4 (a signal that is "1" for 0.5 seconds and "0" for 0.5 seconds) is input to the second input terminal of this AND gate 75.
76. Therefore, the signal
When PG-ENB becomes a “1” signal, a signal of “1” for 0.5 seconds and “0” for 0.5 seconds is output from the AND gate 75 to the control terminal C of the multiplexer 32. As a result, the multiplexer 32 outputs a signal of “1” for 0.5 seconds and “0” for 0.5 seconds. The first data in the page register 31 and the second data in the page register 31 are output alternately every 0.5 seconds.
Then, the output data is sent to the multiplexer 36
~39 input terminal <1>. Next, when "1, 1, 1, 1" is written in the page mask register 34, a "1" signal is supplied to each control terminal C of the multiplexers 36 to 39.
Instead of the upper 4 bits of the dot data DD7-0, the first and second data in the page registers 30 and 31 are alternately output from the multiplexers 36 to 39, and together with the lower 4 bits of the dot data DD7-0, The data is outputted to the address terminal AT2 of the dual port RAM 11 as data DDa7-0. In other words, dot data DDa7-0 is
It will change every 0.5 seconds, so
The displayed image blinks. In addition, in the page register 34, for example, “1,
If you write “1,0,0”, dot data
Only the upper 2 bits of DDa7-0 can be changed to the data in the page registers 30 and 31, and for example, “1, 0,
If 0,0” is written, dot data
Only the most significant bits of DDa7-0 can be changed. (3-5) Color data modification operation This display controller 1 has dual ports.
By writing “1” to the 7th bit of the attribute bit of RAM11, the VRAM
Color data RD7 without rewriting 4.
-0, GD7-0, BO7-0 can be changed. The operation in this case will be explained below. For example, suppose that "1" is written to the seventh bit of the attribute bit corresponding to a certain color code K1. In this case, dot data DDa
7-0, when the color code K1 is applied to the address terminal AT2 of the dual port RAM 11, the color data RD7-0, GD7 corresponding to the color code K1 is sent from the dual port RAM 11.
-0 and BD7-0 are respectively output, and "1" is output as attribute data AD7. Then, by the next dot clock DCLK, these color data are transferred to registers 47r and 47r.
At the same time, the attribute data AD7 "1" is read into the register 46, and thereby the attribute signal AS becomes a "1" signal. When the attribute signal AS becomes a "1" signal and this "1" signal is applied to the control terminal C of the multiplexer 48r, the color data in the register 52r is transferred to the multiplexer 48.
The color data is supplied to the adder circuit 49r via r, and the adder circuit 49r outputs new color data obtained by adding the color data in the register 47r and the color data in the register 52r.
Here, the color data in register 52r is data that determines the color of a dot to be displayed one dot clock DCLK before the color data in register 47r. Therefore, adding the color data in the register 52r to the color data in the register 47r means adding the color data of a dot displayed one dot clock DCLK ago to the color data in the register 47r. do. The above is the modification operation for color data RD7-0. Color data GD7-0, BD7-
Also for 0, the attribute signal AS is “1”
A similar modification is made in the case of Next, the effect of this color data modification will be explained. Note that the color data corresponding to the color code "0", that is, the color data stored at addresses 0 to 2 in FIG. 5, are each "0". Now, as shown in FIG. 6, for example, we will consider the case where the background is white and boxes with red, blue, and yellow sides are displayed within this background. Note that in the figure, symbol B indicates a border area. In this case, first write the color code "0" to the entire area of VRAM5 (clear VRAM5),
Next, a white color code is written in the memory location of the VRAM 5 corresponding to each dot in the leftmost dot row D1 of the image display area, and then the attribute corresponding to the color code "0" in the dual port RAM 11 is written. Write "1" to the 7th bit. As a result, the entire image display area becomes white. The reason for this is as follows. First, at a certain point in time, the color code of the dot d1 shown in FIG. 6 is read out from the VRAM 5. The dot d1 is displayed in white. Next, dot d2
When "0" is read out as the color code and supplied to the dual port RAM 11, the same
Dot data RD7-0, GD7 from RAM11
-0, BD7-0 is output as "0", and attribute data AD7 is "1". As a result, the adder circuit 4
At 9r, 49g, and 49b, the color code of the previous dot d1 and "0" are added,
This addition result, that is, white color data is output from the addition circuits 49r, 49g, 49b,
This color data is used to display the dot d2 in color. Thereafter, the entire image display area is displayed in white in the same manner. Next, corresponding to each dot in the dot row D2,
Write the red color code to the memory location of VRAM5. As a result, region R1 is displayed in red. Next, correspond to each dot in the dot row D3.
Write the white color code to the memory location of VRAM5. As a result, region R2 within region R1 is displayed in white. Similarly, dot row D4~
Corresponding to D10, blue, blue, red,
If the color codes of yellow, yellow, white, and white are memorized, the display shown in FIG. 6 can be performed. That is, conventionally it was necessary to write the color code in the entire area of the VRAM 5, but according to this embodiment, it is only necessary to write the color code in the storage position of the VRAM 5 corresponding to the boundary line of the image. Now, color codes K2, K3, etc. are written in the VRAM 5 in the state shown in FIG. K
7, the 7th attribute bit of dual port RAM 11 corresponding to K8, K9, K10
Suppose that we write "1" to the dot. here,
For simplicity, each color code K2, K3, . . . is assumed to be a red color code (G color data and B color data are both "0"). Also,
This figure shows the values of R color data corresponding to color codes K2, K3, . . . . Also,
Negative color data (color code K5) is 2
is stored by its complement. In the above writing state, the display state of the line is as shown in FIG. 7B. That is, first,
The leftmost dot d1 is displayed in red corresponding to color code K2, the next dot range D1 is also displayed in red corresponding to color code K2, and the next dot d2 is displayed in red corresponding to color code K3. , the next dot range D2 is displayed in red that changes from dot to dot in a direction where the brightness gradually increases,
The next dot range D3 is displayed in a red color that changes from dot to dot in a direction in which the brightness gradually decreases, the next dot range D4 is displayed in the same red color as the last color of the dot range D3, and the next dot range D3 is code K
Displayed in red corresponding to 6, the next dot range D
5 is displayed in a red color that changes from dot to dot in a direction in which the luminance increases in a curved manner, and the dot range D6 is displayed in the same red as the last color of the dot range D5. In the above display, the advantages obtained by using attribute bits are as follows.
In other words, if attribute bits are not used, 256 colors can be displayed based on the 8-bit color code (dual port RAM 11
(if not rewritten). On the other hand, according to the above display using attribute bits, it is possible to display colors other than 256 colors in the dot ranges D2, D3, and D5 without rewriting the RAM 11. When the value of the color data is extremely small, it is possible to minutely change the color tone in the dot range D2. This advantage is extremely useful especially in displaying three-dimensional figures. The details of one embodiment of the present invention have been described above. Note that in the above embodiment, the attribute bits are stored in the LUT, but instead of this,
The attribute bits may be stored in VRAM5. In this case, R, G, B color data and attribute bits are stored in the VRAM 5 in dot correspondence, each data in the VRAM 5 is read out, and the color data modification circuit 12 shown in FIG.
r, 12g, 12b and register 46. "Effects of the Invention" As explained above, according to the present invention, there is provided a storage means for storing color data and display modification data corresponding to display dots, and a method for synchronizing the color data and display modification data from the storage means with the dot clock. a readout means for sequentially reading out the display modification data read by the readout means; and when the display modification data read out by the readout means is specific data, the color data read out by the readout means corresponds to the color data; a modifying means for performing arithmetic processing using the color data of a dot to be displayed one dot clock timing before the dot that has been displayed, and outputting the result of the arithmetic processing as display-modified color data; A digital/analog converter that converts the color data to be output into an analog signal and outputs it to the color display device is installed, so it is possible to display a wider variety of images than before, and the load on the CPU is lower than before. It becomes possible to do so.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a color display device using a display controller 1 according to an embodiment of the present invention, FIGS. 2 to 4 are circuit diagrams showing details of the display controller 1, and FIG. The figure shows the configuration of the control section, FIG. 3 shows the configuration of the RAM address forming section, and FIG. 4 shows the dual port RAM 11 and color data modification circuit 12.
FIG.
Figures 6 and 7 showing the configuration of the RAM 11a are diagrams for explaining the effects of color data modification, respectively. 1...Display controller, 11...Dual port RAM, 12r, 12g, 12b...Color data modification circuit, 49r...Addition circuit, 55r...
...DAC (digital/analog conversion circuit).

Claims (1)

[Scope of Claims] 1. Storage means for storing color data and display modification data corresponding to display dots; Reading means for sequentially reading color data and display modification data from the storage means in synchronization with a dot clock; and the reading means. When the display modification data read out by the reading means is specific data, one dot clock timing earlier than the dot corresponding to the color data read out by the reading means. a modifying means for performing arithmetic processing using the color data of the dots to be displayed on the screen and outputting the result of the arithmetic processing as display-modified color data; and converting the color data output by the modifying means into an analog signal. A display controller comprising a digital/analog converter for outputting data to a color display device. 2. The display controller according to claim 1, wherein the storage means is a conversion table for converting a color code into color data.