JPH0522269A - Delay correction circuit - Google Patents

Abstract

PURPOSE:To locate a faulty frame by sending a specific pattern while being synchronously with a frame with respect to a memory input allocated to a monitor bit, comparing and collating the output pattern from the memory with a specific pattern and checking each frame together with parity check. CONSTITUTION:While a specific pattern S3 for monitor generated in a pattern generating circuit 2 is sent to an input B1 of a memory 1, a vertical parity signal S4 generated in a parity generating circuit 3 is sent to an input B2 of the memory 1. A pattern S7 from an output B3 is collated with the specific pattern S3 at the pattern collation circuit 4 and an alarm is generated in the presence of the fault together with a check result of a parity check circuit 5.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a delay correction circuit used in a data transmission device.

[0002]

2. Description of the Related Art In a data transmission device of a loop type transmission line that handles data composed of frames of a fixed time length, a delay correction circuit is used to compensate for a phase difference between data on the transmission line and local data. A memory with multiple bit inputs and corresponding outputs is used to check if this delay compensation circuit is normal and there are errors in writing and reading the memory. Vertical parity checks are mainly applied for the purpose of confirming the absence.

[0003]

However, if only the vertical parity check cannot be performed on a frame-by-frame basis, and if a delay correction operation fails, it becomes impossible to separate the generated frames. There are drawbacks. Therefore, it is an object of the present invention to provide a delay correction circuit that can also check each frame.

[0004]

In order to achieve the above object, the present invention generates and sends a specific pattern in synchronization with a frame to the input of the memory assigned to the monitoring bit in the delay correction circuit described above. A pattern generation circuit, a parity generation circuit that generates and sends a vertical parity signal to the input of the memory assigned to the parity check bit, and a pattern sent from the output of the memory corresponding to the input assigned to the monitoring bit. A pattern matching circuit for comparing and matching with a specific pattern and a parity check circuit for checking a signal sent from an output of a memory corresponding to an input assigned to a parity check bit are provided.

[0005]

Therefore, the parity check is performed, the specific pattern is written and read in synchronization with the frame, and the check is performed for each frame by comparing and collating the read pattern and the specific pattern.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The details of the present invention will be described below with reference to the block diagram of FIG. In the figure, a memory (hereinafter referred to as MM) 1 having a plurality of bits of inputs and outputs corresponding to these is provided, which includes an input B1 assigned to a monitoring bit and a parity check bit. The assigned input B2 is determined, and the output B3 corresponding to the input B1 and the output B4 corresponding to the input B2 are determined.

The other input of the MM1 is supplied with an input signal S1 of data consisting of a frame of a fixed time length and a timing signal S2 indicating a write timing for each frame, so that the pattern generation circuit ( Less than,
PTG) 2 generates a specific pattern S3 for monitoring in synchronization with the frame in accordance with the timing signal S2 and sends it to the input B1.
RG) 3 generates a vertical parity signal S4 for parity check based on the input signal S1 and the specific pattern S3, and sends this to the input B2.

Therefore, along with the input signal S1, the specific pattern S3 and the vertical parity signal S4 are sequentially written to the MM1 for each frame according to the timing signal S2.

The contents of MM1 are read out as an output signal S5, which is read locally by a timing signal S6.
Pattern S from output B3
7 is P in the pattern matching circuit (hereinafter referred to as REF) 4.
While the comparison with the specific pattern S3 generated by TG2 is performed, the signal S8 from the output B4 is subjected to the parity check by the parity check circuit (hereinafter, CHK) 5, and either If the result is abnormal, REF4 or CHK5 is drawn by the route omitted in the figure.
The alarm will be sent from the.

Therefore, PRG3 and CHK5 perform the same check as before, and at the same time, PTG
The check of the specific pattern S3 by 2 and REF4 is performed for each frame, and the frame in which the failure has occurred can be immediately detected.

[0011]

As is apparent from the above description, according to the present invention, a specific pattern is transmitted to the input of the memory assigned to the monitoring bit in synchronization with the frame, while the output of the memory corresponding to this input is output. By comparing and collating the pattern with the specific pattern and checking each frame as well as the parity check, it is possible to monitor the delay correction status at the same time. A remarkable effect is obtained in the delay correction of the device.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

[Explanation of reference numerals] 1 memory 2 pattern generation circuit 3 parity generation circuit 4 pattern matching circuit 5 parity check circuit

Claims (1)

Claim: What is claimed is: 1. A delay compensation circuit for a data transmission device, comprising: a memory for handling data constituted by a frame having a fixed time length and using a memory having a plurality of bits of input and an output corresponding thereto; Pattern generating circuit for generating and transmitting a specific pattern in synchronization with the frame to the input of the memory assigned to the memory bit, and generating and transmitting a vertical parity signal to the input of the memory assigned to the parity check bit. Corresponding to a parity generation circuit, a pattern matching circuit for comparing and matching the pattern sent from the output of the memory corresponding to the input assigned to the monitoring bit with the specific pattern, and the input assigned to the parity check bit. A parity check circuit for checking a signal sent from the output of the memory is provided. Delay correction circuit according to claim and.