JPH0522146A - A/d converter - Google Patents

Abstract

PURPOSE:To arbitrarily set a converted bit length and to select conversion time or conversion accuracy corresponding to the purpose of use at the analog/ digital (A/D) converter built in a single chip microcomputer. CONSTITUTION:A voltage to be converted is inputted to a terminal 8, and a reference voltage is inputted to a terminal 9. This A/D converter equipped with a voltage comparator 1, tap selector 2, resistor string 3, sample/hold circuit 4 and successive conversion register 5 is provided with a control circuit 6 to control the operation of the A/D converter and a control counter 7 to count the converted bit length. Therefore, since the above-mentioned circuits are provided, there are effects such as freely setting the bit length to be converted and selecting the conversion time or the conversion accuracy corresponding to the purpose of use.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a single chip microcomputer, and more particularly to an analog / digital converter (hereinafter abbreviated as A / D converter).

[0002]

2. Description of the Related Art A block diagram of a conventional successive conversion type A / D converter is shown in FIG. Further, a timing chart of the operation is shown in FIG.

The converted voltage V _ANI is input to the converted voltage input terminal (8), and the reference voltage V _REF is input to the reference voltage input terminal (9).

V input to the converted voltage input terminal
_ANI is sample and hold (S & H below
The circuit (4) is held at a certain sampling timing.

First, V _{REF is connected} to a series resistor string (3).
The voltage V _REF / 2 _{divided by} 2 with tap selector (2)
The voltage comparator (1) compares this with V _ANI . If it is larger, the most significant bit (MSB) of the successive conversion register (5) is set, and if it is smaller, the MSB is reset.

Next, when the MSB of the successive approximation register is 1, (3/4) V _REF is selected by the tap selector and this is compared with V _ANI by the voltage comparator. The bit lower by 1 bit is set, and if smaller, the bit lower by 1 bit than the MSB is reset.

When the MSB = 0 of the successive approximation register,
Select (1/4) V _REF with the tap selector, and select this
_ANI is compared by a voltage comparator, and if it is larger, the bit one bit lower than the MSB of the successive conversion register is set, and if it is smaller, the bit one bit lower than the MSB is reset.

This is repeated until the LSB of the successive approximation register is set or reset.

The conversion is completed when the LSB of the successive conversion register is set or reset.

[0010]

DISCLOSURE OF THE INVENTION The above-mentioned conventional A / D
Since the converter cannot select the conversion bit length, there is the drawback that the conversion bit length cannot be selected to shorten the conversion time or to increase the conversion bit length in order to obtain a highly accurate conversion result. is there.

[0011]

The A / D converter of the present invention has a register for designating the conversion bit length and a control circuit for controlling the conversion operation.

[0012]

The present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a timing chart thereof.

The converted voltage is input to the converted voltage input terminal (8), and the reference voltage is input to the reference voltage input terminal (9). First, the bit length to be converted is written in the control counter (7). The converted voltage V _ANI is input to the converted voltage input terminal (8), and the reference voltage V _REF is input to the reference voltage input terminal (9). The V _ANI input to the converted voltage input terminal is held by the S & H circuit (4) at a certain sampling timing. First, the voltage V _REF / 2 obtained by dividing V _REF into two by the series resistor string (3) is selected by the tap selector (2), and this is compared with V _ANI by the voltage comparator (1). The most significant bit (MSB) of the conversion register (5) is set, and if smaller, the MSB is reset. At the same time the control counter 1
Decrement.

Next, when the MSB of the successive approximation register is 1, tap selector (3/4) V _REF is selected, and this is compared with V _ANI by a voltage comparator. A bit lower than the bit is set, and if smaller, a bit lower than the MSB by 1 bit is reset. When the serial conversion register MSB = 0,
Select (1/4) V _REF with the tap selector, and select this
_ANI is compared by a voltage comparator, and if it is larger, the bit one bit lower than the MSB of the successive conversion register is set, and if it is smaller, the bit one bit lower than the MSB is reset. At the same time, the control counter is decremented by 1. After that, tap select and voltage comparison are performed in the same way.
The value of the control counter is decremented by 1 each time the voltage comparison ends. When the value of the control counter becomes 0, or when the LSB of the successive conversion register is set or reset, the conversion operation ends.

FIG. 3 is a block diagram of another embodiment of the present invention, and FIG. 4 is a timing chart thereof.

First, a control word is written in the control register (11). Here, the control word is a value in which 1s are arranged from the most significant bit by the conversion bit length and 0 is written in the next bit. (See FIG. 5) The converted voltage V _ANI is input to the converted voltage input terminal (8), and the reference voltage V _REF is input to the reference voltage input terminal (9). V _ANI input to the converted voltage input terminal is a S & H circuit (4),
It is held at a certain sampling timing. First, bit check the MSB of the control register
If = 1, A / D conversion is performed. First, the voltage V _REF / 2 obtained by dividing 2 minutes V _REF series resistor string (3),
It is selected by the tap selector (2) and compared with V _ANI by the voltage comparator (1). If it is larger, the most significant bit (MSB) of the successive conversion register (5) is set, and if it is smaller, the MSB is reset. . Next, bit check the bit one bit lower than the MSB of the control register,
If it is 0, the conversion operation is ended, and if it is 1, the conversion operation is continued. To continue conversion, if the MSB of the successive conversion register = 1, use tap selector (3/4)
V _REF is selected, and this is compared with V _ANI by a voltage comparator. If it is larger, the bit one bit lower than the MSB of the successive conversion register is set, and if it is smaller, the bit one bit lower than the MSB is reset. When MSB = 0 of successive conversion register, tap selector selects (1/4) V
_REF is selected, and this is compared with V _ANI by a voltage comparator, and if it is larger, the bit one bit lower than the MSB of the successive conversion register is set, and if it is smaller, the bit one bit lower than the MSB is reset. Thereafter, the bit check of the control register and the 1-bit conversion are repeated. When the value of the bit of the control register becomes 0, or when the LSB of the successive conversion register is set or reset, the conversion operation ends.

[0018]

As described above, the A / D converter of the present invention has the control block for designating the conversion bit length and controlling the conversion operation, whereby the conversion bit length can be freely set. effective.

[Brief description of drawings]

FIG. 1 shows a block diagram of an embodiment of the present invention.

FIG. 2 shows an operation timing chart of one embodiment.

FIG. 3 shows a block diagram of another embodiment of the present invention.

FIG. 4 shows an operation timing chart of another embodiment.

FIG. 5 shows an example of a control word of another embodiment.

FIG. 6 shows a block diagram of a prior art.

FIG. 7 shows an operation timing chart of the prior art.

[Explanation of symbols]

 (1) Voltage comparator (2) Tap selector (3) Series resistance string (4) Sample and hold circuit (5) Sequential conversion register (6) Control circuit (7) Control counter (8) Converted voltage input terminal ( 9) Analog reference voltage input terminal (10) Analog ground potential input terminal (11) Control register (12) Control block ~: Indicates conversion operation: Converts MSB: Converts MSB to 2nd bit: MSB to 3rd bit Convert: Convert MSB to 4th bit: Convert MSB to 5th bit: Convert MSB to 6th bit: Convert MSB to 7th bit: Convert MSB to 8th bit

Claims (1)

Claim: What is claimed is: 1. A series resistor string, a sample-and-hold circuit, a voltage comparator, and a control block for controlling a conversion operation. The control block freely changes the conversion bit length. An analog / digital converter that can be set.