JPH0522129A - Phase synchronizing detection circuit - Google Patents

Phase synchronizing detection circuit

Info

Publication number
JPH0522129A
JPH0522129A JP3148295A JP14829591A JPH0522129A JP H0522129 A JPH0522129 A JP H0522129A JP 3148295 A JP3148295 A JP 3148295A JP 14829591 A JP14829591 A JP 14829591A JP H0522129 A JPH0522129 A JP H0522129A
Authority
JP
Japan
Prior art keywords
phase
detection circuit
output
logic element
reference voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP3148295A
Other languages
Japanese (ja)
Other versions
JP3098280B2 (en
Inventor
Tatsuyoshi Hamada
樹欣 浜田
Shigeru Fujimoto
繁 藤本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
NEC Engineering Ltd
Original Assignee
NEC Corp
NEC Engineering Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, NEC Engineering Ltd filed Critical NEC Corp
Priority to JP03148295A priority Critical patent/JP3098280B2/en
Publication of JPH0522129A publication Critical patent/JPH0522129A/en
Application granted granted Critical
Publication of JP3098280B2 publication Critical patent/JP3098280B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Abstract

PURPOSE:To realize the phase synchronizing detection circuit, which unnecessitates the control of a reference voltage and automatically follows up a power supply voltage fluctuation or a temperature fluctuation, by constituting a reference voltage generating circuit having the same package circuit configuration as a phase comparator and a phase detector. CONSTITUTION:This phase synchronizing detection circuit to monitor the phase synchronizing state of a phase synchronizing oscillator is equipped with first means 1 and 2 to extract the output of a logic element, which compares the phases of an input signal and an inside reference signal, as an integrating value, second means 3 and 4 to input the above-mentioned reference signal and to extract the output of the same logic element as the above-mentioned first means 1 and 2 as the integrating value while using this logic element, and means 5 to input the output signals of the first and second means and to execute the comparison and judgement of those signals.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は位相同期検出回路に関
し、特に位相同期ループ(PLL)を用いた位相同期発
振器(PLO)における位相同期引き込み範囲の安定化
をはかった位相同期検出回路に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase lock detecting circuit, and more particularly to a phase lock detecting circuit for stabilizing a phase lock pull-in range in a phase locked oscillator (PLO) using a phase locked loop (PLL).

【0002】[0002]

【従来の技術】従来よりディジタル信号伝送方式等位相
同期発振器(PLO)における位相同期検出回路9は図
3に示すように、位相比較器1、位相検出器2、リファ
レンス電圧発生回路8、比較判定器5から構成され、外
部のVCO6との間でPLLを形成していた。このPL
Oの同期状態を確認する方法として、PLOの内部位相
検波器とは別に、例えばPLOの位相比較器1をEX−
ORで構成している場合は、入力信号101と内部基準
信号102とを位相比較し、位相検出器2で積分した後
にリファレンス電圧発生回路8で発生した固定電圧と比
較判定器5で比較し同期状態を検出している。
2. Description of the Related Art Conventionally, as shown in FIG. 3, a phase synchronization detection circuit 9 in a digital signal transmission type equal phase synchronization oscillator (PLO) has a phase comparator 1, a phase detector 2, a reference voltage generation circuit 8 and a comparison judgment. It is composed of a container 5 and forms a PLL with an external VCO 6. This PL
As a method of confirming the synchronization state of O, for example, the PLO phase comparator 1 is EX-
When configured by OR, the input signal 101 and the internal reference signal 102 are phase-compared, integrated by the phase detector 2, and then compared with a fixed voltage generated by the reference voltage generation circuit 8 by the comparison / determination unit 5 and synchronized. The condition is detected.

【0003】[0003]

【発明が解決しようとする課題】上述した従来の位相検
出回路では、基準となるリファレンスとして高安定な電
圧源をツェナーダイオード等で作っており、素子の若干
のバラツキを吸収するために必ずリファレンス電圧を調
整しなければならない。また電源電圧変動や温度変動に
より位相比較器1と位相検出器2の出力の変動と基準と
なるリファレンス電圧発生回路3の変動が相関していな
いので、判定基準が変わってしまうという欠点がある。
In the conventional phase detection circuit described above, a highly stable voltage source is made up of a Zener diode or the like as a reference, and the reference voltage is always used in order to absorb a slight variation of the element. Must be adjusted. Further, there is a drawback in that the determination standard is changed because the variation of the outputs of the phase comparator 1 and the phase detector 2 and the variation of the reference voltage generating circuit 3 serving as a reference are not correlated due to the power supply voltage variation and the temperature variation.

【0004】[0004]

【課題を解決するための手段】本発明の位相同期検出回
路は位相同期発振器の位相同期状態を監視する位相同期
検出回路において、入力信号と内部基準信号との位相比
較を行う論理素子の出力を積分値として取り出す第1の
手段と、前記基準信号を入力して前記第1の手段と同一
の論理素子を用いこの論理素子の出力を積分値として取
り出す第2の手段と、前記第1および第2の手段の出力
信号を入力し比較判定する手段とを有する。
The phase synchronization detection circuit of the present invention is a phase synchronization detection circuit for monitoring the phase synchronization state of a phase synchronization oscillator, and outputs the output of a logic element for phase comparison between an input signal and an internal reference signal. First means for taking out as an integrated value, second means for receiving the reference signal and using the same logic element as the first means, and taking out the output of this logical element as an integrated value, the first and the second means. 2 means for inputting the output signal of the second means for comparison and determination.

【0005】[0005]

【実施例】次に本発明について図面を参照して説明す
る。図1は本発明の一実施例の構成図、図2は本実施例
の動作説明図である。図1において位相比較器1はEX
−ORなどの素子より構成されていて、入力信号101
と内部基準信号102の位相差を比較して双方の位相差
に応じて位相差信号103を出力する。位相検出器2は
C−R積分回路など積分機能等を持ったもので位相差信
号103を積分し位相差検出電圧104を出力する。リ
ファレンス電圧発生回路3は位相比較器1と同一ICパ
ッケージのEX−ORなどの素子より構成されていて、
同様にC−R積分機能等を持ったリファレンス電圧検出
器4と組み合わせており、常時内部基準信号102のレ
ベルを積分し、リファレンス電圧105として出力す
る。リファレンス電圧発生回路3と位相比較器1を同一
パッケージのEX−ORを使用することにより位相比較
回路全体の電源電圧変動や温度変動に対しても連動して
変化するために、個別にリファレンス電圧発生回路を設
けるより簡単にさらに正確に補正が出来る。比較判定器
5は位相検出器2からの位相差検出電圧104とリファ
レンス電圧検出器4からのリファレンス電圧105を比
較して比較判定信号106を出力する。この際、比較判
定器5にヒステリ特性を持たせることにより入力信号1
01,内部信号102,にノイズ等が乗っても比較判定
器5の誤判定を防止できる。
The present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of one embodiment of the present invention, and FIG. 2 is an operation explanatory diagram of this embodiment. In FIG. 1, the phase comparator 1 is EX
An input signal 101
And the phase difference between the internal reference signal 102 and the phase difference signal 103 are output according to the phase difference between the two. The phase detector 2 has a integrating function such as a CR integrating circuit and integrates the phase difference signal 103 and outputs a phase difference detection voltage 104. The reference voltage generation circuit 3 is composed of elements such as EX-OR in the same IC package as the phase comparator 1,
Similarly, it is combined with the reference voltage detector 4 having a C-R integration function and the like, and always integrates the level of the internal reference signal 102 and outputs it as the reference voltage 105. By using the EX-OR in the same package for the reference voltage generation circuit 3 and the phase comparator 1, the reference voltage generation is performed individually because it changes in association with the power supply voltage fluctuation and the temperature fluctuation of the entire phase comparison circuit. Correction can be performed more easily and more accurately than if a circuit is provided. The comparison / determination device 5 compares the phase difference detection voltage 104 from the phase detector 2 with the reference voltage 105 from the reference voltage detector 4 and outputs a comparison determination signal 106. At this time, the input / output signal 1
Even if noise or the like is added to 01 and the internal signal 102, the erroneous determination of the comparison and determination unit 5 can be prevented.

【0006】図2(a)は、一般的なPLOの位相同期
特性を示し、図2(b)はこの位相同期範囲に対応する
位相同期状態の検出回路の比較判定信号106の特性を
示している。今、一例として、電源電圧が高くなった場
合の動作を説明する。図2(b)において、正常電源の
とき同期検出器の出力がVD1であったとし、同期判定
のリファレンス電圧がVr1として与えられている。電
源電圧がΔVだけ高くなった場合に、同期検出器の出力
VD2となりΔVDだけ高くなる。本発明によるとリフ
ァレンス電圧は同一パッケージのICを検波器として使
うためリファレンス用の電圧もVr2となりΔVDだけ
高くなり、誤差の少ない同期判定を行うことが出来る。
FIG. 2A shows the phase-locking characteristic of a general PLO, and FIG. 2B shows the characteristic of the comparison judgment signal 106 of the detection circuit in the phase-locked state corresponding to this phase-locking range. There is. Now, as an example, the operation when the power supply voltage becomes high will be described. In FIG. 2B, it is assumed that the output of the synchronization detector is VD1 when the power supply is normal, and the reference voltage for synchronization determination is given as Vr1. When the power supply voltage increases by ΔV, the output of the synchronization detector becomes VD2, which increases by ΔVD. According to the present invention, since the reference voltage uses the IC of the same package as the wave detector, the reference voltage also becomes Vr2 and increases by ΔVD, and the synchronization determination with less error can be performed.

【0007】[0007]

【発明の効果】以上説明したように本発明の位相同期検
出回路は位相比較器および位相検出器と同一のパッケー
ジの回路構成によるリファレンス電圧発生回路等を構成
することにより、リファレンス電圧が無調整となりま
た、電源電圧変動や温度変動に対して自動追従する位相
同期検波回路が実現できるという効果がある。
As described above, the phase-locking detection circuit of the present invention constitutes a reference voltage generating circuit having the same circuit configuration as the phase comparator and the phase detector, so that the reference voltage is not adjusted. Further, there is an effect that it is possible to realize a phase synchronous detection circuit that automatically follows a power supply voltage fluctuation and a temperature fluctuation.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例の構成図である。FIG. 1 is a configuration diagram of an embodiment of the present invention.

【図2】本実施例の特性を説明する説明図である。FIG. 2 is an explanatory diagram illustrating characteristics of the present embodiment.

【図3】従来の位相同期検出回路の構成図である。FIG. 3 is a configuration diagram of a conventional phase synchronization detection circuit.

【符号の説明】[Explanation of symbols]

1 位相比較器 2 位相検出器 3,8 リファレンス電圧発生回路 4 リファレンス電圧検出器 5 比較判定器 6 VCO 7,9 位相同期検出回路 1 Phase comparator 2 Phase detector 3,8 Reference voltage generation circuit 4 Reference voltage detector 5 Comparative judgment device 6 VCO 7,9 Phase synchronization detection circuit

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 位相同期発振器の位相同期状態を監視す
る位相同期検出回路において、入力信号と内部基準信号
との位相比較を行う論理素子の出力を積分値として取り
出す第1の手段と、前記基準信号を入力して前記第1の
手段と同一の論理素子を用いこの論理素子の出力を積分
値として取り出す第2の手段と、前記第1および第2の
手段の出力信号を入力し比較判定する手段とを有するこ
とを特徴とする位相同期検出回路。
1. A phase synchronization detection circuit for monitoring a phase synchronization state of a phase synchronization oscillator, comprising: first means for extracting an output of a logic element for phase comparison between an input signal and an internal reference signal as an integrated value; A second means for inputting a signal and using the same logic element as the first means to take out the output of this logic element as an integrated value and the output signals of the first and second means are inputted and compared and judged. And a phase synchronization detection circuit.
【請求項2】 前記第1の手段および前記第2の手段の
回路が同一パッケージのICとして構成され同一の電源
で動作するように形成されていることを特徴とする請求
項1記載の位相同期検出回路。
2. The phase synchronization according to claim 1, wherein the circuits of the first means and the second means are formed as ICs in the same package and are configured to operate with the same power supply. Detection circuit.
JP03148295A 1991-06-20 1991-06-20 Phase synchronization detection circuit Expired - Fee Related JP3098280B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP03148295A JP3098280B2 (en) 1991-06-20 1991-06-20 Phase synchronization detection circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP03148295A JP3098280B2 (en) 1991-06-20 1991-06-20 Phase synchronization detection circuit

Publications (2)

Publication Number Publication Date
JPH0522129A true JPH0522129A (en) 1993-01-29
JP3098280B2 JP3098280B2 (en) 2000-10-16

Family

ID=15449585

Family Applications (1)

Application Number Title Priority Date Filing Date
JP03148295A Expired - Fee Related JP3098280B2 (en) 1991-06-20 1991-06-20 Phase synchronization detection circuit

Country Status (1)

Country Link
JP (1) JP3098280B2 (en)

Also Published As

Publication number Publication date
JP3098280B2 (en) 2000-10-16

Similar Documents

Publication Publication Date Title
US6049233A (en) Phase detection apparatus
US6954510B2 (en) Phase-locked loop lock detector circuit and method of lock detection
JP2004120433A (en) Phase-locked loop circuit
JPH09102739A (en) Pll circuit
JPH0522129A (en) Phase synchronizing detection circuit
WO2001022593A1 (en) Phase-locked loop
JPH08130464A (en) Dll circuit
JP2006253869A (en) Phase synchronization circuit
US7050520B2 (en) PLL (Phase-Locked Loop) circuit
JPH10209859A (en) Pll circuit
JP2776334B2 (en) Phase locked loop
US10110237B2 (en) System and a method for detecting loss of phase lock
JPH0884074A (en) Pll circuit
JPS59202736A (en) Phase locked loop circuit
US20020021368A1 (en) PLL circuit for CRT monitor horizontal drive signal
JP3240229B2 (en) Phase comparator
KR100190046B1 (en) Horizontal sync. signal input unit correction apparatus of phase sync. loop
KR100195086B1 (en) Synthesizer circuit of phase locked loop frequency
JPH0575590A (en) Synchronizing clock generating circuit
KR100273965B1 (en) Frequency phase locked loop
JPH08125532A (en) Phase-locked loop
JPH09331254A (en) Pll circuit
JPH04167815A (en) Phase locked loop circuit
JPH0530095A (en) Phase lock oscillating circuit
JPH1155115A (en) External synchronization clock generator

Legal Events

Date Code Title Description
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20000718

LAPS Cancellation because of no payment of annual fees