JPH09331254A - Pll circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a PLL circuit which is not affected by the dispersion at the time of manufacture by surely preventing erroneous locking and, at the same time, to reduce the circuit scale in converting the circuit to and LSI form. SOLUTION: A PLL circuit is constituted so that the circuit can detect the phase difference between the frequency dividing signal of the output of a voltage-controlled oscillator(VCO) 1 by means of a phase comparator 3 and supply the phase difference signal to the VCO 1 through a low-pass filter 4. A multiplexer 8 is provided in the preceding stage of the filter 4 so that a pulse signal having a prescribed frequency from a pulse generator 7 and the phase difference signal from the comparator 3 can be inputted to the multiplexer 8 and the pulse signal is supplied to the filter during a prescribed period after the power supply is made in accordance with a power-on reset signal. After the prescribed period has elapsed, the phase difference signal is supplied to the filter 4.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PLL circuit using a voltage controlled oscillator (hereinafter referred to as VCO),
The present invention relates to a circuit for preventing erroneous lock of a PLL circuit or for recovering from erroneous lock.

[0002]

2. Description of the Related Art Generally, as shown in FIG. 4, a PLL circuit basically comprises a VCO 1 whose oscillation frequency is controlled by an input control voltage, and a frequency divider 2 which divides an output signal of the VCO 1. , A phase comparator 3 for comparing the frequency division output of the frequency divider 2 and the phase of the reference signal and outputting a phase difference signal,
It comprises a low-pass filter 4 which receives the phase difference signal from the phase comparator 3 and supplies a control voltage corresponding to the phase difference signal to the VCO 1. As shown in FIG. 5, the oscillation frequency characteristic of the VCO 1 with respect to the input control voltage has a characteristic that the oscillation frequency rises almost in proportion to the rise of the voltage.

Here, when the power is turned on, the control voltage from the low-pass filter 4 rises gently, so that the frequency of the VCO 1 also gradually rises according to the characteristic of FIG. 5, and when the control voltage becomes Vc, the oscillation of the VCO 1 occurs. The frequency becomes the desired oscillation frequency fc, and the PLL locks. However, when the power is turned on, as shown in FIG. 6, the control voltage does not reach the voltage Vc corresponding to the desired oscillation frequency fc before the control voltage reaches the frequency fc which is an integer 1 / n of the desired oscillation frequency fc.
The voltage becomes Vn corresponding to / n, and in this state, as shown in FIG. 7, a signal obtained by dividing the output signal of VCO 1 (see FIG.
C) and the phase of the reference signal (FIG. 7A) are synchronized, and the PLL is erroneously locked at this frequency. Note that FIG. 7 shows an example in which the phase comparator 3 detects both rising and falling edges of the reference signal when n = 2.

Therefore, conventionally, as shown in FIG. 4, a DC bias circuit composed of a resistance division circuit 51 and an operational amplifier 52 is provided, and a phase comparator is provided for a predetermined period after the power is turned on, specifically, during a power-on reset period. 3 is forcibly set to the high impedance state, and the bias voltage from the DC bias circuit 5 is supplied to the low pass filter 4 via the switch 6 to prevent erroneous lock at the frequency fc / n. Was there.

[0005]

Since the bias circuit that has been used conventionally is composed of analog parts such as operational amplifiers and resistors, it is not suitable for on-chip mounting on a MOS LSI in terms of manufacturing variations and circuit scale. there were.

[0006]

The present invention compares a phase of a voltage-controlled oscillator, a frequency divider for dividing the output of the voltage-controlled oscillator, and a frequency-divided signal from the frequency divider and a reference signal. And a phase comparator for outputting a phase difference signal, a pulse generator for outputting a pulse signal of a predetermined frequency, and a pulse signal output from the pulse generator or the phase difference signal according to a control signal. It is characterized in that a PLL circuit is configured by a multiplexer to be selected by selecting and a low-pass filter which inputs a signal selected by the multiplexer and supplies an output to the voltage controlled oscillator.

Further, as the control signal, a signal which has a first level for a predetermined period after power-on and has a second level for a predetermined period is supplied, and the multiplexer generates the pulse generator when the control signal is at the first level. Output pulse signal is selected, and the phase difference signal is selected at the second level. In the present invention, the bias level can be generated logically without using an analog component, which is most suitable for a MOS LSI.

[0008]

1 is a block diagram showing an embodiment of the present invention, in which a VCO 1, a frequency divider 2, a phase comparator 3,
The low-pass filter 4 has the same configuration as the conventional example shown in FIG. Here, a pulse generator 7 that outputs a pulse signal of a predetermined frequency, a pulse signal from this pulse generator 7 and a phase difference signal from the phase comparator 3 are input, and either signal is output according to the control signal PWR. A multiplexer 8 for selecting and supplying the selected low-pass filter 4 to the low-pass filter 4 in the subsequent stage is provided. The control signal PWR is set to L for a predetermined period after the power is turned on.
A power-on reset signal which becomes H level and becomes H level after a lapse of a predetermined period is applied to the multiplexer 8.

Therefore, for example, the VC to be locked
When the desired oscillation frequency of O1 is fc and the control voltage Vc of VCO1 for setting this frequency is VDD / 2, the pulse generator 7 outputs a pulse signal with an amplitude of VDD and a duty of 50%. I am trying to let you. Then, when the power is turned on, the power-on reset signal PW
Since R is at L level for a predetermined period T as shown in FIG.
The multiplexer 8 selects the output pulse signal of the pulse generator 7 and outputs it to the low-pass filter 4 for the predetermined period as shown in FIG. In the low-pass filter 7, since the input signal is a pulse signal with an amplitude of VDD and a duty of 50%, its output gradually rises as shown in FIG. 3C, and the voltage corresponding to the oscillation frequency fc / n is changed. After passing, it finally becomes a DC voltage of VDD / 2, and this voltage is supplied to VCO1 as a control voltage. Therefore, the oscillation frequency of the VCO 1 rises to fc, as in the case of supplying the DC bias from the DC bias circuit 5 in the conventional example.

After the elapse of the predetermined period T, the power-on reset signal PWR changes to the H level (FIG. 3A). Therefore, the phase difference signal from the phase comparator 3 is selected by the multiplexer 8 and this phase difference signal is selected. It is supplied to the low-pass filter 4. Therefore, the PLL is configured and locked at the desired oscillation frequency fc according to the phase difference. In this way, the PLL is prevented from being erroneously locked at the frequency fc / n when the power is turned on.

By the way, the circuit of the present invention can also be used as a means for recovering from a false lock due to some cause. FIG. 2 is a block diagram showing such another embodiment. In the configuration in which the input data is input to the phase comparator 3 as the reference signal, the output of the VCO 1 is input as the clock signal and based on this clock. A frame synchronization detection circuit 9 for detecting the frame synchronization of the input data is provided. When the frame synchronization detection circuit 9 detects that the frame synchronization cannot be achieved, the frame synchronization detection signal FR, which is normally H level, is set to L level for a predetermined period after the detection, and the frame synchronization detection signal FR is sent to the multiplexer 8 as a control signal. Are typing as.

According to this structure, when the PLL erroneously locks at a frequency other than the desired frequency, the frame synchronization of the input data cannot be achieved, so that the frame synchronization detection signal FR changes to the L level and the multiplexer 8 outputs the pulse for a predetermined period. Select the pulse signal from the generator 7 and use the low-pass filter 4
Output to Therefore, the control voltage of the VCO 1 becomes a voltage corresponding to the amplitude and duty of the pulse signal, and the erroneous lock is released. After the lapse of a predetermined time, the frame synchronization detection signal FR becomes H level, so that the multiplexer 8 selects the phase difference signal from the phase comparator 3 to select the low pass filter 4.
, The PLL enters the normal operation state and locks at the desired frequency. In this way, it is possible to recover from an erroneous lock.

[0013]

According to the present invention, the erroneous lock can be surely prevented, and the erroneous lock can be prevented by using the logic circuit such as the pulse generator and the multiplexer. Can be reduced to realize a PLL circuit that is not affected by variations in manufacturing. Furthermore, by adding an erroneous lock detection circuit, it can be used as a recovery means from an erroneous lock.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram showing another embodiment of the present invention.

FIG. 3 is a timing chart for explaining the operation of the embodiment of the present invention.

FIG. 4 is a block diagram showing a conventional PLL circuit.

FIG. 5 is a characteristic diagram showing a relationship between a control voltage of a VCO and an oscillation frequency.

FIG. 6 is a VCO control voltage waveform diagram when power is turned on in the conventional circuit.

FIG. 7 is a timing chart showing an erroneous lock state in the conventional circuit.

[Explanation of symbols]

 1 VCO 2 Frequency divider 3 Phase comparator 4 Low pass filter 5 DC bias generation circuit 6 Switch 7 Pulse generator 8 Multiplexer

Claims (3)

[Claims] 1. A voltage-controlled oscillator, a frequency divider that divides the output of the voltage-controlled oscillator, and a phase difference signal is output by comparing the phases of the frequency-divided signal from the frequency divider and the reference signal. A phase comparator, a pulse generator that outputs a pulse signal of a predetermined frequency, a multiplexer that selects one of the pulse signal output from the pulse generator and the phase difference signal according to a control signal, and the multiplexer. And a low-pass filter for inputting the signal selected in 1. and supplying the output to the voltage controlled oscillator.
L circuit. 2. The control signal is a signal having a first level for a predetermined period after power-on and a second level for a predetermined period after the power is turned on, and the multiplexer generates the pulse generator when the control signal is at the first level. 2. The PLL circuit according to claim 1, wherein the phase difference signal is selected when the output pulse signal is selected and the second level is selected. 3. A detection circuit which detects that the PLL circuit is erroneously locked and outputs a detection signal for a predetermined period after detection, and by supplying the detection signal as the control signal, the predetermined time in the multiplexer. 2. The PLL circuit according to claim 1, wherein an output pulse signal of the pulse generator is selected for a period, and the phase difference signal is selected after the lapse of the predetermined period.