JPH05218414A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To accomplish high integration and to lessen the consumption of power by a method wherein the lower surface of a second impurity layer is arranged on the equal position, where the impurity density of the first impurity layer becomes highest, or higher than that. CONSTITUTION:A first insulating film 102 is formed on a first conductive type semiconductor substrate 101 having the first impurity density, and a gate electrode 103 is formed thereon. By having the gate electrode 103 as an ion- implantation transmitting film, a first conductive type band-like first impurity layer 104, having first conductive type and second impurity density and formed in the second depth which is deeper than the first depth on both sides of the gate electrode 103, is formed in the first depth from the surface of the semiconductor substrate 101 on the lower part of the gate electrode 10. Also, by using the gate electrode 103 as a mask, the second impurity layer 105, which is located in the position where the impurity density of the first impurity layer 104, having the lower surface of third depth and formed in the first depth, becomes equal to the position where impurity density becomes highest or on the part higher than that, is formed on both sides of the gate electrode 103.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a semiconductor device, particularly a MOS.
The present invention relates to the structure and manufacturing method of a mold or MIS semiconductor device.

[0002]

2. Description of the Related Art In recent years, semiconductor devices have been increasingly miniaturized and highly integrated. The same applies to MOS type transistors, and the element size is being miniaturized to half micron.
As miniaturization progresses in this way, a punch-through phenomenon occurs in which a current flows between the source and the drain regardless of the gate voltage. In order to solve this problem, Japanese Patent Publication No. 54-16194, Japanese Patent Publication No. 53-127273, Japanese Patent Publication No. 60-180167, and Japanese Patent Publication No. 60-235471.
As is known in the art, a method of increasing the impurity concentration in a portion deeper than the surface of the semiconductor substrate as compared with the semiconductor substrate is generally known.
This will be described with reference to FIG. In FIG. 3, 301 is P
Type semiconductor substrate having impurities, 302 a gate insulating film,
Reference numeral 303 is a gate electrode, 304 is an impurity layer having a P-type impurity concentration higher than that of the semiconductor substrate 301, and 305 is a source / drain region made of an impurity layer having an N-type impurity.
Even if a depletion layer spreads from the drain by applying a voltage to the drain while the gate voltage does not reach the threshold voltage, the impurity layer 304 having a higher concentration of P-type impurities than the semiconductor substrate 301 causes the drain to semiconductor substrate side. The punch-through phenomenon is suppressed by suppressing the extension of the depletion layer into the.

[0003]

However, in the conventional semiconductor device, if an impurity layer 304 having a P-type impurity with a higher concentration than that of the semiconductor substrate 301 is formed in the vicinity of the channel in order to suppress punch-through, the N in the drain region is reduced.
Type semiconductor substrate 301 on the entire lower surface of the impurity layer having type impurities
Since the impurity layer 304 having a higher concentration of P-type impurities is formed, not only the drain breakdown voltage is lowered, that is, the leak current is increased, but also the electrical capacitance of the PN junction of the drain is increased to form a semiconductor circuit. In that case, there is a problem that the delay time increases. That is, in order to suppress the punch-through phenomenon, it is better that the impurity layer 304 having a higher concentration of P-type impurities than the semiconductor substrate 301 is closer to the surface of the semiconductor substrate, but the decrease in drain breakdown voltage and the increase in electrical capacity are suppressed. To achieve this, semiconductor substrate 301
There is a problem that it is difficult to perform optimization because the impurity layer 304 having a higher concentration of P-type impurities should be farther from the surface of the semiconductor substrate, which has contradictory characteristics.

[0004]

A semiconductor device of the present invention is a semiconductor substrate of a first conductivity type having a first impurity concentration, a gate electrode formed on the semiconductor substrate via a first insulating film, A second depth deeper than the first depth from the surface of the semiconductor substrate in the semiconductor substrate under the gate electrode, and a depth deeper than the first depth in the semiconductor substrate on both sides of the gate electrode. A band-shaped first impurity layer having a first conductivity type and a second impurity concentration formed at a depth, and a third depth from a surface of the semiconductor substrate in the semiconductor substrate on both sides of the gate electrode. Of the second conductivity type having the third impurity concentration and the position of the lower surface is equal to or higher than the position where the impurity concentration of the first impurity layer formed at the first depth is maximum. Having a second impurity layer The features.

The method of manufacturing a semiconductor device according to the present invention is the first
Forming a first insulating film on a conductive type semiconductor substrate having a first impurity concentration; forming a gate electrode on the first insulating film; and using the gate electrode as one of ion implantation / transmission films. By doing so, in the lower portion of the gate electrode, the first depth from the surface of the semiconductor substrate in the semiconductor substrate is smaller than that in the semiconductor substrate on both sides of the gate electrode from the surface of the semiconductor substrate. A step of forming a band-shaped first impurity layer having a first impurity type and a second impurity concentration formed at a deep second depth by an ion implantation method, and using the gate electrode as a mask The second conductivity type is formed in the semiconductor substrate on both sides so as to be separated from each other at a third depth from the surface of the semiconductor substrate, has a third impurity concentration, and a lower surface is formed at the first depth. Was first The second impurity layer impurity concentration of the impurity layer is present at a position equal to or upper of maximum, characterized in that it comprises a step of forming by ion implantation.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The semiconductor device of the present invention basically has a structure as shown in FIG. FIG. 1 is a sectional view of a semiconductor device of the present invention. 101 is a semiconductor substrate having impurities of the first conductivity type, for example, a P-type semiconductor substrate containing silicon as a main component, 102 is an insulating film such as a silicon oxide film, 10
Reference numeral 3 is a gate electrode, 104 is an impurity layer having a higher concentration of impurities of the first conductivity type than the semiconductor substrate 101, for example, a P-type impurity layer, and 105 is an impurity layer having impurities of the second conductivity type, for example, an N-type impurity layer. Source / drain regions.

Details will be described below while following the steps.
(Refer to FIG. 2) First, a semiconductor substrate of the first conductivity type, here P
Element isolation regions are formed on the silicon substrate 201 by a known technique. Next, the gate oxide film 202 is formed by performing high temperature oxidation of about 850 ° C. to 1000 ° C. in an oxidizing atmosphere. Next, a gate electrode material, here, a polycrystalline silicon film having a thickness of 300 nm is formed by a CVD method, and then a photolithography step and an etching step are performed to form a gate electrode 203 as shown in FIG. Next, as shown in FIG. 2B, the gate electrode is used as one of the ion-implanted permeable films, and a P-type impurity such as boron is used.
acceleration voltage of keV to 500 keV, 1 × 10 ¹² cm ⁻²
The P-type impurity layer 204 is formed by performing ion implantation with a dose amount of 1 × 10 ¹⁴ cm ⁻² . Here, in the semiconductor substrate 201 below the gate electrode 203, since the gate electrode 203 and the gate oxide film 202 serve as an ion implantation / transmission film, the impurity concentration of the P-type impurity layer 204 is 0.7 μm from the semiconductor substrate surface. In the semiconductor substrate 201 on both sides of the gate electrode 203, the gate oxide film 203 serves as an ion implantation / transmission film, so that the depth is about 0.3 μm deeper than that under the gate electrode 203, that is, the semiconductor substrate surface 201. To 0.3 μm
The maximum impurity concentration of the P-type impurity layer 204 is in the range of up to 1.1 μm. Next, using the gate electrode 203 as a mask, N-type impurities such as arsenic are ion-implanted at a dose amount of 1 × 10 ¹⁶ cm ⁻² and an acceleration voltage of 40 keV to 100 keV to form the source / drain regions 205 of the N-type impurity layer. Form. At this time, the depth of the source / drain region formed by the N-type impurity layer is 0.1 μm from the surface of the semiconductor substrate.
It is m to 0.4 μm. By forming the semiconductor device as described above, the source / drain regions 205 are formed.
The lower surface of the semiconductor substrate 20 on both sides of the gate electrode 203.
1 is in contact with the upper surface of the P-type impurity layer 204 or the lower surface of the source / drain region 205 is formed above the P-type impurity layer 204 formed in the semiconductor substrate 201 on both sides of the gate electrode 203. Will be.
Next, in order to activate the impurities in the impurity layer, 800 ° C to 1
Anneal at 100 ° C.

According to the above-described semiconductor device of the present invention, even if the voltage applied to the drain is applied in the state where the gate voltage does not reach the threshold voltage, the P concentration in the semiconductor substrate below the gate electrode is higher than that in the semiconductor substrate. If the position where the impurity concentration of the impurity layer 204 having the type impurities is maximum is deeper than the source / drain region, the punch-through phenomenon is less likely to occur because the extension of the depletion layer of the drain to the source side is suppressed. However, if the position where the impurity concentration of the impurity layer 204 having a higher concentration of P-type impurities is higher than that of the semiconductor substrate is too deep, the extension of the depletion layer of the drain to the source side cannot be suppressed and the punch through phenomenon is likely to occur. Become. On the other hand, by deepening the position where the maximum impurity concentration of the P-type impurity layer 204 in the semiconductor substrate under the gate electrode is deep, the position where the avalanche phenomenon due to the drain electric field occurs near the drain becomes deep from the surface of the semiconductor substrate. It is known that the deterioration of device characteristics due to the carrier phenomenon is reduced. However, since the position where the avalanche phenomenon occurs does not change even if the position where the maximum impurity concentration of the P-type impurity layer 204 is deeper than a certain extent is maintained, the deterioration of the device characteristics due to the hot carrier phenomenon does not change. For the above reason, the position where the impurity concentration of the P-type impurity layer 204 is maximum in the semiconductor substrate below the gate electrode has an optimum range, and the range is 0.2 μm to 0.7 μm from the semiconductor substrate surface. Preferably, more preferably 0.3 μm to 0.5 μm
Is good.

Further, in the semiconductor substrate on both sides of the gate electrode, the P-type impurity layer 204 is not effective in suppressing the punch through phenomenon and preventing the deterioration of the device characteristics due to the hot carrier phenomenon. Moreover, if the position where the impurity concentration of the P-type impurity layer 204 having a higher concentration than that of the semiconductor substrate 201 is maximum is shallow, the extension of the depletion layer from the drain region to the semiconductor substrate side is suppressed when a voltage is applied to the drain. Therefore, it is known that the breakdown voltage of the drain decreases. In the semiconductor device of the present invention, in the semiconductor substrate on both sides of the gate electrode, the position where the impurity concentration of the P-type impurity layer 204 is maximum is formed at a position deeper by about 0.3 μm than in the semiconductor substrate below the gate electrode. Therefore, the drain breakdown voltage can be prevented from lowering.

Although boron is used as the impurity used in forming the P-type impurity layer in the embodiment, the present invention is not limited to this, and aluminum, gallium, or indium may be used, or boron may be used. These impurities may be used in combination, such as aluminum and aluminum. Similarly, in this embodiment, arsenic is used as the impurity used when forming the N-type impurity layer, but the present invention is not limited to this, and phosphorus or antimony may be used, or arsenic and phosphorus. These impurities may be used in combination. Although a polycrystalline silicon film is used for the gate electrode as an example here, the present invention is not limited to this and may be a refractory metal such as titanium, molybdenum, or tungsten, or a semiconductor film such as a polycrystalline film. A refractory metal polycide film in which a refractory metal such as titanium, molybdenum, or tungsten is formed on the silicon film, or a refractory metal silicide film may be used.

[0011]

According to the semiconductor device and the method of manufacturing the semiconductor device of the present invention, the punch-through phenomenon hardly occurs.
Not only is it possible to miniaturize OS-type transistors,
Element characteristics are not deteriorated due to the hot carrier phenomenon, and further, the drain withstand voltage can be improved and the junction leak can be reduced, so that the semiconductor device can be highly integrated, the reliability can be improved, and the power consumption can be reduced.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of a semiconductor device of the present invention.

FIG. 2 is a cross-sectional view showing main steps of a method for manufacturing a semiconductor device of the present invention.

FIG. 3 is a cross-sectional view of a conventional semiconductor device.

[Explanation of symbols]

101, 201, 301 Semiconductor substrate having impurities of the first conductivity type 102, 202, 302 Insulating films 103, 203, 303 Gate electrodes 104, 204, 304 Impurity layer of the first conductivity type 105, 205, 305 Second conductivity type Impurity layer

Claims (2)

[Claims] 1. A semiconductor substrate of a first conductivity type having a first impurity concentration, a gate electrode formed on the semiconductor substrate via a first insulating film, and in the semiconductor substrate below the gate electrode. A first conductivity type formed at a first depth from the surface of the semiconductor substrate, and at a second depth deeper than the first depth from the surface of the semiconductor substrate in the semiconductor substrate on both sides of the gate electrode. A strip-shaped first impurity layer having a second impurity concentration, spaced apart from each other in the semiconductor substrate on both sides of the gate electrode, and separated from the semiconductor substrate surface by a third region.
Of the second conductivity type having the third impurity concentration formed at the depth of, and the position of the lower surface is equal to or higher than the position where the impurity concentration of the first impurity layer formed at the first depth has the maximum value. A semiconductor device having a second impurity layer existing in the semiconductor device. 2. A step of forming a first insulating film on a semiconductor substrate of a first conductivity type having a first impurity concentration, a step of forming a gate electrode on the first insulating film, and a step of forming the gate electrode. By using one of the ion-implanted and permeable membranes, the semiconductor substrate surface in the semiconductor substrate below the gate electrode is at a first depth from the semiconductor substrate surface, and in the semiconductor substrate on both sides of the gate electrode is the semiconductor substrate surface. From the first depth to a second depth deeper than the first depth, a band-shaped first impurity layer having a first impurity type and a second impurity concentration is formed by an ion implantation method, and the gate electrode is used as a mask. As a result, the second conductivity type third impurity concentration is formed in the semiconductor substrate on both sides of the gate electrode so as to be spaced apart from each other at a third depth from the surface of the semiconductor substrate, and the position of the lower surface is the first. Depth of 1 The method of manufacturing a semiconductor device in which the impurity concentration of the first impurity layer is characterized in that it comprises a step of the second impurity layer is formed by ion implantation at the position equal to or upper which maximizes formed.