JPH05218363A - Ecl gate array - Google Patents

Abstract

PURPOSE:To realize an ECL gate array which can operate at a higher speed than that of an ECL gate array formed only by an ECL gate circuit and an ECL gate circuit with APD. CONSTITUTION:An internal cell 11 can selectively be formed as any one of an ECL gate circuit or ECL gate circuit with APD which show the equal power consumption depending on a wiring pattern. Moreover, the corresponding input/ output terminal positions are set equally. Thereby, a gate circuit ensuring higher operation speed of the ECL gate circuit or ECL gate circuit with APD is used, after completion of automatic layout design, depending on the condition that both two outputs 8A, 8B which are complementary to a load capacity CL of each gate circuit are used or only one of these outputs is used.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit used in an information processing device, and more particularly to an ECL gate array.

[0002]

2. Description of the Related Art Generally, ECL (Emitter Co
The gate array 1 includes an internal cell region 3 in which internal cells 2 are arranged in an array and an input / output cell region 4 in which input / output cells 4 are arranged along four sides of the ECL gate array 1 as shown in FIG. 5 and is provided with a pad 6 for electrical connection. This internal cell 2 is
Usually, various elements are arranged so that one cell can form one gate. The input / output cell 4 is an input buffer,
Various elements for arranging an output buffer and an input / output buffer are arranged.

A desired function is realized by connecting these elements in a wiring process of a gate array manufacturing process. The conventional ECL gate array 1 is
The internal cell 2 has a transistor and a resistor as shown in FIG. 7A, and is connected as shown in FIG. 7B by a wiring pattern to form an ECL gate circuit. The ECL gate circuit shown in FIG. 7B has input terminals 7A and 7B.
In the negative logic, an AND output is obtained at the output terminal 8A and a NAND output is obtained at the output terminal 8B according to the input signals applied to 7C and 7C.

In this way, output signals complementary to each other are obtained from the output terminals 8A and 8B, which is a characteristic of the ECL gate circuit together with high speed. In such an ECL gate circuit, the delay time of the gate circuit becomes long when the output falls from a high level to a low level. This will be further described with reference to FIG. 7B. The load of the ECL gate circuit is the E of the next stage.
It is the wiring capacity up to the CL gate circuit and the input capacity of the ECL gate circuit in the next stage.
It is represented by.

Therefore, when the output rises, the load capacitance CL is charged by the transistor T1 which is an active element, so that the load driving capability is high and the delay time of the gate circuit is short, but when the output falls, this Since the load capacitance CL is discharged through the resistor R1 which is a passive element, the load driving capability is low and the delay time of the gate circuit is long. To improve this, the resistance value of the resistor R1 may be reduced and the current may be increased, but the power consumption also increases, and the degree of integration cannot be increased.

In FIGS. 7A and 7B, T2 to T7 are transistors and R2 to R6 are resistors. In addition, recently, in order to improve the defect of the ECL gate circuit that the load driving capability is low when the output falls, an APD (Active Pull) that rapidly discharges the load capacitance using an active element even when the output falls is also provided.
Various ECL gate circuits with Down have been proposed.

FIG. 8 is a circuit diagram showing a conventional ECL gate circuit with an APD, which is described in the literature (IS of 1989 IEEE).
SCC's DIGEST of TECHNICAL P
APERS, PP. 224-225). This ECL gate circuit with APD has a load capacitance CL
When charging the battery, that is, when the output rises,
When the transistor 9A operates to discharge the load capacitance CL, that is, when the output falls, the transistor 9A
B works.

Conventionally, it has been considered that such an ECL gate circuit with an APD always operates at a higher speed than a normal ECL gate circuit when compared at the same power consumption.
It was thought that the fastest ECL gate array could be realized by using the ECL gate circuit with APD for the internal cells of the CL gate array.

[0009]

DISCLOSURE OF THE INVENTION The above-mentioned conventional ECL
In the gate array, when comparing the same power consumption, A
We believe that the ECL gate circuit with PD will always operate faster than the ECL gate circuit. Depending on the load capacity driven by the gate circuit and the usage of the output of the gate circuit, the ECL gate circuit with APD will operate at a higher speed. However, when compared with the same power consumption, there is a problem that the fastest ECL gate array cannot be realized.

[0010]

An ECL gate array according to the present invention has a structure in which an internal cell of the gate array can arbitrarily select either the ECL gate circuit or the ECL gate circuit with APD according to a wiring pattern. To do. The ECL gate circuit is selected and constructed in a region where the load capacitance driven by the gate circuit is small and the ECL gate circuit operates faster than the ECL gate circuit with APL. When only one of the two complementary outputs of the gate circuit is used, the ECL gate circuit with APD that operates faster than the ECL gate circuit is selected and configured. Further, the input / output terminal position of the ECL gate circuit and the input / output terminal position of the ECL gate circuit with APD are made the same.

[0011]

The present invention relates to an ECL gate circuit and an EC with APL.
By properly using the L gate circuit according to the size of the load capacitance and the usage state of the output, it is possible to provide an ECL gate array that operates at higher speed with the same power consumption.
Further, by making the input / output terminal position of the ECL gate circuit the same as the input / output terminal position of the ECL gate circuit with APD, the ECL gate circuit and the gate with APD can be processed even after the computer finishes the automatic placement and wiring process of the gate circuit. The circuit can be arbitrarily replaced.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is an element layout diagram of an internal cell showing an embodiment of an ECL gate array according to the present invention, and particularly shows the element layout of transistors, resistors and capacitors. In the figure, T10 to T22 are transistors, and R10 to R.
Reference numeral 19 is a resistor, and C2 and C3 are capacitors. Then, an ECL gate circuit is prepared by using the internal cell 11 of the ECL gate array of this embodiment, and is shown in FIG. In this case, the transistors T10, T14 to T18
And T21, resistors R10, R13 to R16 and R1.
9 is used.

FIG. 2B shows a gate circuit with an APD formed by using the internal cell 11 of the ECL gate array of this embodiment. In this case, the transistor T1
0 to T22, resistors R11 to R18, and capacitors C2 and C3 are used. The internal cells 11 can be arranged in a matrix to form the internal cell region 3 of the ECL gate array.

Thus, using the embodiment of FIG. 1, EC
Either the L gate circuit (see FIG. 2 (A)) or the ECL gate circuit with APD (see FIG. 2B) can be arbitrarily selected by the wiring pattern, and the corresponding input / output terminal position is relative to the origin 12. Set to be equal. Furthermore, this ECL gate circuit (see FIG. 2A) and APD
The power consumption of the ECL gate circuit with a switch (see FIG. 2B) is set to be equal.

Further, in FIG. 3, the horizontal axis represents the load capacitance CL [P
F], and the vertical axis represents the gate delay time TD [ns], the operating speed with respect to the load capacitance of the ECL gate circuit and the ECL gate circuit with APD, that is, the gate delay time characteristics. In the figure, L1 shows the delay time characteristic of the ECL gate circuit, L2 shows the delay time characteristic of the ECL gate circuit with APD, and L3 shows the ECL with ECL.
The output delay time characteristic of one side of the gate circuit is shown.

As described above, in the region where the load capacity is large,
It operates faster than the ECL gate circuit with APD, but when the load capacitance is small, this reverses and the ECL gate circuit operates faster. In addition, FIG.
FIG. 2B shows a circuit configuration when only one of the two complementary outputs is used in the ECL gate circuit with APD (see FIG. 2B). The one-sided output delay time characteristic at this time can be represented by L3 (see FIG. 3), and is always faster than the ECL gate circuit regardless of the load capacitance.

FIG. 5 is a schematic flow chart for designing an integrated circuit having a certain function by using the ECL gate array of the embodiment shown in FIG. First, in step S1, the specification is decided,
In step S2, functional design is performed, and in step S3, gate-level logic design is performed to design connections between gates to realize the function. Then, in step S4, the layout design for designing the wiring pattern of the gate array is started.
Recently, automatic layout by computer, that is, automatic placement and routing design has been widely used.

In step S5, since the actual wiring length between the gates is known by the layout design, the load capacitance of each gate is calculated from this wiring length and the fanout number of the gate. In step S6, of the two outputs that are complementary to each other,
If the gate uses only one side (NO), A
ECL gate circuit with PD is used. If the gate uses two outputs complementary to each other (YES), the process further proceeds to step S7.

In step S7, the load capacity is 0.1 [P
When it exceeds F] (YES), the ECL gate circuit with APD is used, and when the load capacitance does not exceed 0.1 [PF] (NO), the ECL gate circuit is used. here,
Even if the automatic layout design is completed and the wiring between the gates is completed, since the input / output terminal positions of the ECL gate circuit and the ECL gate circuit with APD are the same, the ECL gate circuit and the APD are included. The ECL gate circuit can be arbitrarily replaced on the layout data in which the wiring between the gates is completed.

The operating speed of the ECL gate circuit and the gate circuit with APD, that is, the load capacitance at which the gate delay time is reversed is 0.1 [PF] in the present embodiment.
It goes without saying that this changes depending on the power consumption of the gate circuit and the circuit constant.

[0021]

As described in detail above, according to the ECL gate array of the present invention, the internal cells of the ECL gate array can be arranged in either the ECL gate circuit or the ECL gate circuit with APD depending on the wiring pattern. Can be configured to.

Further, by making the corresponding input / output terminal positions equal, the actual wiring length between the gates after the completion of the automatic layout design, the load capacitance of the gate calculated by the fan-out number, and the complementary gates ECL gate circuit or ECL with APD depending on whether only one of the two outputs is used or both are used
By using the gate circuit or the faster one,
When compared with the same power consumption, there is an effect that a higher-speed ECL gate array can be realized as compared with the case where only the ECL gate circuit is used or the case where only the ECL gate circuit with APD is used.

[Brief description of drawings]

FIG. 1 is a device layout diagram of an internal cell showing an embodiment of an ECL gate array according to the present invention.

FIG. 2 is a diagram showing an ECL gate circuit and an ECL gate circuit with APD configured by using the device of FIG.

FIG. 3 is a diagram showing a gate delay time characteristic in each circuit of FIG.

FIG. 4 is a diagram configured by using only one of two complementary outputs of the ECL gate circuit with APD.

FIG. 5 is a diagram showing a schematic design flow when the ECL gate array of the present invention is used.

FIG. 6 is a diagram showing an internal configuration of a general ECL gate array.

FIG. 7 is a diagram showing a configuration of an internal cell of a conventional ECL gate array.

FIG. 8 is a circuit diagram showing an example of an ECL gate circuit with APD.

[Explanation of symbols]

 11 Internal Cell 12 Origin T10-T22 Transistor R10-R19 Resistor C2, C3 Capacitor

Claims (4)

[Claims] 1. In an ECL gate array including at least an internal cell region including a plurality of internal cells and an input / output cell region including a plurality of input / output cells, the internal cells forming the internal cell region are interconnected. An ECL gate array, wherein either an ECL gate circuit or an ECL gate circuit with APD can be arbitrarily selected depending on a pattern. 2. The ECL gate circuit with APD is selected when the internal cell drives a load capacitance exceeding a preset load capacitance value.
ECL gate array. 3. The ECL gate array according to claim 1, wherein the internal cell has the same input / output terminal position as an ECL gate circuit and the same input / output terminal position as an ECL gate circuit with APD. 4. When using only one of two types of outputs which are complementary to each other, the internal cell is set to APD.
2. An ECL gate circuit with a switch.
ECL gate array.