JPH05218351A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To enable maintaining of sensitivity of a column decoder, even when a memory cell array is given a high integration density, by setting an arrangement pitch of column decoders for selecting bit lines in the word line direction larger than that of a bit line group selected by column decoders in the word line direction. CONSTITUTION:A memory cell array MA is formed by arranging the connected memory cells at the crossing points of word lines and bit lines. A column decoder 4 selects bit lines depending on an address signal and each bit line of a plurality of bit line groups consisting of the one or more bit lines is selected by each column decoder 4. Here, the arrangement pitch of the column decoder 4 in the word line direction is set larger than that of the bit line group in the word line direction. The region of the column decoder array 40 expanded by forming the column decoder 4 in the wider region is absorbed by the side of the lined region SNT between the memory cell arrays MA and the chip area is not increased.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device having an improved arrangement of column decoders.

[0002]

2. Description of the Related Art DRAM which is one of semiconductor memory devices
(Dynamic Random Access Me
A memory) has a word line arranged in one direction and a bit line arranged in two directions intersecting with the one direction. A memory cell is formed at each intersection of the word line and the bit line, and the memory cell is connected to the word line and the bit line. This DRAM
Further has a column decoder, and the column decoder selects a bit line according to the address signal from the plurality of bit lines.

The plurality of bit lines are divided into a plurality of bit line groups each consisting of one or more bit lines, and each of the bit line groups corresponds to a bit line group of the plurality of column decoders. Selected by the column decoder. The column decoder selects a bit line group from the plurality of bit line groups according to the address signal and connects the bit line of the selected bit line group to the input / output line.

FIG. 3 shows the arrangement of the memory cell array MA and the column decoder 14 in the conventional DRAM.
Each bit line group not shown in FIG.
It consists of 4 bit line pairs. In this case, the column decoder 14 shown in FIG.
Memory cell row (composed of 8 rows of memory cells)
Are placed at the same intervals as. In this DRAM, data of four pairs of memory cells are simultaneously read to the input / output line (I / O line), or data of four pairs of memory cells are simultaneously written to the input / output line (I / O line). ..

With the high integration of DRAMs, the length of word lines is extended, and the delay of signals transmitted on the word lines becomes a problem. Usually the word line is
The wiring is formed of a polycrystalline silicon film (polysilicon gate), or the wiring formed of a polycrystalline silicon film and a silicide film formed thereon (polycide gate). These films have a melting point higher than that of an Al (aluminum) film and therefore have an advantage of being suitable for a self-aligned gate process, and are therefore used as a word line material. However, these films have the drawback of having a higher specific resistance than Al films. Therefore, in order to solve the problem of the signal delay in the word line formed of these films, by connecting the Al wiring formed above the word line (in the upper layer) and the word line in the lower layer at a plurality of points. A technique (so-called Al lining technique) that reduces the wiring resistance as a whole and prevents signal delay is adopted. The lining region SNT is a memory cell array M
It is provided between A.

[0006]

Since the column decoders 14 are arranged at a pitch eight times that of each memory cell, the width of the column decoder 14 in the word line direction depends on the size of the memory cell column M. It is restricted. Therefore, in order to increase the area of the column decoder 14, it is necessary to increase the area in the bit line direction.

Further, since the lining region SNT is provided between the memory cell arrays MA, a dummy pattern or a step reducing pattern of the memory cell is required, and occupies a relatively large area on the chip. In particular, when using the stack type memory cell, the capacitor is formed in the upper layer of the MOS transistor, so that the step between the region of the memory cell array MA and the lining region SNT becomes large, and a wide step reducing pattern is required. Become. Conventionally, the side of this wide backing area SNT has not been used as an empty area.

In view of the above-mentioned circumstances, the present invention maintains the sensitivity of the column decoder by forming the column decoder in a wide width without being confined to the formation region of the memory cell array even if the memory cell array is highly densified. It is an object of the present invention to provide a semiconductor memory device that can be manufactured.

[0009]

A semiconductor memory device according to the present invention includes a word line arranged in one direction, bit lines arranged in two directions intersecting the one direction, and the word line. A semiconductor including a memory cell formed at each intersection with the bit line and connected to the word line and the bit line, and a column decoder that selects a bit line of the bit lines according to an address signal. A storage device, wherein the bit lines are divided into a plurality of groups each of which is composed of one or more bit lines, each of the groups being selected by a column decoder corresponding to the group of the column decoders. The arrangement pitch of each of the column decoders in the one direction is larger than the arrangement pitch of each of the groups in the one direction, thereby achieving the above object.

[0010]

With the above structure, the width of the memory cell column forming region (width in the word line direction) and the number of bit lines (bit number) selected by one column decoder are not limited to each column decoder. The width of the formation region (width in the word line direction) can be increased. Therefore, according to the semiconductor memory device of the present invention, even when the memory cell array is formed at a high density due to the increase in capacity, it is possible to secure a formation region having a sufficient area for the column decoder.

When the width of the formation region of the column decoder is widened according to the present invention, the formation region of the column decoder array formed by arranging a large number of memory cells in the width direction is larger than the length of the memory cell array formed by arranging a plurality of memory cells in the width direction. Will be longer. However, the portion where the formation region of the column decoder array extends from the formation region of the memory cell array can be absorbed in relation to the other circuit regions at both ends on the chip. When the memory cell array is divided and word line lining areas are formed between the memory cell arrays, the side areas of the lining area are conventionally empty areas. Therefore, the column decoder can be used up to this empty area. If it is formed, it is possible to absorb the protruding portion from the memory cell array. Therefore, the present invention hardly increases the chip area of the semiconductor memory device.

[0012]

EXAMPLES The present invention will be described below with reference to examples. As shown in FIG. 2, the semiconductor memory device according to the present embodiment has a word line 1 arranged in one direction (A) and a bit line arranged in two directions (B) intersecting the one direction. 2 and 2. A memory cell 3 is formed at each intersection of the word line 1 and the bit line 2. The memory cells 3 are arranged in a matrix to form a memory cell array. Each memory cell 3 is connected to a corresponding word line 1 and bit line 2.

This semiconductor memory device has a column decoder 4, and the column decoder 4 selects a bit line 2 according to an address signal from a plurality of bit lines 2. The circuit configuration in the column decoder 4 is basically the same as the conventional circuit configuration, and is not shown in FIG.

The plurality of bit lines 2 includes a plurality of bit line groups 20 each including one or more bit lines 2.
Each of the bit line groups 20 is selected by each column decoder 4 corresponding to the bit line group 20 of the plurality of column decoders 4. The column decoder 4 selects the bit line group 20 from the plurality of bit line groups 20 according to the address signal (transmitted on the address signal line 6), and the bit line 2 of the selected bit line group 20. Is connected to the input / output line 5 via the switching element 7. In this embodiment, each bit line group 2
0 consists of 4 pairs of bit lines. In FIG. 2, one bit line group 20 and one column decoder 4 corresponding to the bit line group 20 are shown.

The arrangement pitch (8.0 μm) in each word line group 20 in the word line direction (A) is defined by the total width in the word line direction of the memory cells 3 in eight columns connected to four bit line pairs. It In the present embodiment, the arrangement pitch of each of the plurality of column decoders 4 in the word line direction is 8.8 μm, which is larger than the arrangement pitch of each of the bit line groups 20 in the word line direction.

FIG. 1 schematically shows the arrangement of memory cells and column decoders in the embodiment. As shown in FIG. 1, the memory cell array is divided into a plurality of memory cell arrays MA, and a lining region SNT provided between the memory cell arrays MA lines the word lines. Conventionally, the side of the wide backing area SNT has not been used as an empty area, but in the present embodiment, as shown in FIG. 1, the column decoder arrays 40 corresponding to the respective memory cell arrays MA are respectively formed. It is formed so as to extend to the side of this lining region SNT. Therefore, the memory cell array SNT and the column decoder array 4 are
Since the deviation of the length of 0 is absorbed on the side of the lining region SNT, there is no fear of increasing the chip area by forming the column decoder 4 in a wide region in the word line direction. As described above, since each column decoder 4 of this embodiment corresponds to eight columns of memory cells, each memory cell column M in FIG. 1 has eight columns not shown in FIG. Memory cells.

Generally, in a 64-megabit DRAM, the width of the backing region SNT in the word line direction needs to be about 1 to 10 μm. The width of the dummy cell region and the difference relaxation pattern region formed on both sides thereof is 4 to 8
About μm is necessary. The arrangement pitch of the memory cell columns is
0.8 to 1.0 μm, and the memory cell array M
In A, 128 to 512 memory cell columns are provided. Therefore, the memory cell array MA in the lining region SNT
The ratio of to 2.5 to 25%. In this embodiment, the width of the column decoder 4 in the word line direction is 2.5.
To 25% and the width in the bit line direction is reduced from 2.5 to 25%. Thus, as a result of the effective use of the lining region SNT, the area of the region where the column decoder is formed is reduced by 2.5 to 25%.

As described above, according to this embodiment, each column decoder 4 can be formed wider than its forming region. Moreover, since the expansion of the area of the column decoder array 40 due to the column decoder 4 being formed in a wide area is absorbed by the side of the lining area SNT between the memory cell arrays MA, the chip area is increased. Nor.

[0019]

As is apparent from the above description, according to the semiconductor memory device of the present invention, the column decoder can be formed without being restricted by the arrangement pitch of the memory cell forming regions. Moreover, the expansion of the area of the column decoder array due to the formation of the column decoder in a wide area is
The chip area does not increase due to absorption on the side of the lining region between the memory cell arrays.

[Brief description of drawings]

FIG. 1 is a plan view showing the arrangement of memory cells and column decoders in an embodiment of the present invention.

FIG. 2 is a plan view schematically showing the arrangement of memory cell arrays and column decoders in the embodiment.

FIG. 3 is a plan view showing an arrangement of memory cells and column decoders in a conventional example.

[Explanation of symbols]

 1 word line 2 bit line 3 memory cell 4, 14 column decoder 20 bit line group 40 column decoder array M memory cell column MA memory cell array SNT backing region

Claims (1)

[Claims] 1. A word line arranged in one direction, a bit line arranged in two directions intersecting the one direction, and formed at each intersection of the word line and the bit line, What is claimed is: 1. A semiconductor memory device comprising: a memory cell connected to the word line and the bit line; and a column decoder that selects a bit line of the bit lines according to an address signal. Are divided into a plurality of bit line groups consisting of one or more bit lines, and each of the bit line groups is selected by a column decoder corresponding to the bit line group of the column decoders. A semiconductor memory device, wherein an arrangement pitch in each of the one directions is larger than an arrangement pitch in each of the bit line groups in the one direction.