JPH05218130A - Tab type semiconductor device and manufacturing device therefor - Google Patents

Tab type semiconductor device and manufacturing device therefor

Info

Publication number
JPH05218130A
JPH05218130A JP4015818A JP1581892A JPH05218130A JP H05218130 A JPH05218130 A JP H05218130A JP 4015818 A JP4015818 A JP 4015818A JP 1581892 A JP1581892 A JP 1581892A JP H05218130 A JPH05218130 A JP H05218130A
Authority
JP
Japan
Prior art keywords
semiconductor device
type semiconductor
tab type
bump electrodes
lead
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4015818A
Other languages
Japanese (ja)
Inventor
Keiji Shibata
啓司 柴田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Semiconductor Manufacturing Co Ltd
Kansai Nippon Electric Co Ltd
Original Assignee
Renesas Semiconductor Manufacturing Co Ltd
Kansai Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Semiconductor Manufacturing Co Ltd, Kansai Nippon Electric Co Ltd filed Critical Renesas Semiconductor Manufacturing Co Ltd
Priority to JP4015818A priority Critical patent/JPH05218130A/en
Publication of JPH05218130A publication Critical patent/JPH05218130A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/50Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto

Landscapes

  • Wire Bonding (AREA)

Abstract

PURPOSE:To prevent a short-circuit and a decrease in a withstand voltage due to contact with a semiconductor pellet with longer inner lead in a TAB type semiconductor device having bump electrodes arranged in a zigzag manner. CONSTITUTION:A TAB type semiconductor device 20 has a semiconductor pellet 1 disposed in a through hole 2 of an insulation film 3 and long and short inner leads 15A, 15B extended from the film 3 connected at the ends to bump electrodes 14A, 14B formed in a zigzag manner on the surface. The height of the outer electrode 14A is formed higher than that of the inner electrode 14B, and a recess step 17 to be engaged with the longer lead 15B is formed correspondingly along the peripheral edge of a lead pressing surface of a bonding tool 16.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明はTAB式半導体装置及び
その製造装置に関し、詳しくは、絶縁フィルムの透孔内
に配置された半導体ペレットのバンプ電極と絶縁フィル
ムから延びるインナリードの先端とを接続したTAB式
半導体装置、及び上記半導体ペレットのバンプ電極とイ
ンナリードの先端とを一括して熱圧着するボンディング
ツールを具備したTAB式半導体装置の製造装置に関す
る。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a TAB type semiconductor device and a manufacturing apparatus therefor, and more particularly, it connects a bump electrode of a semiconductor pellet arranged in a through hole of an insulating film and a tip of an inner lead extending from the insulating film. The present invention relates to a TAB type semiconductor device and a TAB type semiconductor device manufacturing apparatus equipped with a bonding tool for collectively thermocompression bonding the bump electrode of the semiconductor pellet and the tip of the inner lead.

【0002】[0002]

【従来の技術】TAB〔Tape Automated Bonding 〕
式半導体装置(10)は、例えば、フレキシブルなフィル
ム状プリント基板等に組み付けられるカメラ用IC等に
使用される。その一例を図3乃至図5を示して説明す
る。
2. Description of the Related Art TAB [Tape Automated Bonding]
The semiconductor device (10) is used, for example, in a camera IC or the like mounted on a flexible film-shaped printed circuit board or the like. An example thereof will be described with reference to FIGS. 3 to 5.

【0003】図3の(A)(B)において、(1)は半
導体ペレット、(3)は絶縁フィルムからなる枠状フィ
ルム、(2)は枠状フィルム(3)に形成された透孔、
(4A)(4B)はAuの盛り上げメッキによって半導体ペ
レット(1)の配線パターン上に千鳥配置状態で形成さ
れたバンプ電極、(5A)(5B)は枠状フィルム(3)に
形成された金属箔からなるインナリードである。インナ
リード(5A)(5B)は、千鳥状に配置されたバンプ電極
(4A)(4B)と対応させて異なった長さを有し、その中
間部分を枠状フィルム(3)に接着した状態でそれぞれ
のインナリード(5A)(5B)の先端をバンプ電極(4A)
(4B)に熱圧着することによって、半導体ペレット
(1)を枠状フィルム(3)の内側に固定支持している。
In FIGS. 3A and 3B, (1) is a semiconductor pellet, (3) is a frame-shaped film made of an insulating film, (2) is a through hole formed in the frame-shaped film (3),
(4A) and (4B) are bump electrodes formed in a staggered arrangement on the wiring pattern of the semiconductor pellet (1) by pile-up plating of Au, and (5A) and (5B) are metal formed on the frame-shaped film (3). It is an inner lead made of foil. The inner leads (5A) (5B) have different lengths corresponding to the zigzag-shaped bump electrodes (4A) (4B), and the intermediate portion is bonded to the frame-shaped film (3). At the tip of each inner lead (5A) (5B) with bump electrode (4A)
The semiconductor pellet (1) is fixedly supported inside the frame film (3) by thermocompression bonding to (4B).

【0004】上記TAB式半導体装置(10)では、半導
体ペレット(1)における集積度の向上によりバンプ電
極(4A)(4B)の数が増加する傾向にあり、そのため、
上述したようにバンプ電極(4A)(4B)を千鳥状に配置
するようにしている。このTAB式半導体装置(10)の
製造において、図4に示すように上記バンプ電極(4A)
(4B)は、ブロック状のボンディングツール(6)を使
用することにより一括してそれぞれ対応するインナリー
ド(5A)(5B)の先端に熱圧着される。
In the TAB type semiconductor device (10), the number of bump electrodes (4A) and (4B) tends to increase due to the improvement in the degree of integration in the semiconductor pellet (1).
As described above, the bump electrodes (4A) and (4B) are arranged in a staggered pattern. In manufacturing the TAB semiconductor device (10), as shown in FIG. 4, the bump electrode (4A) is used.
(4B) are collectively thermocompression bonded to the tips of the corresponding inner leads (5A) (5B) by using a block-shaped bonding tool (6).

【0005】[0005]

【発明が解決しようとする課題】ところで、上記TAB
式半導体装置(10)の製造では、図5に示すように平坦
な加熱押圧面を具えたボンディングツール(6)を使用
している。一方、千鳥状に配置されたバンプ電極(4A)
(4B)にインナリード(5A)(5B)の先端を対応するバ
ンプ電極(4A)(4B)上に熱圧着しようとすると、イン
ナリード(5A)(5B)の先端の長さが異なっているた
め、内側のバンプ電極(4B)上に延びる長い方のインナ
リード(5B)の先端でのボンディングツール(6)によ
る受圧面積及びそれによる熱膨張が、外側のバンプ電極
(4A)上に延びる短い方のインナリード(5A)よりも大
きくなる。この結果、長い方のインナリード(5B)の先
端が変形し、半導体ペレット(1)の表面に形成された
配線パターンに接触し易くなり、短絡や耐電圧の低下等
の問題が引き起こされる。
By the way, the above-mentioned TAB
In manufacturing the semiconductor device (10), a bonding tool (6) having a flat heating and pressing surface is used as shown in FIG. On the other hand, bump electrodes (4A) arranged in a staggered pattern
When the tips of inner leads (5A) (5B) are attached to (4B) by thermocompression bonding to the corresponding bump electrodes (4A) (4B), the tips of the inner leads (5A) (5B) have different lengths. Therefore, the pressure receiving area by the bonding tool (6) at the tip of the longer inner lead (5B) extending on the inner bump electrode (4B) and the resulting thermal expansion are short on the outer bump electrode (4A). It is larger than the inner lead (5A). As a result, the tips of the longer inner leads (5B) are deformed and easily come into contact with the wiring pattern formed on the surface of the semiconductor pellet (1), which causes problems such as short circuit and reduction in withstand voltage.

【0006】[0006]

【課題を解決するための手段】上記課題の解決手段とし
て、本発明に係るTAB式半導体装置は、絶縁フィルム
の透孔内に半導体ペレットを配置し、その表面の周縁に
千鳥状に形成された複数のバンプ電極に上記絶縁フィル
ム上から延びるインナリードの先端部を接続したものに
おいて、複数のバンプ電極のうち、外側のバンプ電極を
内側のバンプ電極よりも高くしたことを特徴とする。
As a means for solving the above problems, in a TAB type semiconductor device according to the present invention, semiconductor pellets are arranged in the through holes of an insulating film, and are formed in a zigzag pattern on the periphery of the surface. In the one in which the tip end portion of the inner lead extending from above the insulating film is connected to the plurality of bump electrodes, the outer bump electrode is made higher than the inner bump electrode among the plurality of bump electrodes.

【0007】また、本発明に係るTAB式半導体装置の
製造装置は、上記半導体ペレットの内、外側のバンプ電
極に、各バンプ電極に対応して長さが異なるインナリー
ドの先端を一括して熱圧着するボンディングツールを具
備し、そのリード押圧面の周縁に沿って凹状の段差部を
形成したことを特徴とする。
In the TAB type semiconductor device manufacturing apparatus according to the present invention, the tips of the inner leads having different lengths corresponding to the bump electrodes are collectively heated to the bump electrodes on the outer side of the semiconductor pellet. It is characterized in that a bonding tool for crimping is provided, and a concave step portion is formed along the periphery of the lead pressing surface.

【0008】[0008]

【作用】本発明では、外側のバンプ電極を内側のバンプ
電極よりも高くしたこと、及びボンディングツールのリ
ード押圧面の周縁に沿って凹状の段差部を形成したこと
により、上記内外側のバンプ電極にインナリードの先端
部を一括して熱圧着する時、内側のバンプ電極に向って
延びる長い方のインナリードを上記凹状の段差部内に位
置させることによって、長い方のインナリードが半導体
ペレット表面の周縁に接触することを未然に防止する。
According to the present invention, the outer bump electrode is made higher than the inner bump electrode, and the concave step portion is formed along the periphery of the lead pressing surface of the bonding tool. When the tips of the inner leads are collectively thermocompressed to each other, the longer inner leads extending toward the inner bump electrodes are positioned in the concave stepped portion, so that the longer inner leads are formed on the surface of the semiconductor pellet. Prevents contact with the peripheral edge.

【0009】[0009]

【実施例】以下、図1及び図2(A)(B)に基づいて
本発明の一実施例を説明する。尚、以下の記述におい
て、従来技術を示す図3乃至図5と同一の構成部材は同
一の参照番号で表示し、重複する事項に関しては説明を
省略する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. 1 and 2A and 2B. In the following description, the same components as those of FIGS. 3 to 5 showing the conventional technique are denoted by the same reference numerals, and the description of the overlapping matters will be omitted.

【0010】TAB式半導体装置(20)は、表面にバン
プ電極(14A)(14B)を千鳥状に整列させた半導体ペレ
ット(1)と、枠状フィルム(3)を、長さの異なるイン
ナリード(15A)(15B)と上記バンプ電極(14A)(14
B)との熱圧着によって接合一体化したものであるが、
図1に拡大して図示するように、短い方のインナリード
(15A)の先端部が熱圧着される外側のバンプ電極(14
A)の高さが、長い方のインナリード(15B)の先端部が
熱圧着される内側のバンプ電極(14B)に比較して高く
なるようにAuの盛り上げメッキ条件を調節する。
The TAB type semiconductor device (20) comprises a semiconductor pellet (1) having bump electrodes (14A) and (14B) arranged in a staggered pattern on the surface and a frame-shaped film (3), and inner leads of different lengths. (15A) (15B) and the bump electrodes (14A) (14
Although it was joined and integrated by thermocompression bonding with B),
As shown in the enlarged view of FIG. 1, the tip of the shorter inner lead (15A) is thermo-compressed to the outer bump electrode (14A).
The height of Au plating is adjusted so that the height of A) is higher than that of the inner bump electrode (14B) to which the tip of the longer inner lead (15B) is thermocompression bonded.

【0011】一方、上記バンプ電極(14A)(14B)の高
さの差に対応して、ボンディングツール(16)の側で
は、リード押圧面の周縁に沿って凹状の段差部(17)を
形成する。図1に拡大して図示するように、ボンディン
グツール(16)がインナリード(15A)(15B)を押圧
し、熱圧着のための熱エネルギーを伝達するとき、枠状
フィルム(3)から内側のバンプ電極(14B)の上方に向
って延びる長い方のインナリード(15B)を上記凹状の
段差部(17)内に位置させ、この部分をボンディングツ
ール(16)の加熱押圧面から離すことによってインナリ
ード(15B)にボンディングツール(16)からの押圧力
及び熱エネルギーが伝達されない状態を作り出す。即
ち、高さの異なるバンプ電極(14A)(14B)に熱圧着さ
れる長短のインナリード(15A)(15B)の先端部のみに
ボンディングツール(16)からの押圧力及び熱エネルギ
ーが伝達される状態を作り出し、これによってボンディ
ング時に、長い方のインナリード(15B)の先端部と短
い方のインナリード(15A)の先端部とに略同等の熱圧
着条件を作り出す。この結果、長い方のインナリード
(15B)の変形が抑制され、両インナリード(15A)(15
B)の先端部は、対応するバンプ電極(14A)(14B)上
に一括して熱圧着される。
On the other hand, a concave step portion (17) is formed along the peripheral edge of the lead pressing surface on the side of the bonding tool (16) corresponding to the height difference between the bump electrodes (14A) and (14B). To do. As shown in the enlarged view of FIG. 1, when the bonding tool (16) presses the inner leads (15A) (15B) to transfer the heat energy for thermocompression bonding, the inner side of the frame film (3) The inner lead (15B), which is longer than the bump electrode (14B), is located inside the concave step (17) and is separated from the heating and pressing surface of the bonding tool (16). A state in which the pressing force and thermal energy from the bonding tool (16) are not transmitted to the leads (15B) is created. That is, the pressing force and the thermal energy from the bonding tool (16) are transferred only to the tips of the long and short inner leads (15A) (15B) which are thermocompression bonded to the bump electrodes (14A) (14B) having different heights. A state is created, and thereby, at the time of bonding, a substantially equal thermocompression bonding condition is created at the tip of the longer inner lead (15B) and the tip of the shorter inner lead (15A). As a result, the deformation of the longer inner lead (15B) is suppressed, and both inner leads (15A) (15A)
The tip end of B) is thermocompression bonded together on the corresponding bump electrodes (14A) (14B).

【0012】[0012]

【発明の効果】本発明によれば、内側のバンプ電極に熱
圧着される長い方のインナリードの変形が抑制されるか
ら、千鳥状に配置した多数のバンプ電極を有するTAB
式半導体装置において、インナリードの半導体ペレット
への接触による短絡や耐電圧の低下等が回避され、製品
歩留まりが大幅に向上すると共に高品質のTAB式半導
体装置を提供することができる。
According to the present invention, the deformation of the longer inner lead which is thermocompression-bonded to the inner bump electrode is suppressed, so that the TAB having a large number of bump electrodes arranged in a staggered pattern is formed.
In the semiconductor device, it is possible to avoid a short circuit, a decrease in withstand voltage, etc. due to the contact of the inner lead with the semiconductor pellet, to significantly improve the product yield, and to provide a high-quality TAB semiconductor device.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明に係るTAB式半導体装置とその製造装
置のボンディングツールを示す部分拡大断面図
FIG. 1 is a partially enlarged cross-sectional view showing a bonding tool of a TAB type semiconductor device and a manufacturing apparatus therefor according to the present invention.

【図2】(A)は図1のボンディングツールを示す正面
図、(B)は(A)のボンディングツールを示す底面図
2A is a front view showing the bonding tool shown in FIG. 1, and FIG. 2B is a bottom view showing the bonding tool shown in FIG.

【図3】(A)は従来のTAB式半導体装置を示す平面
図、(B)は(A)のTAB式半導体装置を示す断面図
3A is a plan view showing a conventional TAB type semiconductor device, and FIG. 3B is a sectional view showing the TAB type semiconductor device of FIG. 3A.

【図4】従来のTAB式半導体装置を示す部分拡大断面
FIG. 4 is a partially enlarged sectional view showing a conventional TAB semiconductor device.

【図5】(A)は図4のボンディングツールを示す正面
図、(B)は(A)のボンディングツールを示す底面図
5A is a front view showing the bonding tool shown in FIG. 4, and FIG. 5B is a bottom view showing the bonding tool shown in FIG.

【符号の説明】[Explanation of symbols]

1 半導体ペレット 2 透孔 3 枠状フィルム 14A バンプ電極 14B バンプ電極 15A インナリード 15B インナリード 16 ボンディングツール 17 凹状の段差部 20 TAB式半導体装置 1 Semiconductor pellet 2 Through hole 3 Frame film 14A Bump electrode 14B Bump electrode 15A Inner lead 15B Inner lead 16 Bonding tool 17 Recessed step 20 TAB type semiconductor device

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 絶縁フィルムの透孔内に半導体ペレット
を配置し、その表面の周縁に千鳥状に形成された複数の
バンプ電極に上記絶縁フィルム上から延びるインナリー
ドの先端部を接続したものにおいて、複数のバンプ電極
のうち、外側のバンプ電極を内側のバンプ電極よりも高
くしたことを特徴とするTAB式半導体装置。
1. A structure in which a semiconductor pellet is arranged in a through hole of an insulating film, and a plurality of bump electrodes formed in a zigzag pattern on the peripheral edge of the surface are connected to the tips of inner leads extending from the insulating film. Among the plurality of bump electrodes, an outer bump electrode is made higher than an inner bump electrode, and a TAB type semiconductor device is provided.
【請求項2】 請求項1記載の半導体ペレットの内、外
側のバンプ電極に、各バンプ電極に対応して長さが異な
るインナリードの先端を一括して熱圧着するボンディン
グツールを具備し、そのリード押圧面の周縁に沿って凹
状の段差部を形成したことを特徴とするTAB式半導体
装置の製造装置。
2. The semiconductor pellet according to claim 1, wherein an outer bump electrode is provided with a bonding tool for collectively thermocompressing the tips of inner leads having different lengths corresponding to the bump electrodes. An apparatus for manufacturing a TAB type semiconductor device, characterized in that a concave step portion is formed along the periphery of the lead pressing surface.
JP4015818A 1992-01-31 1992-01-31 Tab type semiconductor device and manufacturing device therefor Pending JPH05218130A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4015818A JPH05218130A (en) 1992-01-31 1992-01-31 Tab type semiconductor device and manufacturing device therefor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4015818A JPH05218130A (en) 1992-01-31 1992-01-31 Tab type semiconductor device and manufacturing device therefor

Publications (1)

Publication Number Publication Date
JPH05218130A true JPH05218130A (en) 1993-08-27

Family

ID=11899434

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4015818A Pending JPH05218130A (en) 1992-01-31 1992-01-31 Tab type semiconductor device and manufacturing device therefor

Country Status (1)

Country Link
JP (1) JPH05218130A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005117036A (en) * 2003-10-04 2005-04-28 Samsung Electronics Co Ltd Tape circuit board and semiconductor chip package utilizing same
US7023070B2 (en) 2003-06-05 2006-04-04 Oki Electric Industry Co., Ltd. Semiconductor device
US7518691B2 (en) 2004-07-13 2009-04-14 Seiko Epson Corporation Electrooptical device, mounting structure, and electronic apparatus having wiring formed on and protruding from a base material to directly under an input bump on a semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7023070B2 (en) 2003-06-05 2006-04-04 Oki Electric Industry Co., Ltd. Semiconductor device
JP2005117036A (en) * 2003-10-04 2005-04-28 Samsung Electronics Co Ltd Tape circuit board and semiconductor chip package utilizing same
US7518691B2 (en) 2004-07-13 2009-04-14 Seiko Epson Corporation Electrooptical device, mounting structure, and electronic apparatus having wiring formed on and protruding from a base material to directly under an input bump on a semiconductor device

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