JPH0521792A - Zero-cross switching element - Google Patents

Abstract

PURPOSE:To reduce the power loss during a transient period from ON to OFF of a power switching element. CONSTITUTION:A MOS type FET includes a p-type channel layer 13 sandwiched between an n-type source layer 14 and an n-type drain layer 15, and a gate electrode 17 formed on them with a dielectric layer 16 interposed therebetween. Internal layers 3 and 4, having impurity concentrations raised stepwise, are formed in the vicinity of the junction surface 2 between the channel layer 13 and the drain layer 15. A substrate electrode 18 of the channel layer 13 is connected to the electrode of the source layer 14 by an electric conductor. When a current, passing from a drain 20d to a source 20s, is interrupted by lowering the voltage of a gate 20g to zero, the power loss is reduced by storing a given amount of electric charge into the internal layers 3 and 4, and by delaying, stepwlse, the increase of the voltage applied to the channel that is in a semi- conducted state until all of the carriers inside the channel layer 13 substantially disappear.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a zero-cross switching element which reduces loss due to a transient phenomenon in power switching.

[0002]

2. Description of the Related Art Conventionally, switching regulators and DC
A power MOS FET (field effect transistor) used for high-speed switching such as a DC converter or an inverter has a large current passing through the element when it is conductive, but has a small voltage drop in the element. Further, the voltage applied to the element at the time of interruption is large, but the current passing through the element is minute. Therefore, the power loss in the element itself is small as compared with the power to be controlled, and the heat generation amount is small, so that the device is small and lightweight.

By combining such a switching element with an element having a reactance component, the switching element can be used in place of a resistor or a power transistor, and the power can be controlled without being discarded as heat. Therefore, the resistor is used. Not only the current limiter that was used, but also the wound variable transformer is being replaced. Further, in a device such as a converter in which a switching element and a reactance element or a transformer are combined, the reactance element or transformer used can be made smaller and lighter by increasing the switching frequency. Devices using are being developed one after another.

[0004]

However, there is a transient period in the operation of the switching element during switching between conduction and interruption. For example, when the MOS type FET shifts from conduction to cutoff, as shown in FIG.
At time t1 when Id starts to decrease, drain-source voltage Vd
s starts to rise and the drain current Id becomes zero at time t2 when the drain-source voltage Vds reaches the maximum value.
Between t1 and time t2, power loss Pswoff, which becomes heat in the MOS type FET, occurs. This power loss Pswoff is equal to the product of the drain-source voltage Vds and the drain current Id integrated over time from time t1 to time t2.

Further, when transitioning from interruption to conduction, as shown in FIG. 16, the drain-source voltage Vds decreases at the same time as the drain current Id increases. The time when these start
The value obtained by integrating the product of the drain current Id and the drain-source voltage Vds from the time t3 to the time t4 is the power loss Pswon at the time of transition to conduction. Therefore, switching loss Ps
w becomes Psw = Pswon + Pswoff, and Psw loss occurs every cycle. Therefore, when the switching frequency becomes high, the loss in the switching element becomes large and it becomes difficult to reduce the size.

In order to reduce this loss, in a DC-DC converter or the like, the circuit that supplies power to the primary winding of the transformer is a resonant circuit, and the current flowing through the switching element is zero or the voltage drop is zero due to the resonance. A so-called resonance converter, which is a method of switching the state of a switching element at some time, is becoming mainstream. However, the use of resonance causes a problem that electric power much larger than the electric power to be taken out must be handled in the circuit, so that there is a problem that the rating of each element is increased and a high-level control technique is required.

An object of the present invention is to provide a zero-cross switching element that solves the above-mentioned drawbacks and reduces the loss due to a transient phenomenon at the time of switching in the switching element.

[0008]

In order to achieve the above object, a zero-cross switching element according to the present invention is configured so that the impurity concentration of a thin portion in the vicinity of a PN junction surface in at least one of P and N regions is set in a substantially stepwise manner. A PN junction diode in which the impurity concentration of the other region adjacent to the thin portion across the PN junction surface is increased by a MOS transistor.
It is provided on the PN junction surface including the boundary between the drain region and the channel region of the type FET.

[0009]

The zero-cross switching element having the above-mentioned structure is a junction of a charge limiting diode in which a current in a transient semi-conducting state is formed in the drain-source PN junction by a constant charge when switching from on to off. Since it is absorbed by the capacitance, the steep rise of the voltage applied to the switching element is delayed for a fixed time, and the power loss in the switching element is small.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail with reference to the embodiments shown in FIGS. FIG. 1 shows a configuration diagram of a PN junction diode 1 used in the present invention, which is made of a semiconductor in which a PN junction is formed in a central portion and electrodes are attached to both sides. The junction surface 2 of the PN junction is substantially flat, and the impurity concentration is increased stepwise on both sides of the junction surface 2 to the same degree, and the inner layers 3 and 4 having a thickness of, for example, about 0.1 μm are formed. On the outer sides of the boundary surfaces 5 and 6, intermediate layers 7 and 8 having an impurity concentration as low as approximately the same and a thickness of about several μm are formed. Electrodes 11 and 12 are provided on the outer sides of the intermediate layers 7 and 8 with the outer layers 9 and 10 having a particularly high impurity concentration in order to realize ohmic contact interposed therebetween. The inner layer 3, the intermediate layer 7, and the outer layer 9 are all P-type semiconductors, and the inner layer 4, the intermediate layer 8, and the outer layer 10 are N-type semiconductors. Therefore, the electrode 11 becomes the anode 1a and the electrode 12 becomes the cathode 1k.

The impurity concentration distribution along the vertical cross section of the PN junction diode 1 is as shown in FIG. Here, X5 is the coordinate of the boundary surface 5 between the inner layer 3 and the intermediate layer 7, X2 is the coordinate of the joining surface 2, X6 is the coordinate of the boundary surface 6 between the inner layer 4 and the intermediate layer 8, and the vertical axis is the impurity concentration. Is shown.

A reverse voltage Vr is applied to the PN junction diode 1.
When the voltage Vr is sufficiently small, the depletion layer having a thickness proportional to the square root of the voltage Vr with the junction surface 2 as the center is formed on the inner layer 3,
4 occurs, the thickness of the depletion layer is also inversely proportional to the square root of the impurity concentration. Therefore, when the depletion layer reaches the outside of the boundary surfaces 5 and 6, the depletion layer spreads rapidly with respect to the increase of the applied voltage. At this time, the N-type region in the depletion layer is positively charged because there are many donor ions, and the P-type region is negatively charged because there are many acceptor ions. Therefore, the diode 1 should be regarded as a capacitor. You can

The relationship between the reverse voltage Vr applied to the PN junction diode 1 and the junction capacitance Cj of the diode 1 is shown in FIG.
It becomes like the characteristic chart shown in. That is, when the voltage Vr increases, the capacitance Cj decreases, and the rate of decrease partially changes discontinuously. Assuming that the threshold voltage Vth is a voltage at which the thickness of the depletion layer is equal to the thickness of the inner layers 3 and 4, Vr <
The capacitance Cj gradually decreases at Vth, but the rate of decrease sharply increases at Vr = Vth. At Vr> Vth, the capacitance Cj decreases sharply at first, and the rate of decrease of the capacitance Cj increases as the reverse voltage Vr increases. It approaches zero.

The PN junction diode 1 is charged when a reverse voltage is applied, and when the charge amount exceeds a constant value Q _o , the voltage rises sharply and the charged charge amount is substantially constant value Q _o.
It has a charge limiting property of being limited to _o . This charge amount Q _o is determined by Q _o = eNXS. Here, S is the area of the junction surface, N is the impurity concentration in the inner layers 3 and 4, that is, the acceptor ion concentration in the N region and the donor ion concentration in the P region, and X is the thickness of each of the inner layers 3 and 4. is there. The charge limiting characteristic becomes steeper when the change in the impurity concentration at the boundary surfaces 5 and 6 is as large and sharp as possible.

In the above example, the PN junction diode 1
Although the layers 9 and 10 having a particularly high impurity concentration are provided inside the electrodes 11 and 12 of the above, they may be removed if ohmic contact is obtained. Further, the thin layers 3 and 4 or the intermediate layers 7 and 8 may not have the same concentration as each other.
The thicknesses of 4 do not necessarily have to be equal. However, equalization is effective for making the change in the junction capacitance Cj steep.

In the charge limiting diode 1, the charge current sharply decreases when the charge reaches a predetermined charge amount Q _o , so that the delay operation with switching characteristics can be realized.

FIG. 4 is a block diagram of a zero-cross switching element according to the present invention, in which a P-type channel layer 13 is sandwiched between an N-type source layer 14 and an N-type drain layer 15, and a gate electrode 17 is provided with an insulating layer 16 interposed therebetween. MO having a structure provided with
In the vicinity of the junction surface 2 between the P-type channel layer 13 and the N-type drain layer 15 of the S-type FET 20a, the charge limiting diode 2 is provided.
0b is formed. That is, the P-type channel layer 13
Is equivalent to the P ⁻ intermediate layer 7 in FIG. 1, a thin P ⁺ inner layer 3 is formed in the vicinity of the joint surface 2, and the N-type drain layer 15 is in contact with the joint surface 2 and the n ⁺ inner layer 4 is thin. Formed and its outside corresponds to the n ⁻ intermediate layer 8. The substrate electrode 18 is connected to the electrode of the source 20s by a conductor. The zero-cross switching element 20 having such a configuration is an ordinary MOS.
By applying a positive gate voltage Vgs to the gate 20g with respect to the source 20s similarly to the type FET, a drain current Id flows from the drain 20d to the source 20s as shown in the static characteristics in FIG. In addition, the source 20s drain 2
When a positive voltage is applied to 0d, the forward current of the parasitic diode formed on the junction surface 2 flows through the substrate electrode 18. This parasitic diode is the same as the PN junction diode 1 shown in FIG. 1, and the channel layer 13 corresponds to the intermediate layer 7 and the drain layer 15 corresponds to the intermediate layer 8. The circuit diagram shown in FIG. 6 is obtained. This zero-cross switching element 20 is in a semi-conducting state during a transient period because current is absorbed and accumulated in the charge limiting diode 20b when the gate voltage Vgs is rapidly set to zero to shift from conduction to cutoff. A current does not flow in the FET 20a, and switching loss at this time hardly occurs. Further, since the charge limiting diode 20b has a non-linear capacitance, the charging current rapidly becomes zero when the charging charge reaches a predetermined value.

FIG. 7 is a sectional view of the first embodiment.
Gate electrode 1 of polycrystalline silicon doped with phosphorus (P) 1
Of the vertical double-diffused MOS FET 20a using the high-concentration inner layer 3 and 4 at the boundary between the P-type channel layer 13 and the N-type drain layer 15 facing the drain electrode layer 10 The zero-cross switching element 20 is provided with 20b. When conducting, a channel composed of an inversion layer is formed by the carriers gathered in the vicinity of the gate electrode 17 of the P-type channel layer 13, and the N-type region is connected, so that a current flows from the N-type drain layer 15 to the N-type source layer 14. When the gate voltage Vgs is lowered, the carriers are separated from the vicinity of the gate electrode and are attracted to the P ⁺ inner layer 3, and charges are accumulated around the depletion layers formed in the inner layers 3 and 4 by the reverse bias of the junction surface 2. .. Before the potential due to this charge rises almost, the P-type channel layer 1
The carriers of No. 3 almost disappear, and the FET 20a is cut off. After that, the depletion layer in the inner layers 3 and 4 spreads over the entire area of the inner layers 3 and 4, and thereafter spreads to the channel layer 13 and the drain layer 15 which are regions having a low impurity concentration, so that the capacitance rapidly decreases. , The drain-gate voltage, that is, the drain-source voltage Vds rises sharply.

FIG. 8 shows the second embodiment, in which the inner layers 3 and 4 are formed at the boundary between the P-type channel layer 13 and the N-type drain layer 15 of the U-groove MOS FET 20a to provide the charge limiting diode 20b and to achieve zero cross. The switching element 20 is configured. Since the channel is formed along the side surface of the U groove, the inner layers 3 and 4 are provided apart from the U groove while avoiding this. A zero-cross switching element can be formed even with such a shape.

Next, a method of using the zero-cross switching element 20 according to the present invention in a circuit will be described. Figure 9
Shows the main part of the separately excited half-wave partial resonance DC-DC converter, and uses the zero-cross switching element 20 as the main switching element. The drain 20d of the FET 20a is connected to one of the transformer 22 through a saturation reactor 21 in which a conductor is passed through an annular core having a rectangular magnetic hysteresis characteristic.
It is connected to the end of the secondary winding 22a. The terminal of the primary winding 22a is connected to the diode 23 and the clamp capacitor 2
4 to the source 20s, and the anode side of the diode 23 is connected to the primary winding 22a. The drain 20d is connected to the positive electrode of the DC power supply 26 via the saturation reactor 21 and the primary winding 22a, the source 20s is connected to the negative electrode of the DC power supply 26, and the gate 20g and the source 20 are connected.
The FET 20a performs a switching operation by the voltage applied during s.

Diode 23 of clamp capacitor 24
The side is connected to the positive winding of the DC power supply 26 via the reset winding 22b, which is the other primary winding of the transformer 22, and another MOS FET 27, and the drain 27d of the FET 27 is the winding of the reset winding 22b. First, the source 27s is connected to the positive electrode of the DC power supply 26. Then, the gate 20g of the FET 20a and the FET 27
Control signals of opposite phases are applied to the gate 27g of the. An iron core with a gap is used for the transformer 22, and a smoothing circuit is connected to the secondary winding 22c. That is, the anode of the diode 28 is connected to the winding start of the secondary winding 22c, and the anode of the diode 29, the negative output terminal 30, and the negative electrode of the capacitor 31 are connected to the end. And the diode 2
Cathodes 8 and 29 are both connected to one end of the choke coil 32, and the other end of the choke coil 32 is the positive output terminal 3
3 and the positive electrode of the capacitor 31.

In the steady state, when the FET 20a is turned on, the drain current Id starts flowing through the primary winding 22a to the FET 20a. At this time, as shown in FIG. 10, the drain current Id increases extremely slowly only for a short time until the annular core of the saturation reactor 21 is saturated, and the resistance value between the source 20s and the drain 20d is substantially zero during this period. Therefore, the power loss of the FET 20a during the transition period from OFF to ON is small. When the current Id flowing in the saturation reactor 21 increases to a certain constant value Ith, the annular core is saturated and the inductance becomes small.
Also, the current flowing through the primary winding 22a rapidly increases. At this time, the voltage induced in the secondary winding 22c is the diode 28
, The electric current is charged in the capacitor 31 through the choke coil 32 and also flows into the load RL.
Even when the FET 20a is switched from ON to OFF, the voltage of the clamp capacitor 24 hardly drops, and thus the voltage Vc is almost equal to the maximum value of the voltage Vds between the drain 20d and the source 20s up to then.

When the FET 20a is on, the resistance value between the drain 20d and the source 20s is almost zero, and
This resistance value gradually rises during the transition period from t1 to time t2 when it is turned off. This is because the carriers in the inversion layer, which were generated just below the gate electrode (not shown) of the FET 20a, diffuse and disappear as the gate voltage decreases. At this time, since the charge limiting diode 20b acts as a capacitor and shunts the current from the primary winding 22a, the voltage Vds, that is, the voltage Vr rises too rapidly until it reaches the threshold voltage Vth as shown in FIG. do not do. During this time, carriers of the FET 20a are diffused, and the resistance value between the drain 20d and the source 20s increases. In the charge limiting diode 20b, the voltage Vr reaches the threshold voltage Vth at the end of the transition period, and immediately after that, at time t2, Vr rapidly increases and reaches the voltage Vc. Therefore, the current from the primary winding 22a flows into the clamp capacitor 24 through the diode 23.

Next, when the FET 27 is turned on, almost no current flows due to the induced electromotive force generated in the reset winding 22b at the beginning, but when the current in the primary winding 22a decreases and the electromotive force decreases. The reset current starts to flow from the clamp capacitor 24 through the reset winding 22b.
At this time, even if an electromotive force is generated in the secondary winding 22c, no current flows because the diode 28 has a reverse polarity, and the inertia current of the choke coil 32 is charged in the capacitor 31 through the flywheel diode 29.

When the FET 27 is turned off, the primary winding 22a
A reverse voltage is applied to the FET 20a, but a high voltage does not occur due to the discharge of the charge stored in the charge limiting diode 20b connected in parallel and the forward current flowing through the charge limiting diode 20b. At this time, in the saturation reactor 21, the hysteresis of the core is reset by the reverse current. Next, since the FET 20a is turned on, a current starts to flow in the primary winding 22a.

As described above, in the zero-cross switching element 20, the voltage Vds is kept low during the transition period of the FET 20a from on to off, and almost no current flows during the transition period from off to on. The switching loss Psw in the device is extremely small.

FIG. 12 shows the main part of the separately excited half-wave partial resonance DC-DC converter of the second embodiment, in which a MOS type FET 20a and a charge limiting diode 20b are provided on the same substrate.
And a zero-cross switching element 20 which is a main switching element connected in parallel is connected to the terminal end of the primary winding 35a of the transformer 35 via a saturation reactor 21. The DC power source 2 is provided at the beginning of the winding of the primary winding 35a.
The positive electrode of 6 is connected, the negative electrode of the DC power supply 26 is connected to the source 20s, and the FET 20a performs a switching operation by the voltage applied between the gate 20g and the source 20s.

At the end of the primary winding 35a, a clamp capacitor 24 and a diode 23 are connected in series, and the cathode of the diode 23 is connected to the negative electrode of a DC power supply 26. Another MOS type FET2 is used for the diode 23.
7 are connected in parallel, the source 27s is connected to the anode of the diode 23, and the drain 27d is connected to the cathode, and the FET 27 performs a switching operation by the voltage applied between the gate 27g and the source 27s. Control signals of opposite phases are applied to the gate 20g of the FET 20a and the gate 27g of the FET 27. To the secondary winding 35c of the transformer 35, a rectifying circuit and a smoothing circuit having the same configuration as in the first embodiment are connected. And
Load the negative output terminal 30 and the positive output terminal 33 when using
RL is connected.

When the FET 20a is turned on in the steady state, the drain current Id starts to flow to the FET 20a through the primary winding 35a. At this time, as shown in FIG. 10, the drain current Id increases extremely slowly for a short time until the saturation reactor 21 is saturated, and thereafter the annular core is saturated, so that the inductance of the saturation reactor 21 becomes small and the FET 20a Also, the current flowing through the primary winding 35a rapidly increases. At this time, since the voltage induced in the secondary winding 35c is in the forward direction of the diode 28, a current flows,
The capacitor 31 is charged through the choke coil 32 and also flows to the load RL.

When the FET 20a is on, the resistance value between the drain 20d and the source 20s is almost zero, and this resistance value gradually rises during the transition period from the time t1 to the time t2 when the FET 20a is turned off. At this time, the charge limiting diode 20b acts as a capacitor and shunts the current from the primary winding 35a, so that the voltage Vds does not rise very rapidly until it reaches the threshold voltage Vth, as shown in FIG.
The charge limiting diode 20b has a voltage at the end of the transient period.
Vr reaches the threshold voltage Vth, and immediately after that, at time t2, Vr rapidly rises and reaches Vc. Therefore, the current from the primary winding 35a flows into the clamp capacitor 24 through the diode 23. As described above, in the zero-cross switching element 20, the loss due to the switch-off can be suppressed to be extremely small by the action of the charge limiting diode 20b.

Next, when the FET 27 is turned on, no current flows from the clamp capacitor 24 due to the induced electromotive force generated in the primary winding 35a at first, but the primary winding 3
When the current of 5a becomes zero, the reset current starts to flow from the clamp capacitor 24 in the reverse direction through the primary winding 35a. At this time, even if an electromotive force is generated in the secondary winding 35c, no current flows because the diode 28 has a reverse polarity, and the inertia current of the choke coil 32 is charged in the capacitor 31 through the flywheel diode 29. Load RL
Also flows.

When the FET 27 is turned off, the primary winding 35
Although an electromotive force is generated in a and a reverse voltage is applied to the FET 20a, a high voltage does not occur due to discharge of electric charge charged in the charge limiting diode 20b connected in parallel and forward current flowing in the charge limiting diode 20b. At the same time, the core of the saturation reactor 21 is reset, and then the FET 20a
Is turned on, current starts to flow in the primary winding 35a.

In the above two separately excited converters, when the load current flows, the inductance of the transformer 35 hardly works when the FET 20a is turned from OFF to ON, so that the saturation reactor 21 mainly supplies the current. The increase is delayed, and the loss due to switch-on can be suppressed to a small level.

FIG. 13 shows a center tap type switching inverter circuit, which is mainly used for converting a direct current into an insulated alternating current by a push-pull method using two zero-cross switching elements 20, 20 and a transformer 37 with a center tap. It is a department. To the transformer 37 having a rectangular characteristic with no core gap, the drains 20d of the zero-cross switching elements 20 and 20 are connected to both ends of the primary winding via saturation reactors 21, respectively. The saturation reactor 21 is formed by passing a conductor wire or winding a conductor wire on an annular core having a rectangular magnetic hysteresis characteristic. DC power supply 26 for the center tap of the primary winding
Of the zero-cross switching elements 20 and 20 is connected to the negative electrode of the DC power supply 26. In the two zero-cross switching elements 20, 20, control signals having opposite phases are applied from the signal sources 38, 39 between the gate 20g and the source 20s, and the secondary winding of the transformer 37 is applied. Is to obtain an AC voltage insulated from the DC power supply 26.

In this circuit, the two zero-cross switching elements 20, 20 alternately perform the same operation, so the operation of one of them will be described. First, one FET 20a
In the ON state, the resistance value between the drain 20d and the source 20s is almost zero, and this resistance value gradually increases during the transition period in which the drain is off. At this time, since the charge limiting diode 20b functions as a capacitor to absorb the current from the transformer 37, the drain-source voltage Vds does not rise very rapidly as shown in FIG. The threshold voltage Vth is reached at the end of the transition period, and immediately after that, at time t2, it rises sharply and causes an overshoot exceeding the power supply voltage, but almost no carriers flow, so almost no drain current Id flows. ..

Next, the charge limiting diode 20b is discharged through the primary winding of the transformer 37, and this current resets the annular core of the saturation reactor 21. Furthermore, depending on the operating state of the circuit, due to the inertia current of the transformer 37,
After the charge limiting diode 20b has finished discharging, the voltage of the charge limiting diode 20b is reversed. However, since the voltage is the forward voltage of the charge limiting diode 20b, the charge limiting diode 20b conducts and no charge is accumulated, so ringing does not occur.

When a positive voltage is applied to the gate 20g, the FET 20a is switched from off to on and the charge limiting diode 20b is discharged, and at the same time, the drain current Id from the DC power supply 26 through the transformer 37 to the FET 20a.
Begins to flow. At this time, as shown in FIG. 10, the drain current Id increases very slowly only for a short time until the annular core of the saturation reactor 21 is saturated, and the resistance value between the source 20s and the drain 20d is increased during this period. It drops to almost zero. Therefore, the power loss during the transition period from OFF to ON of the FET 20a is small. When the current Id flowing through the saturation reactor 21 increases to a certain constant current value Ith, the annular core is saturated and the inductance becomes small, and as a result, the current flowing through the zero-cross switching element 20 and the transformer 37 rapidly increases. At this time, the other zero-cross switching element 20 is about to be switched from on to off, and by alternately conducting the two zero-cross switching elements 20 in this manner, magnetic fluxes in different directions are alternately generated in the transformer 37, Induced electromotive force is induced in the secondary winding, and an insulated AC voltage is obtained.

The switching circuit according to the present invention is
This is effective not only for the inverter circuits shown in FIGS. 9, 12, and 13 but also for many switching circuits. Figure 1
Reference numeral 4 causes the zero-cross switching element 20 to switch the drive current of the heating wire 40. When the current from the DC power supply 26 is turned on, the saturation reactor 2
The increase is delayed by 1 and is absorbed by the charge limiting diode 20b during the transition period when the FET is turned off.
In 20b, loss at the time of switching, that is, heat generation is suppressed to a low level.

Further, the zero-cross switching element 20
The voltage applied to the gate 20g of the
Power control can be performed by control. Alternatively, the zero-cross switching element 20 may be used simply for breaking the circuit.

[0040]

As described above, in the zero-cross switching element according to the present invention, the parasitic diode of the MOS type FET is formed in the charge limiting diode, and the switch element is turned on and off without using other elements or circuits. It is possible to suppress the switching loss in the transient state to the.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a built-in PN junction diode.

FIG. 2 is an explanatory diagram of an impurity concentration distribution of a built-in PN junction diode.

FIG. 3 is a characteristic diagram of voltage and junction capacitance of a built-in PN junction diode.

FIG. 4 is a configuration diagram of a zero-cross switching element.

FIG. 5 is an explanatory diagram of input / output static characteristics.

FIG. 6 is a circuit symbol diagram.

FIG. 7 is a cross-sectional view of the first embodiment.

FIG. 8 is a cross-sectional view of the second embodiment.

FIG. 9 is a configuration diagram of an application example to a half-wave partial resonance DC-DC converter.

FIG. 10 is an explanatory diagram of changes in voltage and current from off to on.

FIG. 11 is an explanatory diagram of changes in voltage and current from on to off.

FIG. 12: Second half-wave partial resonance DC-DC converter
It is a block diagram of the application example of.

FIG. 13 is a configuration diagram of an application example to a center tap type inverter.

FIG. 14 is a configuration diagram of an application example of switching of a driving current of a heating wire.

FIG. 15 is an explanatory diagram of changes in current and voltage when the MOS type FET is turned off.

FIG. 16 is an explanatory diagram of changes in current and voltage when the MOS FET is turned on.

[Explanation of symbols]

 1 PN junction diode 1a Anode 1k Cathode 2 Junction surface 3,4 Inner layer 5,6 Boundary surface 7,8 Intermediate layer 9,10 Outer layer 11, 12, 17, 18 Electrode 13 P-type channel layer 14 N-type source layer 15 N-type Drain layer 16 Insulating layer 20 Zero cross switching element 20a, 27 MOS type FET 20b Charge limiting diode 21 Saturation reactor 22, 35, 37 Transformer 40 Heating wire

Claims (1)

Claim: What is claimed is: 1. An impurity concentration of a thin portion in the vicinity of a PN junction surface in at least one of P and N regions is increased in a substantially stepwise manner so that the thin portion is separated by the PN junction surface. A zero-cross switching element characterized in that a PN junction diode having a high impurity concentration in the other adjacent region is provided on a PN junction surface including a boundary between a drain region and a channel region of a MOS type FET.