JP2821514B2 - Switching circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a switching circuit for reducing a loss due to a transient phenomenon in power switching.

[0002]

2. Description of the Related Art Conventionally, switching regulators, DC
A switching element such as a power MOSFET or a thyristor used for high-speed switching such as a DC converter and an inverter has a large current passing through the element when conducting, but a small voltage drop in the element. Also,
At the time of cutoff, the voltage applied to the element is large, but the current passing through the element is small. For this reason, the power loss in the element itself is smaller than the power to be controlled, and the device is small and light because of a small amount of heat generation.

[0003] By combining such a switching element with an element having a reactance component, it can be used in place of a resistor or a power transistor, and can be controlled without discarding power as heat. Not only current limiters, but also wound-type variable transformers are being replaced. Furthermore, a device such as a converter in which a switching element and a reactance element or a transformer are combined can increase the switching frequency, thereby reducing the size and weight of the reactance element or the transformer being used. Devices using are being developed one after another.

[0004]

However, in the operation of the switching element, there is a transient period when switching between conduction and interruption. For example, when the MOSFET switches from conduction to interruption, as shown in FIG.
At time t1 when Id starts decreasing, the drain-source voltage Vd
s starts to rise and the drain current Id becomes zero at time t2 when the drain-source voltage Vds reaches the maximum value.
Between time t1 and time t2, a power loss Pswoff which becomes heat in the MOSFET occurs. This power loss Pswoff is equal to the product of the product of the drain-source voltage Vds and the drain current Id integrated over time from time t1 to time t2.

Further, when the transition from interruption to conduction occurs, the drain-source voltage Vds decreases at the same time as the drain current Id increases, as shown in FIG. The time at which these begin
The value obtained by integrating the product of the drain current Id and the drain-source voltage Vds from time t3 to time t4 is the power loss Pswon at the time of transition to conduction. Therefore, the switching loss Ps
w becomes Psw = Pswon + Pswoff, and a loss of Psw occurs every cycle. For this reason, when the switching frequency increases, the loss in the switching element increases, and miniaturization becomes difficult.

In order to reduce this loss, in a DC-DC converter or the like, a circuit for supplying power to a primary winding of a transformer is a resonance circuit, and the current flowing through the switching element due to resonance becomes zero or the voltage drop becomes zero. The use of a so-called resonant converter, which switches the state of a switching element at times, is becoming mainstream. However, the use of resonance requires that power much larger than the power to be extracted must be handled in the circuit. Therefore, there are problems such as an increase in the rating of each element and a need for advanced control technology.

An object of the present invention is to provide a switching circuit which solves the above-mentioned disadvantages and reduces a loss caused by a transient phenomenon at the time of switching in a switching element.

[0008]

A switching circuit according to the present invention for achieving the above-mentioned object has a high-concentration portion in which P and N regions sandwiching a PN junction surface have an impurity concentration increased in a substantially step-like manner. And forming an electrode surface on both sides thereof, and forming a low concentration portion having an impurity concentration sufficiently lower than the high concentration portion between the high concentration portion of the P region and the N region and the electrode surface. A charge limiting diode whose voltage-to-junction capacitance characteristic rapidly changes at a threshold corresponding to the boundary between the high-concentration portion and the low-concentration portion is connected in parallel with the switching element.

[0009]

In the switching circuit having the above-described configuration, the inertia current due to the inductance of the circuit is absorbed by the junction capacitance of the PN junction diode when switching from on to off, so that the rise in the voltage applied to the switching element is delayed. Power loss in the switching element is small.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail with reference to the embodiments shown in FIGS. FIG. 1 shows a configuration diagram of a charge limiting diode 1 used in the present invention. This charge limiting diode 1 is a kind of a PN junction diode, and is formed from a semiconductor having a PN junction formed at the center and electrodes attached to both sides. Made up of The junction surface 2 of the PN junction is substantially flat, and the both sides of the junction surface 2 are symmetrically increased in substantially the same step with substantially the same impurity concentration, and have a thickness of, for example, 0.1.
Inner layers 3 and 4 having a thickness of about μm are formed.
Intermediate layers 7 and 8 having a thickness of about several μm are formed. Electrodes 11 and 12 are provided outside the intermediate layers 7 and 8 with the outer layers 9 and 10 having a particularly high impurity concentration interposed therebetween to realize ohmic contact. The inner layer 3, the intermediate layer 7, and the outer layer 9 are all P-type semiconductors, and the inner layer 4, the intermediate layer 8, and the outer layer 10 are N-type semiconductors. Therefore, the electrode 11 becomes the anode 1a and the electrode 12 becomes the cathode 1k.

FIG. 2 shows an impurity concentration distribution along a vertical section of the charge limiting diode 1. Here, X5 is the coordinates of the boundary surface 5 between the inner layer 3 and the intermediate layer 7, X2 is the coordinates of the bonding surface 2, X6 is the coordinate of the boundary surface 6 between the inner layer 4 and the intermediate layer 8, and the vertical axis is the impurity concentration. Is shown.

A reverse voltage Vr is applied to the charge limiting diode 1.
When the voltage Vr is sufficiently small, a depletion layer having a thickness proportional to the square root of the voltage Vr is formed around the junction surface 2 when the voltage Vr is sufficiently small.
4, the thickness of the depletion layer is also inversely proportional to the square root of the impurity concentration. Therefore, when the depletion layer reaches the outside of the boundary surfaces 5, 6, the expansion of the depletion layer with an increase in the applied voltage becomes sharp. At this time, the N-type region in the depletion layer is positively charged due to the large amount of donor ions, and the P-type region is negatively charged due to the large amount of acceptor ions. Can be.

The relationship between the reverse voltage Vr applied to the charge limiting diode 1 and the junction capacitance Cj of the diode 1 is shown in FIG.
The characteristic diagram shown in FIG. That is, when the voltage Vr increases, the capacitance Cj decreases, and the rate of the decrease changes partly discontinuously. Assuming that a voltage at which the thickness of the depletion layer is equal to the thickness of the inner layers 3 and 4 is a threshold voltage Vth, as the voltage Vr increases, Vr <
At Vth, the capacitance Cj decreases little by little, but at Vr = Vth, the rate of decrease sharply increases. When Vr> Vth, the capacitance Cj decreases rapidly at first, and the rate of decrease of the capacitance Cj as the reverse voltage Vr increases. Approaches zero.

The charge limiting diode 1 is charged when a reverse voltage is applied, and when the charge amount exceeds a certain value _Qo , the voltage rises sharply and the charged charge amount becomes almost constant value Qo.
_o , and the charge amount Q _o is Q _o
= ENXS. Here, S is the area of the joint surface, N
Is the impurity concentration in the inner layers 3 and 4, that is, the acceptor ion concentration in the N region and the donor ion concentration in the P region.
X is the thickness of each of the inner layers 3 and 4. The change in the impurity concentration at the boundary surfaces 5 and 6 is as large and sharp as possible, and the charge limiting characteristic becomes steeper.

In the above-described embodiment, the layers 9 and 10 having a particularly high impurity concentration are provided inside the electrodes 11 and 12 of the charge limiting diode 1. However, if the ohmic contact is obtained, these layers are excluded. Is also good. Also, the thin layers 3, 4 or the layers 7, 8 need not have equal concentrations. Further, the thicknesses of the thin layers 3 and 4 do not necessarily have to be equal. However,
It is considered effective to increase the initial value of the junction capacitance Cj by making them equal.

FIG. 4 shows a delay circuit using the charge limiting diode 1. The input voltage Vin is connected to the cathode 1k of the diode 1 via a resistor R, and the output voltage Vout is directly output from the diode 1. The anode 1a of the diode 1 is connected to the common terminal GND.
Grounded. Diode 1 as input voltage Vin
When a voltage V that is sufficiently larger than the threshold voltage Vth is input in a step-like manner as shown in FIG. 5, the output voltage Vout rapidly rises and reaches the voltage V after a certain delay time Tr. This delay time Tr is approximately represented by Tr ≒ RQ _o / V.

FIG. 6 shows another delay circuit, in which a diode 1
Is connected so that the input voltage Vin is applied to the resistor R, the cathode 1k of the diode 1 is connected to the input side, and the output voltage Vout is directly extracted from the resistor R. When the voltage V is applied to this circuit in a step-like manner, the output voltage Vout rises to the voltage V at the same time as shown in FIG. 7, and falls rapidly after the delay time Tr.

As described above, since the charge current of the charge limiting diode 1 rapidly decreases when the charge reaches a predetermined charge _Qo , a delay operation with switching characteristics can be realized. This switching characteristic is effective in ensuring the operation of the digital electronic circuit, and can be used as a delay element in an IC including the digital circuit.

FIG. 8 shows the circuit of FIG. 4 in which the resistance R is replaced by an inductance L, and the delay time Tr ′ is Tr ′ ≒ (2Q
_o L / V) ^1/2 . In this circuit, as shown in FIG. 9, when the input voltage Vin which becomes the voltage V in a step-like manner is applied, the output voltage Vout rises rapidly after the delay time Tr ', and after a considerably high overshoot peak is generated, the output voltage Vout is changed to the voltage V. Calm down.

Next, how to use the charge limiting diode 1 in an active circuit will be described. FIG. 10 shows a main part of a separately excited half-wave partial resonance DC-DC converter, in which a MOS type FET 20 is used as a main switching element and its drain 2
The charge limiting diode 1 is connected in parallel between 0d and the source 20s, and a saturation reactor 21 having a square magnetic core with a magnetic hysteresis characteristic passed through a conducting wire is connected in series to these.

The charge limiting diode 1 has an anode 1a connected to a source 20s, a cathode 1k and a drain 20d.
Is the primary winding 2 of the transformer 22 via the saturation reactor 21
2a. The terminal of the primary winding 22a is connected to the source 20s via the diode 23 and the clamp capacitor 24, and the anode side of the diode 23 is connected to the primary winding 22a. Drain 20d
Is connected to a positive electrode of a DC power supply 26 via a saturation reactor 21 and a primary winding 22a.
And the FET 20 performs a switching operation by a voltage applied between the gate 20g and the source 20s.

Diode 23 of clamp capacitor 24
The reset winding 22b whose side is another primary winding of the transformer 22 is connected to the positive electrode of the DC power supply 26 through another MOS-type FET 27, and the drain 27d of the FET 27 is connected to the reset winding 22b. The connection is made first, and the source 27 s is connected to the positive electrode of the DC power supply 26. Control signals having phases opposite to each other are applied to the gate 20g of the FET 20 and the gate 27g of the FET 27.

An iron core with a gap is used for the transformer 22, and a smoothing circuit is connected to the secondary winding 22c. That is, the anode of the diode 28 is connected to the winding start of the secondary winding 22c, and the diode 29 is
Are connected to the negative electrode output terminal 30 and the negative electrode of the capacitor 31. The cathodes of the diodes 28 and 29 are both connected to one end of the choke coil 32,
The other end of the choke coil 32 is connected to the positive output terminal 33 and the positive electrode of the capacitor 31.

In a steady state, when the FET 20 is turned on, a drain current Id starts flowing through the primary winding 22a to the FET 20. At this time, as shown in FIG. 11, the drain current Id increases very slowly only for a short time until the annular core of the saturation reactor 21 is saturated, and during this time, the resistance value between the source 20s and the drain 20d is substantially reduced. Since it drops to zero, the power loss during the transition from FET off to on is small.

When the current Id flowing through the saturation reactor 21 increases to a certain constant value Ith, the annular core saturates, the inductance decreases, and the FET 20 and the primary winding 22
The current flowing through a rapidly increases. At this time, the secondary winding 22c
Is induced in the forward direction of the diode 28, the current flows through the choke coil 32 and the capacitor 31
, And also flows to the load RL. When the FET 20 is switched from on to off, the voltage of the clamp capacitor 24 hardly drops, so that the drain 20d
Voltage approximately equal to the maximum value of the voltage Vds between the source and the source 20s
Vc.

When the FET 20 is on, the drain 2
The resistance value between 0d and the source 20s is almost zero, and at time t1
This resistance value gradually increases during a transitional period from the time t2 to the time t2 when the transistor is turned off. This is because carriers in the inversion layer generated immediately below the gate electrode (not shown) of the FET 20 diffuse and disappear with a decrease in gate voltage. At this time, the charge limiting diode 1 acts as a capacitor and shunts the current from the primary winding 22a.
As shown in (2), the voltage Vds, that is, the voltage Vr, does not rise very rapidly until it reaches the threshold voltage Vth.

During this time, carriers are diffused in the FET 20, and the resistance between the drain 20d and the source 20s increases. At the end of the transition period, the voltage Vr reaches the threshold Vth at the end of the transition period.
Rises sharply and reaches the voltage Vc. Therefore, the primary winding 22 is connected to the clamp capacitor 24 through the diode 23.
The current from a flows in.

Next, when the FET 27 is turned on, at first, almost no current flows due to the induced electromotive force generated in the reset winding 22b, but when the current in the primary winding 22a decreases and the electromotive force decreases. , A reset current starts to flow from the clamp capacitor 24 through the reset winding 22b.
At this time, even if an electromotive force is generated in the secondary winding 22c, no current flows because the diode 28 has the opposite polarity, and the capacitor 31 is charged with the inertial current of the choke coil 32 through the flywheel diode 29.

When the FET 27 is turned off, the primary winding 22a
, And a reverse voltage is applied to the FET 20, but the voltage does not become high due to the discharge of the charges charged in the charge limiting diode 1 connected in parallel and the forward current flowing through the charge limiting diode 1. At this time, the hysteresis of the core of the saturation reactor 21 is reset by the reverse current. Next, since the FET 20 is turned on, the primary winding 2
Current starts to flow through 2a.

In such a circuit, the voltage Vds is kept low during the transition period of the FET 20 from ON to OFF, and almost no current flows during the transition period from OFF to ON. Very few.

FIG. 13 shows a main part of a separately excited half-wave partial resonance DC-DC converter according to the second embodiment, in which a MOS type FET 20 is used as a main switching element and a drain 20d of the cathode of the charge limiting diode 1 is provided. 1k, the anode 1a is connected to the source 20s, and one end of the saturation reactor 21 is also connected to the drain 20d.
The drain 20d is connected to the transformer 3 via the saturation reactor 21.
5 is connected to the end of the primary winding 35a. At the beginning of the winding of the primary winding 35a, the positive electrode of the DC power supply 26 is connected, the negative electrode of the DC power supply 26 is connected to the source 20s, and the gate 2
0g and the voltage applied between the source 20s and the FET 20
Performs a switching operation.

At the end of the primary winding 35a, a clamp capacitor 24 and a diode 23 are connected in series, and the cathode of the diode 23 is connected to the negative electrode of the DC power supply 26. Another MOS type FET2 is provided in the diode 23.
7 are connected in parallel, the source 27s is connected to the anode of the diode 23, the drain 27d is connected to the cathode, and the FET is applied by a voltage applied between the gate 27g and the source 27s.
27 performs a switching operation. Gate 20 of FET 20
Control signals having phases opposite to each other are applied to the gate g and the gate 27g of the FET 27. A rectifier circuit and a smoothing circuit having the same configuration as in the first embodiment are connected to the secondary winding 35c of the transformer 35. In use, the load RL is connected to the negative output terminal 30 and the positive output terminal 33.

In the steady state, when the FET 20 is turned on, a drain current Id starts flowing through the FET 20 through the primary winding 35a. As shown in FIG.
The drain current Id increases very slowly only for a short time until 1 is saturated, and thereafter the annular core saturates, so that the inductance of the saturation reactor 21 decreases and the FE increases.
The current flowing through T20 and the primary winding 35a increases rapidly. At this time, since the voltage induced in the secondary winding 35c is in the forward direction of the diode 28, a current flows, charges the capacitor 31 through the choke coil 32, and also flows to the load RL.

When the FET 20 is on, the drain 2
The resistance value between 0d and the source 20s is almost zero, and this resistance value gradually increases during the transition period from the time t1 when the transistor is turned off to the time t2. At this time, the charge limiting diode 1
Acts as a capacitor and shunts the current from the primary winding 35a, so that the drain-source voltage Vds does not rise very rapidly until it reaches the threshold value Vth as shown in FIG. At the end of the transition period, the voltage Vr reaches the threshold Vth at the end of the transition period.
Rapidly rises to reach the voltage Vc. Therefore, the primary winding 35a is connected to the clamp capacitor 24 through the diode 23.
Current flows from the

Next, when the FET 27 is turned on, at first, no current flows from the clamp capacitor 24 due to the induced electromotive force generated in the primary winding 35a.
When the current of 5a becomes zero, the reset current starts to flow from the clamp capacitor 24 in the opposite direction through the primary winding 35a. At this time, even if an electromotive force is generated in the secondary winding 35c, no current flows because the diode 28 has the opposite polarity, and the inertial current of the choke coil 32 is charged in the capacitor 31 through the flywheel diode 29, and at the same time, Load RL
Also flows.

When the FET 27 is turned off, the primary winding 35
Although an electromotive force is generated in a and a reverse voltage is applied to the FET 20, a high voltage is not attained due to the discharge of the charge charged in the charge limiting diode 1 connected in parallel and the forward current flowing through the charge limiting diode 1. At the same time, the saturation reactor 2
One core is reset. Next, since the FET 20 is turned on, a current starts to flow through the primary winding 35a.

In the two separately-excited converters described above, when the load current flows, the inductance of the transformer 35 hardly works when the FET 20 turns from off to on. The increase is delayed.

FIG. 14 shows a center-tap type switching inverter circuit, which is a main part of a DC-to-insulated AC converter by a push-pull method using two MOS FETs 20, 20 and a transformer 37 with a center tap. is there. A transformer 37 having a square characteristic without a gap in the core has a saturable reactor 21 at both ends of the primary winding.
Are connected to the drains 20d of the MOSFETs 20, 20, respectively. The saturating reactor 21 is formed by passing a conductor through or winding a conductor through an annular core having a square magnetic hysteresis characteristic.

A DC power supply 26 is connected to the center tap of the primary winding.
Are connected to the source 2 of the FET 20, 20.
0s is connected to the negative electrode of the DC power supply 26. And
The two charge limiting diodes 1 and 1 are connected in parallel to the FETs 20 and 20 one by one, and the anode of the diode 1 is connected to the source 20s and the cathode is connected to the drain 20d. In addition, the gate 20 g of the two FETs 20 and 20 is used.
And the source 20 s, control signals having phases opposite to each other are applied from the signal sources 38 and 39 so that an AC voltage insulated from the DC power supply 26 is obtained from the secondary winding of the transformer 37. Has become.

In this circuit, since the two FETs 20 and 20 perform the same operation alternately, the operation of one will be described. First, when one FET 20 is on, the resistance between the drain 20d and the source 20s is almost zero, and gradually increases during a transition period when the FET 20 is off. At this time, since the charge limiting diode 1 absorbs the current from the transformer 37 as a capacitor, the drain-source voltage Vds does not increase very rapidly as shown in FIG. At the end of the transition period, the threshold Vth is reached,
Immediately after that, at time t2, the voltage suddenly rises and exceeds the power supply voltage, causing overshoot. However, since the carriers have almost disappeared, the drain current Id hardly flows.

Next, the charge limiting diode 1 is discharged through the primary winding of the transformer 37, and this current resets the annular core of the saturation reactor 21. Further, depending on the operation state of the circuit, the voltage of the charge limiting diode 1 is reversed after the discharge of the charge limiting diode 1 due to the inertial current of the transformer 37. However, since the voltage is the forward voltage of the charge limiting diode 1, the charge limiting diode 1 conducts and no charge is accumulated, so that ringing does not occur.

Here, when a positive voltage is applied to the gate 20g, the FET 20 is switched from off to on, and the charge limiting diode 1 is discharged. At the same time, a drain current Id flows from the DC power supply 26 through the transformer 37 to the FET 20. Start flowing. At this time, as shown in FIG.
The drain current Id gradually increases only for a short time until one annular core saturates, during which time the resistance value between the source 20s and the drain 20d falls to almost zero. For this reason, the power loss during the transition period of the FET 20 from off to on is small.

When the current Id flowing through the saturating reactor 21 increases to a certain constant value Ith, the inductance decreases because the annular core is saturated, and as a result, the current flowing through the FET 20 and the transformer 37 rapidly increases. At this time, the other F
Since the ET 20 is about to be turned off from on, and the two FETs 20 are turned on alternately, magnetic fluxes having different directions are generated in the transformer 37 alternately.
An induced electromotive force is induced in the next winding, and an insulated AC voltage is obtained.

FIG. 15 shows a bridge type switching inverter circuit, in which four switches 45 to 48 are formed using four MOS type FETs 41 to 44, and these four switches 45 to 48 are assembled in a bridge type. At the same time, the polarity of the voltage of the DC power supply 49 is switched to obtain AC.
The four switches 45 to 48 have exactly the same configuration,
Charge limit diodes 1 in parallel with ET41-44
Are connected, and the saturation reactors 50 are respectively connected in series.

The switch 45 has an anode of the charge limiting diode 1 connected to the source of the FET 41, a cathode connected to the drain of the FET 41, and one end of the saturation reactor 50, and the other end of the saturation reactor 50 connected to the switch 4.
5, the source of the FET 41 is a negative electrode, and the FET 4
The source and the gate of 1 are control input terminals, and the control signal inputted thereto causes conduction between the positive electrode and the negative electrode. The same applies to the switches 46 to 48.

Switches 45 and 46 and switches 47 and 4
8 are connected in series, which are connected in parallel to the DC power supply 49, and the negative electrode of the switch 45 and the switch 4
6 is connected to form one of the output terminals, and the negative electrode of the switch 47 and the positive electrode of the switch 48 are connected to form the other output terminal.

In this inverter circuit, an alternating voltage is generated between the output terminals by alternately repeating a state where the switches 45 and 47 are turned on and the switches 46 and 48 are turned off and a state opposite thereto. I do.

FIG. 16 shows a three-phase switching inverter circuit, in which switches 61 to 66 having the same configuration as described above are connected to a DC power supply 60. Switches 61, 62
Are connected in series, both ends are connected to a DC power supply 60, and an R-phase output 67 is drawn from the connection point.
3 and 64, an S-phase output 68 is extracted, and the switch 6
5, 66, a T-phase output 69 is drawn. By sequentially turning on and off the switches 61, 63, and 65 and shifting the switches 62, 64, and 66 sequentially in half a cycle, the outputs 67, 68,
The voltage 69 is a three-phase switching waveform that changes as shown in FIG.

When any of the switches 45 to 48 and 61 to 66 is turned on, the current increase is delayed by the saturation reactor 50 into two stages, and when turned off, the voltage is increased by the charge limiting diode 1. Since two stages are delayed, power loss during the transition period of the increase or decrease of the carriers in the FETs 41 to 44 hardly occurs.

[0050]

As described above, in the switching circuit according to the present invention, at the time of switching from ON to OFF, the inertial current caused by the inductance of the circuit is absorbed by the junction capacitance of the charge limiting diode. The rise of the applied voltage is delayed, and no power loss occurs in the switching element. For this reason, the heat generation in the switching circuit is small, and the element is also downsized.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a PN junction diode.

FIG. 2 is an explanatory diagram of an impurity concentration distribution.

FIG. 3 is a characteristic diagram of voltage and junction capacitance.

FIG. 4 is a circuit diagram having a delay function.

FIG. 5 is an explanatory diagram of an excessive response of an input / output voltage.

FIG. 6 is a circuit diagram having a delay function.

FIG. 7 is an explanatory diagram of an input / output voltage transient response.

FIG. 8 is a circuit diagram having a delay function.

FIG. 9 is an explanatory diagram of an excessive response of an input / output voltage.

FIG. 10 is a circuit diagram of an embodiment applied to a half-wave partial resonance DC-DC converter.

FIG. 11 is an explanatory diagram of changes in voltage and current from OFF to ON.

FIG. 12 is an explanatory diagram of changes in voltage and current from ON to OFF.

FIG. 13 shows a second half-wave partial resonance DC-DC converter.
FIG. 3 is a circuit diagram of the embodiment of FIG.

FIG. 14 is a circuit diagram of an embodiment applied to a center tap type inverter.

FIG. 15 is a circuit diagram of an embodiment applied to a bridge type inverter.

FIG. 16 is a circuit diagram of an embodiment for a three-phase bridge type inverter.

FIG. 17 is an explanatory diagram of an output of the three-phase bridge type inverter.

FIG. 18 is an explanatory diagram of changes in current and voltage when a MOS FET is turned off.

FIG. 19 is an explanatory diagram of changes in current and voltage when the MOSFET is turned on.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Charge limiting diode 1a Anode 1k Cathode 2 Junction surface 3,4 Inner layer 5,6 Boundary surface 7,8 Intermediate layer 9,10 Outer layer 11,12 Electrode 20,27,41-44 MOS type FET 20d, 27d Drain 20g, 27g Gate 20s, 27s Source 21, 50 Saturation reactor 22, 35, 37 Transformer 22a, 35a Primary winding 22b Reset winding 22c, 35c Secondary winding 23, 28, 29 Diodes 26, 49 DC power supply 30 Negative output terminal 31 Capacitor 32 Choke coil 33 Positive output terminal 38, 39 Signal source 45-48, 61-66 Switch

Continuation of front page (56) References JP-A-62-136068 (JP, A) JP-A-49-69093 (JP, A) JP-A-63-202263 (JP, A) (58) Fields investigated (Int) .Cl. ⁶ , DB name) H03K 17/16 H01L 29/78

Claims (2)

(57) [Claims] 1. An impurity in each of P and N regions sandwiching a PN junction surface.
Thinly form high-concentration parts where the concentration is increased stepwise
And electrode surfaces are formed on both sides thereof, and the P region,
An impurity concentration between the high concentration portion of the N region and the electrode surface;
To form a low-concentration part sufficiently lower than the high-concentration part.
And the voltage-to-junction capacitance characteristic is high and low.
So that it changes abruptly at the threshold corresponding to the minute boundary
A switching circuit, wherein the charge limiting diode is connected in parallel with the switching element. 2. The switching circuit according to claim 1, wherein a square-shaped saturation reactor is connected in series with a circuit in which the charge limiting diode and the switching element are connected in parallel.