JP2018153037A - Dc conversion device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a DC conversion device capable of preventing application of an excessive voltage between a gate and a source of a switching element.SOLUTION: Provided is a DC conversion device in which a first terminal of a first switching element and a control terminal of a second switching element are connected with a first end of a secondary winding of a transformer, and a first terminal of the second switching element and a control terminal of the first switching element are connected with a second end of the secondary winding of the transformer. A second terminal of the first switching element and a second terminal of the second switching element are connected with each other. The DC conversion device comprises: a first voltage restriction element connected between the control terminal and the second terminal of the first switching element; and a second voltage restriction element connected between the control terminal and the second terminal of the second switching element.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a DC converter.

  A DC / DC converter that converts a DC voltage is used in industrial equipment and in-vehicle devices. In the DC / DC converter, a primary side and a secondary side are insulated via a transformer, and a rectifier diode is provided on the secondary winding side of the transformer. Further, since the power loss of the rectifier diode is large, a synchronous rectifier MOSFET (Metal Oxide Semiconductor Field Effect Transistor) is used instead of the rectifier diode, and induced in the secondary winding of the transformer instead of the gate driver circuit for driving the MOSFET. A voltage may be used (see Patent Document 1).

JP-A-11-262263

  However, in a conventional DC / DC converter (direct current converter) such as Patent Document 1, when the output voltage becomes relatively high, the voltage induced in the secondary winding of the transformer also becomes high, and the MOSFET for synchronous rectification The voltage (gate voltage) applied to is increased. For this reason, a voltage exceeding the rated voltage is applied between the gate and source of the MOSFET (switching element), and the MOSFET may be damaged.

  The present invention has been made in view of such circumstances, and an object of the present invention is to provide a DC converter capable of preventing an excessive voltage from being applied between the gate and the source of a switching element.

  A DC converter according to an embodiment of the present invention is a first for synchronous rectification having a transformer, a secondary terminal of the transformer, and two terminals and a control terminal for controlling conduction between the two terminals. A switching device and a second switching device, wherein the first terminal of the first switching device and the second switching device are controlled at the first end of the secondary winding of the transformer. A first terminal of the second switching element and a control terminal of the first switching element are connected to a second end of the secondary winding of the transformer, and a second terminal of the first switching element is connected. A first voltage limiting element connected between the terminal and the second terminal of the second switching element, and connected between the control terminal and the second terminal of the first switching element; and the second switching element. Elementary A control terminal of the second voltage limiting element connected between the second terminal.

  According to the present invention, it is possible to prevent an excessive voltage from being applied between the gate and the source of the switching element.

It is explanatory drawing which shows the 1st example of the circuit structure of the DC converter of this Embodiment. It is a schematic diagram which shows an example of the waveform of each part of the direct-current converter of this Embodiment. It is a schematic diagram which shows an example of the waveform of each part when not having a bypass circuit. It is a schematic diagram which shows an example of the waveform of each part in the case of comprising a bypass circuit. It is explanatory drawing which shows the 2nd example of the circuit structure of the DC converter of this Embodiment.

[Description of Embodiment of Present Invention]
The DC converter according to the present embodiment includes a transformer and a first switching for synchronous rectification that is provided on the secondary side of the transformer and includes two terminals and a control terminal that controls conduction between the two terminals. A DC conversion device including an element and a second switching element, wherein a first terminal of the first switching element and a control terminal of the second switching element are provided at a first end of a secondary winding of the transformer. And connecting the first terminal of the second switching element and the control terminal of the first switching element to the second end of the secondary winding of the transformer, and the second terminal of the first switching element; A first voltage limiting element connected between the second terminal of the second switching element and connected between the control terminal and the second terminal of the first switching element; and System And a second voltage limiting element connected between the terminal and the second terminal.

  The first terminal of the first switching element and the control terminal of the second switching element are connected to the first end of the secondary winding of the transformer, and the second switching element is connected to the second end of the secondary winding of the transformer. The first terminal and the control terminal of the first switching element are connected. The second terminal of the first switching element and the second terminal of the second switching element are connected. The switching element is, for example, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor). The first terminal can be a drain, the second terminal can be a source, and the control terminal can be a gate.

  A first voltage limiting element is connected between the control terminal and the second terminal of the first switching element, and a second voltage limiting element is connected between the control terminal and the second terminal of the second switching element. It is. The voltage limiting element can be a Zener diode, for example.

  The secondary winding of the transformer has, for example, a positive voltage (for example, a voltage at which the second end is higher than the first end) and a negative voltage (for example, a voltage at which the first end is higher than the second end). And induce alternately. When the voltage of the positive electrode is induced, the first switching element is turned on, and a load current flows through the first switching element. In addition, when a negative voltage is induced, the second switching element is turned on, and a load current flows through the second switching element.

  Immediately before the first switching element is turned on, the voltage of the secondary winding is applied between the control terminal and the second terminal of the first switching element. Since the first voltage limiting element is connected between them, the voltage applied between the control terminal and the second terminal is limited by the first voltage limiting element, and the gate of the switching element (eg, MOSFET) The voltage applied between the sources can be prevented from exceeding the rated voltage, and an excessive voltage can be prevented from being applied.

  Immediately before the second switching element is turned on from off, the voltage of the secondary winding is applied between the control terminal and the second terminal of the second switching element. Since the second voltage limiting element is connected between them, the voltage applied between the control terminal and the second terminal is limited by the second voltage limiting element so as not to exceed the rated voltage. It is possible to prevent an excessive voltage from being applied between the gate and source of the switching element (eg, MOSFET).

  The DC converter according to the present embodiment includes a first resistor provided on an electric circuit between a second end of the secondary winding and a control terminal of the first switching element, and the secondary winding. And a second resistor provided in an electric circuit between the first end of the second switching element and the control terminal of the second switching element.

  A first resistor is provided in the electrical path between the second end of the secondary winding and the control terminal of the first switching element, and between the first end of the secondary winding and the control terminal of the second switching element. A second resistor is provided in the electric circuit.

  By providing the first resistor and the second resistor, it is possible to limit the current flowing through the first voltage limiting element and the second voltage limiting element, and thus the first voltage limiting element and the second voltage limiting element. The loss of the element can be reduced.

  The direct-current converter according to the present embodiment is connected in parallel to the first resistor, has a resistance smaller than the first resistance, and flows out from the control terminal of the first switching element. A first bypass circuit for bypassing current and a resistor connected in parallel to the second resistor, having a resistance value smaller than that of the second resistor, and flowing out from the control terminal of the second switching element A second bypass circuit that bypasses the current.

  The first bypass circuit is connected in parallel to the first resistor, has a resistance smaller than the first resistance, and bypasses the current flowing out from the control terminal of the first switching element. The second bypass circuit is connected in parallel to the second resistor, has a resistance smaller than the second resistance, and bypasses the current flowing out from the control terminal of the second switching element.

  When the first switching element is turned off from on, it is necessary to draw out the electric charge accumulated in the first switching element from the control terminal. By having a resistance whose resistance value is smaller than that of the first resistance, the turn-off time during which the first switching element is turned off can be shortened, and the first switching element and the second switching element can be simultaneously A state of being turned on can be prevented.

  In addition, when the second switching element is turned off from on, it is necessary to draw out the electric charge accumulated in the second switching element from the control terminal. By having a resistance whose resistance value is smaller than that of the second resistance, the turn-off time during which the second switching element is turned off can be shortened, and the second switching element and the first switching element can be simultaneously A state of being turned on can be prevented.

  In the DC converter according to the present embodiment, each of the first bypass circuit and the second bypass circuit has a diode connected in series with the resistor.

  Each of the first bypass circuit and the second bypass circuit has a diode connected in series with a resistor. Thereby, when the first switching element and the second switching element are turned on from off, the current flowing through the resistor is cut off by the diode so that the current flows through the first resistor and the second resistor, Losses of the first voltage limiting element and the second voltage limiting element can be reduced by the relatively large first resistance and second resistance.

  When the first switching element and the second switching element are turned from ON to OFF, the current flowing through the first resistor and the second resistor is bypassed to the resistor by the diode, and the first switching element and the second switching element are bypassed. By shortening the turn-off time of the switching element, it is possible to prevent the first switching element and the second switching element from being turned on simultaneously.

[Details of the embodiment of the present invention]
Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is an explanatory diagram illustrating a first example of a circuit configuration of the DC converter 100 of the present embodiment. The DC converter 100 according to the present embodiment includes terminals A and B on the input side and terminals C and D on the output side. A DC power source (not shown) is connected to the terminals A and B on the input side, and outputs A load is connected to the terminals C and D on the side. The DC converter 100 is, for example, a step-down converter.

  The DC converter 100 includes a transformer 20, a FET 11, a FET 12, a capacitor 13 connected in parallel to the FET 11, a capacitor 14 connected in series to the FET 12, and the like provided on the primary winding 21 side of the transformer 20. FET 31 as a first switching element for synchronous rectification, FET 32 as a second switching element, Zener diode 41 as a first voltage limiting element, second voltage provided on the secondary winding 22 side of 20 Zener diode 42 as a limiting element, first resistor 51, second resistor 52, first bypass circuit 61 composed of resistor 611 and diode 612, second bypass circuit composed of resistor 621 and diode 622 62, inductor 71 (choke coil on the output side), capacitor 72 Equipped with a.

  Note that the first resistor 51, the second resistor 52, the first bypass circuit 61, and the second bypass circuit 62 are not essential components and may not be provided. Each of the FET 11, FET 12, FET 31, and FET 32 has a body diode. In this specification, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) is referred to as an FET.

  One end of the primary winding 21 of the transformer 20 is connected to the terminal A. The other end of the primary winding 21 is connected to the drain of the FET 11. The source of the FET 11 is connected to the terminal B. A capacitor 13 (resonance capacitor) is connected between the drain and source of the FET 11.

  A series circuit of the FET 12 and the capacitor 14 is connected to both ends of the primary winding 21. A series circuit of the FET 12 and the capacitor 22 constitutes an active clamp circuit.

  In the example of FIG. 1, one end of the capacitor 14 is connected to one end of the primary winding 21, and the drain of the FET 12 is connected to the other end of the capacitor 14. The source of the FET 12 is connected to the other end of the primary winding 21.

  The FET 11 and FET 12 are ON / OFF controlled at a predetermined duty ratio by a control unit (not shown) (for example, a gate driver). Note that a dead time during which both the FET 11 and the FET 12 are turned off is provided immediately before the FET 11 and the FET 12 are turned on.

  The drain (first terminal) of the FET 31 and the gate (control terminal) of the FET 32 are connected to the first end 22 a of the secondary winding 22 of the transformer 20. The drain (first terminal) of the FET 32 and the gate (control terminal) of the FET 31 are connected to the second end 22 b of the secondary winding 22 of the transformer 20. The source (second terminal) of the FET 31 and the source (second terminal) of the FET 32 are connected. The sources of the FET 31 and FET 32 are connected to the terminal D (ground level).

  One end of the inductor 71 is connected to the connection point between the drain of the FET 32 and the second end 22 b of the secondary winding 22, and the other end of the inductor 71 is connected to the terminal C. A capacitor 72 is connected between the terminals C and D.

  A Zener diode 41 is connected between the gate and source of the FET 31. The anode of the Zener diode 41 is connected to the source of the FET 31, and the cathode of the Zener diode 41 is connected to the gate of the FET 31.

  A Zener diode 42 is connected between the gate and source of the FET 32. The anode of the Zener diode 42 is connected to the source of the FET 32, and the cathode of the Zener diode 42 is connected to the gate of the FET 32.

  A resistor 51 is provided in the electrical path between the second end 22b of the secondary winding 22 and the gate of the FET 31, and a resistor 52 is provided in the electrical path between the first end 22a of the secondary winding 22 and the gate of the FET 32. Yes.

  The first bypass circuit 61 is connected in parallel to the resistor 51, has a resistor 611 having a smaller resistance value than the resistor 51, and bypasses the current flowing out from the gate of the FET 31. The second bypass circuit 62 is connected in parallel to the resistor 52, has a resistor 621 having a resistance value smaller than that of the resistor 52, and bypasses the current flowing out from the gate of the FET 32.

  More specifically, the first bypass circuit 61 includes a diode 612 connected in series with the resistor 611. The anode of the diode 612 is connected to the gate of the FET 31 via the resistor 611, and the cathode of the diode 612 is connected to the second end 22 b of the secondary winding 22.

  The second bypass circuit 62 has a diode 622 connected in series with the resistor 621. The anode of the diode 622 is connected to the gate of the FET 32 via the resistor 621, and the cathode of the diode 622 is connected to the first end 22 a of the secondary winding 22.

  Next, the operation of the DC converter 100 according to the present embodiment will be described.

  FIG. 2 is a schematic diagram showing an example of the waveform of each part of the DC converter 100 of the present embodiment. In the figure, the horizontal axis indicates time. The upper diagram shows the voltage Vtr (induced voltage) of the secondary winding 22 of the transformer 20, the middle diagram shows the gate voltage Vgs1 (gate-source voltage) of the FET 31, and the lower diagram shows the gate voltage Vgs2 of the FET 32. (Gate-source voltage). Note that the voltages Vtr, Vgs1, and Vgs2 are positive in the direction of the arrows shown in FIG. The waveform shown in FIG. 2 is schematically shown for convenience, and may be different from the actual waveform.

  When the FETs 11 and 12 are alternately turned on / off, a voltage as shown in the upper diagram of FIG. 2 is induced in the secondary winding 22 of the transformer 20.

  That is, the secondary winding 22 of the transformer 20 includes, for example, a positive voltage (for example, a voltage V1 having a higher second end 22b than the first end 22a) and a negative voltage (for example, the second end 22b). Thus, the first end 22a is alternately induced with a high voltage V2). When the positive voltage V <b> 1 is induced, the FET 31 is turned on, and a load current flows through the FET 31 and the inductor 71. When the negative voltage V <b> 2 is induced, the FET 32 is turned on, and a load current flows through the FET 32 as energy stored in the inductor 71.

  The voltage V1 of the secondary winding 22 is applied between the gate and the source of the FET 31 immediately before the time t1 when the FET 31 is turned on, but the Zener diode 41 is connected between the gate and the source of the FET 31. Therefore, the voltage applied between the gate and the source of the FET 31 is limited by the Zener diode 41 to Vz, so that the rated voltage Vh between the gate and the source of the FET 31 cannot be exceeded. It is possible to prevent an excessive voltage from being applied.

  Further, immediately before the time point t2 when the FET 32 is turned on from off, the voltage V2 of the secondary winding 22 is applied between the gate and the source of the FET 32, but a Zener diode 42 is provided between the gate and the source of the FET 32. Therefore, the voltage applied between the gate and the source of the FET 32 is limited by the Zener diode 42 to Vz, so that the rated voltage Vh between the gate and the source of the FET 32 is not exceeded. It is possible to prevent an excessive voltage from being applied.

  By providing the resistor 51, the current flowing through the Zener diode 41 can be limited, so that the loss of the Zener diode 41 can be reduced. In addition, since the resistor 52 is provided, the current flowing through the Zener diode 42 can be limited, so that the loss of the Zener diode 42 can be reduced. If the losses of the Zener diodes 41 and 42 are within an allowable range, the resistance values of the resistors 51 and 52 may be set to a relatively small value.

  Next, the operation of the bypass circuits 61 and 62 will be described. First, a case where the bypass circuits 61 and 62 are not provided will be described.

  FIG. 3 is a schematic diagram showing an example of the waveform of each part when the bypass circuits 61 and 62 are not provided. In the figure, the horizontal axis indicates time. The upper diagram shows the gate voltage of the FET 31, the middle diagram shows the gate voltage of the FET 32, and the lower diagram shows the current of the FET 32.

  When the voltage V1 of the secondary winding 22 becomes 0 at time t11, the FET 31 goes from the on state to the off state (however, the on state of the FET 31 continues for a while after time t11). In this case, when the resistance value of the resistor 51 connected to the gate of the FET 31 is relatively large, the time constant for discharging the charge accumulated in the FET 31 from the gate to the outside becomes large, so-called turn-off time is delayed. Therefore, even when the dead time is provided, when the gate voltage of the FET 32 exceeds the threshold voltage Vth at the time t12 and the FET 32 is turned on, the FET 31 is not turned off, so that the FET 31 and the FET 32 are simultaneously turned on. And a relatively large current flows through the FET 32. The same applies when the FET 31 is turned on.

  Therefore, when the current flowing through the FET 32 exceeds the allowable range, the bypass circuits 61 and 62 may be provided.

  FIG. 4 is a schematic diagram showing an example of the waveform of each part when the bypass circuits 61 and 62 are provided. By including the resistor 611 having a resistance value smaller than that of the resistor 51, the bypass circuit 61 can shorten the turn-off time in which the FET 31 is turned off from the on state, and prevent the FET 31 and the FET 32 from being turned on at the same time. Can do. Thereby, the current flowing through the FET 32 when the FET 32 is turned on can be suppressed.

  Although the bypass circuit 62 includes the resistor 621 having a resistance value smaller than that of the resistor 52, the turn-off time during which the FET 32 is turned off can be shortened, and the FET 32 and the FET 31 are simultaneously connected. A state of being turned on can be prevented. Thereby, the current flowing through the FET 31 when the FET 31 is turned on can be suppressed.

  More specifically, when the FET 31 is turned on from OFF, the current flowing through the resistor 611 is cut off by the diode 612 and the current flows through the resistor 51, and the loss of the Zener diode 41 is reduced by the relatively large resistor 51. Can be reduced. Further, when the FET 32 is turned on from off, the current flowing through the resistor 621 is cut off by the diode 622 and the current flows through the resistor 52, and the loss of the Zener diode 41 can be reduced by the relatively large resistor 52. it can.

  When the FET 31 is turned off from on, the current flowing in the resistor 51 by the diode 612 is bypassed to the resistor 611 having a smaller resistance value, and the turn-off time of the FET 31 is shortened so that the FET 31 and the FET 32 are simultaneously turned on. Can be prevented.

  Further, when the FET 32 is turned off from on, the current flowing in the resistor 52 by the diode 622 is bypassed to the resistor 621 having a smaller resistance value, and the turn-off time of the FET 32 is shortened so that the FET 31 and the FET 32 are simultaneously turned on. A state can be prevented.

  The configuration of the current conversion device 100 is not limited to the configuration shown in FIG. Other configurations will be described below.

  FIG. 5 is an explanatory diagram showing a second example of the circuit configuration of the DC converter 100 of the present embodiment. The difference from the first example shown in FIG. 1 is that the transformer 20 is a so-called center tap system. As shown in FIG. 5, one end of the inductor 71 is connected to the center tap (third end) 22 c of the secondary winding 22. Since other configurations are the same as those of the first example, description thereof is omitted.

  Also in the second example, it is possible to prevent an excessive voltage from being applied between the gates and the sources of the FETs 31 and 32.

  Also in the second example, by providing the resistor 51, the current flowing through the Zener diode 41 can be limited, so that the loss of the Zener diode 41 can be reduced. In addition, since the resistor 52 is provided, the current flowing through the Zener diode 42 can be limited, so that the loss of the Zener diode 42 can be reduced.

  By including the resistor 611 having a resistance value smaller than that of the resistor 51, the bypass circuit 61 can shorten the turn-off time in which the FET 31 is turned off from the on state, and prevent the FET 31 and the FET 32 from being turned on at the same time. Can do. Thereby, the current flowing through the FET 32 when the FET 32 is turned on can be suppressed. The same applies to the bypass circuit 62.

  More specifically, when the FET 31 is turned on from OFF, the current flowing through the resistor 611 is cut off by the diode 612 and the current flows through the resistor 51, and the loss of the Zener diode 41 is reduced by the relatively large resistor 51. Can be reduced. Further, when the FET 32 is turned on from off, the current flowing through the resistor 621 is cut off by the diode 622 and the current flows through the resistor 52, and the loss of the Zener diode 41 can be reduced by the relatively large resistor 52. it can. The same applies to the FET 32.

  When the FET 31 is turned off from on, the current flowing in the resistor 51 by the diode 612 is bypassed to the resistor 611 having a smaller resistance value, and the turn-off time of the FET 31 is shortened so that the FET 31 and the FET 32 are simultaneously turned on. Can be prevented. The same applies to the FET 32.

  The switching element is not limited to a MOSFET, and may be a device such as an IGBT (Insulated Gate Bipolar Transistor). In the case where the switching element is a MOSFET as in the present embodiment, there is an equivalently incorporated body diode between the drain and source. When a bipolar transistor is used as the switching element, a diode may be connected in antiparallel between the collector and emitter of the transistor.

  In the present embodiment, the configuration of the DC / DC converter as shown in FIGS. 1 and 5 has been described as an example of the power supply device. However, the configuration of the DC / DC converter is illustrated in FIGS. 1 and 5. The configuration is not limited.

  In this embodiment, FETs may be used instead of the diodes 612 and 622.

  The embodiments and examples disclosed above should be considered as illustrative in all points and not restrictive. The scope of the present invention is shown not by the above embodiments and examples but by the scope of claims, and is intended to include all modifications and variations within the meaning and scope equivalent to the scope of claims. .

11, 12, 31, 32 FET
13, 14, 72 Capacitor 20 Transformer 21 Primary winding 22 Secondary winding 41, 42 Zener diode 61, 62 Bypass circuit 51, 52, 611, 621 Resistance 612, 622 Diode 71 Inductor

Claims (4)

DC including a transformer, and a first switching element and a second switching element for synchronous rectification that are provided on the secondary side of the transformer and have two terminals and a control terminal that controls conduction between the two terminals. A conversion device,
Connecting the first terminal of the first switching element and the control terminal of the second switching element to the first end of the secondary winding of the transformer;
Connecting the first terminal of the second switching element and the control terminal of the first switching element to the second end of the secondary winding of the transformer;
Connecting the second terminal of the first switching element and the second terminal of the second switching element;
A first voltage limiting element connected between a control terminal and a second terminal of the first switching element;
A DC converter comprising: a second voltage limiting element connected between a control terminal and a second terminal of the second switching element. A first resistor provided in an electric circuit between a second end of the secondary winding and a control terminal of the first switching element;
The DC converter according to claim 1, further comprising: a second resistor provided on an electric circuit between a first end of the secondary winding and a control terminal of the second switching element. A first bypass circuit connected in parallel to the first resistor, having a resistance smaller than the first resistance, and bypassing a current flowing out from a control terminal of the first switching element;
A second bypass circuit connected in parallel to the second resistor, having a resistance smaller than the second resistance, and bypassing a current flowing out from a control terminal of the second switching element; The direct-current converter according to claim 2 provided. Each of the first bypass circuit and the second bypass circuit is:
The DC converter according to claim 3, further comprising a diode connected in series with the resistor.

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