JP3166149B2 - DC converter device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a parallel operation of a plurality of synchronous rectification type DC-DC converters constituting a DC converter device.

[0002]

2. Description of the Related Art A diode rectifier such as a Schottky barrier diode (SBD) is generally used in an output rectifier circuit of a low output voltage DC-DC converter. The power loss at the time increases, which causes a reduction in efficiency. For this reason, a synchronous rectification type DC-DC converter has been proposed in which an efficiency is improved by using a switching element such as a MOS-FET having a low electric resistance when conducting to an output rectifier circuit and having no offset voltage as a synchronous rectifier. ing. For example, the synchronous rectification type DC-DC converter shown in FIG.
And a primary winding 3a of a transformer 3 connected in series to both ends of the input capacitor 2 and an MO as a main switching element.
Synchronous rectification MOS-F as a synchronous rectification switching element connected in series to both ends of an S-FET 4 and a secondary winding 3b magnetically coupled with the same polarity as the primary winding 3a of the transformer 3
The ET 5 includes a flywheel diode 6 as a rectifying element for a flywheel, and a filter circuit including an output reactor 7 and an output capacitor 8 connected to both ends of the flywheel diode 6. In FIG. 6, reference numeral 5a denotes a parasitic diode existing between the drain and the source of the synchronous rectification MOS-FET 5. Transformer 3 2
The two ends of the winding 3b resistors 9 and 10 is connected, the secondary winding 3b voltage V _T is synchronized via the resistor 9 rectification MOS-F of
The gate is applied to the gate terminal (control terminal) of ET5, and the synchronous rectification MOS-FET 5 is turned on and off. here,
The resistor 9 is a resistor for suppressing an inrush current flowing through the gate-source capacitance of the synchronous rectification MOS-FET 5.
0 is a resistor for discharging the gate-source capacitance of the MOS-FET 5 for synchronous rectification. Actually, the resistance value of the resistor 9 is several Ω, and the resistance value of the resistor 10 is several kΩ to several tens kΩ.

Further, both ends of the output capacitor 8 and the MOS-
The DC output voltage V supplied to the load 11 connected between both ends of the output capacitor 8 is provided between the output terminal and the gate terminal of the FET 4.
By controlling the pulse width of the control pulse signal applied to the gate terminal of the MOS-FET 4 according to _O , the MOS-F
Constant voltage control circuit 12 for controlling ON / OFF period of ET4
Is provided. Constant voltage control circuit 12 includes a voltage dividing resistor 13 for dividing the DC output voltage V _O, a reference power source 15 for generating a reference voltage V _R which defines the output voltage value, the partial pressure of dividing resistor 13 comparing the reference voltage V _R of the voltage and the reference power source 15 of the point and the error amplifier 16 which outputs a voltage corresponding to the difference, the optical output of the light emitting portion 17a and the light emitting portion 17a is driven by the output of the error amplifier 16 The pulse width of the control pulse signal applied to the gate terminal of the MOS-FET 4 is controlled according to the current flowing through the light receiving unit 17b of the photocoupler 17. And a PWM modulation circuit 18. The PWM modulation circuit 18
The operation of narrowing the pulse width of the control pulse signal output when the light output of the light emitting unit 17a of the photocoupler 17 increases and the current flowing in the light receiving unit 17b increases, and the voltage between the collector and the emitter of the light receiving unit 17b decreases. Then, the light output of the light emitting portion 17a of the photocoupler 17 decreases, the current flowing in the light receiving portion 17b decreases, and the pulse width of the control pulse signal output increases when the voltage between the collector and the emitter of the light receiving portion 17b increases. Work.

The operation of the main circuit of the synchronous rectification type DC-DC converter shown in FIG. 6 is as follows. Constant voltage control circuit 1
When a control pulse signal is given from the PWM modulation circuit 18 in the MOS-FET 2 and the MOS-FET 4 is turned on, the DC power supply 1
Of the transformer 3 via the input capacitor 2
And the current flows through the primary winding 3a of the transformer 3. As a result, as shown in FIG. 7A, a voltage V _T having the same polarity as the primary winding 3a (which is referred to as a positive voltage) is generated in the secondary winding 3b of the transformer 3, and this voltage V _T is applied to the gate terminal of the synchronous rectification MOS-FET 5 via the resistor 9. At this time, MOS-FET for synchronous rectification
As shown in FIG. 7B, the voltage V _GS between the gate and source terminals of the MOS FET 5 becomes high level, and the synchronous rectification MOS-FET 5 is turned on. Also, the flywheel diode 6 is reverse-biased and is in a non-conductive state.
A current flows through the path of the next winding 3b, the output reactor 7, the output capacitor 8, and the load 11-the synchronous rectification MOS-FET 5. Next, when the MOS-FET 4 changes from the on state to the off state, as shown in FIG. 7A, a voltage having a polarity opposite to that of the primary winding 3a is applied to the secondary winding 3b of the transformer 3 (this is a negative voltage). -V _T occurs. Secondary winding 3b of transformer 3
The negative voltage -V _T generated in the synchronous rectification MO
Since the charge between the gate and the source of the S-FET 5 is rapidly discharged through the resistor 9, the secondary winding 3b of the transformer 3, and the synchronous rectification MOS-FET 5, the synchronous rectification MOS-FE is discharged.
The voltage V _GS between the gate and source terminals of T5 decreases, and the synchronous rectification MOS-FET 5 is turned off. Accordingly, the voltage V _DS between the drain and source terminals of the synchronous rectification MOS-FET 5 is as shown in FIG. At this time, the flywheel diode 6 is forward-biased and becomes conductive, so that the synchronous rectification MO as shown in FIG.
The voltage V _GS between the gate and source terminals of S-FET5 is 0V
Thus, a current flows through the path of the output reactor 7-the output capacitor 8 and the load 11-the flywheel diode 6.

The constant voltage control operation of the synchronous rectification type DC-DC converter shown in FIG. 6 is as follows. For example,
When the load 11 is in a light load state and the DC output voltage V _O increases, the voltage at the voltage dividing point of the voltage dividing resistors 13 and 14 increases, and the output voltage of the error amplifier 16 decreases.
The forward current flowing through the light emitting section 17a increases. Therefore, the light output of the light emitting portion 17a of the photocoupler 17 increases and the current flowing to the light receiving portion 17b increases, so that the voltage between the collector and the emitter of the light receiving portion 17b decreases. As a result, the pulse width of the control pulse signal applied from the PWM modulation circuit 18 to the gate terminal of the MOS-FET 4 becomes narrower, and the ON period of the MOS-FET 4 becomes shorter, so that the DC output voltage V _O decreases. Conversely, when the load 11 is overloaded and the DC output voltage V _O decreases, the voltage at the voltage dividing points of the voltage dividing resistors 13 and 14 decreases and the error amplifier 1
6, the output voltage of the light emitting section 17 of the photocoupler 17 increases.
The forward current flowing through a decreases. Therefore, the light output of the light emitting portion 17a of the photocoupler 17 decreases, and the light receiving portion 1
Since the current flowing through 7b decreases, the voltage between the collector and the emitter of the light receiving section 17b increases. With this, PWM
The pulse width of the control pulse signal applied from the modulation circuit 18 to the gate terminal of the MOS-FET 4 is increased,
Since the ON period of the FET 4 becomes longer, the DC output voltage V _O increases. By the above operation, the synchronous rectification type D shown in FIG.
The DC output voltage V _O of the C-DC converter is controlled to a constant value, and a constant-voltage DC output is supplied to the load 11.

[0006]

By the way, two synchronous rectification type DC-DC converters shown in FIG. 6 are connected in parallel between a DC power supply 1 and a load 11 as shown in FIG. In the case of configuring a converter device, for example, the DC output voltage V _{O of the} synchronous rectification type DC-DC converter A
When the set value of the DC output voltage V _O of the synchronous rectification type DC-DC converter B is higher than the set value of the synchronous rectification type DC-DC converter B, and the power required for the load 11 is in a light load state that can be covered by one converter, The DC output is supplied only to the load 11 from the converter B, and the DC output is not supplied to the load 11 from the synchronous rectification type DC-DC converter A. At this time, in the synchronous rectification type DC-DC converter A, since the voltage across the output capacitor 8 becomes larger than the set value of the DC output voltage V _O , the MOS-F
The pulse width of the control pulse signal applied to the gate terminal of the ET4 is narrowed, and the ON period of the MOS-FET 4 in the synchronous rectification type DC-DC converter A becomes extremely short. When the load 11 is further lightly loaded and the DC output voltage V _{O of} the synchronous rectification type DC-DC converter B further increases, the voltage of the output capacitor 8 in the synchronous rectification type DC-DC converter A further increases. The pulse width of the control pulse signal applied to the gate terminal of the MOS-FET 4 by the voltage control circuit 12 is further narrowed, and finally the pulse width becomes zero. Thereby, the MOS-FET 4 of the synchronous rectification type DC-DC converter A is completely turned off,
Voltage V _T of the secondary winding 3b of the transformer 3 becomes 0V. At this time, a DC voltage is applied between the gate and source terminals of the synchronous rectification MOS-FET 5 in the synchronous rectification type DC-DC converter A by the DC output voltage V _O of the synchronous rectification type DC-DC converter B to be turned on. Then, a direct current in the opposite direction starts to flow from the output side of the synchronous rectification type DC-DC converter A to the secondary winding 3b of the transformer 3. Due to the increase of the DC current in the reverse direction, the transformer 3 of the synchronous rectification type DC-DC converter A becomes saturated, and the DC output voltage V
_O decreases. Therefore, the MOS-FET 4 of the synchronous rectification type DC-DC converter A is turned on, an excessive current flows between the drain and the source, and the MOS-FET 4 is damaged. In some cases, synchronous rectification MOS-FE
T5 may also be damaged. Therefore, when there are variations in the respective set values of the DC output voltage V _O of the plurality of synchronous rectification type DC-DC converters constituting the DC converter device, the synchronous rectification type DC having the lowest set value of the DC output voltage V _O is provided. -The MOS-FET which is the main switching element in the DC converter is damaged, and a plurality of synchronous rectification type DC
-There is a disadvantage that parallel operation of the DC converter becomes difficult.

Therefore, the present invention provides a plurality of synchronous rectification type DCs.
The object of the present invention is to provide a DC converter device capable of preventing breakage of a main switching element and satisfactorily operating the synchronous rectification type DC-DC converters in parallel even when there are variations in the respective set values of the DC output voltage of the DC converter. And

[0008]

A DC converter according to the present invention comprises a primary winding (3a) and a main switching element (4) of a transformer (3) connected in series to both ends of a DC power supply (1);
FET for synchronous rectification connected in series to both ends of a secondary winding (3b) magnetically coupled with the same polarity as the primary winding (3a) of the transformer (3)
(5) and a flywheel rectifier (6), and a filter circuit (7,
8), a voltage is generated in the secondary winding (3b) of the transformer (3) by the on / off operation of the main switching element (4),
FET for synchronous rectification by voltage generated in secondary winding (3b)
(5) is turned on and off, and the filter circuit (7,
Turn on the main switching element (4) according to the output voltage of (8).
By turning off the power supply, a plurality of synchronous rectification type DC-DC converters (A, B) for supplying a constant-voltage DC output to the load (11) connected to the filter circuits (7, 8) are connected to the DC power supply.
It is connected in parallel between (1) and load (11). In this DC converter device, in each of the plurality of synchronous rectification type DC-DC converters (A, B), a DC voltage blocking capacitor (2
The series circuit of 1) and the inrush current suppression resistor (9) is
It is connected between the gate terminal of ET (5) and the secondary winding (3b). In addition, each synchronous rectification type DC-DC converter (A, B)
A rectifying element for clamping (22) may be connected between the gate terminal of the synchronous rectifying FET (5) and one of the main terminals, and a resistor (23) is connected in series with the rectifying element for clamping (22). ) May be connected.

A plurality of synchronous rectification type DC-DC converters
During the parallel operation of (A, B), since the other synchronous rectification type DC-DC converter (B) generates a DC output, the synchronous rectification FET (5) in one synchronous rectification type DC-DC converter (A) The DC voltage is applied to the gate terminal of the synchronous rectification FET (5), while the DC voltage blocking capacitors (21) prevent the DC output from being applied to the gate terminal of the synchronous rectification FET (5).
A malfunction of the ET (5) can be prevented. Also, the transformer (3) is increased due to an increase in the reverse DC current flowing from the output side of the other synchronous rectification type DC-DC converter (B) to the secondary circuit of the one synchronous rectification type DC-DC converter (A). By preventing the saturation, the main switching element (4) in one of the synchronous rectification type DC-DC converters (A) can be prevented from being damaged.
Therefore, a plurality of synchronous rectification type DC-DC converters
Even if the set values of the DC output voltages of (A, B) vary, the main switching element (4) is prevented from being damaged and the synchronous rectification type DC-DC converters (A, B) can be operated in parallel well. .
Further, in each of the synchronous rectification type DC-DC converters (A, B), a series circuit of a DC voltage blocking capacitor (21) and an inrush current suppression resistor (9) is connected to a gate terminal of a synchronous rectification FET (5). And the secondary winding (3b), the inrush current flowing from the secondary winding (3b) to the gate-source capacitance of the synchronous rectification FET (5) can be suppressed. In addition, synchronous rectification FETs in each synchronous rectification type DC-DC converter (A, B)
In the case where a rectifying element for clamping (22) is connected between the gate terminal of (5) and one main terminal, respectively,
The negative voltage applied to the gate terminal during the OFF period of ET (5) is clamped by the rectifying element for clamping (22), and the positive voltage applied to the gate terminal during the ON period of the synchronous rectification FET (5). Since the voltage level increases, the FE for synchronous rectification
T (5) can be reliably turned on / off. Further, when a resistor (23) is connected in series with the clamp rectifier (22), the voltage applied to the gate terminal during the off period of the synchronous rectifier FET (5) is shifted to the negative side by the resistor (23). Since the bias is biased, it is possible to prevent the malfunction of the synchronous rectification FET (5) when a positive surge voltage is applied to the gate terminal due to external noise or the like during the off period of the synchronous rectification FET (5). it can.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a DC converter according to the present invention will be described below with reference to FIGS. However, in FIG. 1, the same portions as those shown in FIG. 8 are denoted by the same reference numerals, and description thereof will be omitted. As shown in FIG. 1, the DC converter of this embodiment has a DC blocking capacitor 21 connected in series with the resistor 9 in each of the synchronous rectification type DC-DC converters A and B in the DC converter shown in FIG. It was done. Other circuit configurations are substantially the same as the DC converter device of FIG.

In the configuration shown in FIG. 1, each synchronous rectification type D
The basic operation of the main circuit of the C-DC converters A and B is as follows.
The operation of the main circuit of the synchronous rectification type DC-DC converter shown in FIG. However,
Each synchronous rectification type DC-DC converter shown in FIG. 1 A, B in, MOS-FE for the secondary winding 3b into a DC voltage blocking capacitor 21 and the synchronous rectification voltage V _T generated by the transformer 3
Since the voltage is divided by the gate-source capacitance of T5 and the divided voltage is applied to the gate terminal of the synchronous rectification MOS-FET 5, the waveform of the voltage V _GS between the gate and source terminals of the synchronous rectification MOS-FET 5 is positive or negative. A point of a symmetrical rectangular wave AC voltage waveform (FIG. 3B) is different from the case of the synchronous rectification type DC-DC converter shown in FIG. 6 (FIG. 7B). Each synchronous rectification type DC-DC converter A shown in FIG.
Drain voltage V _T and the synchronous rectification MOS-FET 5 which is generated at the secondary winding 3b of the transformer 3 B - the waveform of the voltage V _DS between the source terminal (FIG. 3 (A) and 3 (C)), respectively The waveforms are substantially the same as those of the synchronous rectification type DC-DC converter shown in FIG. 6 (FIGS. 7A and 7C).

Here, the synchronous rectification type DC-DC shown in FIG.
When the set value of the DC output voltage V _O of the converter B is higher than the set value of the DC output voltage V _O of the synchronous rectification type DC-DC converter A, and in a light load state where the power required for the load 11 can be covered by one converter. The DC output is supplied to the load 11 only from the synchronous rectification type DC-DC converter B, and the DC output is not supplied to the load 11 from the synchronous rectification type DC-DC converter A. At this time, since the voltage across the output capacitor 8 of the synchronous rectification type DC-DC converter A becomes larger than the set value of the DC output voltage V _O , the voltage is applied to the gate terminal of the MOS-FET 4 by the constant voltage control circuit 12. The pulse width of the control pulse signal is narrowed, and the synchronous rectification DC
-The ON period of the MOS-FET 4 in the DC converter A becomes extremely short. When the load 11 further enters a light load state and the DC output voltage V _{O of} the synchronous rectification type DC-DC converter B further increases, the voltage of the output capacitor 8 of the synchronous rectification type DC-DC converter A further increases. The pulse width of the control pulse signal applied to the gate terminal of the MOS-FET 4 by the control circuit 12 is further reduced, and finally the pulse width becomes zero. Thereby, synchronous rectification type D
MOS-FET 4 of C-DC converter A is completely turned off, the voltage V _T of the secondary winding 3b of the transformer 3 is 0V
Becomes At this time, the synchronous rectification type DC-DC converter B
Of the synchronous rectification type DC-DC converter A is blocked by the DC voltage blocking capacitor 21 in the synchronous rectification type DC-DC converter A. Therefore, it is possible to prevent the synchronous rectification type MOS-FET 5 in the synchronous rectification type DC-DC converter A from being turned on by the DC output voltage V _O of the synchronous rectification type DC-DC converter B. Thereby, the synchronous rectification type DC-
From the output side of the DC converter A to the secondary winding 3 of the transformer 3
The direct current flowing in the reverse direction b is prevented, and the saturation of the transformer 3 can be prevented, so that the damage of the MOS-FET 4 can be prevented. The constant voltage operation of each of the synchronous rectification type DC-DC converters A and B shown in FIG. 1 is substantially the same as the constant voltage operation of the synchronous rectification type DC-DC converter shown in FIG. .

In the DC converter device of the embodiment shown in FIG. 1, when the DC output voltages V _O of the synchronous rectification type DC-DC converters A and B vary, the synchronous rectification type DC-DC Synchronous rectification type DC-D is provided by DC voltage blocking capacitor 21 in converter A.
The synchronous rectification MOS-FET 5 in the C converter A is prevented from being turned on by the DC output voltage V _O of the synchronous rectification type DC-DC converter B. Therefore, the output of the synchronous rectification type DC-DC converter A
The DC current in the reverse direction flowing through the secondary winding 3b is blocked, so that the damage of the MOS-FET 4 in the synchronous rectification type DC-DC converter A having the lower set value of the DC output voltage V _O can be prevented, The synchronous rectification type DC-DC converters A and B can be favorably operated in parallel.

By the way, in the DC converter of the embodiment shown in FIG. 1, each of the synchronous rectification type DC-DC
Since the waveform of the voltage V _GS between the gate and the source terminal of the synchronous rectification MOS-FET 5 in the converters A and B is a positive / negative symmetric rectangular wave AC voltage waveform (FIG. 3B), the secondary winding of the transformer 3 is used. line 3b voltage V _T or synchronous rectification MOS-FET 5
Depending electrical characteristics of some cases the voltage level of the positive side of the voltage V _GS does not exceed the threshold voltage level of the synchronous rectification MOS-FET 5. Therefore, synchronous rectification MOS-F
The ET5 cannot be sufficiently turned on, and the on / off operation of the synchronous rectification MOS-FET 5 may become uncertain. This phenomenon is caused by the synchronous rectification type DC-
This also occurs when any one of the DC converters A and B is operated alone. Therefore, in the DC converter of the embodiment shown in FIG. 2, the gate terminal and the source terminal (one main terminal) of the synchronous rectification MOS-FET 5 in each of the synchronous rectification type DC-DC converters A and B shown in FIG. Between them, a clamp diode 22 as a rectifying element for clamping is additionally connected. Here, each synchronous rectification type DC-DC converter A constituting the DC converter device shown in FIG.
B, the voltage V _{T of the} secondary winding 3 b of the transformer 3, the voltage V _GS between the gate and source terminals of the synchronous rectification MOS-FET 5 and the voltage V _DS between the drain and source terminals of the synchronous rectification MOS-FET 5. Each waveform is shown in FIGS.
And (C). Similarly, each of the synchronous rectification type DC-DC converters A and B constituting the DC converter device shown in FIG.
, The voltage V _{T of the} secondary winding 3b of the transformer 3 and the voltage V between the gate and source terminals of the synchronous rectification MOS-FET 5
Drains of _GS and the synchronous rectification MOS-FET 5 - views, respectively of each waveform of the voltage V _DS between the source terminal 4 (A), shown in (B) and (C).

[0015] In DC converter apparatus shown in FIG. 2, each synchronous rectification type DC-DC converter A, in the B, MOS synchronous rectification negative voltage -V _T at the secondary winding 3b of the transformer 3 is generated When the voltage V _GS between the gate and source terminals of the FET 5 becomes negative and the synchronous rectification MOS-FET 5 is turned off, the clamp diode 22 becomes conductive, so that the gate-source terminal of the synchronous rectification MOS-FET 5 The negative voltage −V _GS is clamped near 0 V as shown in FIG. Thus, as shown in FIG. 4B, the waveform of the voltage V _GS between the gate and the source terminal of the synchronous rectification MOS-FET 5 changes to the same voltage V _GS shown in FIG.
Is shifted to the positive side, the voltage level on the positive side of the voltage V _GS between the gate and source terminals during the ON period of the synchronous rectification MOS-FET 5 exceeds the threshold voltage level, -The FET 5 can be reliably turned on and off.

The DC converter of the embodiment shown in FIG. 5 has a resistor 23 connected in series with the clamp diode 22 in each of the synchronous rectification type DC-DC converters A and B shown in FIG.
Is additionally connected. In the DC converter shown in FIG. 5, in each of the synchronous rectification type DC-DC converters A and B, when the synchronous rectification MOS-FET 5 is turned off and the clamp diode 22 is turned on, the resistor 23 is used for synchronous rectification. The voltage V _GS between the gate and source terminals of the MOS-FET 5 is biased to the negative side. Resistance 2
By increasing the resistance value of 3, the bias on the negative side of the voltage V _GS is applied more deeply, and the negative voltage −V _GS can be further increased. Therefore, the MOS-
During the OFF period of the FET 5, for example, when a positive surge voltage is applied to the gate terminal due to external noise or the like, malfunction of the synchronous rectification MOS-FET 5 can be prevented.

The embodiments of the present invention are not limited to the above embodiments, and various modifications are possible. For example, in each of the above embodiments, the MOS-F is used as the main switching element.
ET used, but bipolar transistor, J-FE
Other switching elements such as T (junction field effect transistor), IGBT (insulated gate transistor) or thyristor can also be used. In each of the above embodiments, a PWM (pulse width) that controls the pulse width by keeping the frequency of the control pulse signal constant is used as a constant voltage control method of the DC output voltage V _O of each of the synchronous rectification type DC-DC converters A and B. Although the modulation (modulation) method is adopted, a PFM (pulse frequency modulation) method in which the on-period of the control pulse signal is kept constant and the off-period is controlled may be adopted. In this case, instead of the PWM modulation circuit 18 in each of the above embodiments,
When the light output of the light emitting portion 17a of the photocoupler 17 increases and the current flowing to the light receiving portion 17b increases, and the voltage between the collector and the emitter of the light receiving portion 17b decreases, the operation of extending the off period of the control pulse signal output is performed. Then, the light output of the light emitting portion 17a of the photocoupler 17 decreases, the current flowing in the light receiving portion 17b decreases, and the off period of the control pulse signal output is reduced when the voltage between the collector and the emitter of the light receiving portion 17b increases. What is necessary is just to use the PFM modulation circuit which operates. Further, a rectifier circuit for converting an AC voltage of a commercial AC power supply into a DC voltage is often used as the DC power supply 1 in each of the above embodiments. It is also possible to use as 1. In this case, a stable DC voltage having no ripple component can be obtained, so that the input capacitor 2 can be omitted.

[0018]

According to the present invention, the main switching element can be prevented from being damaged even when the set values of the DC output voltages of the plurality of synchronous rectification type DC-DC converters constituting the DC converter device vary. The DC-DC converters of high efficiency can be connected in parallel by connecting a number of high-efficiency synchronous rectification type DC-DC converters in parallel so that the DC-DC converters of low voltage, large current output and high efficiency can be connected. The device can be easily obtained.

[Brief description of the drawings]

FIG. 1 is an electric circuit diagram showing an embodiment of a DC converter device according to the present invention.

FIG. 2 is an electric circuit diagram showing a modified embodiment of the DC converter device of FIG. 1;

FIG. 3 is a waveform chart showing voltages at various parts of the circuit of FIG. 1;

FIG. 4 is a waveform chart showing voltages of respective parts of the circuit of FIG. 3;

FIG. 5 is an electric circuit diagram showing a modified embodiment of the DC converter device of FIG. 3;

FIG. 6 is an electric circuit diagram showing a conventional synchronous rectification type DC-DC converter.

FIG. 7 is a waveform chart showing voltages at respective parts of the circuit of FIG. 6;

FIG. 8 is an electric circuit diagram showing a conventional DC converter device.

[Explanation of symbols]

1. . . DC power supply, 2. . . Input capacitor, 3. . .
Transformer, 3a. . . Primary winding, 3b. . . Secondary winding,
4. . . MOS-FET (main switching element),
5. . . MOS-FET for synchronous rectification (switching element for synchronous rectification), 5a. . . 5. parasitic diode; . . 6. Flywheel diode (rectifier for flywheel); . . 7. Output reactor, . . Output capacitor, 9,10. . . Resistance, 11. . . Load, 12. . .
Constant voltage control circuit, 13, 14. . . Voltage dividing resistor, 1
5. . . Reference power supply, 16. . . Error amplifier, 17. . .
Photocoupler, 17a. . . Light emitting section, 17b. . . Light receiving section, 18. . . 21. PWM modulation circuit; . . 22. DC voltage blocking capacitor, . . 23. clamp diodes (rectifying elements for clamping); . . Resistance, A, B. . . Synchronous rectification type DC-DC converter

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H02M 3/28 H02J 3/38 H02M 7/21

Claims (3)

(57) [Claims] 1. A primary winding and a main switching element of a transformer connected in series to both ends of a DC power supply, and a series connection to both ends of a secondary winding magnetically coupled to the primary winding of the transformer with the same polarity. A synchronous rectification FET and a flywheel rectifier, and a filter circuit connected to both ends of the flywheel rectifier. The secondary winding of the transformer is turned on and off by the main switching element. A voltage is generated, and the synchronous rectification FET is turned on and off by the voltage generated in the secondary winding, and the main switching element is turned on and off in accordance with the output voltage of the filter circuit. A plurality of synchronous rectification type DC-DC converters each supplying a constant-voltage DC output to a load connected to the filter circuit are provided between the DC power supply and the load. In the DC converter device connected in parallel to the above, in each of the plurality of synchronous rectification type DC-DC converters, a series circuit of a DC voltage blocking capacitor and an inrush current suppression resistor is connected to a gate terminal of the synchronous rectification FET and the second terminal.
A DC converter device connected between a secondary winding and a secondary winding. 2. The DC converter according to claim 1, wherein a clamp rectifying element is connected between a gate terminal of the synchronous rectification FET and one main terminal in each of the synchronous rectification type DC-DC converters. . 3. The DC converter according to claim 2, wherein a resistor is connected in series with the rectifying element for clamping.