JP2666001B2 - Charge limiting diode - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a charge limiting diode for suppressing a transient voltage of a switching element.

[0002]

2. Description of the Related Art Conventionally, switching regulators, DC
A switching element such as a power MOSFET or a thyristor used for high-speed switching such as a DC converter and an inverter has a large current passing through the element when conducting, but a small voltage drop in the element. Also,
At the time of cutoff, the voltage applied to the element is large, but the current passing through the element is small. For this reason, the power loss of the element itself is smaller than the power to be controlled, and the device is small and light because of less heat generation.

[0003] By combining such a switching element with an element having a reactance component, it can be used in place of a resistor or a power transistor, and can be controlled without discarding power as heat. Not only current limiters, but also wound-type variable transformers are being replaced. Furthermore, a device such as a converter in which a switching element and a reactance element or a transformer are combined can increase the switching frequency, thereby reducing the size and weight of the reactance element or the transformer being used. Devices using are being developed one after another.

[0004] Further, it has become common to supply power by direct current and to perform power control by switching using such switching technology.

[0005]

However, in the operation of the switching element, there is a transient period when switching between conduction and interruption. For example, when the MOSFET shifts from conduction to interruption, as shown in FIG. 13, at time t1 when the drain current Id starts to decrease, the drain-source voltage is reduced.
Since Vds starts to rise and the drain current Id becomes zero at the time t2 when the drain-source voltage Vds reaches the maximum value, the power loss Psw that becomes heat in the MOSFET between time t1 and time t2 is reduced. Occurs. This power loss Psw is
The power loss Psw is generated every cycle, which is equal to the product of the source-to-source voltage Vds and the drain current Id integrated over time from time t1 to time t2. For this reason, when the switching frequency increases, the loss in the switching element becomes extremely large, and it is difficult to reduce the size.

[0006] Further, not only in the case of high-frequency switching by a semiconductor, but also in the case of opening and closing a DC current by a mechanical switch, there is a transient period at the time of interruption, and at a large current, arc discharge occurs and interruption is not easy.

[0007] It is an object of the present invention to provide a charge limiting diode for overcoming the above-mentioned drawbacks and for reducing losses associated with switching transients.

[0008]

According to a first aspect of the present invention, there is provided a charge limiting diode comprising a P region and an N region.
In each of the N regions, a high-concentration portion in which the impurity concentration is increased in a substantially step-like manner is formed thinly and electrode surfaces are formed on both sides thereof, and the high-concentration portion and the electrode surface of at least one of the P region and the N region are formed. A low-concentration part where the impurity concentration is sufficiently lower than the high-concentration part is formed, the applied reverse voltage increases, and the depletion layer reaches the boundary between the high-concentration part and the low-concentration part. In this case, the voltage-to-junction capacitance characteristic is changed rapidly.

[0009]

The charge limiting diode having the above-described structure is charged when a reverse current is applied, and the reverse voltage gradually rises. When the voltage exceeds a certain voltage determined by the structure of the element, the reverse voltage rises sharply.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail with reference to the embodiments shown in FIGS. FIG. 1 shows a configuration diagram of a charge limiting diode 1. This charge limiting diode 1 is a kind of PN junction diode, and is formed of a semiconductor having a PN junction surface 2 formed at a center portion and electrodes attached to both sides. . The junction surface 2 of the PN junction is substantially flat, and the impurity concentration on both sides of the junction surface 2 is increased symmetrically and stepwise, and the inner layers 3 and 4 having a thickness of, for example, about 0.1 μm are formed. The intermediate layers 7 and 8 having a thickness of about several μm and having an impurity concentration substantially the same as that of the inner layers 3 and 4 on the outer side of the boundary surfaces 5 and 6 with the impurity concentration being substantially the same as the inner layers 3 and 4 are formed. Is formed. Outside the intermediate layers 7 and 8, an outer layer 9 having a particularly high impurity concentration in order to realize ohmic contact,
Electrodes 11 and 12 are provided with 10 interposed therebetween. The inner layer 3, the intermediate layer 7, and the outer layer 9 are all P-type semiconductors, and the inner layer 4, the intermediate layer 8, and the outer layer 10 are N-type semiconductors. Therefore,
The electrode 11 becomes the anode 1a and the electrode 12 becomes the cathode 1k.

FIG. 2 shows an impurity concentration distribution along a vertical section of the charge limiting diode 1. Here, X5 is the coordinates of the boundary surface 5 between the inner layer 3 and the intermediate layer 7, X2 is the coordinates of the bonding surface 2, X6 is the coordinate of the boundary surface 6 between the inner layer 4 and the intermediate layer 8, and the vertical axis is the impurity concentration. Is shown.

A reverse voltage Vr is applied to the charge limiting diode 1.
When the voltage Vr is sufficiently small, a depletion layer having a thickness proportional to the square root of the voltage Vr is formed in the inner layers 3 and 4 around the junction surface 2, but the thickness of the depletion layer also depends on the square root of the impurity concentration. When the depletion layer reaches the outside of the boundary surfaces 5 and 6, the expansion of the depletion layer with an increase in the applied voltage becomes steep. At this time, the N-type region in the depletion layer is positively charged due to the large amount of donor ions, and the P-type region is negatively charged due to the large amount of acceptor ions. Can be.

The relationship between the reverse voltage Vr applied to the charge limiting diode 1 and the junction capacitance Cj is as shown in the characteristic diagram of FIG. That is, when the voltage Vr increases, the capacitance Cj decreases, and the rate of the decrease changes partly discontinuously. The threshold voltage is a voltage at which the thickness of the depletion layer becomes equal to the thickness of the inner layers 3 and 4.
Assuming that Vth, as Vr increases Vr <Vth, capacitance
Cj decreases little by little, but when Vr = Vth, the rate of decrease sharply increases, and when Vr> Vth, the capacitance Cj rapidly decreases at first,
As the reverse voltage Vr increases, the rate of decrease in the capacitance Cj decreases. Here, since the capacity is considered as a value obtained by differentiating the electric quantity with the voltage, the product of the capacity and the voltage is not equal to the electric quantity.

The charge limiting diode 1 is charged when a reverse voltage is applied, and when the charge amount exceeds a certain value _Qo , the voltage rises sharply, and the charge amount becomes almost constant value Qo.
It has the property of being restricted to _o . This charge amount _Qo
Is determined from Q _o = eNXS. Here, S is the area of the bonding surface, N is the impurity concentration in the inner layers 3 and 4, that is, the acceptor ion concentration in the N region and the donor ion concentration in the P region, and X is the thickness of each of the inner layers 3 and 4. And
When the change in impurity concentration at the boundary surfaces 5 and 6 is as large and sharp as possible, the charge limiting characteristic becomes steeper.

FIG. 4 shows a delay circuit using the charge limiting diode 1. The input voltage Vin is connected to be applied to the cathode of the diode 1 via a resistor R, and the output voltage is
Vout is connected so as to be directly taken out from the diode 1, and the anode of the diode 1 is grounded to the common terminal GND. When a voltage V that is sufficiently larger than the threshold voltage Vth of the diode 1 is input in a step-like manner as shown in FIG. 5 as the input voltage Vin, the output voltage Vout rises rapidly after a certain delay time Tr, Reach. This delay time Tr is approximately represented by Tr ≒ RQ _o / V.

FIG. 6 shows another delay circuit, in which a diode 1
Is connected so that the input voltage Vin is applied to the resistor R, the anode of the diode 1 is connected to the input side, and the output voltage Vout is directly extracted from the resistor R. When a voltage V is applied to this circuit as an input Vin in a stepwise manner as shown in FIG. 7, the output voltage Vout becomes
It rises with Vin and falls quickly after the delay time Tr.

As described above, since the charge current of the charge limiting diode 1 rapidly decreases when the charge reaches the predetermined charge _Qo , a delay operation with switching characteristics can be realized. This switching characteristic is effective in ensuring the operation of the digital electronic circuit, and can be used as a delay element in an IC including the digital circuit.

FIG. 8 shows the circuit of FIG. 4 in which the resistance R is replaced by an inductance L, and the delay time Tr ′ is Tr ′ ≒.
(2Q _o L / V) ^1/2 . In this circuit, FIG.
When the input voltage Vin which becomes the voltage V in a step-like manner as shown in FIG. 4 is applied, the output voltage Vout rises rapidly after the delay time Tr ′, and settles to the voltage V after generating a considerably high overshoot peak.

Next, how to use the charge limiting diode 1 in a circuit will be described. FIG. 10 shows a switching inverter circuit, which is a main part of a circuit that converts a DC voltage into an insulated AC voltage by a push-pull method using two MOS FETs 20 and a transformer 21 with a center tap. The drain 20d of the MOS FET 20 is connected to both ends of the primary winding of the transformer 21, and the center tap is connected to the positive electrode of the DC power supply 22,
The source 20s of each FET 20 is connected to the negative electrode of the DC power supply 22. Two charge limiting diodes 1 are arranged in parallel with the respective FETs 20. An anode 1a is a source 20s, and a cathode 1k is a drain 2
It is connected to 0d. In the two FETs 20, control signals having phases opposite to each other are applied from the signal sources 23 and 24 between the gate 20g and the source 20s.
1 secondary winding. These two F
The control signal of the ET 20 may be such that the two auxiliary windings of the transformer 21 are obtained as the signal sources 23 and 24, and the output of another oscillator (not shown) is divided into two signals of opposite phases through a transformer (not shown). May be used.

In this circuit, since the two FETs 20 perform the same operation alternately, the operation of one will be described. First, when the FET 20 is on, the resistance between the drain 20d and the source 20s is almost zero, and gradually increases during the transition period when the FET 20 is off. This is FE
This is because carriers in the inversion layer generated immediately below the gate electrode (not shown) at T20 diffuse and disappear with a decrease in gate voltage. At this time, the charge limiting diode 1 functions as a capacitor and shunts the current from the transformer 21, so that the voltage between the drain and the source is changed as shown in FIG.
Vds does not rise very rapidly until it reaches the threshold voltage Vth. During this time, carriers in the FET 20 are diffused, and the resistance between the drain 20d and the source 20s increases.

At the end of the transition period, the reverse voltage Vr of the charge limiting diode 1 reaches the threshold voltage Vth. Immediately after that, at time t2, the reverse voltage Vr sharply increases together with the drain-source voltage Vds. Since the carriers have almost disappeared, the drain current Id hardly flows. When the other FET 20 is turned on, the electromotive force generated in the primary winding of the transformer 21 and the voltage of the DC power supply 22 are added and applied to the charge limiting diode 1. When the voltages cancel each other, the charge limiting diode 1 is discharged.

Next, when a positive voltage is applied to the gate 20g, the FET 20 is switched from off to on, the charge limiting diode 1 is discharged, and at the same time, a current starts flowing from the DC power supply 22 to the FET 20 through the transformer 21. At this time, the other FET 20 is about to be turned off from on, and since the two FETs 20 are alternately turned on, magnetic fluxes having different directions are alternately generated in the transformer 21, so that the induction is induced in the secondary winding. Power is induced and an isolated AC voltage is obtained. If this is rectified and smoothed, a DC of a voltage different from that of the DC power supply 22 can be obtained.

In such a circuit, the drain-source voltage Vds is kept low during the transition period from the ON state to the OFF state of the FET 20 by the charge limiting diode 1 connected in parallel. , The switching loss Psw is very small. Further, even if a reverse voltage is applied between the drain 20d and the source 20s via the transformer 21 when the operation of the circuit is not stable, the charge limiting diode 1 connected in parallel , And the bypass is performed, so that the reverse voltage does not become excessive.

FIG. 12 shows another embodiment of the charge limiting diode 1 '. The charge limiting diode 1' is obtained by eliminating the P-type intermediate layer 7 having a low impurity concentration in the previous embodiment. In this case, the reverse voltage Vr becomes the threshold voltage Vt
When h is exceeded, the depletion layer spreads in the intermediate layer 8 and the junction capacitance is rapidly reduced. Even in such a structure, the same function as that of the charge limiting diode 1 of the previous embodiment can be realized, and since the layer with a high impurity concentration is outside the layer with a low impurity concentration, it is manufactured more than that of the previous embodiment. Is easy. This is because it is easy to form a layer with a high impurity concentration on the outside of a substrate with a low impurity concentration, and it is usually performed by an alloy method or the like, but the reverse structure is difficult to manufacture. .

As described above, the charge limiting diode 1 in which the thin layer having a high impurity concentration is provided on both sides of the bonding surface 2 and the layer having a sufficiently low impurity concentration is provided outside at least one of the thin layers.
1 'shows a non-linear characteristic as shown in FIG. 3 when a reverse voltage is applied, and is effective for absorbing a transient current of the switching element.

In the above embodiment, the outer layers 9 and 10 having a particularly high impurity concentration are provided inside the electrodes 11 and 12.
These may be removed if ohmic contact is obtained. Further, the inner layers 3, 4 or the intermediate layers 7, 8 may not have the same concentration. Furthermore, the thicknesses of the inner layers 3 and 4 are not necessarily equal, but are preferably equal to increase the initial value of the junction capacitance Cj. Although the embodiment has been described as functioning as a diode, it is still effective even if only the junction capacitance is used without using the characteristics as a diode.

[0027]

As described above, the charge limiting diode according to the present invention is connected in parallel with the switching element to delay the rise of the voltage during the transition period from ON to OFF and reduce the switching loss. Can be.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a charge limiting diode.

FIG. 2 is an explanatory diagram of an impurity concentration distribution.

FIG. 3 is a characteristic diagram of junction capacitance and voltage.

FIG. 4 is a circuit diagram having a delay function.

FIG. 5 is an explanatory diagram of a transient response of an input / output voltage.

FIG. 6 is a circuit diagram having a delay function.

FIG. 7 is an explanatory diagram of a transient response of an input / output voltage.

FIG. 8 is a circuit diagram having a delay function.

FIG. 9 is an explanatory diagram of a transient response of an input / output voltage.

FIG. 10 is a configuration diagram of a switching circuit.

FIG. 11 is a characteristic diagram of changes in current and voltage.

FIG. 12 is a configuration diagram of a charge limiting diode of another embodiment.

FIG. 13 is an explanatory diagram of changes in current and voltage during a transition period from ON to OFF of the MOS FET.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1, 1 'Charge limiting diode 2 Junction surface 3, 4 Inner layer 5, 6 Boundary surface 7, 8 Intermediate layer 9, 10 Outer layer 11, 12 Electrode 20 MOS type FET 21 Transformer 22 DC power supply 23, 24 Signal source

Claims (1)

(57) [Claims] 1. A diode comprising a P region and an N region, wherein a high concentration portion in which an impurity concentration is increased in a substantially step shape is formed thinly in each of P and N regions sandwiching a PN junction surface, and electrodes are formed on both sides thereof. forming a surface, said P region, between the high density portion and the electrode surface of at least one region of the N regions, to form a low density portion of the impurity concentrations were well below the high-concentration portion, Reverse voltage applied increases
And the depletion layer reaches the boundary between the high concentration part and the low concentration part.
A charge limiting diode characterized in that the voltage-to-junction capacitance characteristic changes abruptly when the voltage changes.