JPH05217908A - Forming method for film transistor - Google Patents

Forming method for film transistor

Info

Publication number
JPH05217908A
JPH05217908A JP4019196A JP1919692A JPH05217908A JP H05217908 A JPH05217908 A JP H05217908A JP 4019196 A JP4019196 A JP 4019196A JP 1919692 A JP1919692 A JP 1919692A JP H05217908 A JPH05217908 A JP H05217908A
Authority
JP
Japan
Prior art keywords
pulse modulation
film
high frequency
frequency power
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP4019196A
Other languages
Japanese (ja)
Other versions
JPH0793273B2 (en
Inventor
Takao Tabata
隆雄 田端
Takahiro Nakahigashi
孝浩 中東
So Kuwabara
創 桑原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nissin Electric Co Ltd
Original Assignee
Nissin Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nissin Electric Co Ltd filed Critical Nissin Electric Co Ltd
Priority to JP4019196A priority Critical patent/JPH0793273B2/en
Publication of JPH05217908A publication Critical patent/JPH05217908A/en
Publication of JPH0793273B2 publication Critical patent/JPH0793273B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Abstract

PURPOSE:To form a film having small surface roughness and to improve flatness of a boundary between a silicon semiconductor film and a gate insulating film by generating a plasma of material gas for forming the film by applying high frequency power obtained by superposing a first pulse modulation and a second pulse modulation having a period shorter than that of the first pulse modulation. CONSTITUTION:A high frequency power source 7 has a high frequency signal generator 71 and a high frequency amplifier 72 for performing an arbitrary high frequency pulse modulation. It can apply high frequency power obtained by performing a high frequency of a predetermined frequency to be conducted by a desired first pulse modulation and a second pulse modulation having a period shorter than that of the first pulse modulation or high frequency power obtained by further performing it by a third pulse modulation having a period shorter than that of the second pulse modulation. Here, plasma is generated in gas by applying the high frequency power obtained by performing film forming gas by the first and second pulse modulations or further the third pulse modulation by the power source 7, and a film is formed on a substrate 9. Thus, flatness of a boundary of the film can be improved.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、薄膜トランジスタ(T
FT)におけるアモルファスシリコン膜や多結晶シリコ
ン膜といったシリコン半導体膜と、これに積層されるゲ
ート絶縁膜(SiNx等)のプラズマCVD法による形
成方法に関する。
The present invention relates to a thin film transistor (T
The present invention relates to a method of forming a silicon semiconductor film such as an amorphous silicon film or a polycrystalline silicon film in FT) and a gate insulating film (SiNx or the like) laminated thereon by a plasma CVD method.

【0002】[0002]

【従来の技術】薄膜トランジスタにおけるシリコン半導
体膜やこれに積層されるゲート絶縁膜は、プラズマCV
D法により形成されることが多い。この場合、それら膜
を形成するための原料ガスのプラズマ化は、所定周波数
の高周波電力を連続的に印加する連続放電によってい
る。
2. Description of the Related Art A silicon semiconductor film in a thin film transistor and a gate insulating film laminated thereon are plasma CVs.
It is often formed by the D method. In this case, the raw material gas for forming the films is made into plasma by continuous discharge in which high frequency power of a predetermined frequency is continuously applied.

【0003】[0003]

【発明が解決しようとする課題】しかし、このような連
続放電によるプラズマCVDにより得られるシリコン半
導体膜やゲート絶縁膜はその表面粗度が30Å〜50Å
程度と平坦度がきわめて悪く、そのため、シリコン半導
体膜とこれに接するゲート絶縁膜の界面の平坦度が悪く
なり、その結果、ソース・ドレイン間の電子移動度が低
くなり(0.3cm2 /V・S以下)、最終製品トラン
ジスタの性能が満足できるものでなくなるという問題が
あった。
However, the surface roughness of a silicon semiconductor film or a gate insulating film obtained by plasma CVD by such continuous discharge is 30Å to 50Å.
The degree and flatness are extremely poor, so that the flatness of the interface between the silicon semiconductor film and the gate insulating film in contact therewith becomes poor, and as a result, the electron mobility between the source and the drain becomes low (0.3 cm 2 / V・ There was a problem that the performance of the final product transistor was not satisfactory.

【0004】そこで本発明は、薄膜トランジスタ(TF
T)用のシリコン半導体膜及びこれに接するゲート絶縁
膜の界面の平坦度を向上させ、それによってTFTにお
けるソース・ドレイン間の電子移動度を大きくさせ得る
プラズマCVD法による薄膜トランジスタ用の膜形成方
法を提供することを目的とする。
Therefore, the present invention provides a thin film transistor (TF).
A film forming method for a thin film transistor by a plasma CVD method, which can improve the flatness of the interface between a silicon semiconductor film for T) and a gate insulating film in contact with the silicon semiconductor film, thereby increasing electron mobility between a source and a drain in a TFT. The purpose is to provide.

【0005】[0005]

【課題を解決するための手段】本発明者は、前記連続放
電による原料ガスのプラズマ化によると、気相反応が律
促となり、反応種が基板から離れた位置から基板へ向け
降り注ぐことになるため、成膜表面粗度が大きくなって
しまうことに着目し、さらに研究を進め、パルス変調を
かけた高周波、換言すれば断続を繰り返す高周波を印加
すると、従来の気相反応だけでなく、基板表面及び(又
は)それに近い位置での反応(以下「表面反応」とい
う)も起こり、これによって、成膜表面粗度が小さくな
ることを見出した。
The inventor of the present invention, when the raw material gas is turned into plasma by the continuous discharge, facilitates the gas phase reaction, and the reactive species flow down from the position away from the substrate toward the substrate. Therefore, paying attention to the fact that the film formation surface roughness becomes large, further research is carried out, and if a pulse-modulated high frequency, in other words, a high frequency that repeats intermittent is applied, not only the conventional gas phase reaction but also the substrate It was found that a reaction (hereinafter referred to as "surface reaction") on the surface and / or at a position close to the surface also occurs, and this reduces the film surface roughness.

【0006】また、このように第1のパルス変調に該第
1パルス変調より短い周期をもつ第2のパルス変調を重
畳させたり、さらには、該第2パルス変調より短い周期
をもつ第3パルス変調を重畳させることで、前記表面反
応がさらに進むとともに、必要なラジカル生成に寄与す
るプラズマ中の電子温度のコントロールが可能となり、
成膜速度を向上させ得ることを見出し、本発明を完成し
た。
In this way, the second pulse modulation having a shorter period than the first pulse modulation is superimposed on the first pulse modulation, and the third pulse having a shorter period than the second pulse modulation. By superimposing the modulation, it becomes possible to control the electron temperature in the plasma that contributes to the necessary radical generation, while further advancing the surface reaction.
The present invention has been completed by finding that the film formation rate can be improved.

【0007】すなわち本発明は、薄膜トランジスタ用の
シリコン半導体膜及びゲート絶縁膜をプラズマCVD法
により形成し、前記それぞれの膜形成にあたり該膜形成
のための原料ガスのプラズマ化を、第1パルス変調及び
該第1パルス変調より短い周期をもつ第2パルス変調を
重畳させた高周波電力の印加により行うことを特徴とす
る薄膜トランジスタ用の膜形成方法を提供するものであ
る。
That is, according to the present invention, a silicon semiconductor film and a gate insulating film for a thin film transistor are formed by a plasma CVD method, and at the time of forming each film, plasma conversion of a raw material gas for forming the film is performed by first pulse modulation and The present invention provides a film forming method for a thin film transistor, which is characterized in that it is performed by applying a high frequency power on which a second pulse modulation having a shorter period than the first pulse modulation is applied.

【0008】また、本発明は、かかる方法において、前
記第2パルス変調より短い周期をもつ第3のパルス変調
をさらに重畳させた高周波電力により原料ガスのプラズ
マ化を行う方法を提供する。前記第1パルス変調の条件
としては特に限定はないが、前記両膜界面の平坦度を向
上させる観点から、例えば1KHz以下、さらには40
0〜1000Hzの条件が考えられる。
Further, the present invention provides the method as described above, wherein the raw material gas is turned into plasma by the high frequency power further superposed with the third pulse modulation having a shorter period than the second pulse modulation. The condition of the first pulse modulation is not particularly limited, but from the viewpoint of improving the flatness of the interface between both films, for example, 1 KHz or less, and further 40
Conditions of 0 to 1000 Hz are conceivable.

【0009】前記第2パルス変調による高周波入力のオ
ン時間t1、オフ時間t2としては、例えば0.5μs
ec≦t1≦100μsec、3μsec≦t2≦10
0μsecが考えられる。さらに第3パルス変調を重畳
するときは、その変調による高周波入力オン時間t3、
オフ時間t4として、例えば0.05μsec≦t3≦
50μsec、0.05μsec≦t4≦50μsec
が考えられる。
The ON time t1 and the OFF time t2 of the high frequency input by the second pulse modulation are, for example, 0.5 μs.
ec ≦ t1 ≦ 100 μsec, 3 μsec ≦ t2 ≦ 10
0 μsec is conceivable. Furthermore, when superimposing the third pulse modulation, the high frequency input on-time t3 due to the modulation,
The off time t4 is, for example, 0.05 μsec ≦ t3 ≦
50 μsec, 0.05 μsec ≦ t4 ≦ 50 μsec
Can be considered.

【0010】[0010]

【作用】本発明方法によると、薄膜トランジスタ用のシ
リコン半導体膜及びこれに積層されるゲート絶縁膜は、
プラズマCVD法により順次、且つ、各膜の原料ガスを
第1及び第2のパルス変調を重畳させた、或いはさらに
第3パルス変調を重畳させた高周波電力の印加でプラズ
マ化することにより形成される。
According to the method of the present invention, the silicon semiconductor film for the thin film transistor and the gate insulating film laminated thereon are
It is formed by the plasma CVD method sequentially and plasma-converting the source gas of each film by the application of the high-frequency power on which the first and second pulse modulations are superimposed or the third pulse modulation is further superimposed. ..

【0011】このようにパルス変調をかけた高周波電力
の印加、換言すれば断続的な高周波電力の印加によりプ
ラズマの発生、停止が繰り返されるので、基板又はその
上に先に形成された膜から離れた位置で反応種が生成さ
れる気相反応が起こるほか、プラズマ停止時に原料ガス
が基板表面又はその上に先に形成された膜の表面及び
(又は)その近くまで達し、引き続きこれがプラズマ化
されることで反応種がそれら表面及び(又は)その近く
で生成される表面反応も進み、その結果、表面粗度の小
さい膜が形成されることになり、シリコン半導体膜とこ
れに接するゲート絶縁膜の界面の平坦度は良好となる。
Since the generation and stop of plasma are repeated by the application of the pulse-modulated high-frequency power, in other words, the intermittent application of the high-frequency power as described above, the plasma is separated from the substrate or the film previously formed on the substrate. In addition to the gas-phase reaction in which reactive species are generated at different positions, when the plasma is stopped, the source gas reaches the surface of the substrate or the surface of the film previously formed on it and / or near it, and this is subsequently turned into plasma. As a result, the surface reaction in which the reactive species are generated on and / or near those surfaces also progresses, and as a result, a film having a low surface roughness is formed, and the silicon semiconductor film and the gate insulating film in contact therewith are formed. The flatness of the interface is good.

【0012】また、第2パルス変調を重畳し、或いはさ
らに第3パルス変調を重畳することで、プラズマ中の電
子温度を必要なラジカル生成に望ましい状態にコントロ
ールすることができ、それによって成膜速度が向上す
る。
By superimposing the second pulse modulation or the third pulse modulation, it is possible to control the electron temperature in the plasma to a desirable state for radical generation required, thereby forming a film. Is improved.

【0013】[0013]

【実施例】以下、本発明の実施例を図面を参照して説明
する。図1は本発明方法の実施に使用するプラズマCV
D装置の一例の概略構成を示している。図示の装置は、
真空チャンバ1、該チャンバに電磁弁21を介して接続
した真空ポンプ2、チャンバ1内に設置した電極3、
4、チャンバ1に電磁弁61を介して接続した成膜用ガ
ス源5を備えている。
Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a plasma CV used for carrying out the method of the present invention.
The schematic structure of an example of D apparatus is shown. The device shown is
A vacuum chamber 1, a vacuum pump 2 connected to the chamber via a solenoid valve 21, an electrode 3 installed in the chamber 1,
4. A film forming gas source 5 connected to the chamber 1 via an electromagnetic valve 61 is provided.

【0014】電極3は接地電極であり、これには成膜温
度調節用のヒータ31が付設されている。電極4は高周
波電極であり、それ自体既に知られているマッチングボ
ックス8を介して高周波電源7から高周波電圧が印加さ
れる。高周波電源7は、任意の高周波パルス変調が可能
な高周波信号発生器71及び高周波増幅器(RFパワー
アンプ)72を有しており、所定周波数の高周波に所望
の第1パルス変調及び第1パルス変調より短い周期をも
つ第2パルス変調をかけた高周波電力、或いはさらに、
第2パルス変調より短い周期をもつ第3のパルス変調を
もかけた高周波電力を印加できるように構成してある。
The electrode 3 is a ground electrode, and a heater 31 for adjusting the film forming temperature is attached to the ground electrode. The electrode 4 is a high frequency electrode, and a high frequency voltage is applied from a high frequency power supply 7 through a matching box 8 which is already known per se. The high-frequency power source 7 has a high-frequency signal generator 71 and a high-frequency amplifier (RF power amplifier) 72 capable of performing arbitrary high-frequency pulse modulation, and uses a desired first pulse modulation and first pulse modulation for a high frequency of a predetermined frequency. High frequency power with second pulse modulation with short period, or
It is configured so that the high frequency power subjected to the third pulse modulation having a shorter period than the second pulse modulation can be applied.

【0015】第1パルス変調による高周波入力のオン、
オフ状態は図2の上段に概略示するようになり、第2パ
ルス変調による高周波入力のオン、オフ状態は図2の中
段に概略示するようになり、第3パルス変調による高周
波入力のオン、オフ状態は図2の下段に概略示するよう
になる。以上説明した装置によると、本発明方法は次の
ように実施される。
Turning on the high frequency input by the first pulse modulation,
The off state is as schematically shown in the upper part of FIG. 2, the high frequency input by the second pulse modulation is on and the off state is as schematically shown in the middle part of FIG. 2, the high frequency input is on by the third pulse modulation, The off state is as schematically shown in the lower part of FIG. According to the apparatus described above, the method of the present invention is carried out as follows.

【0016】シリコン半導体膜及びゲート絶縁膜のうち
前者を先に形成する場合、後者を先に形成する場合のい
ずれも考えられる。いずれにしても、これら膜は順次形
成される。最初の膜を形成するにあたっては、先ず、成
膜すべき基板9を電極3上に設置する。しかるのち、チ
ャンバ1内を電磁弁21の開成とポンプ2の運転にて所
定圧まで真空引きし、成膜用ガス源5から最初の成膜用
原料ガスをチャンバ内に導入し、且つ、チャンバ内を所
定成膜真空度に維持する。また、基板9をヒータ31に
て所定成膜温度に制御する。次いで、電源7にてこのガ
スに第1及び第2パルス変調された、或いはさらに第3
パルス変調された高周波電力を印加して該ガスをプラズ
マ化させ、基板9上に成膜させる。同様にして、次の原
料ガス源を準備し、そのガスを用いて次の膜を形成す
る。かくしてシリコン半導体膜とゲート絶縁膜の積層が
形成される。
It is conceivable that the former of the silicon semiconductor film and the gate insulating film is formed first or the latter is formed first. In any case, these films are sequentially formed. In forming the first film, first, the substrate 9 to be formed is placed on the electrode 3. Then, the chamber 1 is evacuated to a predetermined pressure by opening the electromagnetic valve 21 and operating the pump 2, and the first film-forming source gas is introduced from the film-forming gas source 5 into the chamber. The inside is maintained at a predetermined film forming vacuum degree. Further, the substrate 9 is controlled by the heater 31 to a predetermined film forming temperature. Then, the gas is first and second pulse-modulated by the power source 7, or the third pulse is further modulated.
A pulse-modulated high-frequency power is applied to turn the gas into plasma, and a film is formed on the substrate 9. Similarly, the next source gas source is prepared, and the next film is formed using the gas. Thus, a stack of the silicon semiconductor film and the gate insulating film is formed.

【0017】前記最初の成膜中、原料ガスには、パルス
変調された高周波電力が印加されるので、基板から離れ
た位置での気相反応だけでなく基板表面及び(又は)そ
れに近い位置での表面反応もあり、従って基板への成膜
は基板表面から離れた位置からの反応種の降り注ぎによ
るだけでなく、表面反応によるゆるやかな反応種の供給
によってもなされ、全体として成膜表面はそれだけ平坦
となる。また、この膜の上に形成される次の膜も先の平
坦な膜表面への気相反応による反応種の供給と表面反応
によるきめ細かい反応種の供給により形成されるので、
最初の膜とその上に形成される次の膜の界面の平坦度は
きわめて良好となる。
Since pulse-modulated high-frequency power is applied to the source gas during the first film formation, not only the gas-phase reaction at a position away from the substrate but also at the substrate surface and / or a position close to it. Therefore, the film formation on the substrate is performed not only by pouring the reactive species from a position distant from the substrate surface but also by slowly supplying the reactive species by the surface reaction. It becomes flat. Further, since the next film formed on this film is also formed by supplying the reactive species by the gas phase reaction to the flat film surface and the fine reaction species by the surface reaction,
The flatness of the interface between the first film and the next film formed thereon becomes extremely good.

【0018】よってシリコン半導体膜、ゲート絶縁膜の
いずれが先で、いずれがあとに形成される場合でも、両
者の界面平坦度はきわめて良好となり、両者はよく密着
する。従って、このような膜を用いた最終TFTトラン
ジスタでは、ソース・ドレイン間の電子移動度は従来に
比べ高いものとなる。また、前記成膜では、第2パルス
変調が重畳され、或いはさらに第3パルス変調が重畳さ
れることで、プラズマ中の電子温度が望ましい状態にコ
ントロールされ、成膜速度が向上する。
Therefore, no matter which of the silicon semiconductor film and the gate insulating film is formed first and which is formed later, the interface flatness between the two becomes extremely good and the two adhere well. Therefore, in the final TFT transistor using such a film, the electron mobility between the source and the drain is higher than in the conventional case. Further, in the film formation, the second pulse modulation is superimposed or the third pulse modulation is further superimposed, whereby the electron temperature in the plasma is controlled to a desired state, and the film formation speed is improved.

【0019】以上説明した方法により、次の具体的条件
で100mm角のガラス基板(コーニング7059)上
にアモルファスシリコン(a−Si)半導体膜とSiN
xゲート絶縁膜の積層膜を形成したところ、後に掲げる
結果を得た。 成膜真空度:100〜600mTorr(但し、ここで
は500mTorr) 高周波電源:13.56MHz、1000W 第1パルス変調の周期:400Hz〜1000Hz(但
し、ここでは500Hz) 第2パルス変調:オン時間t1 0.5μsec オフ時間t2 1.5μsec 第3パルス変調:オン時間t3 0.2μsec オフ時間t4 0.3μsec 電極3、4の面積:700mm×700mm ガラス基板温度:a−Si膜形成時 300℃ SiNx膜形成時 350℃ 成膜ガス:a−Si膜については SiH4 50ccm H2 150ccm SiNx膜については SiH4 50ccm NH3 150ccm N2 50ccm (結果)注:以下において( )内はパルス変調をか
けない従来方法の結果 上記結果から分かるように、本発明方法によると、従来
法に比べ、成膜の表面粗度は約1/4以下に低下し、T
FTにおける電子移動度は約4倍に増加している。
By the method described above, an amorphous silicon (a-Si) semiconductor film and SiN were formed on a 100 mm square glass substrate (Corning 7059) under the following specific conditions.
When a laminated film of x gate insulating film was formed, the following results were obtained. Deposition degree of film formation: 100 to 600 mTorr (however, here 500 mTorr) High frequency power supply: 13.56 MHz, 1000 W Cycle of first pulse modulation: 400 Hz to 1000 Hz (here, 500 Hz) Second pulse modulation: ON time t10. 5 μsec OFF time t2 1.5 μsec Third pulse modulation: ON time t3 0.2 μsec OFF time t4 0.3 μsec Area of electrodes 3 and 700: 700 mm × 700 mm Glass substrate temperature: a-Si film formation 300 ° C. SiNx film formation 350 ° C. Deposition gas: SiH 4 50 ccm H 2 150 ccm for a-Si film SiH 4 50 ccm NH 3 150 ccm N 2 50 ccm for SiNx film (result) Note: The values in parentheses below are for the conventional method without pulse modulation. result As can be seen from the above results, according to the method of the present invention, the surface roughness of film formation is reduced to about 1/4 or less as compared with the conventional method, and T
The electron mobility in FT has increased about 4 times.

【0020】なお、第1及び第2パルス変調を重畳さ
せ、第3パルス変調は重畳させないで、その他の条件は
前記と同様に或いは適宜変更して成膜を行っても、同様
に成膜表面粗度は従来より大きく低下し、a−Si膜、
SiNx膜界面の平坦度が改良される。
It should be noted that the first and second pulse modulations are superimposed, the third pulse modulation is not superimposed, and other conditions are the same as those described above or appropriately changed to perform film formation. The roughness is much lower than before, and the a-Si film,
The flatness of the SiNx film interface is improved.

【0021】[0021]

【発明の効果】以上説明したように本発明によると、薄
膜トランジスタ(TFT)用のシリコン半導体膜及びこ
れに接するゲート絶縁膜の界面の平坦度を向上させ、そ
れによってTFTにおけるソース・ドレイン間の電子移
動度を大きくさせ得る、また成膜速度も向上するプラズ
マCVD法による薄膜トランジスタ用の膜形成方法を提
供することができる。
As described above, according to the present invention, the flatness of the interface between the silicon semiconductor film for a thin film transistor (TFT) and the gate insulating film in contact therewith is improved, whereby electrons between the source and drain in the TFT are improved. It is possible to provide a film forming method for a thin film transistor by a plasma CVD method which can increase the mobility and also improve the film forming rate.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明方法の実施に使用するプラズマCVD装
置の一例の概略構成図である。
FIG. 1 is a schematic configuration diagram of an example of a plasma CVD apparatus used for carrying out the method of the present invention.

【図2】パルス変調による高周波入力のオン、オフ状態
の概略を示す図である。
FIG. 2 is a diagram schematically showing an ON / OFF state of a high frequency input by pulse modulation.

【符号の説明】[Explanation of symbols]

1 真空チャンバ 2 真空ポンプ 21 電磁弁 3 接地電極 31 ヒータ 4 高周波電極 5 成膜用原料ガス源 61 電磁弁 7 高周波電源 71 高周波信号発生器 72 RFパワーアンプ 8 マッチングボックス 1 Vacuum Chamber 2 Vacuum Pump 21 Electromagnetic Valve 3 Grounding Electrode 31 Heater 4 High Frequency Electrode 5 Source Gas Source for Film Formation 61 Electromagnetic Valve 7 High Frequency Power Source 71 High Frequency Signal Generator 72 RF Power Amplifier 8 Matching Box

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 薄膜トランジスタ用のシリコン半導体膜
及びゲート絶縁膜をプラズマCVD法により形成し、前
記それぞれの膜形成にあたり該膜形成のための原料ガス
のプラズマ化を、第1パルス変調及び該第1パルス変調
より短い周期をもつ第2パルス変調を重畳させた高周波
電力の印加により行うことを特徴とする薄膜トランジス
タ用の膜形成方法。
1. A silicon semiconductor film and a gate insulating film for a thin film transistor are formed by a plasma CVD method, and in forming each of the films, plasma conversion of a raw material gas for forming the film is performed by first pulse modulation and the first pulse modulation. A method of forming a film for a thin film transistor, which is performed by applying a high frequency power on which a second pulse modulation having a shorter period than the pulse modulation is superimposed.
【請求項2】 薄膜トランジスタ用のシリコン半導体膜
及びゲート絶縁膜をプラズマCVD法により形成し、前
記それぞれの膜形成にあたり該膜形成のための原料ガス
のプラズマ化を、第1パルス変調、該第1パルス変調よ
た短い周期をもつ第2パルス変調及び該第2パルス変調
より短い周期をもつ第3パルス変調を重畳させた高周波
電力の印加により行うことを特徴とする薄膜トランジス
タ用の膜形成方法。
2. A silicon semiconductor film and a gate insulating film for a thin film transistor are formed by a plasma CVD method, and in forming each of the films, plasma conversion of a raw material gas for forming the film is performed by a first pulse modulation and a first pulse modulation. A method for forming a film for a thin film transistor, which comprises performing high frequency power application by superimposing a second pulse modulation having a short period by pulse modulation and a third pulse modulation having a shorter period than the second pulse modulation.
JP4019196A 1992-02-04 1992-02-04 Film forming method for thin film transistor Expired - Fee Related JPH0793273B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4019196A JPH0793273B2 (en) 1992-02-04 1992-02-04 Film forming method for thin film transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4019196A JPH0793273B2 (en) 1992-02-04 1992-02-04 Film forming method for thin film transistor

Publications (2)

Publication Number Publication Date
JPH05217908A true JPH05217908A (en) 1993-08-27
JPH0793273B2 JPH0793273B2 (en) 1995-10-09

Family

ID=11992600

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4019196A Expired - Fee Related JPH0793273B2 (en) 1992-02-04 1992-02-04 Film forming method for thin film transistor

Country Status (1)

Country Link
JP (1) JPH0793273B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8343857B2 (en) 2010-04-27 2013-01-01 Semiconductor Energy Laboratory Co., Ltd. Manufacturing method of microcrystalline semiconductor film and manufacturing method of semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8343857B2 (en) 2010-04-27 2013-01-01 Semiconductor Energy Laboratory Co., Ltd. Manufacturing method of microcrystalline semiconductor film and manufacturing method of semiconductor device

Also Published As

Publication number Publication date
JPH0793273B2 (en) 1995-10-09

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