JPH05217673A - Manufacture of thin film el element - Google Patents

Manufacture of thin film el element

Info

Publication number
JPH05217673A
JPH05217673A JP4016707A JP1670792A JPH05217673A JP H05217673 A JPH05217673 A JP H05217673A JP 4016707 A JP4016707 A JP 4016707A JP 1670792 A JP1670792 A JP 1670792A JP H05217673 A JPH05217673 A JP H05217673A
Authority
JP
Japan
Prior art keywords
layer
insulating layer
thin film
oxygen plasma
plasma ashing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4016707A
Other languages
Japanese (ja)
Inventor
Yasuo Konishi
庸雄 小西
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Semiconductor Manufacturing Co Ltd
Kansai Nippon Electric Co Ltd
Original Assignee
Renesas Semiconductor Manufacturing Co Ltd
Kansai Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Semiconductor Manufacturing Co Ltd, Kansai Nippon Electric Co Ltd filed Critical Renesas Semiconductor Manufacturing Co Ltd
Priority to JP4016707A priority Critical patent/JPH05217673A/en
Publication of JPH05217673A publication Critical patent/JPH05217673A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To supplement oxygen deficiency and prevent damage to the surface of a thin film EL element by purifying the substrate surface of a specified layer formed by sputtering with oxygen plasma ashing in a chamber. CONSTITUTION:A transparent electrode 2 is laid on a glass substrate 1, and before forming an oxide film 3a and the first insulation layer 3, the board surface as substratum is subjected to oxygen plasma ashing in the condition being set in a chamber. Then sputtering is made in the same chamber to form oxide film 3a, and upon purifying the surface of the oxide film 3a, the first insulation layer 3 is formed by sputtering. After formation of this first insulation layer 3, the surface of the first insulation layer 3 is subjected to oxygen plasma ashing, and then a buffer layer 4a, light emission layer 4, and another buffer layer 4b are formed in lamination. Another oxygen plasma ashing is made after formation of the layers 4, 4a, 4b and before formation of the second insulation layer 5. Then formation of the second insulation layer 5 is conducted in the same chamber continuously with the situation kept as it is.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は薄膜EL素子の製造方法
に関し、詳しくは素子の各層の洗浄方法に関するもので
ある。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a thin film EL device, and more particularly to a method for cleaning each layer of the device.

【0002】[0002]

【従来の技術】薄膜ELマトリクス型ディスプレイパネ
ルにおける薄膜EL素子の構造例を図2及び図3を参照
して次に示す。尚、図2の左半分はX方向の断面図、右
半分はX方向と直交するY方向の断面図である。図にお
いて(1)は透光性絶縁基板、(2)は透明電極、
(3)は第1絶縁層、(4)は発光層、(5)は第2絶
縁層、(6)は背面電極である。上記透光性絶縁基板
(1)はガラス基板からなる。透明電極(2)はガラス
基板(1)上にITO(In23+SnO2)等を蒸着
法によりX方向に定ピッチで多数のストライプ状に形成
してなる。第1絶縁層(3)は透明電極(1)及びガラ
ス基板(1)上に、酸化タンタル(Ta25)又はアル
ミナ(Al23)又は酸化イットリウム(Y23)、或
いは窒化物等をスパッタ法により0.3〜0.5μm厚
で形成した透明膜である。発光層(4)は第1絶縁層
(3)上にZnS:Mnからなる蛍光体を電子ビーム蒸
着法等により0.5〜1.0μm厚で形成してなる。第
2絶縁層(5)は発光層(4)の全表面上にアルミナ
(Al23)や酸化イットリウム(Y23)、或いは窒
化物等を蒸着やスパッタ法で形成した透明膜である。背
面電極(6)は第2絶縁層(5)上にY方向に定ピッチ
で多数のストライプ状に形成したアルミ蒸着膜である。
そして、図示しないが、上記薄膜EL素子(7)を囲繞
するように、凹板状のカバーガラス(8)をガラス基板
(1)上に接着剤を介して固着することにより薄膜EL
マトリクス型ディスプレイが形成され、更に上記ガラス
基板(1)とカバーガラス(8)からなる外囲器内に、
薄膜EL素子(7)の耐湿性を向上させるためシリコン
オイル等の絶縁性保護流体を封入する。
2. Description of the Related Art An example of the structure of a thin film EL element in a thin film EL matrix type display panel is shown below with reference to FIGS. The left half of FIG. 2 is a cross-sectional view in the X direction, and the right half is a cross-sectional view in the Y direction orthogonal to the X direction. In the figure, (1) is a transparent insulating substrate, (2) is a transparent electrode,
(3) is a first insulating layer, (4) is a light emitting layer, (5) is a second insulating layer, and (6) is a back electrode. The translucent insulating substrate (1) is a glass substrate. The transparent electrode (2) is formed by forming ITO (In 2 O 3 + SnO 2 ) or the like on the glass substrate (1) by vapor deposition in a large number of stripes at a constant pitch in the X direction. The first insulating layer (3) is formed on the transparent electrode (1) and the glass substrate (1) by tantalum oxide (Ta 2 O 5 ), alumina (Al 2 O 3 ), yttrium oxide (Y 2 O 3 ), or nitriding. It is a transparent film formed by sputtering to a thickness of 0.3 to 0.5 μm. The light emitting layer (4) is formed by forming a phosphor of ZnS: Mn on the first insulating layer (3) to a thickness of 0.5 to 1.0 μm by an electron beam evaporation method or the like. The second insulating layer (5) is a transparent film formed by depositing alumina (Al 2 O 3 ) or yttrium oxide (Y 2 O 3 ) or nitride on the entire surface of the light emitting layer (4) by vapor deposition or sputtering. is there. The back electrode (6) is an aluminum vapor deposition film formed on the second insulating layer (5) in a large number of stripes at a constant pitch in the Y direction.
Although not shown, a concave plate-shaped cover glass (8) is fixed on the glass substrate (1) via an adhesive so as to surround the thin film EL element (7), and thus the thin film EL element is attached.
A matrix type display is formed, and further, in an envelope composed of the glass substrate (1) and the cover glass (8),
An insulating protective fluid such as silicon oil is enclosed in order to improve the moisture resistance of the thin film EL element (7).

【0003】上記薄膜ELマトリクス型ディスプレイで
は、図3に示すように、薄膜EL素子(7)の透明電極
(2)と背面電極(6)がマトリクス状に交差して多数
のマトリクス状の画素(m)…を形成する。又、上記透
明電極(2)と背面電極(6)の各端子部(2a)(6
a)…を1本おきにガラス基板(1)上の反対側の周辺
部上まで延設し、図示しないが、適宜、その上に外部取
り出し用パッドを設けている。そこで、両電極(2)
(6)の端子部(2a)(6a)間に駆動電圧を選択的
に印加すると、発光層(4)の画素部分が選択的に発光
して所望の情報のドットマトリクス表示を行なう。
In the thin film EL matrix type display, as shown in FIG. 3, a transparent electrode (2) and a back electrode (6) of a thin film EL element (7) intersect in a matrix to form a large number of matrix pixels ( m). In addition, the respective terminal portions (2a) (6) of the transparent electrode (2) and the back electrode (6)
Every other a) is extended to the opposite peripheral portion on the glass substrate (1), and although not shown, an external extraction pad is appropriately provided thereon. Therefore, both electrodes (2)
When a drive voltage is selectively applied between the terminal portions (2a) and (6a) of (6), the pixel portion of the light emitting layer (4) selectively emits light to perform dot matrix display of desired information.

【0004】上記薄膜EL素子(7)の製造において、
ガラス基板(1)上に透明電極(2)、第1絶縁層
(3)、発光層(4)、第2絶縁層(5)及び背面電極
(6)を積層形成する際、各層間にゴミやダスト等が付
着していると、その上部に形成される層にピンホールが
発生する原因となる。そうすると、各層には1.5×1
6V/cm程度の比較的高い電界を印加しているた
め、絶縁破壊を生じ易くなり、且つ、その絶縁破壊箇所
だけでなく、その箇所のストライプ自体も不良となる。
そこで、従来、各層を形成する直前にチャンバ外に搬出
して素子表面のウェット洗浄を実施した後、チャンバ内
に搬入しており、特に、第1絶縁層(3)と第2絶縁層
(5)ではスパッタリングを用いているため、チャンバ
内にセットした状態でスパッタエッチングにて素子基板
表面にアルゴンイオンを照射して清浄化処理している。
更に、チャンバ外への薄膜EL素子(7)の搬出時には
スローガス導入すると共に、チャンバ内への搬入時には
スロー排気してダスト等の舞い上がりを防止している。
In the manufacture of the thin film EL element (7),
Transparent electrode (2), first insulating layer on glass substrate (1)
(3), light emitting layer (4), second insulating layer (5) and back electrode
When laminating (6), dust, dust, etc. are attached between the layers.
When worn, there are pinholes in the layers formed on top of it.
It causes to occur. Then, 1.5 × 1 for each layer
0 6A relatively high electric field of about V / cm is applied.
Therefore, dielectric breakdown is likely to occur, and the location of the dielectric breakdown
Not only that, the stripes themselves at that location also become defective.
Therefore, conventionally, it was carried out to the outside of the chamber just before forming each layer.
After performing the wet cleaning of the element surface,
The first insulating layer (3) and the second insulating layer.
Since (5) uses sputtering, the chamber
Element substrate by sputter etching with it set inside
The surface is irradiated with argon ions for cleaning.
Furthermore, when carrying out the thin film EL element (7) to the outside of the chamber
While introducing slow gas, when carrying it into the chamber
Slow exhaust is used to prevent dust from rising.

【0005】[0005]

【発明が解決しようとする課題】解決しようとする課題
は、特にスパッタエッチングにて清浄化処理する際、特
に清浄化される下地表面が発光層の場合、スパッタダメ
ージを受けて表面が荒らされ、マイクロクラックを生じ
たり、或いは酸化物からなる絶縁層が下地の場合、酸素
欠損が生じて耐圧特性が低下する点である。
The problem to be solved by the invention is that when the cleaning treatment is carried out by sputter etching, particularly when the underlying surface to be cleaned is the light emitting layer, the surface is damaged by spattering and the surface is roughened. This is the point that when a microcrack is generated or an insulating layer made of an oxide is a base, oxygen deficiency occurs and the withstand voltage characteristic is deteriorated.

【0006】[0006]

【課題を解決するための手段】本発明は、透光性絶縁基
板上に透明電極、第1絶縁層、発光層、及び第2絶縁層
を順次、積層形成して薄膜EL素子を形成するにあた
り、スパッタリングにより形成する所定の層の下地表面
をチャンバ内で酸素プラズマアッシングにて清浄化処理
することを特徴とし、又、
According to the present invention, a transparent electrode, a first insulating layer, a light emitting layer, and a second insulating layer are sequentially laminated on a transparent insulating substrate to form a thin film EL element. Characterized in that the underlayer surface of a predetermined layer formed by sputtering is cleaned by oxygen plasma ashing in the chamber, and

【0007】第1絶縁層を酸化物にて形成すると共に、
発光層の第2絶縁層側表面に酸素プラズマアッシングの
下地となる酸化膜からなるバッファ層を設けることを特
徴とする。
The first insulating layer is formed of oxide, and
It is characterized in that a buffer layer made of an oxide film, which is a base of oxygen plasma ashing, is provided on the surface of the light emitting layer on the side of the second insulating layer.

【0008】[0008]

【作用】上記技術的手段によれば、透光性絶縁基板上に
透明電極、第1絶縁層、発光層、及び第2絶縁層を順
次、積層形成して薄膜EL素子を形成するにあたり、ス
パッタリングで形成される第1、第2絶縁層の下地表面
をチャンバ内で酸素プラズマアッシングによりゴミ、ダ
スト等の有機系付着物を除去して清浄化処理する。特
に、第1絶縁層及び発光層の第2絶縁層側に酸素プラズ
マアッシングの下地となる酸化膜よりなるバッファ層を
設けると、酸素欠損を補充することが出来る。
According to the above technical means, when the transparent electrode, the first insulating layer, the light emitting layer, and the second insulating layer are sequentially laminated on the translucent insulating substrate to form a thin film EL element, sputtering is performed. The underlying surfaces of the first and second insulating layers formed in step 1 are cleaned by oxygen plasma ashing in the chamber to remove organic deposits such as dust and dust. In particular, when a buffer layer made of an oxide film which is a base of oxygen plasma ashing is provided on the second insulating layer side of the first insulating layer and the light emitting layer, oxygen vacancies can be replenished.

【0009】[0009]

【実施例】本発明の実施例を図1を参照して以下に説明
する。図2に示す部分と同一部分には同一参照符号を付
してその説明を省略する。尚、第1絶縁層(3)は透明
電極(2)と馴染みの良い酸化膜(SiO2)(3a)
を介して積層形成され、又 、第2絶縁層(5)も同様に
背面電極(6)側に酸化膜(SiO2)(5a)を 積層
形成される。更に、発光層(4)を上下から対称に50
0オングストローム厚の酸化膜(Y23)からなるバッ
ファ層(4a)(4b)にて挾んで保護した構造とな
る。
An embodiment of the present invention will be described below with reference to FIG.
To do. The same parts as those shown in FIG. 2 are designated by the same reference numerals.
And its description is omitted. The first insulating layer (3) is transparent
An oxide film (SiO 2) that is familiar to the electrode (2)2) (3a)
Is laminated through , The second insulating layer (5) as well
On the back electrode (6) side, an oxide film (SiO 22) (5a) Stacking
It is formed. Further, the light emitting layer (4) is symmetrically arranged from above and below.
0 Å thick oxide film (Y2O3)
The structure is such that it is sandwiched between the fur layers (4a) and (4b) for protection.
It

【0010】上記構成に基づき本発明の動作(本発明方
法)を次に説明する。その特徴は、第1、第2絶縁層
(3)(5)の積層形成前の下地表面清浄化処理手段と
して従来のスパッタエッチングに代えて酸素プラズマア
ッシングを用いたことである。即ち、ガラス基板(1)
上にITOからなる透明電極(2)を積層形成した後、
酸化膜(3a)及び第1絶縁層(3)をスパッタリング
にて形成する前に、下地としての基板表面をチャンバ内
にセットした状態で、圧力が2×10-3〜5×10-2
orr、電力が0.56〜2.22W/cm2、及び周
波数(13.56MHz)にて酸素プラズマアッシング
して前処理しておく。そうすると、高温プラズマにより
基板表面のゴミやダスト等の主成分である有機物が強制
燃焼されて除去され、基板表面が清浄化処理される。そ
の後、同じチャンバ内でそのままスパッタリングを行な
って酸化膜(3a)を形成し、更に、上記同様、その表
面を連続して酸素プラズマアッシングにて清浄化した
後、そのまま続いてスパッタリングにより第1絶縁層
(3)を形成する。
The operation of the present invention (method of the present invention) will be described below based on the above configuration. The feature is that oxygen plasma ashing is used instead of the conventional sputter etching as a means for cleaning the underlying surface before forming the first and second insulating layers (3) and (5). That is, the glass substrate (1)
After stacking the transparent electrode (2) made of ITO on the top,
Before the oxide film (3a) and the first insulating layer (3) are formed by sputtering, the pressure is 2 × 10 −3 to 5 × 10 −2 T with the substrate surface as a base set in the chamber.
Pretreatment is performed by oxygen plasma ashing at orr, power of 0.56 to 2.22 W / cm 2 , and frequency (13.56 MHz). Then, the high temperature plasma compulsorily combusts and removes the organic substances which are the main components such as dust and dust on the substrate surface, and the substrate surface is cleaned. Thereafter, sputtering is performed in the same chamber as it is to form an oxide film (3a), and the surface thereof is continuously cleaned by oxygen plasma ashing as described above. (3) is formed.

【0011】次に、第1絶縁層(3)の形成後に同様に
チャンバ内にセットした状態で下地としての第1絶縁層
(3)の表面を酸素プラズマアッシングして前処理した
後、そのバッファ層(4a)と発光層(4)とバッファ
層(4b)を電子ビーム蒸着により積層形成する。更
に、発光層(4)とそのバッファ層(4a)(4b)を
形成した後で第2絶縁層(5)の形成前に酸素プラズマ
アッシングして前処理する。そうすると、それぞれ高温
プラズマにより有機系のゴミやダスト等が除去されて下
地表面を清浄化処理すると共に、下地の第1絶縁層
(3)及びバッファ層(4b)が酸化物層であるため、
それ以上、過酸化されることは殆どなく、酸素欠損を補
充して下地表面にダメージを与えない。その後、上記同
様に同じチャンバ内でそのまま連続してスパッタリング
により第2絶縁層(5)を形成すれば良い。
Next, after the first insulating layer (3) is formed, the surface of the first insulating layer (3) as an underlayer is pretreated by oxygen plasma ashing in a state where it is set in the chamber in the same manner, and then the buffer is formed. The layer (4a), the light emitting layer (4) and the buffer layer (4b) are laminated by electron beam evaporation. Further, after the light emitting layer (4) and its buffer layers (4a) and (4b) are formed and before the formation of the second insulating layer (5), oxygen plasma ashing is performed for pretreatment. Then, each of the high temperature plasma removes the organic dust and the like to clean the underlying surface, and the underlying first insulating layer (3) and the buffer layer (4b) are oxide layers.
Further, it is hardly overoxidized, and oxygen vacancies are replenished to prevent damage to the underlying surface. After that, similarly to the above, the second insulating layer (5) may be continuously formed in the same chamber by sputtering.

【0012】又、第1、第2絶縁層(3)(5)は酸化
物の一層構造でも良い。
The first and second insulating layers (3) and (5) may have a single layer structure of oxide.

【0013】[0013]

【発明の効果】本発明によれば、薄膜EL素子を製造す
るにあたり、スパッタリングにより形成する所定の層の
下地表面をチャンバ内で酸素プラズマアッシングにて清
浄化処理したから、有機系のゴミやダスト等が除去され
ると共に、下地として酸化物層を設けておくと、酸素欠
損を補充して表面のダメージを防止する。
According to the present invention, when manufacturing a thin film EL device, the underlying surface of a predetermined layer formed by sputtering is cleaned by oxygen plasma ashing in a chamber, so that organic dust and dirt are produced. When an oxide layer is provided as a base while removing the above, oxygen vacancies are supplemented to prevent surface damage.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明に係る薄膜EL素子の製造方法の実施例
を示す素子の要部側断面図である。
FIG. 1 is a side sectional view of an essential part of an element showing an embodiment of a method of manufacturing a thin film EL element according to the present invention.

【図2】従来の薄膜EL素子の一例を示す側断面図であ
る。
FIG. 2 is a side sectional view showing an example of a conventional thin film EL element.

【図3】従来の薄膜EL素子の一例を示す部分平面図で
ある。
FIG. 3 is a partial plan view showing an example of a conventional thin film EL element.

【符号の説明】[Explanation of symbols]

1 透光性基板 2 透明電極 3 第1絶縁層 4 発光層 5 第2絶縁層 6 背面電極 1 translucent substrate 2 transparent electrode 3 first insulating layer 4 light emitting layer 5 second insulating layer 6 back electrode

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 透光性絶縁基板上に透明電極、第1絶縁
層、発光層、及び第2絶縁層を順次、積層形成して薄膜
EL素子を形成するにあたり、 スパッタリングにより形成する所定の層の下地表面をチ
ャンバ内で酸素プラズマアッシングにて清浄化処理する
ことを特徴とする薄膜EL素子の製造方法。
1. A predetermined layer formed by sputtering when a transparent electrode, a first insulating layer, a light emitting layer, and a second insulating layer are sequentially laminated on a translucent insulating substrate to form a thin film EL element. 2. A method of manufacturing a thin film EL element, characterized in that the underlayer surface is cleaned by oxygen plasma ashing in a chamber.
【請求項2】 第1絶縁層を酸化物にて形成すると共
に、発光層の第2絶縁層側表面に酸素プラズマアッシン
グの下地となる酸化膜からなるバッファ層を設けること
を特徴とする請求項1記載の薄膜EL素子の製造方法。
2. The first insulating layer is formed of an oxide, and a buffer layer made of an oxide film serving as a base of oxygen plasma ashing is provided on the surface of the light emitting layer on the side of the second insulating layer. 1. The method for manufacturing a thin film EL element according to 1.
JP4016707A 1992-01-31 1992-01-31 Manufacture of thin film el element Pending JPH05217673A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4016707A JPH05217673A (en) 1992-01-31 1992-01-31 Manufacture of thin film el element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4016707A JPH05217673A (en) 1992-01-31 1992-01-31 Manufacture of thin film el element

Publications (1)

Publication Number Publication Date
JPH05217673A true JPH05217673A (en) 1993-08-27

Family

ID=11923747

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4016707A Pending JPH05217673A (en) 1992-01-31 1992-01-31 Manufacture of thin film el element

Country Status (1)

Country Link
JP (1) JPH05217673A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100741093B1 (en) * 2005-12-07 2007-07-20 삼성에스디아이 주식회사 A method for preparing a flat panel display device and a flat panel display device prepared using the method
JP2010147027A (en) * 2005-07-06 2010-07-01 Samsung Mobile Display Co Ltd Flat panel display device, and manufacturing method thereof
JP2011222630A (en) * 2010-04-06 2011-11-04 Mitsubishi Electric Corp Manufacturing method for photovoltaic device
WO2014174805A1 (en) * 2013-04-22 2014-10-30 パナソニック株式会社 El display device production method
JP2015521806A (en) * 2012-06-25 2015-07-30 ザ リージェンツ オブ ザ ユニヴァシティ オブ ミシガン Large area organic solar cells

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010147027A (en) * 2005-07-06 2010-07-01 Samsung Mobile Display Co Ltd Flat panel display device, and manufacturing method thereof
KR100741093B1 (en) * 2005-12-07 2007-07-20 삼성에스디아이 주식회사 A method for preparing a flat panel display device and a flat panel display device prepared using the method
JP2011222630A (en) * 2010-04-06 2011-11-04 Mitsubishi Electric Corp Manufacturing method for photovoltaic device
JP2015521806A (en) * 2012-06-25 2015-07-30 ザ リージェンツ オブ ザ ユニヴァシティ オブ ミシガン Large area organic solar cells
JP2018152590A (en) * 2012-06-25 2018-09-27 ザ リージェンツ オブ ザ ユニヴァシティ オブ ミシガン Large area organic photovoltaics
WO2014174805A1 (en) * 2013-04-22 2014-10-30 パナソニック株式会社 El display device production method
US9343710B2 (en) 2013-04-22 2016-05-17 Joled Inc Method of manufacturing EL display device

Similar Documents

Publication Publication Date Title
US6099746A (en) Organic electroluminescent device and method for fabricating the same
EP0645073B1 (en) Low resistance, thermally stable electrode structure for electroluminescent displays
JP2663909B2 (en) Method for manufacturing plasma display panel
JPH05217673A (en) Manufacture of thin film el element
JP4310843B2 (en) Method for manufacturing organic electroluminescent device
US6717356B1 (en) Organic electroluminescent device with trapezoidal walls
JP2000106275A (en) Manufacture of organic electroluminescent display device
JP4045656B2 (en) Method for manufacturing electroluminescent element
JP3511719B2 (en) Thin film electroluminescent device
JP2773773B2 (en) Method for manufacturing thin-film EL panel
JP2803803B2 (en) Thin film EL device and method of manufacturing the same
JP4817609B2 (en) Method for manufacturing organic electroluminescence element and method for manufacturing display device
JPH0424639Y2 (en)
JPH05152069A (en) Thin film el element and manufacture thereof
JPS6344684A (en) Manufacture of electroluminescence light emitting element
JPH056319B2 (en)
JPH04141983A (en) Thin film electroluminescent element
JPH05205874A (en) Thin film el panel
JP2006237426A (en) Organic el panel and its manufacturing method
JPS6147096A (en) Method of producing thin film el element
JP2004079364A (en) Organic electroluminescent element and organic electroluminescent panel
JPH01204394A (en) Thin film el element
JPH08115791A (en) Thin film el element and its manufacture
JPS5932880B2 (en) EL display panel
JPS63250090A (en) Thin film el panel