JPH0521764A - Manufacturing for semiconductor device - Google Patents

Manufacturing for semiconductor device

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Publication number
JPH0521764A
JPH0521764A JP17028391A JP17028391A JPH0521764A JP H0521764 A JPH0521764 A JP H0521764A JP 17028391 A JP17028391 A JP 17028391A JP 17028391 A JP17028391 A JP 17028391A JP H0521764 A JPH0521764 A JP H0521764A
Authority
JP
Japan
Prior art keywords
substrate
layer
silicon
silicon substrate
oxide film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP17028391A
Other languages
Japanese (ja)
Inventor
Hiroshi Goto
広志 後藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP17028391A priority Critical patent/JPH0521764A/en
Publication of JPH0521764A publication Critical patent/JPH0521764A/en
Withdrawn legal-status Critical Current

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Abstract

PURPOSE:To make it easy to form an ultrathin SOI layer uniformly, by controlling with high accuracy the depth of a thermal oxide layer and a buried insulating layer in ion implantation. CONSTITUTION:A mask layer 13 with an opening part 12 is formed on a Si substrate 11. Through the opening part 12, an oxigen-ion implantation is carried out for a separation region between devices in the Si substrate 11. A mask layer 13 is removed, and then on the surface of the Si substrate 11, a thermal oxide film 15 is formed so that the lower face thereof is located at about 0.5mum in depth with respect to an original surface of the Si substrate 11. In this case, an oxigen-ion-implantation region 114 is changed into a buried oxide silicon layer 14. After the silicon substrate 11 is put on a supporting substrate 16, heating is carried out and the silicon substrate 11 is bonded through the thermal oxide film 15 to the supporting substrate 16. Since the thermal oxide film 15 with uniform thickness is formed all over the silicon substrate 11, the silicon substrate 11 can be bonded through all the face thereof to the supporting substrate 16. Consequently, an SOI substrate having an ultrathin SOI layer can be formed.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は半導体基板の製造方法、
特に極薄いシリコン層を有するSOI(Silicon on Insu
lator)基板の製造方法に関する。
BACKGROUND OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor substrate,
In particular, SOI (Silicon on Insu) having a very thin silicon layer
lator) substrate manufacturing method.

【0002】近年、寄生容量の低減や、放射線耐性の向
上等の目的から、半導体素子の底部に絶縁膜を設けたS
OI構造の半導体ICが注目されている。このSOI構
造の半導体ICを形成する際に用いられるSOI基板の
形成には、幾つかの製造方法が知られているが、シリコ
ンの結晶性の最も優れたSOI基板は、シリコン基板を
絶縁膜を介して支持基板上に貼り合わせ研摩するウエー
ハ貼り合わせ方法によって得られる。このウエーハ貼り
合わせ法によるSOI基板においては、無欠陥単結晶シ
リコン基板が用いられるので結晶品質には問題がない
が、このシリコン基板を研摩して薄膜化する過程での膜
厚のばらつきが素子領域の活性層の厚さのばらつきに直
結し、特に極薄SOI層によるMOSトランジスタを作
製する際には、上記膜厚のばらつきが特性のばらつきの
原因となるので、膜厚を精度良く且つ均一に制御するこ
とが極めて重要である。
In recent years, for the purpose of reducing parasitic capacitance and improving radiation resistance, an S film provided with an insulating film on the bottom of a semiconductor element is used.
Attention has been paid to a semiconductor IC having an OI structure. Several manufacturing methods are known for forming an SOI substrate used when forming a semiconductor IC having this SOI structure. However, an SOI substrate having the highest silicon crystallinity has a silicon substrate with an insulating film. It is obtained by a wafer laminating method in which laminating and polishing is performed on a supporting substrate via a via. Since the defect-free single crystal silicon substrate is used in the SOI substrate formed by this wafer bonding method, there is no problem in crystal quality, but variations in the film thickness in the process of polishing and thinning the silicon substrate cause variations in the element region. Is directly connected to the variation in the thickness of the active layer, and particularly when the MOS transistor with the ultra-thin SOI layer is manufactured, the variation in the film thickness causes the variation in the characteristics. Control is extremely important.

【0003】[0003]

【従来の技術】当初、ウエーハ貼り合わせ方式のSOI
基板の製造に際しては、シリコン基板の表面全面に一様
な厚さの熱酸化膜を形成し、このシリコン基板を前記熱
酸化膜を介して支持基板上に加熱貼着し、このシリコン
基板を背面から所定の厚さになるまで研摩してSOI層
が形成されていた。
2. Description of the Related Art Initially, a wafer bonding type SOI
When manufacturing a substrate, a thermal oxide film having a uniform thickness is formed on the entire surface of the silicon substrate, the silicon substrate is heat-bonded onto the supporting substrate through the thermal oxide film, and the silicon substrate is placed on the back surface. Was polished to a predetermined thickness to form an SOI layer.

【0004】しかしこの方法では、SOI層の厚さの制
御が研摩装置の精度のみに頼っているために、極薄のS
OI層を形成する際には、充分な厚さの精度及び均一性
が得られないという問題を生ずる。
However, in this method, since the control of the thickness of the SOI layer depends only on the precision of the polishing apparatus, the ultrathin S
When forming the OI layer, there arises a problem that sufficient accuracy and uniformity of thickness cannot be obtained.

【0005】そこで従来、高精度で均一性に優れた極薄
SOI層を有するSOI基板を製造する方法として、以
下に図4を参照して示す方法が提案されている。図4
(a) 参照 即ちその方法は、シリコン基板51の全面に例えば 0.2μ
m程度の厚さの熱酸化膜55を形成した後、この熱酸化膜
上に例えば素子間分離領域に相当する部分に開口部52を
有する耐酸化膜パターン53を形成し、この耐酸化膜パタ
ーン53をマスクにしてシリコン基板51面を選択酸化し、
上記耐酸化膜パターン53の開口部52に厚さ 0.6μm程度
の選択酸化膜54を形成する。
Therefore, conventionally, as a method of manufacturing an SOI substrate having an ultrathin SOI layer with high accuracy and excellent uniformity, a method shown below with reference to FIG. 4 has been proposed. Figure 4
(a) Reference, that is, the method is, for example, 0.2 μm on the entire surface of the silicon substrate 51.
After forming a thermal oxide film 55 having a thickness of about m, an oxidation resistant film pattern 53 having an opening 52 in a portion corresponding to, for example, an element isolation region is formed on the thermal oxidation film, and the oxidation resistant film pattern is formed. The surface of the silicon substrate 51 is selectively oxidized using 53 as a mask,
A selective oxide film 54 having a thickness of about 0.6 μm is formed in the opening 52 of the oxidation resistant film pattern 53.

【0006】図4(b) 参照次いで、上記耐酸化膜パター
ン53を除去した後、上記シリコン基板51を反転し、前記
選択酸化膜54の上面を介して例えばシリコンからなる支
持基板56上に加熱貼着する。(57は空洞部)図4(c) 参
照 そして、このSi基板51を背面側から、前記選択酸化膜54
の底面をストッパとして研摩し、上記Si基板51からな
り、この選択酸化膜54と前記熱酸化膜55との高さの差に
相当する例えば 0.2μm程度の膜厚の薄いSOI層51S
を備えたSOI基板を形成する方法である。
Referring to FIG. 4B, after removing the oxidation resistant film pattern 53, the silicon substrate 51 is inverted and heated on the support substrate 56 made of, for example, silicon through the upper surface of the selective oxide film 54. Stick it. (57 is a cavity) See FIG. 4 (c). Then, from the rear side of the Si substrate 51, the selective oxide film 54 is formed.
Is polished by using the bottom surface of the Si substrate 51 as a stopper, and the SOI layer 51S is made of the Si substrate 51 and has a thin film thickness of, for example, about 0.2 μm, which corresponds to the height difference between the selective oxide film 54 and the thermal oxide film 55.
A method for forming an SOI substrate having

【0007】[0007]

【発明が解決しようとする課題】上記従来方法による
と、SOI層51Sの厚さは前記熱酸化膜55及び選択酸化
膜54の厚さによって厳密に制御し得るので、極薄の一様
な膜厚を有するSOI層の形成は可能になる。しかしな
がら、この従来方法においては、シリコン基板51がその
全面で支持基板56に接着しておらず、シリコン基板51面
に選択的に形成されている選択酸化膜54を介し部分的に
接着されているので、シリコン基板51の支持基板56に対
する接着力が部分的に弱くなり、前記研摩の際や、SO
I基板をチップ状に分割する際等に、前記選択酸化膜55
の周辺部においてSOI層51Sの支持基板56上からの剥
離や破損を生じ、SOI構造の半導体IC等を高品質、
高歩留りで製造することが、困難になるという問題があ
った。
According to the above-mentioned conventional method, the thickness of the SOI layer 51S can be strictly controlled by the thicknesses of the thermal oxide film 55 and the selective oxide film 54, so that an extremely thin uniform film is obtained. It is possible to form an SOI layer having a thickness. However, in this conventional method, the silicon substrate 51 is not adhered to the support substrate 56 over the entire surface, but is partially adhered through the selective oxide film 54 selectively formed on the surface of the silicon substrate 51. Therefore, the adhesive force of the silicon substrate 51 to the support substrate 56 is partially weakened, and during the polishing or the SO
When the I substrate is divided into chips, etc., the selective oxide film 55
In the peripheral portion of the SOI layer 51S, peeling or damage of the SOI layer 51S from the support substrate 56 occurs, and a semiconductor IC or the like having an SOI structure is of high quality.
There is a problem that it becomes difficult to manufacture with a high yield.

【0008】そこで本発明は、均一な膜厚を有し、支持
基板に均一に接着された極薄SOI層が安定して得られ
るSOI基板を、高歩留りで製造することが可能な、S
OI基板の製造方法を提供することを目的とする。
Therefore, the present invention makes it possible to manufacture an SOI substrate having a uniform film thickness and stably obtaining an ultra-thin SOI layer that is uniformly adhered to a supporting substrate at a high yield.
An object is to provide a method for manufacturing an OI substrate.

【0009】[0009]

【課題を解決するための手段】図1は本発明の原理説明
用工程断面図である。上記課題は、図1(a) に示すよう
に、シリコンと化合して絶縁物を形成する物質例えば酸
素(O+ )を、シリコン基板1内の一部領域に、主面側
から所定の深さd1 にイオン注入する工程(2は開口
部、3はマスク層、104 はO+ 注入領域)、次いで図1
(b) に示すように、該シリコン基板1の主面に、前記イ
オン注入領域の底面より浅い深さd2 に底面を有する熱
酸化膜5を形成すると同時に、前記O+ 注入領域104 に
例えば酸化シリコン(SiO2)からなる埋込み絶縁物層4を
形成する工程、次いで図1(c) に示すように、該シリコ
ン基板1を前記熱酸化膜5を介し支持基板6上に加熱貼
着する工程、次いで図1(d) に示すように、該シリコン
基板1を背面側から前記埋込み絶縁物層4をストッパと
して研摩し、支持基板6上に前記熱酸化膜5を介し該半
導体基板1の薄層即ち薄いSOI層1Sが貼着されてなる
SOI基板を形成する工程を有する本発明による半導体
基板の製造方法、若しくは、シリコン基板の主面に絶縁
膜を形成する工程、シリコンと化合して絶縁物を形成す
る物質を、該シリコン基板の主面側から前記絶縁膜を通
し、該絶縁膜の底面より深くイオン注入する工程、該シ
リコン基板を前記絶縁膜を介して支持基板上に加熱貼着
すると同時に、前記イオン注入領域に埋込み絶縁物層を
形成する工程、該シリコン基板を背面側から前記埋込み
絶縁物層をストッパとして研摩し、支持基板上に前記絶
縁膜を介し該シリコン基板の薄層が貼着されてなるSO
I基板を形成する工程を有する本発明による半導体基板
の製造方法によって解決される。
FIG. 1 is a process sectional view for explaining the principle of the present invention. As shown in FIG. 1 (a), the above-mentioned problem is that a substance that combines with silicon to form an insulator, such as oxygen (O + ), is applied to a partial region in the silicon substrate 1 at a predetermined depth from the main surface side. Ion implantation to a depth d 1 (2 is an opening, 3 is a mask layer, 104 is an O + implantation region), and then FIG.
As shown in (b), a thermal oxide film 5 having a bottom surface is formed on the main surface of the silicon substrate 1 at a depth d 2 shallower than the bottom surface of the ion implantation region, and at the same time, in the O + implantation region 104, for example. Step of forming a buried insulator layer 4 made of silicon oxide (SiO 2 ), and then, as shown in FIG. 1 (c), the silicon substrate 1 is heat-bonded onto the supporting substrate 6 via the thermal oxide film 5. Step, and then, as shown in FIG. 1D, the silicon substrate 1 is polished from the back side using the embedded insulator layer 4 as a stopper, and the semiconductor substrate 1 is formed on the support substrate 6 with the thermal oxide film 5 interposed therebetween. A method for manufacturing a semiconductor substrate according to the present invention, which has a step of forming an SOI substrate having a thin layer, that is, a thin SOI layer 1S attached thereto, or a step of forming an insulating film on the main surface of a silicon substrate, and combining it with silicon. The material forming the insulator is the silicon substrate. A step of implanting ions deeper than the bottom surface of the insulating film through the insulating film from the main surface side, heating the silicon substrate to a support substrate through the insulating film, and at the same time, embedding the insulator in the ion implantation region. A step of forming a layer, wherein the silicon substrate is polished from the back side using the embedded insulator layer as a stopper, and a thin layer of the silicon substrate is attached onto a supporting substrate through the insulating film.
This is solved by the method for manufacturing a semiconductor substrate according to the present invention, which includes the step of forming an I substrate.

【0010】[0010]

【作用】即ち本発明の方法においては、図1に示すよう
に、選択的に酸素或いは窒素をイオン注入してシリコン
基板1の内部に形成した埋込み絶縁物層4をこのシリコ
ン基板1を研摩して薄層化する際の研摩の停止層として
用いるので、このシリコン基板1の支持基板6上への接
着はシリコン基板1の全面に均一な厚さに形成した熱酸
化膜3を用い、シリコン基板1の平坦性を損なわずその
全面を介して行うことができる。従って上記シリコン基
板1を背面研摩して形成されるSOI層1Sの支持基板6
上への接着不良はなくなるので、SOI層1Sの反りや剥
離が回避されこのSOI層1Sに形成される半導体IC等
の収率は向上する。
That is, in the method of the present invention, as shown in FIG. 1, the buried insulating layer 4 formed inside the silicon substrate 1 by selectively ion-implanting oxygen or nitrogen is polished to the silicon substrate 1. Since the silicon substrate 1 is used as a polishing stop layer when it is thinned, the silicon substrate 1 is adhered onto the support substrate 6 by using a thermal oxide film 3 formed on the entire surface of the silicon substrate 1 to have a uniform thickness. It can be performed through the entire surface without impairing the flatness of No. 1. Therefore, the support substrate 6 of the SOI layer 1S formed by polishing the silicon substrate 1 on the back surface
Since the adhesion failure to the top is eliminated, the warp and peeling of the SOI layer 1S are avoided, and the yield of semiconductor ICs and the like formed on the SOI layer 1S is improved.

【0011】また、本発明の方法においては、SOI層
1Sの厚さが、ストッパとなる埋込み絶縁物層4の深さd
1 と熱酸化膜5の深さd2との差によって規定され、前
記イオン注入による埋込み絶縁物層4の深さd1 、及び
熱酸化に際しての熱酸化膜5の深さの制御が高精度に行
なえることから、極薄の均一な厚さを有するSOI層の
形成が容易になる。
In the method of the present invention, the SOI layer
The thickness of 1S is the depth d of the embedded insulator layer 4 that serves as a stopper.
It is defined by the difference between 1 and the depth d 2 of the thermal oxide film 5, and the depth d 1 of the buried insulating layer 4 by the ion implantation and the depth of the thermal oxide film 5 at the time of thermal oxidation are highly controlled. Therefore, it becomes easy to form an SOI layer having an extremely thin uniform thickness.

【0012】以上により、本発明によれば均一な膜厚の
極薄SOI層を有するSOI基板を、歩留り良く、且つ
安定に製造することができる。
As described above, according to the present invention, an SOI substrate having an ultrathin SOI layer having a uniform film thickness can be manufactured with good yield and stability.

【0013】[0013]

【実施例】以下本発明を、図示実施例により具体的に説
明する。図2は本発明の方法の一実施例の工程断面図、
図3は本発明の方法の他の実施例の工程断面図である。
全図を通じ同一対象物は同一符合で示す。
EXAMPLES The present invention will be described in detail below with reference to illustrated examples. FIG. 2 is a process sectional view of one embodiment of the method of the present invention,
FIG. 3 is a process sectional view of another embodiment of the method of the present invention.
The same object is denoted by the same reference numeral throughout the drawings.

【0014】図2(a) 参照本発明に係る第1の方法によ
り、例えば 0.1〜0.2 μm程度の厚さのSOI層を有す
るSOI基板を形成するに際しては、通常半導体装置の
製造に用いられるものと同等の高品質を有するSi基板11
上に、膜厚1〜2μm程度の有機或いは無機物質からな
り、例えば素子間分離領域に相当する部分を露出する開
口部12有するマスク層13を形成し、このマスク層13の開
口部12を介しSi基板11の素子間分離領域に相当する部分
に、例えば 300〜400KeV の加速エネルギーで、1×10
17〜1×1018cm-2程度のドーズ量で酸素( O+ )をイオ
ン注入する。本実施例においてはこのイオン注入によ
り、例えば深さ 0.6〜0.7 μm程度の位置にピーク濃度
を有するO+ 注入領域114 を形成する。
Referring to FIG. 2 (a), when a SOI substrate having an SOI layer having a thickness of, for example, about 0.1 to 0.2 μm is formed by the first method according to the present invention, it is generally used for manufacturing a semiconductor device. Si substrate with high quality equivalent to 11
A mask layer 13 made of an organic or inorganic material having a film thickness of about 1 to 2 μm and having, for example, an opening 12 that exposes a portion corresponding to an element isolation region is formed on the upper surface of the mask layer 13. At a portion corresponding to the element isolation region of the Si substrate 11, at an acceleration energy of, for example, 300 to 400 KeV, 1 × 10
Oxygen (O + ) is ion-implanted at a dose of about 17 to 1 × 10 18 cm -2 . In this embodiment, this ion implantation forms an O + implantation region 114 having a peak concentration at a depth of about 0.6 to 0.7 μm, for example.

【0015】図2(b) 参照次いで、前記マスク膜13を除
去した後、通常の1000℃程度の温度におけるウエット酸
化により上記シリコン基板11の表面に1μm程度の厚さ
即ち当初のSi基板1の表面から深さ 0.5μm程度の位置
に底面を有する熱酸化膜15を形成し、且つ同時に前記O
+ 注入領域114 を埋込み酸化シリコン(SiO2)層14に変化
せしめる。なおこの際、埋込みSiO2層14の底面は前記熱
酸化膜15の底面より 0.1〜0.2 μm(d3)程度下方に突
出して形成される。
Referring to FIG. 2 (b), after the mask film 13 is removed, the surface of the silicon substrate 11 is wet-oxidized at a normal temperature of about 1000.degree. A thermal oxide film 15 having a bottom surface is formed at a depth of about 0.5 μm from the surface, and at the same time, the thermal oxide film 15 is formed.
The implantation region 114 is changed to the buried silicon oxide (SiO 2 ) layer 14. At this time, the bottom surface of the embedded SiO 2 layer 14 is formed so as to project downward by about 0.1 to 0.2 μm (d 3 ) from the bottom surface of the thermal oxide film 15.

【0016】図2(c) 参照次いで上記シリコン基板11
を、反転して例えばシリコン等からなる支持基板16上に
載置し、1000℃程度に加熱して、基板表面の熱酸化膜15
を介し支持基板16上に貼着する。なお熱酸化膜15はシリ
コン基板11の全面に一様な厚さで形成されているので、
このシリコン基板11は平坦性を維持したまま、その全面
で支持基板16上に貼着される。
Referring to FIG. 2 (c), the silicon substrate 11 is then used.
Is inverted and placed on a support substrate 16 made of, for example, silicon and heated to about 1000 ° C. to form a thermal oxide film 15 on the substrate surface.
It is stuck on the support substrate 16 via. Since the thermal oxide film 15 is formed on the entire surface of the silicon substrate 11 with a uniform thickness,
The silicon substrate 11 is stuck on the support substrate 16 over the entire surface while maintaining the flatness.

【0017】図2(d) 参照次いで周知のアルカリ系のエ
ッチング液を用いるメカノケミカルポリッシング手段に
より、シリコン基板11を背面から埋込みSiO2層14の底面
をストッパとして研摩し、支持基板16上に熱酸化膜15を
介して貼着され、埋込みSiO2層14により複数の領域に分
割された厚さ(t) 0.1 〜0.2 μm程度の極薄SOI層11
S を有するSOI基板17が完成する。
Referring to FIG. 2 (d), the silicon substrate 11 is embedded from the back side by a well-known mechanochemical polishing means using an alkaline etching solution, and the bottom surface of the SiO 2 layer 14 is polished as a stopper to heat the support substrate 16. An ultrathin SOI layer 11 having a thickness (t) of 0.1 to 0.2 μm, which is attached through an oxide film 15 and divided into a plurality of regions by a buried SiO 2 layer 14.
The SOI substrate 17 having S is completed.

【0018】図3(a) 参照また本発明に係る第2の方法
により、例えば 0.1〜0.2 μm程度の厚さのSOI層を
有するSOI基板を形成するに際しては、先ずウェット
酸化等の方法により、前記実施例同様のSi基板11の表面
に厚さ 0.5〜2μm程度の絶縁膜例えば熱酸化膜15を形
成する。
Referring to FIG. 3 (a), when forming an SOI substrate having an SOI layer having a thickness of about 0.1 to 0.2 μm by the second method according to the present invention, first, a method such as wet oxidation is used. An insulating film, for example, a thermal oxide film 15 having a thickness of about 0.5 to 2 μm is formed on the surface of the Si substrate 11 similar to the above embodiment.

【0019】図3(b) 参照次いで、前記熱酸化膜15上
に、例えば素子間分離領域に相当する部分を露出する開
口部12を有するマスク層13を形成し、このマスク層13の
開口部12を介し、熱酸化膜15を通して、所定の加速エネ
ルギーで前記実施例同様のドーズ量の酸素(O+ )をイ
オン注入し、その部分のシリコン基板11内に熱酸化膜の
底面から 0.1〜0.2 μm程度の深さを有するO+ 注入領
域114 を形成する。
Next, referring to FIG. 3B, a mask layer 13 having an opening 12 for exposing a portion corresponding to an element isolation region is formed on the thermal oxide film 15, and the opening of the mask layer 13 is formed. Oxygen (O + ) with the same dose amount as that in the above-mentioned embodiment is ion-implanted through the thermal oxide film 15 through the thermal oxide film 15 through 0.1 to 0.2 to 0.2 from the bottom surface of the thermal oxide film into the silicon substrate 11. An O + implantation region 114 having a depth of about μm is formed.

【0020】図3(c) 参照次いで上記シリコン基板11
を、反転して例えばシリコン等からなる支持基板16上に
載置し、1000℃程度に加熱して、基板表面の熱酸化膜15
を介し支持基板16上に貼着する。この際、前記O+ 注入
領域114 は埋込みSiO2層14に変化する。
Referring to FIG. 3 (c), the silicon substrate 11
Is inverted and placed on a support substrate 16 made of, for example, silicon and heated to about 1000 ° C. to form a thermal oxide film 15 on the substrate surface.
It is stuck on the support substrate 16 via. At this time, the O + implantation region 114 changes into the buried SiO 2 layer 14.

【0021】なお、シリコン基板11が平坦性を維持した
まま、その全面で支持基板16上に貼着されのは前記実施
例と同様である。図3(d) 参照次いで、前記実施例同様
の方法により、シリコン基板11を背面から埋込みSiO2
14の底面をストッパとして研摩し、支持基板16上に熱酸
化膜15を介して貼着され、埋込みSiO2層14により複数の
領域に分割された厚さ(t) 0.1 〜0.2 μm程度の極薄S
OI層11S を有するSOI基板17が完成する。
Note that the silicon substrate 11 is stuck on the support substrate 16 over the entire surface while maintaining the flatness, as in the above-described embodiment. Then, as shown in FIG. 3 (d), the silicon substrate 11 is buried from the back side in the same manner as in the above-mentioned embodiment by a SiO 2 layer.
The bottom surface of 14 is polished as a stopper, and is adhered on the support substrate 16 via the thermal oxide film 15, and is divided into a plurality of regions by the embedded SiO 2 layer 14 and has a thickness (t) of about 0.1 to 0.2 μm. Thin S
The SOI substrate 17 having the OI layer 11S is completed.

【0022】なお上記実施例においては埋込み絶縁物層
に、酸素(O+ )のイオン注入により形成した埋込みSi
O2層14を用いたが、窒素(N+ )のイオン注入及び実施
例同様の熱処理により形成される埋込み窒化シリコン(S
i3N4) 層を用いてもよい。
In the above-mentioned embodiment, the embedded Si layer formed by implanting oxygen (O + ) ions into the embedded insulator layer.
Although the O 2 layer 14 is used, a buried silicon nitride (S) formed by nitrogen (N + ) ion implantation and heat treatment similar to the embodiment is used.
An i 3 N 4 ) layer may be used.

【0023】[0023]

【発明の効果】以上説明のように本発明によれば、SO
I層の支持基板面への貼着が、平坦性を損なわずにその
全面でなされ、且つSOI層の厚さが、深さの制御精度
の高いイオン注入により形成される埋込み絶縁物層の深
さと、表面に厚さの制御性良く形成される熱酸化膜の深
さとの差によって規定される。
As described above, according to the present invention, the SO
The adhesion of the I layer to the surface of the supporting substrate is performed on the entire surface without impairing the flatness, and the thickness of the SOI layer is the depth of the buried insulating layer formed by ion implantation with high depth control accuracy. And the depth of the thermal oxide film formed on the surface with good thickness controllability.

【0024】従って本発明によれば、 0.1μm程度の極
薄いSOI層を均一な厚さで安定に形成することがで
き、且つSOI層の剥離も防止されるので、極薄いSO
I層を有するSOI基板の品質及び製造歩留りの向上が
図れる。
Therefore, according to the present invention, an extremely thin SOI layer of about 0.1 μm can be stably formed with a uniform thickness, and peeling of the SOI layer is prevented.
The quality and manufacturing yield of the SOI substrate having the I layer can be improved.

【図面の簡単な説明】[Brief description of drawings]

【図1】 本発明の原理説明用工程断面図FIG. 1 is a process sectional view for explaining the principle of the present invention.

【図2】 本発明の方法の一実施例の工程断面図FIG. 2 is a process sectional view of an embodiment of the method of the present invention.

【図3】 本発明の方法の他の実施例の工程断面図FIG. 3 is a process sectional view of another embodiment of the method of the present invention.

【図4】 従来方法の工程断面図FIG. 4 is a process sectional view of a conventional method.

【符号の説明】[Explanation of symbols]

1 シリコン基板 2 開口部 3 マスク層 4 埋込み絶縁物層 5 熱酸化膜 6 支持基板 1 Silicon substrate 2 openings 3 Mask layer 4 Embedded insulator layer 5 Thermal oxide film 6 Support substrate

Claims (5)

【特許請求の範囲】[Claims] 【請求項1】 シリコンと化合して絶縁物を形成する物
質を、シリコン基板内の一部領域に、主面側から所定の
深さにイオン注入する工程、 該シリコン基板の主面に、前記イオン注入領域の底面よ
り浅い底面を有する熱酸化膜を形成すると同時に、前記
イオン注入領域に埋込み絶縁物層を形成する工程、 該シリコン基板を前記熱酸化膜を介し支持基板上に加熱
貼着する工程、 該シリコン基板を背面側から前記埋込み絶縁物層をスト
ッパとして研摩し、支持基板上に前記熱酸化膜を介し該
シリコン基板の薄層が貼着されてなるSOI基板を形成
する工程を有する半導体基板の製造方法。
1. A step of ion-implanting a substance that combines with silicon to form an insulator into a partial region in a silicon substrate from a main surface side to a predetermined depth, wherein the main surface of the silicon substrate is Forming a thermal oxide film having a bottom surface shallower than the bottom surface of the ion-implanted region and simultaneously forming a buried insulating layer in the ion-implanted region, the silicon substrate being heat-bonded onto the supporting substrate via the thermal oxide film. And a step of polishing the silicon substrate from the back side using the embedded insulator layer as a stopper to form an SOI substrate in which a thin layer of the silicon substrate is adhered on a supporting substrate via the thermal oxide film. Manufacturing method of semiconductor substrate.
【請求項2】 シリコン基板の主面に絶縁膜を形成する
工程、 シリコンと化合して絶縁物を形成する物質を、該シリコ
ン基板の主面側から前記絶縁膜を通し、該絶縁膜の底面
より深くイオン注入する工程、 該シリコン基板を前記絶縁膜を介して支持基板上に加熱
貼着すると同時に、前記イオン注入領域に埋込み絶縁物
層を形成する工程、 該シリコン基板を背面側から前記埋込み絶縁物層をスト
ッパとして研摩し、支持基板上に前記絶縁膜を介し該シ
リコン基板の薄層が貼着されてなるSOI基板を形成す
る工程を有する半導体基板の製造方法。
2. A step of forming an insulating film on a main surface of a silicon substrate, a substance which combines with silicon to form an insulator is passed through the insulating film from the main surface side of the silicon substrate, and a bottom surface of the insulating film. A step of implanting ions deeper, a step of heat-bonding the silicon substrate on a support substrate via the insulating film, and a step of forming an embedded insulator layer in the ion-implanted region, and a step of implanting the silicon substrate from the back side. A method for manufacturing a semiconductor substrate, which comprises a step of polishing an insulator layer as a stopper and forming an SOI substrate in which a thin layer of the silicon substrate is adhered on a supporting substrate via the insulating film.
【請求項3】 前記シリコンと化合して絶縁物を形成す
る物質が酸素からなり、前記埋込み絶縁物層が酸化シリ
コン層からなることを特徴とする請求項1若しくは2記
載の半導体基板の製造方法。
3. The method of manufacturing a semiconductor substrate according to claim 1, wherein the substance that combines with the silicon to form an insulator is oxygen, and the buried insulator layer is a silicon oxide layer. .
【請求項4】 前記シリコンと化合して絶縁物を形成す
る物質が窒素からなり、前記埋込み絶縁物層が窒化シリ
コン層からなることを特徴とする請求項1若しくは2記
載の半導体基板の製造方法。
4. The method of manufacturing a semiconductor substrate according to claim 1, wherein the substance that combines with the silicon to form an insulator is nitrogen, and the buried insulator layer is a silicon nitride layer. .
【請求項5】 前記埋込み絶縁物層が素子間分離領域と
なるように、前記シリコンと化合して絶縁物層を形成す
る物質の注入領域を定めたことを特徴とする請求項1若
しくは2記載の半導体基板の製造方法。
5. The injection region of a substance that combines with the silicon to form an insulating layer is defined so that the buried insulating layer serves as an element isolation region. Of manufacturing a semiconductor substrate.
JP17028391A 1991-07-11 1991-07-11 Manufacturing for semiconductor device Withdrawn JPH0521764A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17028391A JPH0521764A (en) 1991-07-11 1991-07-11 Manufacturing for semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17028391A JPH0521764A (en) 1991-07-11 1991-07-11 Manufacturing for semiconductor device

Publications (1)

Publication Number Publication Date
JPH0521764A true JPH0521764A (en) 1993-01-29

Family

ID=15902078

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17028391A Withdrawn JPH0521764A (en) 1991-07-11 1991-07-11 Manufacturing for semiconductor device

Country Status (1)

Country Link
JP (1) JPH0521764A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05315564A (en) * 1992-05-06 1993-11-26 Toshiba Corp Semiconductor device and manufacture thereof
JP2006294957A (en) * 2005-04-13 2006-10-26 Shin Etsu Handotai Co Ltd Joined soi wafer and method for manufacturing the same
JP2007109961A (en) * 2005-10-14 2007-04-26 Shin Etsu Handotai Co Ltd Method of manufacturing multilayer soi wafer, and multilayer soi wafer
US7291538B2 (en) * 2001-09-26 2007-11-06 Renesas Technology Corp. Semiconductor memory device and manufacturing method of the same
US7790567B2 (en) * 2007-12-17 2010-09-07 Electronics And Telecommunications Research Institute Semiconductor device and method for forming the same
TWI588918B (en) * 2014-04-01 2017-06-21 亞太優勢微系統股份有限公司 Micro-eletromechanical wafer structure having accurate gap and manufacturing method thereof

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05315564A (en) * 1992-05-06 1993-11-26 Toshiba Corp Semiconductor device and manufacture thereof
US7291538B2 (en) * 2001-09-26 2007-11-06 Renesas Technology Corp. Semiconductor memory device and manufacturing method of the same
US7498207B2 (en) 2001-09-26 2009-03-03 Renesas Technology Corp. Semiconductor memory device and manufacturing method of the same
JP2006294957A (en) * 2005-04-13 2006-10-26 Shin Etsu Handotai Co Ltd Joined soi wafer and method for manufacturing the same
JP2007109961A (en) * 2005-10-14 2007-04-26 Shin Etsu Handotai Co Ltd Method of manufacturing multilayer soi wafer, and multilayer soi wafer
US7790567B2 (en) * 2007-12-17 2010-09-07 Electronics And Telecommunications Research Institute Semiconductor device and method for forming the same
TWI588918B (en) * 2014-04-01 2017-06-21 亞太優勢微系統股份有限公司 Micro-eletromechanical wafer structure having accurate gap and manufacturing method thereof

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