JPH05217374A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To reduce current consumption of a semiconductor memory in which a cache memory is incorporated. CONSTITUTION:When the two-way transfer gate BTG is operated, at least the clamp function of a clamp circuit which receives transferred data is stopped, out of the clamp circuit (CRS) which is provided at a pair of the SRAM bit line(SBL) and the clamp circuit (CRD) which is provided at the DRAMIO line(DIO). Therefore, since the clamp operation of the clamp circuit which receives transferred data is stopped, a path in which a through current flows from the clamp circuit to the driving transistor of the transfer gate at the time of data transfer is stopped, and current consumption is reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device in which a high-speed operating memory and a relatively low-speed large-capacity memory are integrated on the same semiconductor chip, and more particularly to a large-capacity dynamic memory as a main memory. Random access memory (DRAM) and small capacity static random access memory (SRA) as cache memory
And M) are related to the configuration of a semiconductor memory device with a cache integrated on the same semiconductor chip.

More specifically, the present invention relates to a structure for reducing the current consumption of the semiconductor memory device with a built-in cache, especially the current consumption during data transfer between a high speed memory and a large capacity memory.

[0003]

2. Description of the Related Art A recent 16-bit or 32-bit microprocessing unit (MPU) has a very high operating clock frequency of 25 MHz or higher. In data processing systems, standard DRA
Since M has a low bit unit price, it is often used as a main memory with a large storage capacity. Although the access time of the standard DRAM has been shortened, the speedup of the MPU is higher than that of the standard DRAM.

Therefore, the data processing system using the standard DRAM as the main memory needs to sacrifice such as an increase in the wait state. This MPU
The problem of the operating speed gap between the standard DRAM and the standard DRAM is essential because the standard DRAM has the following features.

(I) Row address signals and column address signals are time-division multiplexed and applied to the same address pin terminal. The row address signal is taken into the inside of the device at the falling edge of row address strobe signal / RAS.
The column address signal is the column address strobe signal / C.
It is taken inside the device at the falling edge of AS. Row address strobe signal / RAS defines the start of a memory cycle and activates the row selection system. The column address strobe signal / CAS activates the column selection system.

A predetermined time called "RAS-CAS delay time (tRCD)" is required from the activation of signal / RAS until the activation of signal / CAS. Due to this delay time tRCD, there is a limitation due to address multiplexing that the shortening of access time is also limited.

(Ii) Row address strobe signal /
When the RAS is once raised and the DRAM is set to the standby state, the row address strobe signal / RAS can be lowered to "L" only after the time called the RAS precharge time (tRP) has elapsed. .. The RAS precharge time tRP is required to surely precharge various signal lines of the DRAM to predetermined potentials. Therefore, RAS precharge time tRP
Therefore, the cycle time of DRAM cannot be shortened. Also, shortening the cycle time of DRAM is
In the DRAM, the number of times of charging / discharging the signal line increases, which leads to an increase in current consumption.

(Iii) High integration of circuits and improvement of circuit technology such as layout improvement and process technology or improvement of application such as improvement of driving method
The speed of the RAM can be increased. However, M
The speeding up of PUs has greatly exceeded that of DRAMs. ECLRAM (emitter coupled RAM)
There is a hierarchical structure in the operating speed of a semiconductor memory such as a high speed bipolar RAM using a bipolar transistor such as a static RAM and a relatively low speed DRAM using a MOS transistor (insulated gate type field effect transistor). It is very difficult to expect a speed (cycle time) of several tens nS (nanoseconds) in a standard DRAM having MOS as a constituent element.

In order to fill the speed gap (difference in operating speed) between the MPU and the standard DRAM, various improvements have been made in terms of application. The major improvements are (1) using the high-speed mode and interleaving method of DRAM, and (2) high-speed cache memory (SRA).
M) is provided outside.

In the case of the above method (1), there are a method of using a high speed mode such as a static column mode or a page mode, and a method of combining the high speed mode and the interleave method. The static mode is a method in which one word line (one row) is selected and then only the column address is sequentially changed to sequentially access the memory cells in this one row. The page mode is a method in which, after selecting one word line, the signal / CAS is toggled to sequentially take in column address signals and sequentially access the memory cells connected to this one word line. In any of these modes, the memory cell can be accessed without including the toggle of the signal / RAS, which is faster than the usual access using the signals / RAS and / CAS.

The interleave system is a system in which a plurality of memory devices are provided in parallel with a data bus and the plurality of memory devices are accessed alternately or sequentially to effectively shorten the access time. The method using the high-speed mode of the DRAM and the method combining the high-speed mode and the interleave method have been conventionally known as a method for easily and relatively efficiently using the standard DRAM as the high-speed DRAM.

The above method (2) has been widely used for a long time in mainframes. High speed cache memory is expensive. However, in the field of personal computers, which are required to have high performance at a low price, they are unavoidably used in some areas at the expense of becoming expensive to some extent in order to improve the operating speed thereof.
There are the following three possibilities as to where the high-speed cache memory is provided.

(A) Built in the MPU itself. (B) Provided outside the MPU.

(C) Instead of separately providing a high-speed cache memory, the high-speed mode built in the standard DRAM is used like a cache (making the high-speed mode a pseudo cache memory). That is, the standard DRAM is accessed in the high speed mode when the cache hits, and the standard DRAM is accessed in the normal mode when the cache miss occurs.

The above three methods (a) to (c) have already been adopted in a data processing system in some form or another. However, from the viewpoint of price, in many MPU systems, in order to prevent the unavoidable RAS precharge time (tRP) from appearing effectively in the table, the memory has a bank structure, and each memory bank has The method of interleaving is used. According to this method, the cycle time of the DRAM can be substantially halved to the specification value (specification value).

However, the interleaving method is effective only when the memory devices are accessed sequentially. That is, the effect cannot be obtained when the same memory bank is continuously accessed. In addition, this method cannot substantially improve the access time of the DRAM itself. Also, the minimum unit of memory must be at least two banks.

When using the high-speed mode such as the page mode or the static column mode, the access time is effectively shortened only when the MPU continuously accesses a certain page (a specified one row of data). be able to. This method is effective to some extent because different rows can be accessed for each bank when the number of banks is relatively large, 2 to 4. The case where the memory data requested by the MPU does not exist in the given page is called a “miss hit (cache miss)”. Normal,
A chunk of data is stored at adjacent or sequential addresses. In the high speed mode, since the row address which is half of the address is already designated, the probability of "miss hit (cache miss)" is high.

As the number of banks increases from 30 to 40, different pages of data can be stored in each bank, so that the "miss hit" rate is drastically reduced. However, it is not realistic to envision 30 to 40 banks in the data processing system. Further, when a "cache miss" occurs, it is necessary to raise the signal / RAS and return to the DRAM precharge cycle in order to newly select the row address, which sacrifices the bank configuration performance. become.

In the case of the above method (2), MPU and standard D
A high speed cache memory is provided between the RAM and the RAM.
In this case, the standard DRAM may be relatively slow. On the other hand, standard DRAM is 4M (mega) bit, 16M
Bits and large storage capacity are emerging. In a small-scale system such as a personal computer, its main memory can be composed of one chip to several chips of standard DRAM.

When a high-speed cache memory is provided externally, this method is not effective in a small-scale system in which the main memory can be composed of, for example, one standard DRAM. This is because when the standard DRAM is used as the main memory, the data transfer rate between the high speed cache memory and the main memory is limited by the number of data input / output terminals of the standard DRAM, which becomes a bottleneck to the system speed.

Further, in the case of using the pseudo cache memory in the high speed mode, its operating speed is slower than that of the high speed cache memory, so that it is difficult to realize the desired system performance.

A high-speed cache memory (SRAM) is a DR as a method of eliminating the sacrifice in system performance that occurs when the above-described interleave method or high-speed operation mode is used and constructing a relatively inexpensive and small-scale system.
It may be built into the AM. That is, as shown in FIG. 21, the DRAM is the main memory and the SRAM is
It is possible to consider a one-chip memory having a hierarchical structure that includes as a cache memory. A one-chip memory having such a hierarchical structure is used as a cache DRAM (CDR A
M).

FIG. 21 is a diagram showing a schematic structure of a CDRAM. In FIG. 21, a CDRAM 550 is a large storage capacity DRAM 560 including dynamic memory cells.
And a transfer gate 570 for performing data transfer between a selected memory cell of DRAM 560 and a selected memory cell of SRAM 580. Transfer gate 570 can transfer data bidirectionally.

FIG. 22 is a diagram showing a structure of a main part of a conventional standard CDRAM. DRAM 560 includes a memory cell array 500 having a plurality of dynamic memory cells DMC arranged in a matrix of rows and columns. One row of memory cells DMC has one word line DWL
Connected to. One column memory cell DMC has one column line C
Connected to L. The column line CL is usually composed of a pair of bit lines. One word line DWL selects a memory cell located at an intersection with one bit line of a pair of bit lines. In the 1M DRAM, the memory cells DMC are arranged in a matrix of 1024 rows × 1024 columns. That is, this memory cell array 500
Is 1024 word lines DWL and 1024 column lines C
L (1024 pairs of bit lines).

The DRAM 560 further decodes a row address signal (not shown) given from the outside to select a corresponding row of the memory cell array 500.
02, a sense amplifier for detecting and amplifying data of a memory cell connected to the word line selected by the row decoder 502, and a column address signal (not shown) given from the outside to decode the data, and to correspond to the memory cell array 500. Includes a column decoder for selecting a column of. In FIG. 22, the sense amplifier and the column decoder are shown to be included in one block 504. Actually, an internal address signal from the address buffer is applied to the row decoder and column decoder, but this address buffer is not shown.

When DRAM 560 has a × 1 bit structure for inputting / outputting data in 1-bit units, one column line (one bit line pair) CL is selected by the column decoder. When the DRAM has a × 4 bit structure for inputting / outputting data in units of 4 bits, four column lines CL are selected by the column decoder. One sense amplifier included in the block 504 is provided for each column line (bit line pair) CL.

At the time of memory access for writing or reading data to or from memory cell DMC in DRAM 560, the following operation is performed. First, the row decoder 50
A row address signal (to be exact, an internal row address signal) is given to 2. The row decoder 502 decodes a given row address signal, and
The potential of the word line DWL of the book is raised to "H". The data of the 1024-bit memory cell DMC connected to the selected word line DWL is transmitted onto the corresponding column line CL. The data on the column line CL is amplified by the sense amplifier included in the block 504.

Of the memory cells connected to the selected word line DWL, a memory cell to be written or read with data is selected by a column selection signal from a column decoder included in block 504. The column decoder decodes a column address signal (to be exact, an internal column address signal) and generates a column selection signal for selecting a corresponding column in the memory cell array 500.

The SRAM 580 is a cache register (SRAM cell) 506a, 50 capable of storing data of one row of the DRAM memory cell array 500.
6b, 506c and 506d. SRAM580
In each of the cash registers 506a-506d of
A cache register is provided corresponding to each column line CL of the DRAM memory cell array 500. Ie SRAM
580 includes 4 × 1024 cash registers. The cash register is usually composed of static memory cells (SRAM cells). This CDR
The AM realizes a 4-way set associative mapping method.

When a signal indicating a cache hit is externally applied, SRAM 580 is accessed and a memory cell is accessed at high speed. When a cache miss occurs, DRAM 560 is accessed. The way is selected by the selector 510 according to the way address (given from the outside),
Four cash register blocks 506a-506d
One of them is selected. The capacity of this SRAM cache is 4 Kbits (the cash register 506a.
~ 506d each include 1x1024 cash registers).

A transfer gate 570 is provided between the DRAM 560 and the SRAM 580. The column lines (bit line pairs CL) of the DRAM memory cell array 500 and the respective column lines (bit line pairs) of the SRAM (cache memory) are connected via the transfer gate 570 in a one-to-one correspondence relationship.

The so-called block size of the cache is
In the SRAM 580, it can be considered as the number of bits whose contents are rewritten by one data transfer operation. Therefore, this block size is the same as the number of memory cells physically coupled to one word line DWL of DRAM memory cell array 500. In the case of the configuration shown in FIG. 22, since 1024 memory cells are physically connected to one word line DWL in the DRAM memory cell array 500, the block size is 1024.

FIG. 23 is a diagram showing a specific configuration of one column line (DRAM array associated with a bit line pair) and a cash register.

The SRAM cell SMC forming the cash register is composed of MOS (insulated gate type field effect) transistors SQ1, SQ2 and SQ forming the inverter latch.
3 and SQ4. The p-channel MOS transistor SQ1 and the n-channel MOS transistor SQ3 are complementarily connected between the operating power supply potential Vcc and the other power supply potential (ground potential) Vss to form one inverter circuit.

P-channel MOS transistors SQ2 and n
The channel MOS transistor SQ4 and the operating power supply potential V
Complementary connection is made between cc and the ground potential Vss to form the other inverter circuit. Transistors SQ1 and S
The gate of Q3 is connected to node SN1, and the gates of transistors SQ2 and SQ4 are connected to node SN2. Node SN1 is an output node of one inverter circuit (transistors SQ1 and SQ3), and node S
N2 is an output node of the other inverter circuit (transistors SQ2 and SQ4).

The SRAM cell SMC is further rendered conductive in response to a signal on the SRAM word line SWL, and the node SN1.
And SN2 are connected to SRAM bit lines SBL and * SBL, respectively, n channel MOS transistor SQ
5 and SQ6. Bit lines SBL and * SBL
Is provided with diode-connected n-channel MOS transistors SQ7 and SQ8. MOS transistors SQ7 and SQ8 are connected to bit lines SBL and * SB
The potential of "H" of L is clamped to the potential of Vcc-Vth. Here, Vth is the transistors SQ7 and SQ8.
Is the threshold voltage of. The transistors SQ7 and SQ8 are also connected to the SRAM bit lines SBL and * SBL.
The "L" potential level is set to a level higher than the ground potential Vss.

The DRAM cell DMC includes one select transistor TM and a capacitor C for storing information. In FIG. 23, the DRAM word lines DWL1 and DWL
The DRAM cell DMC1 is provided corresponding to the intersection with the RAM bit line * DBL, and the DRAM word lines DWL2 and DWL2.
The DRAM cell DMC2 is provided at the intersection with the RAM bit line DBL.
Is shown as an example. One electrode (cell plate) of the capacitor C is connected to a predetermined potential Vg.
The potentials of the DRAM bit line DBL and the DRAM bit line * DBL are set to the sense amplifier activation signal SA.
A DRAM sense amplifier DSA for differentially amplifying in response to is provided. DRAM sense amplifier DSA typically includes a P sense amplifier in which p channel MOS transistors are cross-coupled and an N sense amplifier in which n channel MOS transistors are cross coupled.

Bidirectional transfer gate 507 responds to transfer instruction signal φT from SRAM cell to DRAM cell or D cell.
Data is transferred from the RAM cell to the SRAM cell. Here, only one type of transfer control signal φT is generically shown. The configuration of the bidirectional transfer gate will be specifically described later.
Next, operations of the DRAM cell and the SRAM cell will be briefly described. First, the operation of writing and reading data in the SRAM cell will be described.

During data writing, complementary data are transmitted to SRAM bit line SBL and complementary SRAM bit line * SBL. Now, "H" is applied to the bit line SBL,
Consider a state in which the potential of "L" is transmitted to the complementary bit line * SBL. The potential of the SRAM word line SWL is at "H", and the nodes SN1 and SN2 are respectively connected to the bit line SBL through the transistors SQ5 and SQ6 in the conductive state.
And * SBL respectively. The potential of the node SN1 is applied to the gates of the transistors SQ2 and SQ4, the transistor SQ4 is turned on, and the transistor SQ4 is turned on.
Q2 becomes non-conductive.

The "L" potential of node SN2 is applied to the gates of transistors SQ1 and SQ3, turning on transistor SQ1 and turning off transistor SQ3. As a result, the potential of the node SN1 is set to "H" and the potential of the node SN2 is set to "L", and these potentials are latched by the inverter latch circuit including the transistors SQ1 to SQ4. SRAM word line SW
Writing of data is completed when the potential of L falls to "L".

When reading data, the SRAM is also used.
The potential of word line SWL rises to "H", and transistors SQ5 and SQ6 are rendered conductive. Node SN1
The stored data (potential) latched by SN2 and SN2 are transmitted to bit lines SBL and * SBL, respectively. Complementary data of "H" and "L" are transmitted to the bit lines SBL and * SBL. This bit line SB
The signal potentials of L and * SBL are amplified by an SRAM sense amplifier (not shown) and read via the data output circuit.

Next, the operation of the DRAM cell will be described. Now, consider the case where the DRAM word line DWL1 is selected. Select transistor TM of DRAM cell DMC1
Is turned on and the capacitor of cell DMC1 becomes DRA
Connected to M bit line * DBL. Then, the DRAM sense amplifier DSA is activated by the sense amplifier activation signal SA and differentially amplifies the potentials of the bit lines * DBL and DBL. Since no memory cell is connected to the DRAM bit line DBL, the potential of the bit line DBL is an intermediate potential. When the potential of the bit line * DBL is slightly lower than this intermediate potential, the DRAM sense amplifier DSA sets the bit line DBL to "H" and the bit line * DB.
Charge and discharge L to "L". In the opposite case, the bit line DB
The potential of L becomes "L" and the potential of the bit line * DBL becomes "H".

In the case of data writing, data from a write circuit (not shown) is transmitted onto the bit lines DBL and * DBL, and the potentials of the bit lines DBL and * DBL become values corresponding to the write data. It is written in the memory cell DMC1. When reading data, the sense amplifier DS
The data amplified by A is read.

The structure of the data input / output circuit is not clearly shown. This is because it depends on the configuration of the CDRAM. Normally, in the case of the simple cache as shown in FIG. 23, the SRAM bit lines SBL and * SBL are connected to the internal data input / output line (IO line). In the case of a cache miss, the bidirectional transfer gate 507 opens and the DRAM
In the array 500, a word line is selected and a sensing operation is performed, and thereafter, the S line is transferred through the bidirectional transfer gate 507.
Data is read or written via BL and * SBL.

When data is transferred from DRAM array 500 to SRAM array 506 in one direction, bidirectional transfer gate 507 includes a pair of transfer gate transistors. In this case, the drive capability of the DRAM sense amplifier DSA is made larger than the latch capability of the SRAM cell SMC. The drive capability of the data write circuit (not shown) is larger than the latch capability of the DRAM sense amplifier DSA. As a result, the DRAM is accessed in the case of a cache miss and the SRAM is accessed in the case of a cache hit. A CDRAM having such a simple structure is disclosed in, for example, Japanese Patent Laid-Open No. 1-146187. Next, the functions of the transistors SQ7 and SQ8 will be described with reference to FIG. 24 showing the operating functions thereof.

Transistors SQ7 and SQ8 are diode-connected to clamp the "H" potential of bit lines SBL and * SBL to potential Vcc-Vth. That is, the potential level of the "H" level of the potential amplitude of SRAM bit lines SBL and * SBL is set to Vcc-Vth. The "H" data latched at the node SN1 has a potential of Vcc level. When this "H" latch data is transmitted to the bit line SBL, its potential level is Vc due to signal loss due to the transistor SQ5.
It becomes c-Vth.

On the other hand, the bit line SBL (or * SBL)
The potential VL1 at the “L” level of the potential amplitude of the transistors SQ4, SQ5 and SQ8 (or SQ3, SQ5
And SQ7) resistance division. This "L" level potential VL1 of the bit line potential amplitude is the ground potential V
Higher than ss.

That is, the transistors SQ7 and SQ
8 also has a function of increasing the potential of "L" of the bit lines SBL and * SBL. The transistors SQ7 and SQ8 clamp the potentials of the bit lines SBL and * SBL to a predetermined potential, and are referred to as clamp transistors in the following description.

First, for comparison, consider a case where the clamp transistors SQ7 and SQ8 are not provided.
In this case, the "L" level potential VL2 of the bit lines SBL and * SBL is the same as that of the transistors SQ6 and SQ4.
(Or SQ5 and SQ3) discharges to the ground potential Vss, and becomes almost the ground potential level. Transistor S
Bit line S when Q7 and SQ8 are not provided
BL (or * SBL) "H" level potential is Vcc
-Vth. In this case, the "H" level applied to word line SWL is the operating power supply potential Vcc level, and there is a loss in threshold voltage Vth of transistor SQ5 or SQ6 in transistor SQ5 (or SQ6). Suppose

In FIG. 24, assume that the potential of SRAM word line SWL rises to "H" at time TWL. If the transistors SQ7 and SQ8 are provided, the SRAM cell S is connected to the bit lines SBL and * SBL.
The data stored in MC is transferred, and the potentials "H" and "L" of the bit lines SBL and * SBL intersect at time T1.

On the other hand, when the transistors SQ7 and SQ8 are not provided, the potentials of "H" and "L" in the bit lines SBL and * SBL intersect at time T2.

The data of each bit line SBL and * SBL is fixed at a time after the time point when the potential "H" and the potential "L" of the bit lines SBL and * SBL intersect. Therefore, by providing the transistors SQ7 and SQ8, the logical amplitude of the bit lines SBL and * SBL can be reduced and the access time can be shortened. In particular, when the SRAM has a plurality of rows and the bit line becomes long, this clamp function is effectively exhibited.

[0053]

As described above, by using the clamp transistor, the logical amplitude of the SRAM bit line can be reduced, and the SR for high speed access can be obtained.
The AM can be driven at a higher speed. However, the use of such a clamp transistor causes a problem of large current consumption. Hereinafter, this problem will be described in detail.

FIG. 25 is a diagram showing an example of a specific configuration of the transfer gate section. In FIG. 25, the transfer gate 570
Is the SRAM bit line SBL and the DRAM bit line DBL
Transfer gate transistor TSQa provided between
And SRAM bit line * SBL and DRAM bit line * D
Transfer gate transistor TSQ provided between BL and
b is included. Transfer gate transistors TSQa and TSQb are rendered conductive in response to transfer instruction signal φT.

This structure has a DRAM sense amplifier DSA.
2 shows the configuration in the case where the driving power and the latching capacity of the SRAM cell are larger than the latching capacity of the SRAM cell SMC.

DRAM sense amplifier DSA includes cross-coupled n-channel MOS transistors NQ100 and NQ101 and cross-coupled p-channel MOS transistors PQ100 and PQ101. Transistors NQ100 and NQ101 are activated in response to N sense amplifier activation signal SAN to discharge the low potential bit line potentials of bit lines DBL and * DBL to the ground potential.

P-channel MOS transistor PQ100
And PQ101 are activated in response to P sense amplifier activation signal SAP to boost the potential of the high potential bit lines of bit lines DBL and * DBL to the power supply potential Vcc level.

In the case of the above structure, only the SRAM is accessed at the time of cache hit. Since the clamp transistors SQ7 and SQ8 reduce the logical amplitude of the bit lines SBL and * SBL, the data in the SRAM cell SMC can be read at high speed. The same applies when writing data.

Now, consider a state in which a cache miss has occurred and a data transfer signal φT has been generated. This transfer instruction signal φT
Is generated after the DRAM sense amplifier DSA is activated. That is, the sense amplifier activation signal S
After AN and / SAP are activated. In this case, the data in the DRAM cell DMC is the SRAM cell SM.
It is transmitted to C. Normally, in the DRAM sense amplifier DSA, after the bit lines DBL and * DBL are amplified to "H" and "L", the signal potential is latched, but no through current is generated after the sensing operation is completed. That is, for example, the DRAM bit line DBL is now "H",
When the DRAM bit line * DBL is "L", the transistor NQ101 is in the off state, and the "H" bit line DB
No current flows from L to the sense amplifier activation signal transmission line SAN (denoted by the same reference numeral as the signal above it). On the other hand, although the transistor PQ101 is turned on, the sense amplifier activation signal SAP is "H" and the bit line DB
No current flows from L through the transistor PQ101.

Now, when the transfer instruction signal φT becomes "H", a current is supplied from the clamp transistor SQ8,
A current flows to the sense amplifier drive activation signal line SAN through the transistor NQ100. Therefore, there is a problem that the current is unnecessarily consumed.

As described above, the SRAM bit line pair S
BL and * SBL and SRAM bit line pair DBL and * DBL are not provided one to one, but only one memory cell block of DRAM array 500 is selected and S is selected.
A configuration in which data transfer is performed in block units with the ARAM array 506 can also be considered.

FIG. 26 shows such an SRAM array 506.
FIG. 10 is a diagram showing a configuration for transferring data between a block of DRAM array 500 and a block of DRAM array 500. In FIG. 26, the DRAM array 500 has four array blocks B
Includes # 1, B # 2, B # 3, and B # 4. Bidirectional transfer gate 570 includes a unit gate circuit provided corresponding to each bit line pair of SRAM array 506. DRA between the bidirectional transfer gate 570 and the DRAM array 500
An MIO line 575 is provided. This DRAM IO line 57
5 to one block B # i of the DRAM array 500
(I = 1 to 4). As a result, one block of the DRAM array 500 and S
Data transfer to and from the RAM array 506 can be performed.

FIG. 27 is a diagram showing a structure of a main part of the apparatus shown in FIG. In FIG. 27, only the connection form between one SRAM bit line SBL and one DRAM bit line DBL is representatively shown. Bidirectional transfer gate 57
0 is a transfer circuit 5702 for transmitting the data on the SRAM bit line SBL to the DRAM IO line DIO in response to the transfer instruction signal φTA, and D in response to the transfer instruction signal φTS.
The data on the RAMIO line DIO is transferred to the SRAM bit line SB
A transfer circuit 5701 for transmitting to L is included. This transfer circuit 5
701 and 5702 are provided for each SRAM bit line. Array block B of DRAM array 500
# Connects the DRAM bit line DBL included therein to the DRAM IO line DIO via the block selection gate BG. The block selection gate BG has a block selection signal Bi.
Conducts in response to. Block selection gates BG and DRA
A column selection gate YG which is turned on in response to a column selection signal Yi is provided between the M bit line DBL and the M bit line DBL. As a result, the bit line DBL of the selected block B # is DR
It is connected to the bidirectional transfer gate 570 via the AMIO line DIO.

A clamp transistor DQC is similarly provided on the DRAMIO line DIO, and the DRAMIO line DIO
The logic amplitude of IO is reduced to speed up the data transfer operation.

Considering the configuration as described above, the SRAM
Data transfer between the array 506 and the DRAM array 500 is not limited to the direct mapping method, and a flexible mapping method can be realized.

However, in the case of such a configuration, when the clamp transistors SQC and DQC are always turned on, the same problem of current consumption arises. That is, since the transfer circuits 5701 and 5702 are normally formed by using MOS transistors, current consumption does not occur on the input side thereof. However, a problem occurs in the drive transistor on the output side.

That is, for example, the DRAM array 500
Consider a case where data is transmitted from block B # to the SRAM bit line SBL of the SRAM array. When the data to be transferred is “L”, no current flows from DRAM array IO line DIO to transfer circuit 5701. However, in the drive circuit included in this transfer circuit 5701, the transistor discharging to the ground potential is in the on state, and the through current flows through the transistor in the on state and the clamp transistor SQC. A large current consumption occurs when data is transferred in multiple bits (for example, in block units).

Similarly, the SRAM bit lines SBL to D
When transferring data to RAM bit line DBL, an operation similar to that at the time of normal writing works on DRAM block B # and is performed via transfer circuit 5702. In this case, similarly, a current flows from the clamp transistor DQC that clamps the potential of the DRAM IO line DIO to the drive transistor of the transfer circuit 5702. Therefore, similarly, there arises a problem that the current consumption increases.

Therefore, the object of the present invention is the above-mentioned CD.
It is an object of the present invention to provide a semiconductor memory device capable of eliminating the drawbacks of a RAM and transferring data at high speed with low current consumption.

[0070]

In the semiconductor memory device according to the present invention, the clamp transistor provided on the side receiving the data transfer is turned off during the data transfer.

That is, a semiconductor memory device according to a first aspect of the present invention includes a high-speed memory array having a plurality of static memory cells, a large-capacity memory array having a large storage capacity including a plurality of dynamic memory cells, and the high-speed memory array. Data transfer means for transferring data between the selected memory cell of and the selected memory cell of the large capacity memory array. Large capacity memory arrays have greater storage capacity than high speed memory arrays.

According to the semiconductor memory device of the present invention, a signal line for connecting the selected memory cell of the large-capacity memory array and the data transfer means, and a potential for the signal line are clamped. A clamp means and a control means for inhibiting the clamp operation of the clamp means in response to a data transfer instruction from the high speed memory array to the large capacity memory array are provided.

According to another aspect of the semiconductor memory device of the present invention, there are provided a high-speed memory array having a plurality of static memory cells arranged in a matrix, a large-capacity memory array having a plurality of dynamic memory cells, and a high-speed memory array. Included is data transfer means for transferring data between the selected memory cell and the selected memory cell of the mass memory array.

The semiconductor memory device according to the present invention is further provided in each of the SRAM column lines and has a corresponding SRAM.
Clamping means for clamping the potential of the column line and control means for inhibiting the clamping operation of the clamping means in response to a data transfer instruction from the large capacity memory array to the high speed memory array.

[0075]

In the semiconductor memory device according to the first and second aspects, the control means prohibits the clamp operation of the clamp means provided on the side receiving the data transfer. This prevents a current from flowing from the clamp means to the transfer means, and realizes low current consumption.

[0076]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Before describing an embodiment of the present invention,
The configuration of the CDRAM to which the present invention is applied will be described. However, the present invention is a CDRAM described below.
SRAM and DR are not intended to be applied only to
SRAM integrated with AM on the same semiconductor chip
The present invention can be applied to any semiconductor memory device that can transfer data between memory and DRAM.

FIG. 2 is a diagram showing a pin arrangement of a package which houses a CDRAM to which the present invention is applied. The package shown in FIG. 2 is a CDRA in which a 4M bit DRAM and a 16K bit SRAM are integrated on the same chip.
Store M. CDRAM has a lead pitch of 0.8 m
m, chip length 18.4 mm, number of pin terminals 44 300 m
It is housed in Type II of il TSOP (Thin Small Outline Package).

The CDRAM includes two types of data input / output methods: D / Q separation and masked write. D /
The Q separation mode is a method in which the write data D and the read data Q are input / output via separate pin terminals. The masked write mode is an operation mode in which the write data D and the read data Q can be output via the same pin terminal and the writing of data from the outside can be masked.

The power supply potential is efficiently supplied to the CDRAM,
Further, in order to facilitate the layout of the power supply wiring, three pin terminals are provided for each of power supply potentials Vcc and GND. Power supply potential Vcc is externally supplied to the pin terminals of pin numbers 1, 11 and 33. Power supply potential V applied to the pin terminals of pin numbers 1, 11, and 33
cc may be the operating power supply potential in this CDRAM, or may be configured to be stepped down internally.
The ground potential GND is applied to the pin terminals of pin numbers 12, 22, and 34. Pins numbered 1 and 22 are DRA
It is a power supply pin terminal for M and has pin numbers 11, 12, 33,
Pins 34 and 34 are power supply pin terminals for SRAM.
Pin numbers 6-8, 15-17, 28-30
Address signals Ac0 to Ac11 for SRAM are applied to pin terminals 37 and 39. The address signals Aa0 to Aa9 for the DRAM have pin numbers 2, 3, 1
9 to 21, 24 to 26 and 42, 43 to the pin terminals. Command addresses Ar0 and Ar1 for setting various operation modes of this CDRAM are also given to the pin terminals of pin numbers 2 and 3.

A cache inhibition signal CI # indicating inhibition of cache access is applied to the pin terminal of pin number 4. When the cache inhibit signal CI # is set to "L", access to the SRAM array is inhibited and the DRAM
Direct access to the array (array access) becomes possible.

Write enable signal W # indicating the data write mode is applied to the pin terminal of pin number 5. A chip select signal E # indicating that this chip has been selected is applied to the pin terminal of pin number 18.

Command register designating signal CR # for designating the special mode is applied to the pin terminal of pin number 23. When command register designating signal CR # is "L", command addresses Ar0 and Ar applied to the pin terminals of pin numbers 2 and 3 are valid, and the special mode is set (register is selected). A burst mode instruction signal BE # generated when an externally provided arithmetic processing unit transfers data according to the burst mode is also applied to the pin terminal of pin number 23. When burst mode instructing signal BE # is activated, this CDRAM automatically generates an address signal internally, and batch data transfer according to the burst mode is executed between the external arithmetic processing unit and CDRAM.

A cache hit signal CH # indicating a cache hit is applied to the pin terminal of pin number 27. If the cache hit signal CH # is at "L", the cache (SRAM array) can be accessed. Output enable signal G # indicating the output mode is applied to the pin terminal of pin number 40. A clock signal (for example, a system clock) is input to the pin number 41.
K is given.

A refresh instruction signal R for instructing refresh of the DRAM array is applied to the pin terminal of the pin number 44.
EF # is given. When the refresh instruction signal REF # becomes "L", the DRAM is internally used in that cycle.
The array is automatically refreshed. CDRAM
Has an auto refresh mode and a self refresh mode. The setting of the refresh mode is determined by the refresh mode setting signal set in the command register. In the auto refresh mode, the DRAM array is refreshed according to the above-described refresh instruction signal REF #.

When the self refresh is designated, the pin terminal of the pin number 44 is switched to the output terminal.
At the time of executing the self-refresh, a signal BUSY # indicating the execution of the self-refresh is output from the pin terminal of pin number 4. This signal BUSY # causes CDRA
It becomes possible to know the self-refresh timing outside the M, and the self-refresh can be used even in the normal cycle.

Pin numbers 9, 10, 13, 14, 31, 3
Data to be supplied to the pin terminals of 2, 35 and 36 are different depending on two kinds of operation modes of D / Q separation and masked write. The operation mode of D / Q separation and masked write is set by the command register.

In the masked write mode, the pins of pin numbers 10, 13, 32 and 35 are used as data input / output terminals for common data input / output. Masked write instruction data M0, M1, M2, and M3 indicating which input / output pin is to be masked are supplied to the pins of pin numbers 9, 14, 31, 35, and 36, respectively.

In the D / Q separation mode, the pin terminals of the pin numbers 9, 14, 31 and 36 are the write data D.
Used as pin terminals for inputting 0, D1, D2 and D3. Pin numbers 10, 13, 32, and 3
The pin terminals of 5 are read data Q0, Q1, Q2 and Q.
It is used as a data output pin terminal for outputting 3.

SRAM addresses Ac0 to Ac11 and DR
AM addresses (array addresses) Aa0 to Aa9 are
Each is independently provided through a separate pin terminal. In the pin arrangement shown in FIG. 2, the external operation control signals normally used in the standard DRAM, that is, the row address strobe signal / RAS and the column address strobe signal / CAS are not used. In the CDRAM housed in the package shown in FIG. 2, control signals and data are input in response to a clock signal K from the outside.

FIG. 3 shows a CD housed in this package.
It is a figure which shows schematic structure of RAM. In Figure 3, the CD
The RAM is a DRAM array 1 including dynamic memory cells arranged in a matrix of rows and columns.
And an SRAM array 2 made up of static memory cells arranged in a matrix of rows and columns, and a bidirectional transfer gate circuit 3 for transferring data between the DRAM array 1 and the SRAM array 2. including.

The DRAM array 1 has a storage capacity of 1M.
In the case of a bit, it includes 1024 word lines DWL and 1024 pairs of bit lines BL and / BL. However, in FIG. 3, the bit line pair is indicated by DBL. DRAM array 1 is divided into a plurality of blocks along the row and column directions, respectively. In FIG. 3, the DRAM array 1 is divided into eight blocks MBi1 to MBi8 (i = 1 to 4) in the column direction and four blocks MB1j to MB4j in the row direction.
An example is shown in which (j = 1 to 8) is divided into a total of 32 memory blocks.

Eight blocks MBi divided in the column direction
1 to MBi8 form one row block 11. Memory blocks MBi1 to MBi1 included in one row block 11
MBi8 shares one word line DWL. Memory blocks MB1j to M included in the same column block 12
B4j shares the column selection line CSL. A sense amplifier IO block 13 is provided in each of the memory blocks MB11 to MB48. Column select line CSL is 2 at the same time
Select a column (two pairs of bit lines).

The CDRAM further includes an internal address int
Row decoder 14 for selecting the corresponding row from DRAM array 1 in response to -Aa, and internal column address int-Aa
Column decoder 15 for selecting one column select line CSL in response to. The column block 12 is connected to the bidirectional transfer gate circuit 3 via two pairs of IO lines 16a and 16b which are independent of each other.

The SRAM array 2 includes 16 pairs of SRAM bit line pairs SBL connected to the 16 pairs of IO lines (16a and 16b) via the bidirectional transfer gate circuit 3.
including. The SRAM array 2 includes 16 pairs of bit lines and 256 word lines for a capacity of 4 Kbits.
In this case, the SRAM array 2 has 16 bits per row.

The CDRAM further decodes the SRAM address int-Ac given from the outside to generate the SRAM.
SRAM row decoder 2 for selecting the corresponding row of array 2
1 and an SRAM column decoder 22 which decodes the internal address signal int-Ac and selects a corresponding column of the SRAM array 2, and a memory cell selected by the SRAM row decoder 21 and the SRAM column decoder 22 at the time of data reading. A sense amplifier circuit 23 for amplifying data is included.

The SRAM bit line pair SBL selected by the SRAM column decoder 22 is the common data bus 251.
Connected to. Data is input / output through the input / output buffer 274. Address in applied to DRAM row decoder 14 and DRAM column decoder 15
The addresses int-Ac applied to t-Aa and the SRAM row decoder 21 and the SRAM column decoder 22 are addresses independent of each other, and are applied via different address pins as described above.

CDRAM is further activated in response to chip enable signal E, and responds to external addresses Aa and Ac with internal addresses int-Aa and int.
An address buffer 252 that generates -Ac; a DRAM array drive circuit 260 that drives the DRAM array in response to internal control signals E, CH, CI and REF; and an SRAM that drives the SRAM array in response to the chip enable signal E. Array drive circuit 264, internal control signal E,
Bidirectional transfer gate circuit 3 in response to CH, CI and W
A transfer gate control circuit 262 for controlling the transfer operation of. In the structure shown in FIG. 3, DRAM array 1
The selected column is connected to the internal data line (common data bus) 251 via the bidirectional transfer gate circuit 3 (in the case of array access). Connection between the DRAM array 1 and the internal data line 251 via the bidirectional transfer gate circuit 3 is performed by using a column selection gate provided in the bidirectional transfer gate circuit 3 in response to a column selection signal from the DRAM column decoder 15. May be done. Other configurations may also be used. The connection between the DRAM array 1 and the internal data line 251 and the connection between the SRAM array 2 and the internal data line 251 will be described later in detail.

Although the SRAM column decoder 22 is provided between the bidirectional transfer gate circuit 3 and the SRAM array 2, the SRAM column decoder 22 is provided between the bidirectional transfer gate circuit 3 and the DRAM array 1. It may be configured to be.

Next, the CDRAM data transfer operation shown in FIG. 3 will be schematically described. First, the operation of the DRAM portion will be described. Row address A given from outside
The row decoder 14 performs a row selection operation according to a.
The potential of the word line DWL of the book is raised to "H". From the memory cells connected to the selected one word line DWL, the corresponding 1024 bit lines BL (or / BL)
The data is read.

Then, the sense amplifiers (included in block 13) included in row block 11 including the selected DRAM word line DWL are activated all at once, and the potential difference between each bit line pair is differentially amplified. .. In this way, only one row block among the four row blocks 11 is activated in order to reduce the current consumption (power) associated with the charging / discharging of the bit line during the sensing operation (including this selected row). An operation method that activates only row blocks is called a block division operation method).

Then, DRAM column decoder 15 performs a column selecting operation according to a column address applied from the outside.
In each column block 12, one column selection line CSL is brought into a selected state. One column select line CSL selects two pairs of DRAM bit lines DBL, and connects the two pairs of bit lines to two pairs of DRAM IO lines 16a and 16b provided corresponding to the column block. This allows
A plurality of bits (16 bits in this embodiment) of data from the DRAM array 1 are transferred to a plurality of DRAM IO line pairs 16.
read on a and 16b.

On the other hand, the following operation is executed for the SRAM part. The SRAM row decoder 21 performs a row selection operation according to an SRAM address given from the outside, and selects one word line from the SRAM array 2.
A 16-bit memory cell is connected to one SRAM word line as described above. Therefore, 16 static memory cells (SRAM cells) have 16 pairs of SRAM bit lines SB from the selection operation of this one word line.
Connected to L.

1 for DRAMIO line pair 16a and 16b
After 6-bit data is transmitted, the bidirectional transfer gate circuit 3 is turned on, and 16 pairs of DRAMIO line pairs 16
a and 16b and 16 pairs of SRAM bit lines SBL are connected to each other. As a result, the SRAM array 2
The data transmitted on 16 pairs of DRAM IO line pairs 16a and 16b are written (or the reverse data transfer is executed) into the 16-bit memory cell already selected in.

The sense amplifier circuit 23 and the column decoder 22 provided in the SRAM are provided in the SRAM array 2
It is used for exchanging data between the memory cell in and the internal data line 251 for inputting / outputting external data.

The address Ac for selecting the SRAM cell in the SRAM array 2 can be set completely independently of the address Aa for selecting the dynamic memory cell (DRAM cell) in the DRAM array 1. Therefore, the 16-bit memory cell selected in the DRAM array 1 can transfer data to and from the memory cell at an arbitrary position (row) of the SRAM array 2, and the direct mapping method, the set associative method, and the full associative method can be used. All mapping schemes of the scheme can be realized without changing the arrangement and configuration of the array.

As described above, batch transfer of 16-bit data is executed between the SRAM array 2 and the DRAM array 1. The present invention relates to SRAM bit line pair S
A clamp means is provided in the BL and DRAM IO line pairs 16a and 16b to speed up data transfer, writing and reading, and to reduce current consumption during data transfer. Next, the configuration of each part will be described.

FIG. 4 is a diagram showing an example of address distribution in the CDRAM shown in FIG. In the structure shown in FIG. 4, writing / reading of data in DRAM array 1 is performed through bidirectional transfer gate circuit 3, and in this case, in order to select a 4-bit memory cell from a 16-bit memory cell. The SRAM column decoder 22 is used.

In FIG. 4, a DRAM address buffer 252a is provided with external DRAM addresses Aa0-Aa.
Upon receiving a9, the internal address int-Aa is generated. D
The RAM row decoder 14 uses the internal address int-
Word line drive signal DWL for decoding the internal row address of Aa and selecting the corresponding word line from the DRAM array
To occur.

The DRAM column decoder 15 is a DRAM
It receives a part of the internal column address from address buffer 252a and generates a column selection line selection signal CSL for selecting a column selection line from the DRAM array. The remaining part of the internal column address from DRAM address buffer 252a is applied to multiplexer 30.

The multiplexer 30 has an S input at the other input.
It receives an internal column address from RAM address buffer 252b. Multiplexer 30 passes one of the DRAM internal column address and the SRAM internal column address in response to internal control signals CH and CI to pass SRA.
It is given to the M column decoder 22. The column selection signal CD is generated from the SRAM column decoder 22.

The SRAM row decoder 21 decodes the internal row address from the SRAM address buffer 252b to bring the corresponding row of the SRAM array into the selected state.
The M word line drive signal SWL is generated.

Normally, when the cache hit instruction signal CH is generated, access to the SRAM array is permitted and access to the DRAM is prohibited. When cache access prohibition signal CI is generated, access to the DRAM array is permitted, and writing / reading of data to / from the memory cell of this DRAM array is executed.

Therefore, the multiplexer 30 receives the SRAM address buffer 252 when the signal CH is generated.
The internal column address from b is selected and transmitted to the SRAM column decoder 22. When signal CI is generated, multiplexer 30 selects the internal column address from DRAM address buffer 252a and transmits it to SRAM column decoder 22.

FIG. 5 is a diagram showing a specific structure of a main part of the CDRAM shown in FIG. In FIG. 5, a portion related to data transfer of one memory block MBij of the DRAM array is representatively shown. In FIG.
Memory block MBij includes a plurality of DRAM cells DMC arranged in a matrix. One row DRAM cell DMC
Are connected to one DRAM word line DWL. One column of DRAM cells DMC is connected to DRAM bit line pair DBL. The DRAM bit line pair DBL is two DRAMs.
Includes bit lines DBLa and * DBLa. Signals complementary to each other are transmitted to the DRAM bit line DBLa and the complementary bit line * DBLa. DRAM cell DMC is DRA
It is arranged corresponding to the intersection of M word line DWL and DRAM bit line pair DBL.

A DRAM sense amplifier DSA for detecting and amplifying the potential difference on the corresponding bit line pair is provided for each DRAM bit line pair DBL. The DRAM sense amplifier DSA has a sense amplifier activation signal / SAP.
Sense amplifier drive signal SA in response to E and SANE
Sense amplifier activation circuit SA for generating P and SAN
Its operation is controlled by K.

As shown in FIG. 25, DRAM sense amplifier DSA includes cross-coupled p-channel MOS transistors and cross-coupled n-channel MOS transistors.

Sense amplifier activating circuit SAK is turned on in response to sense amplifier activating signal / SAPE, and sense amplifier activating transistor TR1 for activating P sense amplifier of DRAM sense amplifier DSA.
And a sense amplifier activation transistor TR2 which is turned on in response to the sense amplifier activation signal SANE and activates the N sense amplifier of the DRAM sense amplifier DSA.
including. Transistor TR1 is formed of a p-channel MOS transistor, and transistor TR2 is formed of an n-channel MOS transistor. When the transistor TR1 is turned on, the operating power supply potential Vcc
The level drive signal / SAP is transmitted to the sense amplifier DSA. When the transistor TR2 is turned on, D
Signal SAN of potential Vss level is transmitted to the other node of the RAM sense amplifier.

Signal from sense amplifier activation circuit SAK /
Equalizing transistor TEQ for equalizing the potentials of both signal lines in response to equalize instruction signal φEQ is provided between signal lines / SAP and SAN to which SAP and SAN are transmitted. As a result, the sense amplifier drive signal lines / SAP and SAN are set to (Vcc
It is precharged to an intermediate potential of + Vss) / 2. Here, the signal line and the signal on it are indicated by the same reference numeral.

For each DRAM bit line pair DBL,
A precharge / equalize circuit PE is provided which is activated in response to precharge / equalize instructing signal φEQ and precharges and equalizes each bit line of the corresponding bit line pair to a predetermined precharge potential VBL.

DRAM memory block MBij is further provided for each DRAM bit line pair DBL and turned on in response to the signal potential on column select line CSL, and the corresponding DRAM bit line pair DBL is set to local I.
It includes a column select gate CSG connected to the O line pair LIO. The column selection line CSL is provided in common for two pairs of DRAM bit lines, whereby two DRAM bit line pairs DBL are simultaneously selected.

MBij further has a block activation signal φ.
Local IO line pair LIOa and LIO in response to BA
b are global IO line pairs GIOa and GIO, respectively
Includes IO gates IOGa and IOGb connected to b. The column selection line CSL extends in the row direction over one column block shown in FIG. 3, and also has a global IO line pair GIO.
a and GIOb extend in the row direction over one column block. Local IO line pair LIOa and LIO
b extends in the column direction only within one memory block.

Corresponding to FIG. 3, DRAM IO line pairs 16a and 16b are local IO line pairs LI, respectively.
Oa and LIOb and LIO gates IOGa and I
OGb and global IO line pair GIOa and GIOb
Corresponding to.

Clamping means is provided for the DRAMIO line pair. This clamp means is a global IO line pair GI
Clamp circuit CRDa and global I provided in Oa
It includes a clamp circuit CRDb provided in O line pair GIOb. This clamp circuit may be provided for each of the local IO line pairs LIOa and LIOb as shown by the broken line in the figure. The structure provided in both may be sufficient. The clamp circuits CRDa, CRDb (and / or CRDa 'and CRDb') have the same structure as the clamp transistors SQ7 and SQ8 shown in FIG. 23 and clamp the potential of the corresponding signal line to a predetermined potential.

The SRAM array has one row of SRs each.
SRAM word line SWL to which AM cell SMC is connected
, An SRAM bit line pair SBL to which one row of SRAM cells SMC are connected, and an SRAM bit line pair SB
Each L includes an SRAM sense amplifier SSA for detecting and amplifying the potential difference between the corresponding bit line pair. SR
A clamp circuit CRS for clamping the potential of the corresponding bit line is provided for the AM bit line pair SBL. The clamp circuit CRS has a configuration similar to that shown in FIG.

Bidirectional transfer gate circuit 3 includes SRAM bit line pair SBL and global IO line pair GIOa and GI.
It includes bidirectional transfer gates BTGa and BTGb provided between it and Ob. Bidirectional transfer gates BTGa and B
Both TGb are data transfer instruction signals DTS and DTA.
In response to the SRAM bit line pair SBL and global IO
Data transfer between line pair GIOa and GIOb is performed. The data transfer instruction signal DTS is from DRAM to SRA.
Data transfer instruction signal DTA for instructing data transfer to M
Indicates data transfer from SRAM to DRAM.

ON / OFF of clamp circuit CRS is controlled by an inverted signal / DTS of data transfer instruction signal DTS.

The clamp circuits CRDa and CRDb provided for the DRAM are on / off controlled by an inverted signal / DTA of the data transfer instruction signal DTA.

At the time of data transfer from the DRAM to the SRAM, the transfer instruction signal DTS becomes the active state of "H", and S
The clamp circuit CRS provided in the RAM array becomes inactive and the clamp operation is prohibited. On the other hand, S
At the time of data transfer from the RAM to the DRAM, the transfer instruction signal DTA becomes the active state of "H", and the clamp circuit CRD
a and CRDb (and / or CRDa ′ and C
RDb ') becomes inactive.

FIG. 1 is a diagram showing a structure of a portion related to one data transfer gate in the structure shown in FIG. In FIG. 1, the local IO line pair LIO and the global IO line pair GIO are collectively shown as a DRAM IO line pair DIO. The local IO line pair is provided only for one memory block, and the global IO line pair GIO is commonly provided for the memory blocks in the column block. Therefore, the clamp circuit CRD is preferably provided in at least the global IO line pair GIO. 5, block select gates IOGa and IOGb are provided, but in FIG. 1, local IO line pairs LIO and global IO line pairs GIO are collectively DRAMIO.
Since it is shown as a line pair DIO, correspondingly, the block selection gate IOG and the column selection gate CSG are shown as one selection gate SG.

Since only the DRAMIO line pair DIO connected to one bidirectional transfer gate BTG is shown,
The column selection signal CSL transmitted on the column selection line CSL is shown in FIG.
In, only one select gate SG is selected.

The DRAM bit line pair DBL is a bit line DB.
SRAM bit line pair SB including La and * DBLa
L includes bit lines SBLa and * SBLa. DRA
M bit line pair DBLa, * DBLa is a bit line pair DB
This includes La0, * DBLa0 to DBLan, * DBlan. The SRAM array also includes the SRAM word line SWL0.
-SWLn, the DRAM array includes DRAM word lines DWL0-DWLp.

The SRAM clamp circuit CRS is an SRAM
It includes an n-channel MOS transistor SQ70 provided on bit line SBLa and an n-channel MOS transistor SQ80 provided on SRAM bit line * SBLa.
Inversion signal / DTS of transfer instruction signal DTS is applied to the gates of transistors SQ70 and SQ80.

The DRAM clamp circuit CRD is a DRAM
It includes an n-channel MOS transistor DQ80 connected to IO line * DIOa and an n-channel MOS transistor DQ70 connected to DRAM IO line DIOa. Inversion signal / DTA of transfer instruction signal DTA is applied to the gates of transistors DQ70 and DQ80.

Various configurations can be considered as the configuration of the bidirectional transfer gate BTG. In the following description of the operation, first consider a bidirectional transfer gate having the configuration shown in FIG.

In FIG. 6, bidirectional transfer gate BTG transfers data on SRAM bit line SBLa (* SBLa) to DRAMIO line D in response to data transfer instruction signal DTA.
Transfer circuit TGA transmitting to IOa (* DIOa) and DRAM IO line DI in response to data transfer instruction signal DTS
Data on Oa (* DIOa) is transferred to SRAM bit line SB
It includes a transfer circuit TGS for transmitting to La (* SBLa).
In the structure shown in FIG. 6, a transfer circuit between one SRAM bit line and one DRAM IO line is shown.

Next, the operation will be described. First, referring to the operation waveform diagram shown in FIG. 7, from the DRAM array to the SRAM.
The operation of data transfer to the array will be described. This D
Data transfer from the RAM array to the SRAM array is executed at the time of cache miss (when the signal CI is active at "H").

Before time t1, precharge instructing signal φEQ is in the active state of "H", and sense amplifier drive signal lines SAN and / SAP are equalized to the precharge potential of Vcc / 2 by equalizing transistor TEQ. The DRAM bit line pair DBL (bit lines DBLa, * DBLa) is precharged / equalized to an intermediate potential of Vcc / 2 by the precharge / equalize circuit PE.

DRAMIO lines DIOa and * DIOa
Is precharged to the "H" level of the potential Vcc-Vth by the clamp circuit CRD. The SRAM bit lines SBLa and * SBLa are similarly clamped by the clamp circuit C.
Precharged to a potential level of Vcc-Vth by RS.

At time t1, precharge instruction signal φ
When EQ falls, precharge / equalize circuit PE and equalize transistor TEQ are inactivated. As a result, the equalizing operation of the sense amplifier drive signal lines SAN and / SAP is completed, the equalizing / precharging operation of the DRAM bit line pair DBL is stopped, and the DRAM bit lines DBLa, * DBLa and the sense amplifier drive signal line SAN and / SAP is the intermediate potential V
It becomes a floating state at cc / 2.

Then, row decoder 14 (see FIG. 3) performs a row selecting operation in accordance with an externally applied address. Shortly after time t1, one word line DWL is selected by the DRAM array 1, and the potential of this word line DWL rises to "H". One row of DRAM memory cells DMC connected to the selected word line DWL (any one of DWL0 to DWLp) corresponds to a corresponding DRAM bit line pair DBL (DBLa or * DBL).
connected to a), the potential of each DRAM bit line pair DBL changes according to the data of the connected memory cell.

In FIG. 7, the DRAM bit line DB when the memory cell storing "H" data is selected.
The potential change of La (or * DBLa) is shown.

At time t2, sense amplifier activation signal SANE rises from ground potential Vss to operating power supply potential Vcc level, and transistor TR2 included in sense amplifier activation circuit SAK is turned on. As a result, sense amplifier drive signal SAN rises from the intermediate potential Vcc / 2 to the ground potential Vss level, and the N sense amplifier portion included in DRAM sense amplifier DS is activated. As a result, the potential of the bit line on the low potential side of the DRAM bit line pair DBL is discharged to the ground potential Vss level.

At time t3, sense amplifier activation signal / SAPE falls from the potential Vcc to the ground potential Vss level, and transistor TR1 included in sense amplifier activation circuit SAK is turned on. In response to this,
The intermediate potential sense amplifier drive signal / SAP is the intermediate potential V
cc / 2 rises to the power supply potential Vcc level, and DRA
The P sense amplifier portion of the M sense amplifier DSA is activated, and the potential of the high potential bit line of the DRAM bit line pair DBL is boosted to the potential Vcc level.

At time t4, column select signal CSLi is generated in accordance with the column select operation by DRAM column decoder 15 (see FIG. 3). As a result, the selection gate SG
i becomes conductive, and the corresponding DRAM bit line pair DBL
i (DBLai, * DBLai) is the DRAMIO line pair D
It is connected to IO (DIOa, * DIOa). DRAM
The driving capability of the sense amplifier DSA is the clamp circuit CR.
It is sufficiently larger than the current supply capacity of D. This gives D
The potential of the RAMIO line pair DIO becomes a potential level according to "H" and "L" amplified by the sense amplifier DSA.

In this case, since current is supplied from clamp circuit CRD, the "L" level of DRAM IO line DIO is slightly higher than the ground potential level due to the pull-up function of clamp circuit CRD. This level is used for clamping transistors DQ70 and DQ80 and select gate S
Gi transistor Determined by the current driving capability of the discharging transistor (n-channel MOS transistor; see FIG. 23) included in the DRAM sense amplifier DSA. The resistance value of the select gate SGi is high, and the DRAMIO line DIO
Of the clamp transistor DQ70 (DQ
80) and the on resistance of the transistor in the select gate SGi. The sense amplifier DSA causes the DRAM bit line to have a logical amplitude of approximately Vcc.

DRAMIO line DIOa (or / DIO
The capacity of a) is DRAM bit line DBLa (or * DB
It is sufficiently larger than the capacity of La). Therefore, when the column selection signal CSLi rises, the DRAM bit line DBL
The "L" level of a (or * DBLa) rises a little, but the DRAM sense amplifier D that drives this small capacity
It is possible to immediately discharge to the ground potential Vss level by SA. It can be considered that this is the same as the data reading when the internal data line (I / O line) is precharged to the "H" level in the normal DRAM. Therefore, even if the clamp transistors DQ70 and DQ80 are in the ON state, the clamp transistor DQ70
The current from Q70 and DQ80 does not destroy the memory cell data of the DRAM.

On the other hand, in the SRAM array, time t
In s1, the row selection operation by the SRAM row decoder 21 (see FIG. 3) is performed, and one SRAM word line S
WL (one of SWL0 to SWLm) is selected, and the potential of the selected SRAM word line SWL rises to “H”. Row selection operation in DRAM and SR
The row selection operation in AM is performed asynchronously. S
The data of the SRAM cells connected to the RAM word line SWL are transmitted onto the corresponding SRAM bit line pair SBL. As a result, the SRAM bit lines SBLa, * S
The potential of BLa changes from the clamp potential Vcc-Vth to the potential corresponding to the stored information of the corresponding SRAM cell.

At time t5, the DRAM array outputs SR
Data transfer instruction signal DTS for instructing data transfer to the AM array rises to "H". Before this time t5, the data of the DRAM cell has already been transmitted to the DRAM IO lines DIOa and * DIOa. Also SRA
An SRAM cell is already connected to the M bit line pair SBL. In response to the data transfer instruction signal DTS, the transfer circuit TGS shown in FIG. 6 is activated to activate the DRAM IO line DI.
The data of Oa (and * DIOa) is transmitted to the SRAM bit line SBLa (and * SBLa).

At this time, the clamp transistors SQ70 and SQ80 included in the SRAM clamp circuit CRS.
Is turned off. Therefore, this SRAM bit line S
"H" and "L" levels of BLa and * SBLa become potential levels given by the transfer circuit TGS.

At time t5 when the data transfer instruction signal DTS is activated, the column selection signal CSLi is generated and DRA is generated.
Time ts1 when the potential of the data on the MIO line DIO is determined and when the SRAM word line SWL is selected
As long as the relationship that is later than both of the above is satisfied, the front-rear relationship between time ts1 and time t1 to time t5 is arbitrary. Signal DTA instructing data transfer from SRAM to DRAM is maintained in the inactive state of "L" in this cycle.

At time t6, the potential of the selected DRAM word line DWL falls and transfer instruction signal DT
S also falls to "L". As a result, the clamp circuit CRS of the SRAM bit line pair SBL is activated again, and this S
The "L" level of the potentials of the RAM bit lines SBLa and * SBLa rises.

At time t7, sense amplifier drive signals SAN and / SAP are both returned to the intermediate potential Vcc / 2, and the latch operation by sense amplifier DSA is stopped, whereby the DR provided in DRAMIO line DIO is stopped.
The function of the AM clamp circuit CRD causes the DRAM IO line D
IOa and * DIOa are both “H” of Vcc-Vth
Return to the level. After this, the column selection signal CSLi falls to "L", and the DRAM bit line pair and the DRAMIO
Separation from line pairs is performed.

In the SRAM, the SRAM word line SW
The potential of L falls to “L” at time ts2, and DR
The data transfer cycle from AM to SRAM is completed.

If the logical amplitude of the signal line is reduced by using the clamp circuits CRD and CRS, the SRAM bit line SB
La, * SBLa and DRAM IO lines DIOa, * D
The potential of IOa is set to a definite state at high speed, which allows data to be transferred at high speed.

At this time, the clamp circuits CRS and CR
When the clamp operation of D is maintained even during data transfer, the transistor SQ7 for clamping the SRAM bit line is used.
Current flows from 0 (or SQ80) to the ground line via the drive transistor of the transfer circuit TGS, and the current consumption increases. It is considered that this shoot-through current will not be so large if only data is transferred in 1-bit units. However, when multiple bits of data such as 16 bits are collectively transferred as one block, The through current becomes large, and low current consumption is impaired.

Therefore, as described above, the shoot-through current can be reduced by prohibiting the clamp operation of SRAM clamp circuit CRS provided for the SRAM bit line receiving the data transfer during the data transfer.

In the DRAM on the data transfer side, the clamp circuit CRD is operating. This clamp circuit only performs a normal pull-up function operation. The current supply capability of the clamp transistors DQ70 and DQ80 is small, and the current drive capability of the sense amplifier DSA is related DR.
Only the ability to drive AM bit lines is required. The on resistance of the select gate SGi is relatively large. Therefore, the current from the clamp circuit CRD is not so large and has a small value.

Since the current driving capability of bidirectional transfer gate BTG is sufficiently large, the current driving capability is sufficiently larger than the discharging capability (or latching capability) of the transistor included in SRAM memory cell SMC. Therefore, when the bidirectional transfer gate BTG operates, the clamp transistor SQ7
A relatively large current flows from 0 or SQ80 through the drive transistor of the bidirectional transfer gate BTG, and this current becomes larger when a plurality of bits of data are transferred in the block size. This relatively large current is saved by deactivating the clamp circuit CRS.

In the SRAM data transfer from the DRAM described above, the SRAM is synchronized with the transfer instruction signal DTS.
The clamp operation of the clamp circuit CRS provided in the bit line pair SBL is prohibited. However, this is SR
The potential of the AM word line SWL rises to "H" and SRA
A column current (a through current flowing between the SRAM memory cell SMC and the clamping transistors (SQ70 and SQ80)) flows while the M bit line pair SBL is being clamped. In order to further reduce the column current, the clamp operation of the SRAM clamp circuit CRS is prohibited in synchronization with the selection operation of the SRAM word line SWL. This configuration is from DRAM to SRAM
At the time of instructing the data transfer to, the AND signal of this data transfer instruction signal (this is the operation at the time of cache miss and can be known before the SRAM word line selection operation) and the SRAM word line drive signal SWL is applied to the transistor SQ7.
It is realized by the configuration given to the gates of 0 and SQ80.

Next, the data transfer operation from SRAM to DRAM will be described with reference to the operation waveform diagram of FIG.

In the DRAM, from time t1 to time t
Up to 4, the DRAM to SR previously described with reference to FIG.
The same operation as the data transfer operation to AM is executed. S
In the RAM as well, the SRAM word line SWL is selected at time ts1 and its potential rises to "H".

Transfer instruction signal DTA for permitting data transfer from SRAM to DRAM after times t4 and ts1.
Is activated for a certain period from time t5. The transfer circuit TGA shown in FIG. 6 is activated in response to the transfer instruction signal DTA, and the SRAM bit line SBLa (and * SB) has already been activated.
The signal potential appearing on La) is the DRAMIO line DI.
Transmitted on Oa (and * DIOa). At this time,
The potential levels of DRAMIO lines DIOa and * DIOa are set to Vcc level "H" and ground potential Vss level "L" level due to the large driving force of transfer circuit TGA. These DRAM IO lines DIOa and * DIOa
The upper signal potential is D selected via the selection gate SGi.
It is transmitted onto RAM bit lines DBLa and * DBLa. Since the drive capability of the transfer circuit TGA is sufficiently larger than the latch capability of the DRAM sense amplifier DSA, this DRA
The potentials of the M bit lines DBLa and * DBLa are SRAM
The value corresponds to the data transmitted from.

In response to the data transfer permission signal DTA at time t5, the clamp operation of the DRAM clamp circuit CRD is prohibited. That is, the transistors DQ70 and DQ80 are in the off state. As a result, the clamping transistors DQ70 and DQ
No current flows from Q80, there is no through current flowing into the drive transistor of the transfer circuit TGA, and the current consumption is reduced.

When transfer instruction signal DTA rises to "L" at time t6, DRAM word line DWL also rises to "L" at almost the same timing. Writing of data to the selected memory cell is completed by the fall of the potential of the DRAM word line DWL. On the other hand, the clamp circuit CRD is activated again, and its clamp operation causes the DRAMIO
Of the potentials on lines DIOa and * DIOa, the low-level potential rises. On the other hand, the potential levels of the DRAM bit lines DBLa and * DBLa may be slightly raised because the sense amplifier DSA is in the active state, but still retain the "H" and "L" levels.

At time t7, the sense amplifier drive signal S
When AN and / SAP become inactive and the column selection signal CSLi rises to "L", the DRAM
Returns to the precharged state. In SRAM, at time ts2, SRAM word line SWL rises to "L", the memory cell is disconnected from the bit line, and the potentials of bit line potentials SBLa and * SBLa are "H" defined by clamp transistors SQ70 and SQ80. It becomes a level.

As described above, when the clamp operation of the clamp circuit CRD of the DRAM is prohibited during the data transfer from the SRAM to the DRAM, the discharge current (penetration current) flowing through the drive transistor of the transfer circuit TGA having a large drive capability is obtained. Generation can be prevented, and low current consumption can be realized.

FIG. 9 shows a CDR which is another embodiment of the present invention.
It is a figure which shows the structure of AM. In FIG. 9, the SRAM bit line clamp circuit CRS receives a data transfer enable signal DTS at its gate and is a p-channel MOS transistor S.
Includes Q71 and SQ81. The DRAM IO line clamp circuit CRD has a gate to which a data transfer enable signal DTA is sent.
P-channel MOS transistor DQ7 which receives at its gate
1 and DQ81. Transistor SQ71 is SR
The transistor SQ8 provided on the AM bit line SBLa
1 is provided on the SRAM bit line * SBLa. The transistor DQ71 is provided in the DRAMIO line DIOa,
Transistor DQ81 is provided on DRAMIO line DIOa. Even if a p-channel MOS transistor is used as the clamp transistor as shown in FIG. 9, the same effect as that of the configuration shown in FIG. 1 can be obtained.

Here, the operating power supply potential of clamp circuit CRD provided on the DRAMIO line may be power supply potential Vcc or intermediate potential Vcc / 2 or (Vcc / 2) + Vth. DRA provided in the selected DRAM bit line pair DBL at any of these levels
The M sense amplifier DSA amplifies the potential of the DRAM IO line DIO to the potential corresponding to the data of the selected DRAM cell. Even in this case, since the clamp function is exerted, the "L" level is the ground potential Vs.
It is higher than s, and high-speed operability is guaranteed. Further, current consumption is further reduced (in the case of Vcc / 2 precharge).

FIG. 10 is a diagram showing another configuration example of the bidirectional transfer gate. In the structure of the bidirectional transfer gate shown in FIG. 6, the data transfer direction is always one direction from DRAM to SRAM or SRAM to DRAM. Therefore, for example, the selected memory cell D of the SRAM array is
Two data transfer operations are required when exchanging data between a RAM array and a corresponding memory cell. In the case of the configuration shown in FIG. 10, SRAM to DRAM
Data can be transferred from the DRAM to the SRAM in parallel with the data transfer to.

In FIG. 10, the bidirectional transfer gate BTG is shown.
Becomes the active state in response to the data transfer enable signal DTA0, and the SRAM bit line SBLa (or * SBLa)
The drive circuit TGA0 for transmitting the above signal data, the buffer BU2 for buffering the output of the drive circuit TGA0, and the buffer BU2 which is activated in response to the data transfer enable signal DTA1 and outputs the output of the buffer BU2 to the DRAMIO line DIO
A drive circuit TGA1 for transmitting on the a is included. The data transfer permission signals DTA0 and DTA1 are generated at different timings.

Transfer gate BTG is further activated in response to data transfer enable signal DTS0, and DRAMI
A drive circuit TGS0 that transmits a signal on the O line DIOa (or * DIOa), a buffer BU1 that buffers the output of the drive circuit TGS0, and an output of the buffer BU1 that is activated in response to the data transfer enable signal DTS1. SRAM bit line SBLa (or * SBLa)
It includes a drive circuit TGS1 for transmitting upward. The transfer permission signal DTA0 and the transfer permission signal DTS0 are generated at substantially the same timing, and the transfer permission signal DTA1 and the transfer permission signal DTS1 are generated at substantially the same timing (D
D from RAM to SRAM and SRAM to DRAM
When RAM transfer is performed together).

Bidirectional transfer gate BTG shown in FIG.
In the case of the above structure, transfer control signals DTA0 and DTS0 are first generated. The selection operation in the SRAM array and the DRAM up to that point is similar to that shown in FIGS. Transfer enable signals DTS0 and DTA0
Is generated, the selected memory cell data of the SRAM is transmitted to the buffer BU2 and buffered. On the other hand, the selected memory cell data of the DRAM is stored in the buffer B.
It is given to U1 and buffered. This buffer B
After the outputs of U1 and BU2 are determined, the data transfer permission signals DTA1 and DTS1 are activated. As a result, the output data of the buffer BU1 is changed to the drive circuit TG.
SRAM bit line SBLa (or * SB) via S1
La).

On the other hand, the output data of the buffer BU2 is transferred to the DRAM bit line via the drive circuit TGA1 to the DRAMI.
It is transmitted through the O line DIOa (or * DIOa). Regarding transfer permission signals DTA0, DTA1, DTS1 and DTS0, each of transfer instruction signals DTA and DTS in FIGS. 7 and 8 may be regarded as two pulse signals. With this configuration, data transfer from DRAM to SRAM and data transfer from SRAM to DRAM can be performed in parallel, and efficient data transfer can be performed.

Transfer enable signals DTA0, DTA1, DTS
1, DTS1 shipping timing is from DRAM to SRAM
The data transfer from the SRAM to the DRAM may be determined to partially overlap. SRAM bit line SBLa (* SBLa) for faster data transfer operation
Is provided with a clamp transistor SQ75, while D
A clamp transistor DQ85 is provided on the RAMIO line DIOa (or * DIOa). The transistor SQ75 constitutes the SRAM clamp circuit CRS, and the transistor DQ85 is the DRAM IO line clamp circuit CRD.
Make up. In this case, when receiving data transfer, in order to prevent the current from flowing from the clamp transistor SQ75 to the drive transistor of the drive circuit TGS1, the clamp circuit CRS is prohibited from its clamp operation by the inverted signal of the transfer permission signal DTS1. .. That is, signal / DTS1 is applied to the gate of transistor SQ75. On the other hand, similarly, the clamp operation of the clamp circuit CRD of the DRAMIO line is prohibited by the inverted signal / DTA1 of the enable signal DTA1. That is, signal / DTA1 is applied to the gate of transistor DQ85.

With this structure, data transfer can be efficiently performed with low current consumption. Other configurations and operations are similar to those shown in FIGS. 1 to 9 above.

In the case of the bidirectional transfer gate shown in FIG. 10, 1
The data transfer cycle can only exchange data with selected memory cells in the SRAM array and selected memory cells in the DRAM array. At the time of cache miss, write the memory cell data of cache miss to the corresponding data memory cell of DRAM,
In addition, D requested by the external computing device (external CPU) for access
It is necessary to write the data of the memory cell of the RAM to the corresponding SRAM cell. In this case, a so-called copy back operation is executed.

Normally, at this time, the DRAM memory cell for storing the cache miss memory cell data of the SRAM and the D for storing the data accessed by the external CPU.
It is different from a RAM cell. At this time, it is necessary to access the DRAM twice and select the memory cell. In order to perform this operation at high speed, there is an operation mode called "first copy back". The data transfer mode of this first copy back is DR in one cycle.
This is a data transfer mode in which the AM data is stored in the SRAM and the data is read from the SRAM. A bidirectional transfer gate that realizes the first copy back mode will be described.

FIG. 11 is a diagram showing still another structure of the bidirectional transfer gate BTG. FIG. 11A is a block diagram showing the configuration of a bidirectional transfer gate that realizes this first copy back operation, and FIG. 11B shows its detailed circuit configuration.

In FIG. 11A, a bidirectional transfer gate BTG is responsive to a transfer control signal DTL and a gate circuit 1810 for connecting SRAM bit lines SBLa, * SBLa to a latch circuit 1811 and a transfer control signal DTA. The latched data of the latch circuit 1811 to DRAMIO
Gate circuit 18 transmitting to lines DIOa and * DIOa
12, an amplifier circuit 1814 that amplifies the signal potential on the DRAM IO lines DIOa and * DIOa in response to the transfer control signal DTS, and the data amplified by the amplifier circuit 1814 in response to the transfer control signal DTS to the SRAM bit line SB.
A gate circuit 1815 for transmitting to La and * SBLa is included.

The gate circuit 1812 uses the transfer control signal DT.
When activated in response to A, the data (latched in the latch circuit 1811) from the SRAM array is transferred to the DRAM.
It is used for timing adjustment when collectively transferring data to the array in units of blocks of multiple bits. Similarly, the gate circuit 1815 is connected to the S from the DRAM array.
It is used for timing adjustment when collectively transferring data to the RAM array in units of blocks of a plurality of bits.

In FIG. 11B, the gate circuit 181
0 is an n-channel MOS transistor T10 that amplifies the signal potential on the SRAM bit lines SBLa and * SBLa.
2, T103, and an n-channel M that becomes conductive in response to the transfer control signal DTL and transmits the data amplified by the transistors T102 and T103 to the latch circuit 1811.
It includes OS transistors T100 and T101. The gate of the transistor T102 is the SRAM bit line SBLa.
, And one conduction terminal thereof is connected to the ground potential Vss, and the other conduction terminal thereof is connected to one conduction terminal of the transistor T100. Transistor T103 has its gate connected to SRAM bit line * SBLa, one conduction terminal thereof connected to ground potential Vss, and the other conduction terminal thereof connected to one conduction terminal of transistor T101.

The latch circuit 1811 has inverter circuits HA10 and HA1 whose inputs are connected to the outputs of the other.
Including 1. Inverter circuits HA11 and HA10 form an inverter latch. Latch circuit 1811 further includes inverter circuits HA12 and HA13 that invert the latch data of an inverter latch (composed of inverter circuits HA10 and HA11).

The gate circuit 1812 is used for the DRAM IO line D.
Gate circuit 1812b for transmitting data to IOa
And a gate circuit 1812a for transmitting data to DRAMIO line * DIOa. Gate circuit 1812a
Is composed of an n-channel MOS transistor T105, and the gate circuit 1812b is composed of an n-channel MOS transistor T106. Transfer control signal DTA is applied to the gates of transistors T105 and T106.

The amplifier circuit 1814 uses the DRAM IO line *.
An n-channel MOS transistor T113 for amplifying the potential on DIOa, an n-channel MOS transistor T112 which is turned on in response to the transfer control signal DTS, and which transfers the data amplified by the transistor T113 to the node N100, and a transfer control. N channel MOS transistor T111 for precharging node N110 to power supply potential Vcc in response to signal DTS, and power supply potential Vcc
And a node N100, a p-channel MOS transistor T110 connected in parallel with transistor T111 is included.

The amplifier circuit 1814 also includes the DRAMI
The n-channel MOS transistor T117 for amplifying the signal potential on the O line DIOa and the ON state in response to the transfer control signal DTS, the signal potential on the DRAM IO line DIOa amplified by the transistor T117 is transferred to the node N.
N-channel MOS transistor T11 transmitting to 110
6, a p-channel MOS transistor T114 for precharging the node N110 to the power supply potential Vcc in response to the transfer control signal DTS, the power supply potential Vcc and the node N11.
P connected in parallel with the transistor T114 between 0 and
It includes a channel MOS transistor T115.

Transistor T110 has its gate connected to node N110, and transistor T115 has its gate connected to node N100. Transistor T1
10 and the transistor T115 form a differential amplifier circuit.

Gate circuit 1815 is a gate circuit 1815 for transferring data to SRAM bit line SBLa.
a and a gate circuit 1815b for transferring data to the SRAM bit line * SBLa. Gate circuit 181
5a is turned on in response to the transfer control signal DTA,
The signal potential on the node N100 is applied to the SRAM bit line SBL
It includes an n-channel MOS transistor T120 transmitting to a. The gate circuit 1815b is turned on in response to the transfer control signal DTS, and transmits the signal potential on the node N110 to the SRAM bit line * SBLa n channel M.
It includes an OS transistor T121. Next, the operation of this bidirectional transfer gate will be described.

The bidirectional transfer gate shown in FIG. 11 includes two operation cycles. In the first operation cycle, the SRAM
Latch circuit 1 for data of a selected memory cell in the array
The operation of latching at 811 and simultaneously writing the selected memory cell data of the DRAM array to the selected memory cell of the SRAM array is performed. In the second cycle, the data latched by latch circuit 1811 is transmitted to another selected memory cell in the DRAM array. First, the first operation cycle will be described with reference to FIG.

Before time t1, the DRAM completes the precharge cycle and enters the memory cycle. DRA
In M, DRA according to the given internal row address
M word line DWL is selected.

At time t1, DRAM word line DW
L becomes the selected state and its potential rises to "H". When the signal potential on DRAM bit line pair DBL changes in response to this, sense amplifier drive signals SAN and / SAP are activated at times t2 and t3, respectively, and D
The signal potential on the RAM bit line pair becomes a potential level corresponding to the data of the read memory cell.

In the SRAM, the SRAM word line SWL is selected at time ts1, and the data of the memory cell connected to this selected word line SWL corresponds to the corresponding SRA.
It is transmitted to the M bit line pair SBL. When the signal potential on SRAM bit line pair SBL is determined, transfer control signal DTL rises to "H" at time ts2, and gate circuit 1
810 is activated, and the signal potential on the SRAM bit line pair SBL is transmitted to the latch circuit 1811.

That is, in the circuit structure shown in FIG. 11B, the transistor T10 responds to the transfer control signal DTL.
0 and T101 are turned on and the transistor T1
02 and T103 are turned on and the other is turned off, the transistor (T10
2 or T103), the potential of "L" is transmitted to the latch circuit 1811. The latch circuit 1811 latches the supplied “L” signal potential to the corresponding node.

In the DRAM, this latch circuit 181
The DRAM bit line pair DBL is selected in parallel with the data latch operation by 1, and the column selection signal CSLi rises to "H" at time t4. As a result, the signal potential on the selected DRAM bit line pair DBL is
It is transmitted onto the line pair DIO.

At time t5, DRAMIO line pair DI
When the signal potential on O is determined, the transfer control signal DTS rises to "H". As a result, amplifier circuit 1814 is activated to amplify the signal potential on DRAMIO line pair DIO and transmit it to gate circuit 1815. Gate circuit 1815
Is activated in response to the transfer control signal DTS, and transmits the data amplified by the amplifier circuit 1814 onto the SRAM bit line pair SBL.

That is, in FIG. 11B, the transistors T111 and T111 are responsive to the transfer control signal DTS.
114 is turned off and nodes N100 and N11
Stop precharge to 0. On the other hand, the transistor T1
10 and T115 are transistors T112 and T1.
The signal potentials on DRAMIO lines DIOa and * DIOa transmitted via 16 are differentially amplified. As a result, the signal potentials of the nodes N100 and N110 become DRA.
It becomes a potential obtained by inverting the signal potential on the MIO lines * DIOa and DIOa.

Consider, for example, the case where the signal potential on DRAMIO line DIOa is "H" and the signal potential on DRAMIO line * DIOa is "L". At this time, the transistor T117 is turned on, the transistor T113 is turned off, the potential of the node N110 becomes “L”, and the potential of the node N100 becomes “H”. This node N110
Potential of "L" turns on the transistor T110, and potential of "H" at the node N100 changes to the transistor T1.
15 is turned off. Transistors T110 and T
The signal potentials of nodes N100 and N110 are differentially amplified and latched by 115.

In parallel with the amplification operation in the amplifier circuit 1814, the transistors T120 and T121 of the gate circuits 1815a and 1815b are turned on,
The signal potential on the node N100 is the SRAM bit line SBL
The signal potential on node N110 is transmitted onto SRAM bit line * SBLa. At this time, since the transfer control signal DTA is fixed at "L", the gate circuit 18
12a and 1812b are in the closed state, and the latch circuit 1
The data latched at 811 is the DRAM IO line DIOa.
And * DIOa are not transmitted.

At time t6, DRAM word line DWL
Rises to "L" and the transfer control signal DTS falls to "L" at almost the same timing. This makes SR
Clamp circuit C provided in the AM bit line pair SBL
RS is activated, and the "L" level of the potential of the SRAM bit line pair SBL rises above the level of the ground potential Vss by the clamp circuit CRS.

At time t7, the DRAM completes its memory cycle and enters the precharge period. In SRAM, the potential of SRAM word line SWL falls to "L" at time ts4, and one cycle is completed.

At time t5, transfer control signal DTS
Rises to "H", the SRAM bit line SB
The clamp transistors SQ70 and SQ80 provided in La and * SBLa are turned off. In the structure shown in FIG. 11B, the transistor T120,
Path of T112 and T113 or transistor T1
Through current does not flow from clamp transistor SQ70 or SQ80 through the paths 21 and T116 and T117, and the current consumption is reduced. When the transfer control signal DTS falls to "L" at time t6, the transistor T
Since 120 and T121 are turned off, even if the clamp circuit CRS is activated again, the path of the through current flowing from the SRAM bit line clamping transistors SQ70 and SQ80 into the bidirectional transfer gate BTG is cut off.

At and after time t6 when transfer control signal DTS falls to "L", the DRAM array and SRA
Separated from the M array, the SRAM array can be accessed, and the data transferred from the DRAM array can be read at high speed.

By providing the latch circuit 181 as described above, in the case of a cache miss, the data requested by the external processing device (eg, CPU) to access is DRAed.
The data can be transferred from M to the SRAM and read at high speed, and the access time at the time of a cache miss can be shortened.

Then, the second cycle in which the data transmitted from the SRAM array to latch circuit 1811 is transmitted to the DRAM is executed. The operation of the second operation cycle will be described with reference to the operation waveform charts of FIGS. 1, 11, and 13.

In the DRAM, the operation similar to that shown in FIG. 12 is performed until time t5, and the data on DRAM bit line pair DBL is transmitted to DRAM IO line pair DIO.

At time t5, transfer control signal DTA rises to "H". In this transfer cycle, transfer control signals DTS and DTL are both "L". In response to the transfer control signal DTA, the gate circuit 1812 shown in FIG. 11A becomes conductive. That is, FIG.
In (B), the transistors T105 and T106 are turned on, and the data latched by the latch circuit 1811 is transmitted onto the DRAMIO line pair DIO. At this time, the clamp circuit CRD provided in the DRAMIO line pair DIO is inactivated, and its clamp operation is prohibited. As a result, the DRAMIO line pair DI
The signal potentials of O and above become "H" and "L" levels corresponding to the data latched by the latch circuit 1811.

At this time, since the transfer control signal DTA is "H", the clamp transistors DQ70 and DQ80 shown in FIG. 1 are off. This allows the DRAM
IO line DIOa, transistor T106 and inverter circuit HA13 (see FIG. 11B) or DRAMI
The path through which the clamp current (through current) flows via the O line * DIOa, the transistor T105, and the inverter circuit HA12 (see FIG. 11B) is cut off, and the current consumption is reduced.

The data from the latch circuit 1811 transferred onto the DRAMIO line pair DIO is the column selection signal CSL.
It is transmitted to the DRAM bit line pair DBL selected by i, and the potential of the DRAM bit line pair DBL is latched by the latch circuit 18.
It has a value corresponding to the signal potential transmitted from 11 through the DRAMIO line pair DIO.

At time t6, DRAM word line DWL
Potential falls, and the transfer control signal DTA also falls to "L" at almost the same timing. This allows DRAMIO
The clamp circuit CRD provided for the line pair DIO is activated again, and the potential level of "L" of the DRAMIO line pair DIO rises.

At time t7, the memory cycle of the DRAM is completed, the column selection signal CSLi subsequently falls to "L", and the potential level of the DRAM IO line pair DIO becomes "H" level determined by the clamp circuit CRD.

In this transfer cycle, transfer control signals DTS and DTL are both at "L". Therefore, the DRAM array and the SRAM array are separated. Addresses can be set in the DRAM and SRAM independently of each other. Therefore, this latch circuit 18
When transferring data from 11 to the DRAM array,
In the SRAM, the SRAM cell can be accessed and data writing / reading can be executed independently of this transfer operation. That is, in SRAM, word line SWL is selected at time ts1 in accordance with external access, and the potential of SRAM bit line pair SBL changes from the potential level clamped by clamp circuit CRS according to the selected memory cell data. Then, access to the selected memory cell and data reading are executed.

At time ts4, SRAM word line SW
The potential of L falls to "L", and the SRAM bit line pair SB
The potential level of L returns to the potential level determined by the clamp circuit CRS.

As described above, the latch circuits 1811 to D
DRAMIO line pair DI during data transfer to RAM array
By prohibiting the clamp operation of the clamp circuit CRD provided in O, the clamp current does not flow into the drive transistor of the bidirectional transfer gate (the discharge transistor of the inverter circuits HA12 and HA13 in FIG. 11B) and the consumption current is reduced. Is reduced. In the DRAM, the on resistance value of the transistor forming the selection gate SG is relatively large. Therefore, when the clamp circuit CRD operates, the current flowing from the clamp transistors DQ70 and DQ80 to the selected DRAM bit line pair is extremely small. On the other hand, the drive circuit for data transfer included in the bidirectional transfer gate BTG has a sufficiently large drive capability. DRAMIO line D
High-speed charging / discharging of IOa and * DIOa and selected D
It is necessary to invert the latch data of the sense amplifier DSA of the RAM bit line pair. Therefore, the current flowing from the clamp circuit CRD to the drive transistor of the bidirectional transfer gate is much larger and has a non-negligible value.
This is a non-negligible value when a block-unit data batch transfer is performed in units of a plurality of bits. Therefore, as described above, by prohibiting the clamp operation of the clamp circuit on the data receiving side during data transfer,
It is possible to significantly reduce current consumption.

FIG. 14 shows another embodiment C of the present invention.
It is a figure which shows the structure of the principal part of DRAM. C shown in FIG.
The DRAM realizes high-speed data transfer, high-speed data read at the time of cache miss, and high-speed copyback mode. In FIG. 14, only the configuration of the portion related to one memory block is shown.

In the DRAM, a data read path and a data write path are separately provided, and the DRAM has an IO separation structure. Therefore, unlike the structure shown in FIG. 5, global IO line has global read line pairs GOLa and G for transmitting the data read from the DRAM array.
It includes OLb and a global write line pair GILa and GILb for transmitting write data to the DRAM array. Global read line pair GOLa and global write line pair GILa are arranged in parallel with each other, and global read line pair GOLb and global write line pair GILb are arranged in parallel with each other. The global read line pair GOL (generally indicates the global read line pair) and the global write line pair G
IL (generally indicates a global write line pair) corresponds to global IO line pair GIO shown in FIG.

Global read line pair GOLa and GOL
Local read line pairs LOLa and LOLb are provided corresponding to b. Local write line pairs LILa and LILb are provided corresponding to global write line pairs GILa and GILb.

A read block selection signal φRBA is provided between the global read line pair GOLa and the local read line pair LOLa.
A read gate ROGa that is turned on in response to is provided. A read gate ROGb which is turned on in response to a read block selection signal φRBA is provided between global read line pair GOLb and local read line pair LOLb.

A write block select signal φWBA is provided between global write line pair GILa and local write line pair LILb.
Write block select gate WI which is turned on in response to
Ga is provided. A write block selection gate WIGb which is turned on in response to a write block selection signal φWBA is provided between global write line pair GILb and local write line pair LILb.

For the DRAM bit line pair DBL, a local transfer gate LTG for transmitting selected memory cell data to the local read line pair LOL, and a write for connecting the selected memory cell to the local write line pair LIL. Gate I
G is provided.

A write column selection line WCSL and a read column selection line RCSL are provided to bring local transfer gate LTG and write gate IG into a selected state (conductive state). Write column select line WCSL and read column select line RCSL form a pair and are arranged in parallel. A write column select signal generated at the time of writing data from the DRAM column decoder is transmitted onto write column select line WCSL. The read column select line RCSL has this DRAM
A read column select signal generated from the DRAM column decoder is transmitted when data is read from the array. Write column select line WCSL and read column select line RCS
L is arranged so as to select two columns each. This structure corresponds to a structure in which the column selection line CSL shown in FIG. 5 is divided into two, a signal line for selecting a writing column and a signal line for selecting a reading column.

Local transfer gate LTG includes transistors LTR3 and LTR4 for differentially amplifying the signal of DRAM bit line pair DBL, and read column select line RCSL.
It includes switching transistors LTR1 and LTR2 which are turned on in response to the signal potential of and transmit the signals amplified by transistors LTR3 and LTR4 to local read line pair LOL. Transistor LTR
One terminal of 3 and LTR4 is connected to a fixed potential Vss, which is a ground potential, for example. In this structure, local transfer gate LTG inverts the potential of DRAM bit line pair DBL and transmits it to local read line pair LOL. Transistors LTR3 and LTR4 are formed of MOS transistors, and their gates are connected to DRAM bit line pair DBL. Therefore, the local transfer gate LTG is driven to the local read line pair LOL without adversely affecting the signal potential on the DRAM bit line pair DBL.
The signal potential on the RAM bit line pair DBL is transmitted at high speed.

The write gate IG is connected to the write column selection line WC.
In response to the signal potential on SL, it is turned on and the DRAM
It includes switching transistors IGR1 and IGR2 connecting bit line pair DBL to local write line pair LIL. The structure of the remaining DRAM is similar to that shown in FIG. 5, and the corresponding portions bear the same reference numerals.

Bidirectional transfer gates BTGa and BTGb
Are provided corresponding to a global write line pair and a global read line pair GIL and GOL, respectively. Transfer control signals DTL, DTA and DTS are applied to these bidirectional transfer gates BTGa and BTGb.

Bidirectional transfer gate BTG, the structure of which will be described later, includes pull-up means for pulling up the potentials of global read line pair GOL and local read line pair LOL. The pull-up means included in this bidirectional transfer gate also has a clamp function.

Global write line pair GIL is provided with a clamp circuit CRDW for clamping the potential of global write line pair GIL. This clamp circuit CRD
An inverted signal / DTA of transfer control signal DTA is applied to W. The clamp circuit CRDW may be provided in the local write line pair LIL or both write line pairs GIL and LIL.

In the SRAM array, each SRAM bit line pair SBL is provided with a clamp circuit CRS whose clamp operation is controlled in response to an inverted signal / DTS of transfer control signal DTS.

FIG. 15 shows a structure of a portion of bidirectional transfer gate BTG for transferring data from the DRAM array to the SRAM array. Referring to FIG.
The data transfer system BTGR from the DRAM array of the bidirectional transfer gate to the SRAM array is a global read line GOL.
And * GOL (where the symbols GOL and * GOL are 1
P signal MOS transistors Tr500 and T for differentially amplifying the signal potential on the signal line).
r501, and switching transistors Tr502 and Tr503 for transmitting the signal potentials on global read lines GOL and * GOL to SRAM bit lines SBLa and * SBLa in response to transfer control signal DTS. The gate of transistor Tr500 is also coupled to global read line * GOL. Global read lines GOL and * GOL are coupled to local read lines LOL and * LOL, respectively. In the structure shown in FIG. 15, the read block select gate is omitted.

In transfer gate circuit portion BTGR, transistors Tr500 and Tr501 form a current mirror circuit, and global read lines GOL and * are used.
Supply the same amount of current to GOL.

In the local transfer gate LTG, DR
When the potential of the AM bit line DBLa becomes higher than that of the bit line * DBLa, the conductivity of the transistor LTR4 becomes higher than that of the transistor LTR3.
When the read column selection signal RCSL is "H", the transistors Tr500 to LT
The amount of current flowing through R2 and LTR4 becomes larger than the amount of current flowing through transistors Tr501, LTR1 and LTR3. As a result, the potential of the global read line * GOL becomes lower than the potential of the global read line GOL. In response to the decrease in the potential of global read line * GOL, the conductivity of transistors Tr500 and Tr501 further increases, and global read line GO
The potential of L rises to "H" level, and the potential of the read line * GOL falls to "L". The circuit portion BTGR and the local transfer gate LTG form a current mirror type sense amplifier. These global read lines GOL and * G
After the signal potential of OL is sufficiently amplified to "H" and "L", the transfer control signal DTS rises to "H" and the signal potentials of the global read lines GOL and * GOL are SR.
It is transmitted to AM bit lines * SBLa and SBLa, respectively.

When the read gate shown in FIG. 15 is used, when a minute potential difference occurs in the DRAM bit line pair DBL, the signal of the DRAM bit line pair DBL is not adversely affected without adversely affecting the potential of the bit line pair DBL. SR potential
It can be transmitted to the AM bit line pair SBL. As a result, data can be transferred from the DRAM array to the SRAM array at high speed.

In this state, when the clamp circuit CRS in the SRAM array is in the operating state, a current flows from the transistor Tr502 or Tr503 to the local transfer gate LTG and is discharged through the transistor LTR4 or LTR3. This clamp circuit C
In order to prevent the inflow current from RS, the transfer control signal D
In response to TS, the clamp operation of the clamp circuit CRS provided for the SRAM bit line pair is prohibited. This reduces the current consumption during data transfer.

FIG. 16 shows a circuit portion of the bidirectional transfer gate BTG for transferring data from the SRAM array to the DRAM array.

In FIG. 16, this circuit portion BTGW is
The gate circuit 1810 and the latch circuit 1 illustrated in FIG.
811 and the gate circuit 1812 are provided. Therefore, in FIG. 16, the same reference numerals are given,
Detailed description thereof will be omitted. A clamp circuit CRDW is provided on the write lines GIL and / or LIL of the DRAM. Therefore, when data is transferred from the SRAM array to the DRAM array, a through current flows through the gate circuit 1812 and the discharging transistor of the inverter circuit included in the latch circuit 1811. Therefore, in this case, when the data is transferred from the SRAM array to the DRAM array, the clamp operation of clamp circuit CRDW is prohibited in response to transfer control signal DTA.

FIG. 17 shows a circuit structure for driving write column select signal line WCSL and read column select signal line RCSL. 17, the DRAM column decoder 103 (corresponding to the column decoder 15 in FIG. 3)
To the column selection line CSL from the signal line drive circuit 51
10 are provided. The signal line driver circuit 5110 is a DRA.
Gate circuit 5111 receiving column selection signal CSL from M column decoder 103 and internal write enable signal * W
And a column circuit 5112 receiving a column selection signal CSL, a sense completion signal SC and an internal write enable signal W. From gate circuit 5111 to read column select line RCS
A signal for driving L is output. Gate circuit 51
A signal for driving write column select line WCSL is output from 12.

Internal write enable signals * W and W are
Clock K in response to externally applied control signal W #
It may be a signal that is taken in in synchronization with. Alternatively, it may be a one-shot pulse signal generated at a predetermined timing. Sense completion signal SC is a signal indicating the completion of the sense operation of sense amplifier DSA in the DRAM array, and is a signal generated by delaying sense amplifier activation signal SANE or / SAPE by a predetermined time. By using the configuration shown in FIG. 17, the DRA
The read column select line RCSL is selected at the time of writing data from M to the SRAM, and the write column select line WCSL is selected in the case of data writing to the DRAM array (data transfer directly from the outside or data transfer from the SRAM array). The configuration is obtained.

FIG. 18 shows a structure of a circuit generating block select signals φRBA and φWBA. The circuit that generates read block selection signal φRBA is a delay circuit 512 that delays read column selection signal RCSL for a predetermined time.
0, the output of the delay circuit 5120 and the block selection signal φB
A gate circuit 5121 for receiving A (see FIG. 5) is included. Gate circuit 5121 outputs read block selection signal φRBA.

The circuit for generating write block selection signal φWBA is a delay circuit 5130 for delaying write column selection signal WCSL for a predetermined time, and a gate circuit 513 receiving the output of delay circuit 5130 and block selection signal φBA.
Including 1. Write block selection signal φWBA is generated from gate circuit 5131. Gate circuits 5121 and 5
131 is "H" when both inputs become "H"
Generate the signal.

In the above-described structure in which the data write path and the read path in the DRAM array are separate, it is preferable to transfer data from the DRAM array to the SRAM array as soon as possible. Therefore, the block selection signal φ
It is preferable to drive RBA and read column select line RCSL at the earliest possible timing. To achieve this configuration, it is most effective to use a configuration in which the address signals of the DRAM array and the SRAM array are shared. According to this structure, a row address signal and a column address signal can be applied to the DRAM array in accordance with a multiplexing method, a read column selection signal RCSL is generated immediately after the word line DWL of the DRAM array is selected, and the local address signal is generated. Transfer gate LTG can be rendered conductive, and DRAM bit line pair DBL can be coupled to transfer gate BTG via local read line pair LOL and global read line pair GOL.

The data transfer operation of the CDRAM shown in FIG. 14 will be described. First, referring to FIG. 19, DR
The data transfer operation from the AM array to the SRAM array will be described.

First, at time t1, equalize signal EQ
Falls to "L", and the precharge state in the DRAM array is completed. Next, at time t2, DRA
The M word line DWL is selected and the potential of the selected word line rises. On the other hand, at time ts1, the row selection operation is performed in the SRAM array, and the selected SRA
The potential of M word line SWL rises to "H", and the memory cell data connected to this selected word line is transmitted onto SRAM bit line SBL. SRAM bit line pair SBL
The upper signal potential is transferred to the latch means included in the transfer gate in response to the transfer instruction signal DTL and latched there.

On the other hand, in the DRAM, when the signal potential of the selected word line DWL rises to "H" at time t2 and the signal potential of the DRAM bit line pair DBL reaches a sufficient level, the sense amplifier drive signal is reached at time t3. SAN falls to "L", and sense amplifier drive signal / SAP rises to "H" at time t4. As a result, the signal potentials of the DRAM bit line pair DBL are set to "H" and "L" corresponding to the respective read data. The local transfer gate LTG is a DRAM bit line pair D
It directly receives the signal potential of BL.

Sense amplifier drive signal S at time t3
Before the fall of AN, the signal potential of the read column select line WCSL rises to "H". As a result, a small change in signal potential before the sensing operation, which has occurred in the DRAM bit line pair DBL, is rapidly amplified by the local transfer gate LTG and transmitted to the local read line pair LOL. Although not clearly shown in FIG. 2, the operation waveform diagram shown in FIG. 19 shows a state in which both the local read line LOL and the global read line GOL are precharged to “H”. A clamp transistor may be provided in this global read line GOL. This is because the transistors Tr500 and Tr are included in the circuit portion BTGR of the bidirectional transfer gate.
It is realized by providing a clamping transistor in parallel with 501.

When the signal potential of DRAM bit line pair DBL is transmitted to local read line pair LOL, read block selection signal φRBA rises to "H" at time t7 '. As a result, the local read line pair LOL is connected to the global read line pair GOL, and the DRAM bit line pair DBL is connected.
The signal potential change generated at is transmitted to the transfer gate BTG via the global read line pair GOL.

At time t7 ', global read line pair G
The transfer control signal DTS is generated at time t3 before the change in the signal potential of OL occurs. Global read line pair G
The signal potential change generated in the OL is transmitted at high speed to the corresponding memory cell of the SRAM array. At this time, if the clamp circuit is operating in the SRAM array, a current flows through the clamping transistors SQ70 and SQ80 before the signal potential change of the global read line pair GOL occurs to charge the global read line pair, A through current flows from the clamp circuit CRS via the local transfer gate LTG. Therefore, in response to the transfer control signal DTS, the operation of the clamp circuit CRS for the SRAM bit line pair is stopped. As a result, the SRAM bit line pair SBL can operate at high speed by using the current mirror type circuit (transistors Tr500 and Tr50) included in the bidirectional transfer gate.
It is charged / discharged by 1) and becomes a potential state corresponding to the data of the corresponding DRAM cell.

Therefore, in the operation waveform diagram shown in FIG. 19, DRAM sense amplifier DSA at time t5.
By the time the amplification operation (sense operation) of the DRAM bit line pair DBL is completed, the data transfer to the SRAM array has already been completed.

As described above, the local transfer gate LTG is provided and the DRAM bit line pair DBL is directly connected to the transfer gate BT.
By connecting to G, data transfer can be executed without waiting for the completion of the sense amplifier operation of the DRAM sense amplifier DSA.

At this time, by prohibiting the clamp operation of the clamp circuit CRS of the SRAM array in response to the data transfer instruction signal, the current consumption is low and the amplification operation by the local transfer gate is not adversely affected and the operation is surely performed at high speed. Data can be transferred.

In the signal waveform diagram shown in FIG. 19, arrows indicate the data transfer direction, and the signal waveform diagram shown by the broken line shows the data transfer operation in the CDRAM shown in FIG. As is clear from the comparison of the signal waveform diagrams, DRA
By making M an IO isolation structure, the bidirectional transfer gate BTG can be activated (generate the control signal DTS) before the DRAM sense amplifier DSA is activated, and data can be transferred at high speed. .. Where signal φR
BA may be generated at time t3.

The SRAM array is ready to access data transfers from this DRAM array. Therefore, the SRAM array can be accessed at high speed even when there is a cache miss. Next, the data transfer operation from the SRAM array to the DRAM array will be described with reference to the operation timing chart of FIG.

Data transfer from the SRAM array to the DRAM array is performed via global write line pair GIL. In this case, the global read line pair GOL and the local read line pair LOL are not used.

The operation shown in FIG. 20 shows the operation when both local write line pair LIL and global write line pair GIL are pulled up to the level of Vcc-Vth by clamp circuit CRWD.

At time t1, the DRAM array precharge cycle is completed. DRA at time t2
The M word line DWL is selected, and the potential of the selected word line rises to "H". Time t3 and time t4
In, the sense amplifier drive signals SAN and / SAP are activated respectively, and the signal potential on the DRAM bit line pair DBL becomes a value corresponding to the data of the selected memory cell.

At time t5, write column select line WCS
L is selected, and the signal potential of the selected write column select line WCSL rises to "H". As a result, the write gate IG is turned on, and the local write line pair LOL is connected to the selected DRAM bit line pair DBL. At this time, the write gate IG has a large resistance value, and DR
The potential of the AM bit line pair DBL is fully swung to "H" and "L" levels by the internal DRAM sense amplifier DSA, while the local write line pair LIL is grounded at its L level by the operation of its clamp circuit. Potential Vss
Rise above the level.

At time t6, write block selection signal φ
WBA rises to "H". As a result, the local write line pair LIL and the global write line pair GIL are connected, and the signal potential of the global write line pair GIL becomes a level corresponding to the signal potential of the local write line pair LIL. At this time,
If the resistance of the gate WIG is larger than that of the gate IG, the "L" potential level of the global write line pair GIL becomes higher than the "L" level of the local write line pair LIL (the clamp circuit is the global write line pair). Only when provided).

At time t7, transfer control signal DTA rises to "H", and the data latched in bidirectional transfer gate BTG is transferred to DRAM bit line pair DBL via global write line pair GIL and local write line pair LIL.
Transmitted to.

At this time, the write line pair GIL (and LIL)
The clamp operation of the clamp circuit CRDW provided in is prohibited. As a result, the path from the clamp circuit CRDW to the discharge transistor of the inverter circuit included in the latch circuit of the bidirectional transfer gate is cut off, and the current consumption is reduced.
Local write line pair LIL and global write line pair GI
The potential level of L becomes the potential levels "H" and "L" level latched by the latch circuit 1811.

At time t8, sense amplifier activation signals SANE and / SAPE are inactivated, sense amplifier drive signals SAN and / SAP are restored to the potential level of Vcc / 2 which is the intermediate potential (time t9), and subsequently, The potential level of write column selection line WCSL falls to "L" and block selection signal φWBA also falls to "L". This completes the data transfer cycle.

Here, the global write line pair GIL has a parasitic capacitance larger than that of the local write line pair LIL (the global write line pair GIL extends over a plurality of blocks, and the local write line pair LIL. Is provided for only one memory block). Therefore, even if the data transfer control signal DTA falls to "L", the change of the signal potential is slower in the global write line pair GIL than in the local write line pair LIL.

As described above, also in the DRAM structure having the IO separation structure, the clamp circuits are provided for the signal lines GIL and LIL receiving the data write, and the clamp operation of the clamp circuits is prohibited during the data transfer. It becomes possible to transmit the data latched by the latch circuit to the selected bit line pair DBL of the DRAM array with low current consumption and at high speed.

That is, by prohibiting the clamp operation of the clamp circuit provided on the data receiving side, a through current to the discharging transistor included in the bidirectional transfer gate circuit is not generated, and the current consumption is significantly reduced. It can be reduced.

In the CDRAM shown in FIGS. 14 to 20, a clamp circuit in which both global write line pair GIL and local write line pair LIL are precharged to the potential level of Vcc / 2 which is the intermediate potential may be used. ..

Further, global read line pair GOL and local read line pair LOL each have an intermediate potential of Vcc /.
A structure precharged to the potential level of 2 may be used, and a clamp circuit for clamping the read line pair GOL and LOL to the level Vcc-Vth may be provided.

In the above embodiment, the structure in which the SRAM address and the DRAM address can be independently set in the CDRAM is described. However, the present invention is not limited to SRAM arrays and DRAs.
If the semiconductor memory device can transfer data to and from the M array and the clamp circuit is provided in the transfer path, the same effect as the above embodiment can be obtained.

[0263]

As described above, according to the present invention, the SR
In a semiconductor device in which AM and DRAM are integrated,
Since the clamp operation of the clamp circuit provided on the side receiving the data transfer is prohibited during the data transfer between the SRAM array and the DRAM array, the drive transistor (discharging transistor) included in the bidirectional transfer gate from this clamp circuit. It is possible to obtain a semiconductor memory device capable of preventing the occurrence of a through current flowing through the semiconductor memory device and significantly reducing the current consumption without impairing the high-speed data transfer operation performance.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a main part of a semiconductor memory device according to an embodiment of the present invention.

FIG. 2 is a diagram showing an external appearance of a package that houses a semiconductor memory device according to the present invention.

FIG. 3 is a diagram schematically showing an overall configuration of a semiconductor memory device according to an embodiment of the present invention.

FIG. 4 is a diagram showing an address distribution system in a semiconductor memory device according to the present invention.

5 is a diagram showing a detailed configuration of a main part of the semiconductor memory device shown in FIG.

FIG. 6 is a diagram showing an embodiment of a bidirectional transfer gate.

FIG. 7 is a signal waveform diagram representing an operation of the semiconductor memory device according to the present invention.

FIG. 8 is a signal waveform diagram representing an operation of the semiconductor memory device according to the present invention.

FIG. 9 is a diagram showing a configuration of a main part of a semiconductor memory device according to another embodiment of the present invention.

FIG. 10 is a diagram showing another configuration example of a bidirectional transfer gate.

FIG. 11 is a diagram showing still another configuration example of the bidirectional transfer gate.

12 is a signal waveform diagram showing a data transfer operation when the bidirectional transfer gate shown in FIG. 11 is used.

13 is a signal waveform diagram showing a data transfer operation when the bidirectional transfer gate shown in FIG. 11 is used.

FIG. 14 is a diagram showing a configuration of a main part of a semiconductor memory device according to another embodiment of the present invention.

15 is a diagram showing a data transfer system from the DRAM to the SRAM of the bidirectional transfer gate shown in FIG.

16 is a diagram showing a data transfer system of the bidirectional transfer gate shown in FIG. 14 from SRAM to DRAM.

17 is a diagram showing a column selection signal generation system in the semiconductor memory device shown in FIG.

18 is a diagram showing an example of a configuration of a block selection signal generation system in the semiconductor memory device shown in FIG.

19 is a signal waveform diagram representing an operation of the semiconductor memory device shown in FIG.

20 is a signal waveform diagram representing an operation of the semiconductor memory device shown in FIG.

FIG. 21 is a diagram showing a schematic configuration of a general semiconductor memory device with a built-in cache.

FIG. 22 is a diagram showing an array arrangement of a conventional semiconductor memory device with a built-in cache.

FIG. 23 is a diagram showing a configuration of a main part of the cache built-in semiconductor memory device shown in FIG. 22;

FIG. 24 is an SRA in the semiconductor memory device shown in FIG. 23.
It is a figure for demonstrating the function of the clamp circuit of M array.

FIG. 25 is a diagram showing a specific configuration example of the DRAM sense amplifier and the transfer gate shown in FIG. 23.

FIG. 26 is a diagram showing another configuration example of a semiconductor memory device with a built-in cache.

FIG. 27 is a diagram showing a specific configuration example of a main part of the semiconductor memory device having the configuration shown in FIG. 26.

[Explanation of symbols]

 1 DRAM array 2 SRAM array 3 Bidirectional transfer gate circuit BTG Bidirectional transfer gate CRS SRAM Bit line clamp circuit CRD DRAM IO line clamp circuit SMC SRAM memory cell DMC DRAM memory cell GIO Global IO line LIO Local IO line CRDW DRAM write line clamp Circuit GIL Global write line GOL Global read line LIL Local write line LOL Local read line

Claims (2)

[Claims] 1. A high-speed memory array having a plurality of static memory cells, a large-capacity memory array having a plurality of dynamic memory cells and having a storage capacity larger than that of the high-speed memory array, and selecting the high-speed memory array. Data transfer means for performing data transfer between the selected memory cell and the selected memory cell of the large capacity memory array, the selected memory cell of the large capacity memory array and the data transfer means. A signal line for connection, a clamp means for clamping the potential of the signal line,
And a control means for prohibiting a clamp operation of the clamp means in response to a data transfer instruction from the high speed memory array to the large capacity memory array. 2. A high-speed memory array comprising a plurality of static memory cells arranged in rows and columns, said high-speed memory array including SRAM column lines to which one row of static memory cells are connected, respectively. A large-capacity memory array having a dynamic memory cell and having a storage capacity larger than that of the high-speed memory array; between a selected memory cell of the high-speed memory array and a selected memory cell of the large-capacity memory array; Data transfer means for performing data transfer, clamp means provided in each of the SRAM column lines for clamping the potential of the corresponding SRAM column line, and data transfer from the large capacity memory array to the high speed memory array. A semiconductor device including control means for prohibiting a clamp operation of the clamp means in response to an instruction. Storage device.