JPH04318389A - Data transfer device in semiconductor storage device - Google Patents

Abstract

PURPOSE:To provide the data transfer device which can execute a data transfer at a high speed between a large capacity memory and a high speed memory. CONSTITUTION:The data transfer device contains a latch circuit 1811 for latching data from an SRAM 2 being a high speed memory, an amplifying circuit 1814 and a gate circuit 1815 for amplifying the data from a DRAM 1 being a large capacity memory and transferring to the SRAM, and a gate circuit 1813 for transferring write data to the corresponding memory cell of the DRAM in response to a DRAM write enable signal AWDE. After the data of the SRAM is latched to the latch circuit 1811, the write data is transformed to the DRAM from the gate circuit 1813, and this write data is transferred to the SRAM through the amplifying circuit 1814 and the gate circuit 1815. At the time of cache miswrite, this transfer data is rewritten to the write data, therefore, after the data transfer to the SRAM from the DRAM is completed, an access to the SRAM can be executed, and write and readout of the data can be executed at a high speed even at the time of cache miss.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transfer device in a semiconductor memory device in which a high-speed memory cell and a large-capacity memory are formed on the same semiconductor chip. In particular, large capacity dynamic random access memory (DRAM) as main memory and small capacity static random access memory (SR) as cache memory.
The present invention relates to a data transfer device for transferring data between DRAM and SRAM in a semiconductor memory device with a built-in cache.

0002

2. Description of the Related Art Recent 16-bit or 32-bit microprocessing units (MPUs) have become extremely fast with operating clock frequencies of 25 MHz or higher. In data processing systems, standard D
RAM (dynamic random access memory)
Because of its low cost per bit, it is often used as main memory with large storage capacity. Although the access time of this standard DRAM has been shortened, the MPU speed has exceeded that of the standard DRAM. For this reason, data processing systems that use standard DRAM as main memory must make sacrifices such as an increase in wait states. This problem of the gap in operating speed between the MPU and the standard DRAM is essential because the standard DRAM has the following characteristics.

(1) Row addresses and column addresses are time-division multiplexed and applied to the same address pin terminal. Row address is row address strobe signal/RAS
It is taken into the device at the falling edge of. The column address is taken into the device at the falling edge of the column address strobe signal /CAS. Row address strobe signal/R
AS defines the start of a memory cycle and activates the row selection system. Column address strobe signal /CAS activates a column selection system. “RAS-CA” is maintained from when the signal /RAS becomes active until when the signal /CAS becomes active.
Since a predetermined time called "S delay time (tRCD)" is required, there is a restriction due to address multiplexing that there is a limit to the reduction of access time.

(2) Row address strobe signal/
Once RAS is turned on and the DRAM is set to standby, the row address strobe signal /RAS cannot be brought down to "L" again until a time called the RAS precharge time (tRP) has elapsed. . This RAS precharge time is required to reliably precharge various signal lines of the DRAM to predetermined potentials. Therefore, the DRAM cycle time cannot be shortened by the RAS precharge time tRP. In addition, shortening the cycle time of DRAM
In AM, the number of times the signal line is charged and discharged increases, which also leads to an increase in current consumption.

(3) Improvements in circuit technology and process technology, such as higher circuit integration and improved layout, as well as application innovations and improvements, such as improved driving methods, have made it possible to improve DRA.
It is possible to increase the speed of M. However, the progress in increasing the speed of MPUs has far exceeded that of DRAMs. EC
The operating speed of semiconductor memory has increased, such as high-speed bipolar RAM using bipolar transistors such as LRAM (emitter-coupled RAM) and static RAM, and relatively low-speed DRAM using MOS transistors (insulated gate field effect transistors). has a hierarchical structure. It is extremely difficult to expect a speed (cycle time) of several tens of nanoseconds in a standard DRAM that includes MOS transistors.

Various improvements have been made from an application standpoint to fill the speed gap (difference in operating speed) between MPUs and standard DRAMs. The main improvements include:
(1) Using DRAM high-speed mode and interleaving method; (2) High-speed cache memory (SRA)
M) is provided externally.

In the case of the above method (1), there are two methods: a method that uses a high-speed mode such as a static column mode or a page mode, and a method that combines this high-speed mode and an interleaving method. The static mode is a method in which one word line (one row) is selected and then the memory cells of this one row are sequentially accessed by sequentially changing only the column address. The page mode is a method in which, after selecting one word line, the signal /CAS is toggled to sequentially take in column addresses, and the memory cells connected to this one word line are sequentially accessed. Either of these modes allows access to memory cells without toggling the signal /RAS, and the normal signals /RAS and
This is faster than access using CAS.

The interleaving method is a method for effectively shortening the access time by providing a plurality of memories in parallel on a data bus and accessing the plurality of memories alternately or sequentially. The method using the high-speed mode of DRAM and the method of combining the high-speed mode and the interleaving method are conventionally known as methods for easily and relatively efficiently using a standard DRAM as a high-speed DRAM.

The above method (2) has been widely used in mainframes for a long time. This high speed cache memory is expensive. However, in the field of personal computers, which require high performance while being low in price, in order to improve the operating speed, some of them have no choice but to sacrifice some increase in price. Regarding where to install high-speed cache memory, see the following 3.
There are several possible types.

(a) Built into the MPU itself.

(b) Provided outside the MPU.

(c) Also, instead of providing a separate high-speed cache memory, the high-speed mode built into the standard DRAM is used like a cache (the high-speed mode becomes a pseudo-cache memory). That is, when a cache hit occurs, the standard DRAM is accessed in high-speed mode, and when a cache miss occurs, the standard DRAM is accessed in normal mode. These three methods (a) to (c) have already been employed in some form in data processing systems.

However, from the viewpoint of price, many M
In the PU system, in order to effectively hide the inevitable RAS precharge time (tRP) of DRAM, a method is used in which the memory is arranged in banks and each memory bank is interleaved. According to this method, the cycle time of the DRAM can be substantially reduced to approximately half of the specification value. Interleaving methods are effective only when memory accesses are sequential. That is,
No effect can be obtained when accessing the same memory bank consecutively. Furthermore, this method cannot substantially improve the access time of the DRAM itself. Furthermore, the minimum unit of memory must be at least two banks.

[0014] When using a high-speed mode such as page mode or static column mode, the access time can only be effectively shortened when the MPU continuously accesses a certain page (one specified row of data). can. This method is effective to some extent when the number of banks is relatively large, such as 2 to 4, because different rows can be accessed for each bank. A case where there is no memory data requested by the MPU within a given page is called a "mishit." Typically, chunks of data are stored at adjacent or sequential addresses. In high-speed mode, the probability of a "mishit" occurring is high because the row address, which is half of the address, has already been specified. However, when the number of banks increases to 30 to 40, the "mishit" rate decreases dramatically because each bank can store data of a different page. However, it is not realistic to envisage 30 to 40 banks in a data processing system. Furthermore, if a "mishit" occurs, it is necessary to raise the signal /RAS and return to the DRAM precharge cycle in order to select a new row address, which may result in sacrificing the performance of the bank configuration. Become.

In the case of method (2) above, MPU and standard DR
A high speed cache memory is provided between the AM and the AM. In this case, the standard DRAM may be relatively slow. On the other hand, standard DRAM is 4M (mega) bits, 16
Devices with M bits and large storage capacity are emerging. In small-scale systems such as personal computers, the main memory is one or several chips of standard DRAM.
It can be configured by Providing an external high-speed cache memory is not effective in small-scale systems where the main memory can be constructed from, for example, one standard DRAM. When using standard DRAM as main memory,
This is because the data transfer speed between the high-speed cache memory and the main memory is limited by the number of data input/output terminals of this standard DRAM, which becomes a bottleneck to the speed of the system.

Furthermore, in the case of a high-speed mode pseudo cache memory, its operating speed is slower than that of a high-speed cache memory, making it difficult to achieve desired system performance.

[0017] As a method of eliminating the sacrifice in system performance that occurs when using the interleaving method or high-speed operation mode as described above and constructing a relatively inexpensive and small-scale system, it is possible to use high-speed cache memory (SRAM) with DR.
It is possible to incorporate it into AM. That is, DRAM
It is possible to consider a one-chip memory with a hierarchical structure, in which the main memory is the main memory, and the SRAM is the cache memory. A one-chip memory having such a hierarchical structure is called a cache DRAM (CDRAM). This CD
The RAM will be explained below.

FIG. 88 shows a conventional standard 1 megabit DR.
It is a figure showing the composition of the main part of AM. In FIG. 88, D
The RAM includes a memory cell array 50 consisting of a plurality of memory cells MC arranged in a matrix of rows and columns.
Contains 0. One row of memory cells is connected to one word line WL. One column of memory cells MC is connected to one column line CL. This column line CL usually consists of a pair of bit lines. One word line WL selects a memory cell located at the intersection with one of the pair of bit lines. In a 1M (mega) DRAM, memory cells MC are arranged in a matrix of 1024×1024 columns. That is, this memory cell array 500 has 10
24 word lines WL and 1024 column lines CL (102
4 pairs of bit lines).

The DRAM further includes a row decoder 502 that decodes an externally applied row address (not shown) and selects a corresponding row of the memory cell array 500, and a word line connected to the row decoder 502. The memory cell array 500 includes a sense amplifier that detects and amplifies data in a memory cell, and a column decoder that decodes an externally applied column address (not shown) and selects a corresponding column of this memory cell array 500. In FIG. 88, a sense amplifier and a column decoder are shown as one block 504. If this DRAM has a ×1 bit configuration in which data input/output is performed in units of 1 bit, one column line CL (bit line pair) is selected by a column decoder. DRAM
In the case of a ×4 bit configuration in which data is input/output in units of 4 bits, four column lines CL are selected by a column decoder. One sense amplifier in block 504 is provided for each column line (bit line pair) CL.

During memory access to write data to or read data from memory cell MC in this DRAM, the following operations are performed. First, a row address is given to row decoder 502. The row decoder 502 decodes this row address,
The potential of one word line WL in memory cell array 500 is raised to "H". Data in the 1024-bit memory cell MC connected to the selected word line WL is transmitted onto the corresponding column line CL. Data on this column line CL is amplified by a sense amplifier included in block 504. Among the memory cells connected to the selected word line WL, a memory cell to which data is to be written or read is selected by a column selection signal from a column decoder included in block 504.

In the aforementioned high speed mode, column addresses are sequentially given to the column decoders included in block 504. During static column mode operation, the column decoder decodes the column address given at predetermined intervals as a new column address, and connects the memory cell connected to the selected word line WL to the column line CL.
Select via. In the page mode, a new column address is given to the column decoder for each toggle of the signal /CAS, and the column decoder decodes this column address to select the corresponding column line. In this way, by setting one word line WL in the selected state and changing only the column address, the 1 word line WL connected to this selected word line WL is
Memory cells MC in a row can be accessed at high speed.

FIG. 89 is a diagram showing the general configuration of a conventional 1M bit CDRAM. In Figure 89, conventional CDR
In addition to the standard DRAM configuration shown in FIG.
It includes a RAM 506 and a transfer gate 508 for transferring data between one row of the DRAM memory cell array 500 and the SRAM 506. SRAM50
Reference numeral 6 includes a cache register provided corresponding to each column line CL of the DRAM memory cell array 500 so that data of one row of the DRAM memory cell array 500 can be stored at the same time. Therefore, 1024 cash registers are provided. Further, this cache register is composed of SRAM cells. In the case of the CDRAM configuration shown in FIG. 89, when a signal indicating a cache hit is applied from the outside, this SRAM 506 is accessed, and the memory can be accessed at high speed. At the time of a cache miss (mishit), the DRAM section is accessed.

[0023] As mentioned above, large capacity DRAM and high speed S
CDRAM, which is integrated with RAM on the same chip, is disclosed in, for example, Japanese Patent Laid-Open No. 60-7690 and Japanese Patent Laid-open No. 62-3.
This is disclosed in Publication No. 8590 and the like.

[0024]

[Problem to be solved by the invention] The conventional C
In the DRAM configuration, the column lines (bit line pairs) CL of the DRAM memory cell array 500 and the column lines (bit line pairs) of the SRAM (cache memory) 506 are connected via transfer gates 508 in a one-to-one correspondence. Ru. That is, in the conventional CDRAM configuration described above, the data of the memory cells connected to one word line WL in the DRAM memory cell array 500 and the data of the same number of SRAM cells as one row of the memory cell array 500 are transferred. A configuration is adopted in which bidirectional batch transfer is performed via gate 508. In this configuration, S
RAM 506 is used as cache memory and DR
AM is used as main memory.

In this case, the so-called block size of the cache is considered to be the number of bits whose contents can be rewritten in one data transfer in the SRAM 506. Therefore, this block size is the same as the number of memory cells physically coupled to one word line WL of the DRAM memory cell array 500. When 1024 memory cells are physically connected to one word line WL as shown in FIGS. 88 and 89, the block size is 1024.

Generally, the hit rate increases as the block size increases. However, when the cache memory size is the same, the number of sets decreases in inverse proportion to the block size, so the hit rate decreases. For example, when the cache size is 4K bits, if the block size is 1024, the number of sets is 4, but if the block size is 32, the number of sets is 128. Therefore, in the case of the conventional CDRAM configuration, a problem arises in that the block size becomes larger than necessary and the cache hit rate cannot be improved much.

A configuration for reducing the block size is shown in, for example, Japanese Patent Laid-Open No. 1-146187. In this prior art, the DRAM array and the SRAM array have column lines (bit line pairs) arranged in one-to-one correspondence, but each is divided into a plurality of blocks in the column direction. Block selection is performed by a block decoder. At the time of cache miss (mishit), one block is selected by the block decoder. Data is transferred only between the selected DRAM block and SRAM block. If this configuration is followed, the block size of the cache memory can be reduced to an appropriate size, but
The following issues remain unresolved.

FIG. 90 is a diagram showing a standard array configuration of a 1M bit DRAM array. In FIG. 90, DR
The AM array has eight memory blocks DMB1 to DMB8.
divided into. A row decoder 502 is provided in common to memory blocks DMB1 to DMB8 on one side in the long side direction of the memory array. Memory block DMB1~DM
For each of B8 (sense amplifier + column decoder)
Blocks 504-1 to 504-8 are provided.

Memory blocks DMB1 to DMB8 each have a capacity of 128 Kbits. In FIG. 90, one memory block DMB has 128 rows and 102 rows.
An example is shown in which they are arranged in four columns. One column line CL is composed of a pair of bit lines BL and /BL.

As shown in FIG. 90, if the DRAM memory cell array is divided into a plurality of blocks, the length of one bit line BL (and /BL) can be shortened. When reading data, charges accumulated in a capacitor within a memory cell (memory cell capacitor) are transmitted to a corresponding bit line BL (or /BL). At this time, the amount of potential change occurring on the bit line BL (or /BL) is the capacitance Cs of the memory cell capacitor and the capacitance Cb of the bit line BL (or /BL).
It is proportional to the ratio of Cs/Cb. As the length of the bit line BL (or /BL) becomes shorter, the bit line capacitance Cb becomes smaller. This makes it possible to increase the amount of potential change that occurs on the bit line.

Furthermore, during operation, the row decoder 502
A memory block (
In FIG. 90, only a sensing operation is performed on memory block DMB2), and the remaining blocks are maintained in a standby state. This makes it possible to reduce power consumption associated with bit line charging and discharging during sensing operation.

In a DRAM as shown in FIG. 90, when the above-described block division method CDRAM is applied, an SRAM is assigned to each memory block DMB1 to DMB8.
Registers and block decoders need to be provided. This causes a problem in that the chip area increases significantly.

Furthermore, as mentioned above, the DRAM array and SR
Bit lines correspond to each other on a one-to-one basis with the AM array. When a direct mapping method is adopted as a memory mapping method between the main memory and the cache memory, as shown in FIG. 89, the SRAM 506 is composed of 1024 cache registers arranged in one row. In this case, the capacity of the SRAM cache is 1K bits.

Further, when a 4-way set associative method is adopted as the mapping method, the SRAM array 506 has four rows of cache registers 5 as shown in FIG.
06a to 506d. One of these four lines of cache registers 506a-506d is selected by selector 510 according to the way address. In this case S.R.
The capacity of the AM cache is 4K bits.

As described above, the mapping method of memory cells between the DRAM array and the cache memory is determined by the internal configuration of the chip. Changing the mapping method requires changing the cache size as described above.

Furthermore, in any of the above-mentioned CDRAM configurations, since the bit lines of the DRAM array and the SRAM array have a one-to-one correspondence, the column address of the DRAM array and the column address of the SRAM array are necessarily the same. Therefore, it is theoretically impossible to implement a fully associative method in which a memory cell in a DRAM array is mapped to an arbitrary position in an SRAM array.

Another structure of a semiconductor memory device in which DRAM and SRAM are integrated on the same chip is also disclosed in Japanese Patent Laid-Open No. 2-87.
It is disclosed in Publication No. 392. In this prior art, a DRAM array and an SRAM array are connected via an internal common data bus. This internal common data bus is connected to an input/output buffer for inputting and outputting data to and from the outside of the device. The selected positions of the DRAM array and the SRAM array can be designated by separate addresses. However, in the configuration of this prior art, D
Data transfer between the RAM array and the SRAM array is performed via an internal common data bus, so the number of bits that can be transferred at one time is limited by the number of internal data bus lines, and the data can be cached at high speed. The contents of memory cannot be rewritten. Therefore, as in the case of the configuration in which the SRAM cache is provided outside the standard DRAM as described above, the data transfer speed between this DRAM array and the SRAM array becomes a bottleneck, making it impossible to construct a high-speed cache memory system.

Furthermore, in this prior art, data is transferred between the DRAM array and the SRAM array via an internal common data bus. Therefore, a problem arises in that an operation commonly called "copyback mode" cannot be performed at high speed. In other words, the "copy back mode" involves the steps of transferring the data of the corresponding memory cell in the SRAM array to the original memory cell location of the DRAM array in the event of a cache miss, and transferring the data of the DRAM memory cell requested for access to the corresponding memory cell location of the SRAM array. and transferring the data to the memory cells of the memory cell. Although the internal common data bus is a bidirectional bus, the direction of data transfer that occurs at one time is from SRAM to DRAM, and
One direction is from M to SRAM. Therefore, this prior art configuration involves selecting a word line in the DRAM array, transferring data from the SRAM array to the DRAM array, precharging the DRAM array (setting it to standby state), and selecting another word line in the DRAM array. This requires many steps of selecting and transferring the data of the corresponding memory cell of the selected word line to the SRAM, resulting in the problem that "copying back" cannot be performed at high speed.

Furthermore, in this prior art, since data is transferred between the DRAM array and the SRAM array via an internal common data bus, in the event of a cache miss, the data transfer from the DRAM array to the SRAM array is delayed. The SRAM array cannot be accessed and data read from the SRAM array until this is completed and the DRAM array is set to standby. Therefore, another problem arises in that data reading cannot be performed at high speed in the event of a cache miss or the like.

[0040] Therefore, the object of the present invention is to
It is an object of the present invention to provide a data transfer device capable of transferring data between an array and an SRAM array at high speed and efficiently.

Another object of the present invention is to provide a data transfer device for a semiconductor memory device that can write and read data at high speed even in the event of a cache miss.

Still another object of the present invention is to provide a data transfer device in a semiconductor memory device that is capable of performing copyback operations at high speed.

[0043]

[Means for Solving the Problems] A data transfer device according to a first aspect of the invention transfers data in a memory cell of a high-speed memory selected according to an external address to a corresponding memory cell of a large-capacity memory when a cache miss occurs. and a second transfer means for transferring data in a memory cell of a large capacity memory specified by an external address to the selected memory cell of the high speed memory at the time of a cache miss. The second transfer means is provided separately from the first transfer means, and transfers data via a route different from the data transfer route of the first transfer means.

The data transfer device of the first invention further inhibits the data transfer operation of the first transfer means in response to the data write instruction signal to the large capacity memory, and controls the selection of the large capacity memory. and a third transfer means for transferring the write data to the selected memory cell and transferring the write data to the selected memory cell of the high speed memory via the second transfer means.

The data transfer device according to the second invention includes a first transfer means for transferring data of a memory cell of a high-speed memory selected according to the external address to a corresponding memory cell of a large-capacity memory at the time of a cache miss. and a second transfer means for transferring the data of the memory cell of the large capacity memory selected according to the external address to the selected memory cell of the high speed memory at the time of a cache miss. The first transfer means includes latch means for temporarily storing data transferred from a selected memory cell of the high speed memory.

The second transfer means transfers the memory cell data of the large capacity memory to the selected memory cell of the high speed memory via a path different from the data transfer path of the first transfer means.

The data transfer device according to the second invention further transfers write data to the selected memory cell of the large capacity memory in response to a data write instruction signal to the large capacity memory. and a third transfer means for prohibiting the transfer operation of the first transfer means; and in response to a data write instruction signal to the high speed memory, the write data is transferred to the selected one of the high speed memory. A fourth transfer means for transferring data to the memory cell bypassing the second transfer means is provided.

The second transfer means is activated after the third transfer means starts transferring the write data to the selected memory cell of the large capacity memory, and is activated by the latch means of the first transfer means. It is activated after data latching of the selected memory cell of the high speed memory.

[0049]

[Operation] According to the data transfer device according to the first invention, the third transfer means transfers the write data to the memory cell designated by the external address of the large capacity memory, and the second
The write data is transmitted to the selected memory cell of the high speed memory via the transfer means of the high speed memory. Therefore, the data transferred from the large-capacity memory to the high-speed memory at the time of a cache miss is replaced with write data. Therefore, since the data write operation is completed at the time when data transfer to the high speed memory is completed, data is written at high speed even in the event of a cache miss.

According to the second invention, at the time of a cache miss, the fourth transfer means directly transfers the write data to the selected memory cell of the high speed memory. Therefore, even if the access time of the large-capacity memory becomes shorter and there is less time to transfer write data via the second and third transfer means, the fourth transfer means can reliably transfer the write data. is transmitted to the selected memory cell of the high-speed memory, data is written at high speed even in the event of a cache miss.

[0051]

Embodiment The overall structure of a semiconductor memory device will be explained.

FIG. 2 is a diagram schematically showing an example of the configuration of a memory array section of a semiconductor memory device to which the present invention is applied. In FIG. 2, the semiconductor memory device includes a DRAM array 1 including dynamic memory cells arranged in a matrix of rows and columns, and an SRAM array 1 including static memory cells arranged in a matrix of rows and columns. 2, this DRAM array 1 and SRA
It includes a bidirectional transfer gate circuit 3 for transferring data to and from the M array 2.

When the DRAM array 1 has a storage capacity of 1M bits, it includes 1024 word lines WL and 1024 pairs of bit lines BL and /BL. However, in the figure, the bit line pair is indicated by DBL. This DRAM array 1 is divided into a plurality of blocks along the row and column directions, respectively. In FIG. 2, the DRAM array 1 has eight columns in the column direction.
blocks MBi1 to MBi8 (i=1 to 4), and four blocks MB1j to MB4j in the row direction.
(j=1 to 8), for a total of 32 memory blocks, is shown as an example.

Eight blocks M divided in the column direction
Bi1 to MBi8 constitute one row block 11. Four blocks MB1j to MB4j divided in the row direction
constitute column block 12. Memory blocks MBi1 to MBi8 included in one row block 11 share one word line WL. Memory blocks MB1j to MB4j included in the same column block 12 are connected to column selection line C.
Share SL. Each memory block MB11 to MB48
A sense amplifier+IO block 13 is provided for each. The configuration of this sense amplifier+IO block 13 will be explained later. Column selection line CSL selects two columns (two pairs of bit lines) at the same time.

This semiconductor memory device further includes a row decoder 14 that selects a corresponding row from the DRAM array 1 in response to an externally applied address, and a row decoder 14 that selects a corresponding row from the DRAM array 1 in response to an externally applied address, and a row decoder 14 that selects a corresponding row from the DRAM array 1 in response to an externally applied address. selection line CS
It includes a column decoder 15 for selecting L. column block 1
2 are connected to the bidirectional transfer gate circuit 3 via two pairs of mutually independent I/O lines 16a and 16b, respectively.

SRAM array 2 includes 16 bit line pairs SBL each connected to 16 pairs of I/O lines via bidirectional transfer gate circuit 3. This SRAM array 2 includes 16 pairs of bit lines and 256 word lines in the case of a capacity of 4K bits. Therefore, this SRA
In the M array 2, one row has 16 bits. This SRAM
An SRAM that decodes a row address given externally to the array and selects one row of this SRAM array 2.
A row decoder 21, an SRAM column decoder 22 that decodes an externally applied column address and selects the corresponding column of the SRAM array 2, and a column address selected by the SRAM row decoder 21 and the SRAM column decoder 22 when reading data. It includes a sense amplifier circuit 23 that amplifies and outputs data in memory cells. This S
The SRAM bit line pair SBL selected by the RAM column decoder 22 is connected to a common data bus, and data is input/output to/from the outside of the device via an input/output buffer (not shown). DRAM row decoder 14 and DRAM
The address given to column decoder 15 and the addresses given to SRAM row decoder 21 and SRAM column decoder 22 are mutually independent addresses, and are given through different address pin terminals. Next, a data transfer operation of the semiconductor memory device shown in FIG. 3 will be schematically explained.

The operation of the DRAM portion will be explained. First, the row decoder 14 performs a row selection operation according to an externally applied row address and raises the potential of one word line DWL to "H". Data is read from the memory cells connected to the selected word line DWL to the corresponding 1024 bit lines BL (or /BL).

Next, the sense amplifiers (included in block 13) included in row block 11 including this selected word line DWL are activated all at once to differentially amplify the potential difference between each bit line pair. The reason why only one row block out of the four row blocks 11 is activated in this way is to reduce power consumption associated with bit line charging and discharging during this sensing operation (row blocks including this selected row (The operation method that activates only the block is called the block division operation method).

Next, in accordance with the externally applied column address, the DRAM column decoder 15 performs a column selection operation, and one column selection line C is selected in each column block 12.
SL is placed in the selected state. This one column selection line CS
L selects two pairs of bit lines, and connects the two pairs of bit lines to two pairs of I/O lines 16a and 16b provided corresponding to the block, respectively. This allows multiple bits (16 bits in this embodiment) from DRAM array 1.
data is read onto multiple I/O line pairs 16a and 16b.

Next, the operation of the SRAM portion will be explained. The SRAM row decoder 21 performs a row selection operation according to the row address given from the outside, and the SRAM array 2
Select one word line from . As described above, 16-bit memory cells are connected to one SRAM word line. Therefore, according to the selection operation of this one word line, 16 static type memory cells (SRAM cells) are connected to 16 pairs of bit lines SBL.

I/O line pair 16 for DRAM array 1
After 16 bits of data are transmitted to a and 16b, this bidirectional transfer gate circuit 3 is turned on, and 16 bits of data are transmitted to 16 bits.
A pair of I/O lines 16a and 16b are connected to 16 pairs of bit lines SBL of the SRAM, respectively. As a result, the data transmitted on the 16 I/O line pairs 16a and 16b are written into the 16-bit memory cells already selected in the SRAM array 2, respectively.

A sense amplifier circuit 23 and a column decoder 22 provided in the SRAM are used for transmitting and receiving data between memory cells in the SRAM array 2 and internal data lines for inputting and outputting external data.

The address for selecting an SRAM cell in this SRAM array 2 can be set completely independently of the address for selecting a dynamic memory cell (DRAM cell) in the DRAM array 1. Therefore, the 16-bit memory cell selected in the DRAM array 1 can exchange data with the memory cell at any position (row) in the SRAM array 2, and the direct mapping method, set associative method, and full All associative mapping schemes can be implemented without changing the array arrangement and configuration.

In the above explanation, from DRAM to SRA
Although the operation of the batch transfer of 16 bits to M has been explained in principle, the batch transfer of 16 bits from the SRAM array 2 to the DRAM array 1 is performed according to the same operation, and the data is simply transferred by the bidirectional transfer gate circuit 3. The only difference is that the direction of flow is reversed. Next, the configuration and operation of the cache built-in semiconductor memory device according to the present invention will be explained in detail.

FIG. 3 is a diagram showing a specific configuration of the main parts of the semiconductor memory device shown in FIG. 3. In Figure 3, DRA
A portion related to data transfer of one memory block MBij of M array is representatively shown. In Figure 3, D
RAM memory block MBij includes a plurality of DRAM cells DMC arranged in rows and columns. DRAM cell DMC
includes one transistor Q0 and one capacitor C0. A constant potential Vgg is applied to one electrode (cell plate) of this memory capacitor C0.

Memory block MBij further includes a DRAM word line DWL to which one row of DRAM cells DMC is connected, and a DRAM bit line pair DBL to which one column of DRAM cells DMC is connected. This DRA
M bit line pair DBL consists of two bit lines BL and /B.
It is composed of L. Complementary signals are transmitted to bit line BL and bit line /BL. DRAM cell DMC
is the DRAM word line DWL and DRAM bit line pair DB
They are placed at each intersection of L.

A DRAM sense amplifier DSA is provided for each DRAM bit line pair DBL to detect and amplify the potential difference on the corresponding bit line pair. This DR
AM sense amplifier DSA receives sense amplifier activation signal φS
Its operation is controlled by a sense amplifier activation circuit SAK which generates sense amplifier drive signals φSAN and /φSAP in response to ANE and /φSAPE. DRAM
The sense amplifier DSA includes a first sense amplifier part in which p-channel MOS transistors are cross-coupled and boosts the bit line potential on the high potential side to the operating power supply potential Vcc level in response to the signal /φSAP, and an n-channel MOS transistor. M.O.S.
It includes a second sense amplifier section in which the transistors are cross-coupled and discharge the potential of the bit line on the low potential side to, for example, the ground potential level potential Vss in response to the signal φSAN.

The sense amplifier activation circuit SAK turns on in response to the sense amplifier activation signal /φSAPE, and includes a sense amplifier activation transistor TR1 for activating the first sense amplifier portion of the DRAM sense amplifier DSA; It is turned on in response to the sense amplifier activation signal φSANE, and the second
includes a sense amplifier activation transistor TR2 that activates the sense amplifier portion of the transistor. Transistor TR1 is composed of a p-channel MOS transistor, and transistor TR2 is composed of an n-channel MOS transistor. When transistor TR1 is turned on, it transmits a drive signal /φSAP at the operating power supply potential Vcc level to one power supply node of each sense amplifier DSA. When the transistor TR2 is turned on, it supplies a signal φ at the potential Vss level to the other power supply node of the DRAM sense amplifier DSA.
Convey the SAN.

Signal line /φ to which signals /φSAP and φSAN from sense amplifier activation circuit SAK are output.
An equalize transistor TEQ is provided between SAP and signal line φSAN to equalize both signal lines in response to equalize instruction signal φEQ. As a result, sense amplifier drive signal lines /φSAP and φSAN are precharged to an intermediate potential of (Vcc+Vss)/2 during standby.

For each DRAM bit line pair DBL,
A precharge/equalize circuit PE is provided which is activated in response to a precharge/equalize signal φEQ to precharge and equalize each bit line of a corresponding bit line pair to a predetermined precharge potential Vbl.

The DRAM memory block MBij is further provided for each DRAM bit line pair DBL and turns on in response to a signal potential on a column selection line CSL, and connects the corresponding DRAM bit line pair DBL to the local I.
Includes a column selection gate CSG connected to /O line pair LIO. Column selection line CSL is provided in common for two pairs of DRAM bit lines, thereby selecting two DRAM bit line pairs DBL at the same time. Two pairs of local I/O lines, LIOa and LIOb, are provided so that they can each receive data from the two simultaneously selected DRAM bit line pairs.

Memory block MBij further includes an IO gate IOG that connects local I/O line pair LIOa and LIOb to global I/O line pair GIOa and GIOb, respectively, in response to block activation signal φBA.
a and IOGb. Column selection line CSL extends in the row direction across one column block shown in FIG. 2, and global I/O line pair GIOa and GIOb also extends in the row direction across one column block. Local I/
O line pair LIOa and LIOb extends in the column direction only within one memory block.

In correspondence with FIG. 2, I/O lines 16a and 16b connect local I/O line pairs LIOa and LIOb and LIO gates IOGa and IOGb, respectively.
corresponds to global I/O line pair GIOa and GIOb.

The SRAM has SRAM word lines SWL to which one row of SRAM cells SMC is connected, and SRAM word lines SWL to which one column of SRAM cells SMC is connected.
The bit line pair SBL and the SRAM bit line pair SBL each include an SRAM sense amplifier SSA that is provided to detect and amplify the potential difference between the corresponding bit line pair.

Bidirectional transfer gate circuit 3 includes bidirectional transfer gates BTGa and BTGb provided between SRAM bit line pair SBL and global I/O line pair GIO. Bidirectional transfer gates BTGa and BTGb both transfer SRAM bit line pair SBL and global I/O line pair G in response to data transfer instruction signals φTSD and φTDS.
Data is transferred between IOa and GIOb. The data transfer instruction signal φTSD is transferred from the SRAM part to the DR
The data transfer instruction signal φTDS instructs data transfer to the AM portion, and the data transfer instruction signal φTDS instructs data transfer from the DRAM portion to the SRAM portion.

FIG. 4 is a diagram showing an example of the configuration of bidirectional transfer gate BTG. In FIG. 4, the bidirectional transfer gate BT
G (BTGa or BTGb) is activated in response to data transfer instruction signal φTSD, and SRAM bit line pair S
Drive circuit DR1 that transmits data on BL to global I/O line pair GIO and data transfer instruction signal φTDS
includes a drive circuit DR2 that is activated in response to and transmits data on the global I/O line pair GIO onto the SRAM bit line pair SBL. Drive circuit DR1 and DR
2 is set to an output high impedance state when data transfer instruction signals φTSD and φTDS are inactive.

FIG. 5 is a signal waveform diagram showing the operation during data transfer from the DRAM array to the SRAM array. The data transfer operation from the DRAM array to the SRAM will be described below with reference to FIGS. 3 and 5.

Precharge instruction signal φE before time t1
While Q is in the active state "H", sense amplifier drive signal lines φSAN, /φSAP, local I/O line pair LIO, and global I/O line pair GIO are each at Vcc/2.
It is held at the precharge potential. At this time, the precharge/equalize circuit PE is activated, precharging the DRAM bit line pair DBL to a precharge potential of Vcc/2 (=Vbl) and equalizing the potential of each bit line BL, /BL. .

At time t1, precharge instruction signal φ
When EQ falls, precharge equalization circuit PE
And the equalizing transistor TEQ becomes inactive. As a result, the equalization operation of the sense amplifier drive signal lines φSAN and /φSAP is completed, and the equalization/precharge operation of the DRAM bit line pair DBL is stopped, and the DRAM bit line pair DBL and the sense amplifier drive signal lines φSAN and /φSAP are is the intermediate potential Vcc/2(
However, it is in a floating state with Vss=0V).

Thereafter, a row selection operation is performed by the row decoder 14 (see FIG. 2) according to an externally applied address, and one word line DWL is selected in the DRAM array 1 (see FIG. 2) at time t2. The potential of this selected word line DWL rises to "H". One row of memory cells connected to this selected word line DWL is connected to a corresponding DRAM bit line pair DBL (DRAM bit line BL or /BL), and the potential of each DRAM bit line pair DBL is set to the memory to which it is connected. Changes according to the data in the cell. In FIG. 5, a DRAM bit line pair DB when a memory cell storing a potential "H" is selected is shown.
It shows the potential change of L.

At time t3, sense amplifier activation signal φSANE rises from the ground potential Vss to the operating power supply potential Vcc level, and transistor TR2 included in sense amplifier activation circuit SAK is turned on. As a result, the second sense amplifier section included in DRAM sense amplifier DSA is activated, and the bit line on the low potential side of DRAM bit line pair DBL is discharged to the ground potential GND level.

At time t4, sense amplifier activation signal /φSAPE falls from potential Vcc to ground potential GND level, and transistor TR1 included in sense amplifier activation circuit SAK is turned on. This results in DR
A first sense amplifier portion included in AM sense amplifier DSA is activated, and the potential of the high potential bit line of DRAM bit line pair DBL is charged to the operating power supply potential Vcc level.

At time t5, one column selection line CSL is selected according to the column selection signal from the DRAM column decoder 15 (see FIG. 2), and the potential of the selected column selection line CSL rises to "H". . This results in 2
DRAM bit line pair DBL is connected to local I/O line pair LIO (LIOa and LI
Ob). As a result, the potential on the selected DRAM bit line pair DBL is transmitted onto the local I/O line pair LIO, and the potential on the local I/O line pair changes from the precharge potential Vcc/2.

At time t6, block activation signal φB
A rises to "H" only for the selected row block, and the I/O gate IOG is turned on. This causes the signal potential on the local I/O line pair LIO to change to the global I/O line pair LIO.
/O line pair GIO. Here, the selected row block indicates a row block including the selected word line DWL. The selected row block is designated, for example, by decoding the upper two bits of the row address used for DRAM word line selection. By performing the block division operation in this manner, current consumption can be reduced.

On the other hand, in the SRAM, a row selection operation is performed by the SRAM row decoder 21 (see FIG. 2) at time ts1, and one SRAM is selected in the SRAM array.
RAM word line SWL is selected and this selected SR
The potential of AM word line SWL rises to "H". DRA
The row selection operation in M and the row selection operation in SRAM are performed asynchronously. The data of the SRAM cells connected to the SRAM word line SWL are stored in the corresponding SRAM.
The signal is transmitted onto bit line pair SBL. This allows S.R.A.
The potential of M bit line pair SBL is precharge potential Vcc/
2 to a potential corresponding to the storage information of the corresponding SRAM cell.

At time t7, data transfer instruction signal φT
DS rises to "H" for a certain period of time. Before time t7, the data of the DRAM cell has already been transmitted to the global I/O line pair GIO, and the SRAM bit line pair SB
An SRAM cell is connected to L. In response to data transfer instruction signal φTDS, bidirectional transfer gate BTG is activated and transmits the signal potential on global I/O line pair GIO onto corresponding SRAM bit line pair SBL. Data is thereby transferred from the DRAM cell to the SRAM cell.

The relationship is such that the time t7 at which this data transfer instruction signal φTDS is activated is later than both the time t6 at which the block activation signal φBA rises and the time ts1 at which the SRAM word line SWL is selected. As long as the following is satisfied, time ts1 and time t1 to time t6
The context is arbitrary. Data transfer instruction signal φTSD from SRAM to DRAM is maintained at an inactive state of "L" in this cycle.

At time t8, the potential of the selected DRAM word line DWL falls to "L", and at time ts2
The potential of the SRAM word line SWL selected in “
The data transfer cycle from DRAM to SRAM is completed by falling to "L" and each signal returning to its initial state.

As mentioned above, DRAM column decoder 1
5 (see FIG. 2) selects one column selection line CSL in each column block 12. One column selection line C
SL selects two DRAM bit line pairs DBL. D
Data transfer from RAM to SRAM is performed in parallel for each column block. Therefore, in the embodiment shown in this figure, 16 bits of data are transferred at once. However, this relationship applies to a configuration in which eight column blocks are provided and two DRAM bit line pairs are selected from each column block, and the number of bits of data transferred at once is the same as that of this column block. or the number of DRAM bit line pairs selected at one time. This makes it possible to set an appropriate block size.

As shown in FIG. 5, when the DRAM word line drive signal DWL falls to the inactive state at approximately time t8, the data transfer instruction signal φTDS also falls to "L". At this time t8, local I/O
Line pair LIO and SRAM bit line pair SBL are disconnected, and the DRAM array and SRAM array are electrically disconnected. After this time t8, the DRAM section and the SRAM
It is possible to operate independently of the section. Therefore, as shown in FIG. 6, at time t8', the data transfer instruction signal φTDS
is inactive, the word line drive signal DWL is still in the active state "H" in the DRAM array.
is maintained. At this time, the DRAM cannot be newly accessed from the outside, but the SRAM array section can be accessed from the outside.

That is, as shown in FIG. 6, at time t8'
When the data transfer instruction signal φTDS is brought down to “L”, even if the DRAM array is in the active state,
After the SRAM array enters the standby state at time ts2, it becomes possible to newly access it after a predetermined period of time. Therefore, after this time t8', SR
The AM section can be accessed regardless of the state of the DRAM. For example, at time t8', data at the time of a cache miss can be read from the SRAM array.

It is also possible to access the SRAM by setting a new external address before returning the DRAM to the standby state. This means that SRAM is a RAM like DRAM.
This is because it does not require any S precharge operation and can be accessed at high speed after returning to the standby state.

In FIG. 6, at time t9', DR
AM word line drive signal DWL falls to "L", equalize signal φEQ is activated at time t10, and D
Equalization and precharging operations of RAM bit line pair DBL begin. At this time, the sense amplifier drive signal lines φSAN and /φSAP are similarly equalized. In DRAM, from time t9', the number 10
At time t11 after n seconds have elapsed, the device including its peripheral circuits returns to the standby state. This DRAM array cannot be accessed until after a predetermined RAS precharge time has elapsed. However, in the SRAM array, SRA at time ts2
After setting the M word line SWL1 to a non-selected state, at time ts3 several nanoseconds later, another SRA is selected according to the external address.
M word line SWL2 is selected and this selected SRAM
Memory cells connected to word line SWL2 can be accessed (data read or written).

From time ts2 when data transfer instruction signal φTDS falls to the inactive state "L", then SRA
Time ts at which M word line SWL2 is activated
The time between 3 and 3 is set to an appropriate value using external specifications. In this way, before the DRAM returns to standby state, the SRA
By enabling access to M, it is possible to obtain a semiconductor memory device that operates at high speed, especially a semiconductor memory device with a built-in cache.

The selection period of the word line SWL2 of this SRAM is very short because it is not necessary to perform a column selection operation after the sensing and latching operations of the sense amplifier in the DRAM.
access is completed. From this time ts3 to time ts
In normal SRAM, the time of 4 is at most 10n.
It takes about seconds, and when the DRAM is on standby, its SRAM
Access is completed. In this configuration, the SRAM is accessed before the DRAM array returns to standby state.
This is made possible by the semiconductor memory device of the present invention, in which SRAM and DRAM can be addressed and accessed using separate addresses.

FIG. 7 is a signal waveform diagram showing the operation during data transfer from SRAM to DRAM. The data transfer operation from SRAM to DRAM will be described below with reference to FIGS. 3 and 7. The operation of the DRAM part is from time t1 to time t6 from DRAM to S shown in FIG.
This is exactly the same as when transferring data to RAM. Also, in the operation of the SRAM part, S
The rise of the potential of RAM word line SWL to "H" is exactly the same as the waveform diagram shown in FIG.

After time ts1 and time t6, DRAM bit line pair DBL becomes global I/O line pair GI.
SRA is connected to SRAM bit line pair SBL.
After the M cell (SMC) is connected, the data transfer instruction signal φTSD is activated for a certain period from time t7 and becomes “H”.
stand up. In response, bidirectional transfer gate BTG is activated to transfer the signal on SRAM bit line pair SBL to global I/O line pair GIO (GIOa, GIOb) and local I/O line pair LIO (LIOa, LIOb). The data is transmitted to the DRAM bit line pair DBL via the DRAM bit line pair DBL. This results in
DR connected to the selected DRAM bit line pair DBL
Data in the AM cell is rewritten. That is, S
Data in the RAM cell is transferred to the DRAM cell. During this data transfer cycle from the SRAM array to the DRAM array, the data transfer instruction signal φTDS is in the inactive state “
In the configuration of the bidirectional data transfer circuit shown in FIG. 4, the transfer instruction signals φTDS and φTSD
Accordingly, only one of the drive circuits DR1 and DR2 is driven. In this case, data transfer from the SRAM array to the DRAM array and data transfer from the DRAM array to the SRAM array cannot be performed simultaneously. For this reason, SRAM arrays and DRAM
There may be cases where it is not possible to cope with the need for array data transfer.

FIG. 8 is a diagram showing another example of the structure of the bidirectional data transfer gate. In FIG. 8, a bidirectional transfer gate circuit 80 corresponds to the transfer gate BTG included in the bidirectional transfer gate circuit 3 shown in FIG. The unit bidirectional data transfer circuit 80 includes a first latch 8 that amplifies and holds data transferred from the SRAM array through the gate 81.
5 and the data transferred from the DRAM array to gate 8.
4, and includes an amplifier 86 that receives and amplifies the signal via the signal. This amplifier circuit 86 also has a data holding function. Gate 81 transmits data on SRAM bit line pair SBL, *SBL to latch 85 in response to transfer control signal DTL. The gate 82 transfers the latched data of the latch 85 to the global I/O line GIO,* in response to the transfer control signal DTA.
Convey to GIO. The gate 83 transfers the data amplified by the amplifier 86 to a control signal DTS2 (control signal DTS).
In response, the signal is transmitted to the SRAM bit line pair SBL, *SBL. Gate 84 connects global I/O lines GIO, *GI in response to transfer control signal DTS1 (control signal DTS).
The data on O is transmitted to amplifier 86. Control signal WDE
is a control signal generated when requesting access to the DRAM array, and is connected to the internal data bus (write data line pair) D.
The data on BW and *DBW are transmitted to the input section of gate 81. Transfer control signals DTL and DTA are sequentially generated when transmitting data on SRAM bit line pair SBL, *SBL to global I/O line pair GIO, *GIO of the DRAM array. Control signals DTS1 and DTS2 are D
Generated during data transfer from RAM array to SRAM array. The control signals DTS1 and DTS2 are substantially the same control signals and are generated at substantially the same timing. These control signals DTL, DTA, DTS1 and DTS2 are generated in the same manner as the aforementioned control signals φTDS and φTSD. These control signals are generated from a bidirectional data transfer control circuit, as will be explained later. Here, the symbols SBL and GIO indicate one signal line when used in pairs with the symbols *SBL and *GIO.

FIG. 9 is a diagram showing an example of a specific configuration of the unit bidirectional transfer gate circuit 80 shown in FIG. 8. In FIG. 9, the gate 81 includes a gate circuit 81a coupled to the SRAM bit line SBL and a complementary SRAM bit line *SBL.
includes a gate circuit 81b coupled to the gate circuit 81b. Gate circuit 81
A includes an n-channel MOS transistor 811a whose gate is connected to the SRAM bit line SBL, and an n-channel MOS transistor 812a whose gate is supplied with a transfer control signal DTL. Gate circuit 81b includes an n-channel MOS transistor 811b whose gate is coupled to SRAM bit line *SBL, and an n-channel MOS transistor 812b whose gate is supplied with transfer control signal DTL. Transistors 811a and 81
One conduction terminal of 1b is connected to ground potential Vss. Gate circuits 81a and 81b invert data on corresponding SRAM bit lines SBL and *SBL in response to control signal DTL and transmit the inverted data to latch circuit 85.

Latch circuit 85 includes an inverter latch that latches data in gate circuits 81a and 81b. This inverter latch is composed of inverter circuits IVL1 and IVL2. This latch circuit 85 is an inverter circuit IVL3 that inverts and transmits the inverter output.
and IVL4. Inverter circuit IVL3
inverts the data from the gate circuit 81a. Inverter circuit IVL4 inverts the output of gate circuit 81b. Gate 82 turns on in response to transfer control signal DTA, and connects the output of latch circuit 85 to global I/O line G.
IO, *GIO, and n-channel MOS transistors 82a and 82b for transmitting to the input of gate 84.

Gate 84 is turned on in response to an n-channel MOS transistor 841a which receives data on global I/O line GIO and the output of gate 82a at its gate, and data transfer control signal DTS1, and controls the output of transistor 841a. n transmitted to the input of amplifier 86
Channel MOS transistor 842 and transfer control signal D
Turns on in response to TS1, and transistor 842
a and an n-channel M that transmits one output of the amplifier 86.
Includes an OS transistor 843a.

Gate circuit 84b, like gate circuit 84a, is an n-channel MOS whose gate receives data on global I/O line *GIO and the output of gate 82b.
It includes a transistor 841b and an n-channel MOS transistor 843b that turns on in response to a transfer control signal DTS1 and transmits the output of a transistor 842b.

[0103] The amplifiers 86 have p
Channel MOS transistors TM1a, TM1b and p-channel MOS transistors T connected in parallel with each other
Contains M2a and TM2b. The transfer control signal DTS1 is applied to the gate of the transistor TM1a, and the gate of the transistor TM1b is applied to the gate of the transistor TM2a, TM2b.
One of the conduction terminals is connected. One conduction terminal of transistors TM1a and TM1b is connected to the gate of transistor TM2a. Transfer control signal DTS1 is applied to the gate of transistor TM2b. Transistor TM1
The other conductive terminals of a, TM1b, and TM2a, TM2b are connected to the power supply potential (Vcc).

Gate 83 includes an n-channel MOS transistor 83a that turns on in response to transfer control signal DTS2 and transmits data from transistor 843a to SRAM bit line *SBL and gate 87a. This gate 83 also turns on in response to the transfer control signal DTS2, and connects the output of the transistor 843b to the SR.
It includes an n-channel MOS transistor 83b that transmits information to AM bit line SBL and gate circuit 87b.

Gate 87 connects data line DBW and SRAM
It includes a gate circuit 87a that connects the bit line *SBL, and a gate circuit 87b that connects the data line *DBW and the SRAM bit line SBL. The gate circuit 87a is a DRAM
A MOS transistor 871a is turned on in response to the output CD of a column decoder (which may be shared with the output of the SRAM column decoder), and a MOS transistor 871a is turned on in response to an access instruction signal WED to the DRAM array. It includes an n-channel MOS transistor 872a that connects internal data line DBW to transistor 871a. Gate circuit 87b connects internal data line *DBW to transistor 871b, which turns on in response to SRAM column decoder output CD, and turns on in response to DRAM array access instruction signal WDE.
n-channel MOS transistor 872 connected to 71b
Contains b.

This control signal WDE will be explained later, but
This is a control signal generated when a DRAM array of a semiconductor memory device is accessed from the outside (particularly when data is written). This instruction to access the DRAM array is generated in response to external control signals (CI#, W#; explained later). Internal data lines DBW and *DBW are data lines for transmitting write data and are connected to an input circuit (described later) included in the input/output circuit. Next, the operation of the bidirectional data transfer gate circuit shown in FIGS. 8 and 9 will be described with reference to FIGS. 10 and 11, which are operational waveform diagrams.

First, the data transfer operation from the SRAM array to the DRAM array will be explained with reference to FIG.

First, at time t1, a word line is selected in the SRAM array, and the SRAM bit line pair S
The data on BL is determined according to the data of the memory cell connected thereto.

Subsequently, in response to a data transfer instruction from the SRAM array to the DRAM array, a data transfer instruction signal DTL is first generated at time t2. In response, transistors 812a and 812b shown in FIG. 9 are turned on, and SRAM bit lines SBL and *SBL
The data is inverted and transmitted to the latch 85. latch 8
5 uses this data to inverter latches IVL1, IVL2
Latch with. This latched data is inverted by inverter circuits IVL3 and IVL4 and sent to gate circuit 82.
a and 82b. Therefore, when the data transfer instruction signal DTL is generated at time t2, the latched data of the latch 85 is transferred to the corresponding SRAM bit line SBL,
*The value corresponds to the contents of SBL.

When the latched data in latch 85 is determined, transfer control signal DTA is then generated at time t3. In response, gate circuits 82a and 82
b is turned on, and the latched data of latch 85 is transmitted to global I/O lines GIO and *GIO, respectively.

At this time, since data transfer from the DRAM array to the SRAM array is not performed, the control signal DTS(
DTS1, DTS2) and the DRAM array access instruction signal WDE are in an inactive "L" state. Therefore, transistors 842a, 842b and gate circuits 83a, 83b are all in an off state. Amplifier 86 is also inactive.

Next, the data transfer operation from the DRAM array to the SRAM array will be explained with reference to FIG.

[0113] Before time t1 shown in FIG.
A word line selection operation is performed in the M array, and the data of the selected memory cell is transferred to the global I/O line pair GIO.
It is transmitted upward and is finalized at time t1.

Subsequently, at time t2, a control signal DTS (DTS1, DTS2) instructing data transfer from the DRAM array to the SRAM array is generated. In response, transistors 842a, 842b, 83a, 83
b is turned on, and gate 84 and gate 83 are turned on. In the amplifier 86, the control signal DTS
When (DTS1) is “L”, transistors TM1a and TM2b are on, and the transistor 84
The potential of one node of nodes 2a and 842b is held at "H". When the control signal DTS is generated at time t2, transistors TM1a and TM2b are turned off. The on/off states of transistor TM1a and transistor TM2b are determined by D via transistors 842a and 842b.
It changes depending on the data transmitted from the global I/O lines GIO and *GIO of the RAM array. Control signal DTS
is not generated, the input/output nodes of amplifier 86 are charged to power supply potential Vcc. Global I/O line GI
When the data to O is "H", the transistor 841a is on and the transistor 841b is off. In this state, when transfer control signal DTS1 is generated, transistors 842a and 842b are turned on, and transistors TM1a and TM2b are turned off. Therefore, the potentials at the input/output nodes of transistors TM1b and TM1a are discharged to ground potential Vss via transistors 842a and 841a. On the other hand, transistor 8
Since the transistor 41b is in the off state, the transistors TM2a,
The input/output node of TM2b is maintained at "H" by turning on the transistor TM2a. As a result, the data on the global I/O line GIO is inverted and transmitted onto the SRAM bit line *SBL via transistors 843a and 83a, and the data on the global I/O line *
Data on GIO is transferred to transistors 843b and 83b
The signal is inverted and transmitted onto the SRAM bit line SBL via the SRAM bit line SBL.

At this time, since data is not transferred from the SRAM array to the DRAM array, the control signal DTA
and DTL are at "L". This transfer control signal DTS
is the transfer control signal φ shown in FIGS. 4, 5, 6, and 7.
This becomes a signal equivalent to TDS.

According to the configuration shown in FIGS. 8 and 9,
SRAM bit line SBL, *SBL data is sent to gate 8
1, global I via latch 85 and gate 82
It is transmitted to /O lines GIO and *GIO. In addition, data on global I/O lines GIO and *GIO is transferred to SRAM bit line SB via gate 84, amplifier 86 and gate 83.
L, *SBL. Therefore, according to this configuration, the data transfer paths are different, and the latch 85
and the functions of the amplifier 86, the D
Data transfer to RAM array and SR from DRAM array
It is possible to overlap the execution with data transfer to the AM array, and data transfer between both arrays can be performed at high speed.

Particularly, according to this configuration, write data is sent to the gates 87a and 87b via the data lines DBW and *DBW.
It becomes possible to transmit the data from the signal to the global I/O lines GIO and *GIO via the gate 81, latch 85, and gate 82. Therefore, the common write data line DBW
, *DBW can be used to selectively write data to the DRAM array and the SRAM array. In this case, it is possible to write to both or only one. An instruction to write data into the DRAM array is given by signal WDE.

Therefore, if the configuration shown in FIGS. 8 and 9 is used, even if data is written to the DRAM array via the SRAM bit lines SBL, *SBL, the word line selection signal in the SRAM array On the other hand, there is no need to add an access instruction signal to the DRAM array as a condition signal, and data in the selected memory cell of the high-speed SRAM array can be transferred to the write data bus DBW.
*It is no longer necessary to add the DRAM array access instruction signal as a condition signal to the signal connected to the DBW, making it possible to write data to the SRAM array at high speed, and also to write data to the DRAM array at high speed. becomes.

FIG. 12 is a diagram showing another example of the structure of the bidirectional transfer gate circuit. In addition to the configuration shown in FIG. 8, the unit bidirectional transfer gate circuit 90 shown in FIG.
It includes a gate 88 that communicates to latch 85 in response to E1. Control signals WDE0 and WDE1 correspond to control signal WDE shown in FIG. 8, and set conditions on the column decoder output of the DRAM. That is, the control signal WDE0 applied to the gate 87 is not generated when writing data to the DRAM array, and the gate 87 is turned off. At this time, only control signal WDE1 is generated, gate 88 is turned on, and data on write data transmission lines DBW, *DBW is transmitted to latch 85. In this way, you can write data to both the SRAM array and the DRAM array, or write data to both the SRAM array and the DRAM array.
By selectively generating write control signals WDE0 and WDE1 depending on whether data is to be written only to the M array, data can be written more efficiently to a large capacity DRAM at high speed.

FIG. 13 is a diagram showing the configuration of yet another bidirectional transfer gate circuit. In this configuration, gate 8
Gate GT1 is turned on in response to the data write instruction signal WDE to the DRAM array, and gate 8 is turned on in response to the output CD of the column decoder (this is an output for selecting a column of the DRAM array). Including gate GT2. In this configuration, gate 88 connects direct write data lines DBW, *DBW to latch 85 . The configurations of other circuit blocks are similar to the configuration of the bidirectional transfer gate circuit shown in FIG. According to this configuration, the transfer control signals WDE0 and WDE1 (these control signals are substantially the same) are conditioned (ANDed) by the column decoder output, and this signal The operation of gate 88 is controlled.

[0121] Note that FIGS. 8, 12, and 13 described above
The bidirectional transfer gate circuit shown in FIG.
, *SBL and global I/O lines GIO, *GIO. However, the configuration of this bidirectional transfer gate circuit can also be applied to a general semiconductor memory device, as shown in FIG. That is, in FIG. 14, a semiconductor storage device 95 includes a large capacity memory (generally a DRAM array) 93 and a high speed memory (generally an SRAM array) 94. When performing data transfer such as "copy back" between the memory 93 and the memory 94, FIGS. 8, 12 and 13
By using the configuration shown in , it is possible to provide the first latch 91 and the second latch 92 and set their respective data transfer paths independently, and it is possible to transfer data from a large-capacity memory 93 made of DRAM to a high-speed memory 94 made of SRAM. It is possible to transfer data in the opposite direction while transferring data to the other direction. In this case, independent data transfer paths include data transfer from large capacity memory 93 to latch 91 and high speed memory 9
Data transfer from the latch 91 to the high-speed memory 94 made of SRAM and data transfer from the latch 92 to the large-capacity memory 93 made of DRAM can be performed independently. This means that they can be performed in parallel. Therefore, no problem occurs even if data transfer within each memory 93 and 94 is performed via a common bus. In this way, as shown in FIG. 14, data transfer can be performed at high speed by activating the latch 91 and the latch 92 at overlapping timings or by activating both at the same time.

FIG. 15 is a diagram showing the layout of an array of a semiconductor memory device according to another embodiment of the present invention. Figure 1
The CDRAM shown in Figure 5 is a 4 Mbit DRAM array and 1
6K bit SRAM array. That is, Figure 1
The CDRAM No. 5 includes four CDRAMs shown in FIG. In FIG. 15, the CDRAM includes four memory mats MM1, MM2, MM3 and MM4 each having a capacity of 1 Mbit. DRAM memory mat MM1~MM
4 includes a memory cell arrangement of 1024 rows (word lines) and 512 columns (bit line pairs). DRAM memory mats MM1 to MM4 are each divided into 32 memory blocks MB each having a configuration of 128 columns (bit line pairs)×256 rows (word lines).

One memory mat MM is divided into four memory blocks in the row direction and eight blocks in the column direction. As shown in FIG. 15, unlike the arrangement of the DRAM shown in FIG. 2, the 1M bit memory mat is divided into eight parts in the column direction and four parts in the row direction.
This is for storing it in a rectangular package which will be explained later. A DRA is installed in the center of each column in the memory block MB.
An M sense amplifier DSA and a column selection gate CSG are arranged corresponding to each bit line pair DBL. Memory block MB is divided into an upper memory block UMB and a lower memory block LMB centering around sense amplifier DSA and column selection gate CSG. During operation, one of the upper and lower memory blocks UMB and LMB is connected to sense amplifier DSA and column selection gate CSG. This sense amplifier DSA and column selection gate CS
Which of the upper and lower memory blocks UMB and LMB is connected to G is determined by the address. Such a configuration in which one memory block MB is divided into two upper and lower memory blocks UMB and LMB, and only one is connected to the sense amplifier DSA and column selection gate CSG, is common in, for example, a DRAM with a shared sense amplifier configuration of 4 Mbits or more. It is used.

One memory mat MM includes two activation sections AS. One word line is selected in this activation section AS. That is, in the configuration shown in FIG. 15, unlike the configuration shown in FIG. 2, one word line is divided into two and distributed to each activation section. Therefore, selecting one word line in one memory mat MM is equivalent to selecting one word line in each activation section AS.

This semiconductor device (CDRAM) further includes four DRAM row decoders DRD1, DRD2, DRD3 and DRD4 for selecting one word line from four DRAM memory mats MM1 to MM4. The DRAM row decoders DRD1-DRD4 select one word line from each memory mat MM1-MM4. Therefore, in the CDRAM shown in FIG. 15, four word lines are selected at once. DRAM
Row decoder DRD1 connects memory mats MM1 and MM
2. Select one row from the corresponding activation section AS. DRA
M row decoder DRD2 selects one row from lower activation section AS of memory mats MM1 and MM2. DRAM row decoders DRD3 and DRD4 are DRA
One row is selected from each of the upper activation section AS and the lower activation section AS of M memory mats MM3 and MM4.

The CDRAM further includes a DRAM column decoder DCD for selecting two columns (bit line pairs) from each column block of memory mats MM1 to MM4 of the DRAM. A column selection signal from DRAM column decoder DCD is transmitted to column selection line CSL shown in FIG. This column selection line CSL extends so as to be shared by the upper activation section AS and the lower activation section AS. Therefore, in the configuration shown in FIG. 15, four columns are selected from one column block (in FIG. 15, a block consisting of eight memory blocks MB divided in the column direction) by a column selection signal from the DRAM column decoder DCD. Select.

Columns selected by column decoder DCD are connected to respective global I/O line pairs GIO. Two global I/O line pairs GIO extend in the column direction in each column block in one activation section AS. The connection structure between the global I/O line pair GIO and the local I/O line pair LIO in each column block will be described in detail later.

The CDRAM shown in FIG.
SRAM consisting of SRAM cells with a capacity of K bits
It includes array blocks SMA1 to SMA4. two SRs
SRAM row decoders SRD1 and SRD2 are provided in the center of both AM array blocks so as to be shared by both blocks. SRAM row decoder SRD1 is shared by SRAM array blocks SMA1 and SMA3. SRAM row decoder SRD2 is shared by SRAM array blocks SMA2 and SMA4. The details of the configuration of this SRAM array block SMA will be explained later.

This CDRAM has four input/output buffer circuits I to input and output data in units of 4 bits.
Includes OB1, IOB2, IOB3 and IOB4. These input/output buffer circuits IOB1 to IOB4 are connected to the sense amplifier and column decoder block SC for SRAM via a common data bus (internal data bus), respectively.
Connected to DA. In the configuration shown in FIG. 15,
Data input/output is shown to be performed via the sense amplifier and column decoder block SCDA for the SRAM, but this is configured so that data input/output is performed from the bidirectional transfer gate BTG. Good too.

In operation, one word line is selected in each activation section AS. Only the row block containing this selected word line is activated. The remaining row blocks maintain the precharged state. In this selected row block, only the small block UMB (or LMB) including the selected word line is connected to the DRAM sense amplifier DSA and the column selection gate CSG, and the other small memory block LMB (or UMB) is connected to the DRAM sense amplifier DSA and the column selection gate CSG. It is separated from sense amplifier DSA and column selection gate CSG. Therefore, 1/8 of the bit lines are activated (charged and discharged) as a whole. By performing the divided operation in this manner, it is possible to reduce the power consumption associated with charging and discharging the bit lines. Also, one memory block MB is divided into an upper memory block UMB and a lower memory block LMB.
By dividing the bit line into two parts and arranging the sense amplifier DSA in the center, the length of the bit line is shortened, and the ratio of the bit line capacitance Cb to the memory capacitor capacitance Cs, Cb/Cs
can be made small, and a sufficient read voltage can be obtained at high speed.

In each activation section AS, sensing operations are performed in four small blocks UMB (or LMB) in the row direction. In each activation section AS, two pairs of bit lines are selected in one column block by a column selection signal from the DRAM column decoder DCD. The global I/O line pair GIO extends in the column direction so as to be shared by the column blocks of each activation section AS. In each activation section AS, two pairs of bit lines are selected from each column block and connected to two corresponding pairs of global I/O lines GIO. Four pairs of global I to bidirectional transfer gate BTG
/O line pair GIO is connected. 1 memory mat MM
Four bidirectional transfer gates BTG are provided for each. Therefore, from one memory mat MM, 16 pairs of global I/O lines GIO are connected to the SR of the corresponding SRAM array.
It can be connected to AM bit line pair SBL. Next, the layout of this global I/O line will be explained.

FIG. 16 is a diagram showing the arrangement of global I/O lines for one memory mat. In FIG. 16, the global I/O line pair GIO is an upper global I/O line pair UGIO provided for the upper activation section UAS, and a lower global I/O line pair provided for the lower activation section LAS. Including LGIO. This upper global I
/O line pair UGIO and lower global I/O line pair LGIO
are arranged in parallel. Lower global I/O line pair LGI
O passes through the upper activation section UAS, but is not connected to the local I/O line pair LIO in this upper activation section UAS. Global I/O line pair GIO and local I
/O line pair LIO is connected via an IO gate IOG which is a block selection switch. This IO gate IOG
Only those provided in the row block containing the selected word line are turned on by the block selection signal φBA, and connect the corresponding local I/O line pair LIO and the corresponding global I/O line pair GIO. .

Local I/line pair LIO has DRAM sense amplifier DSA and column selection gate CSG arranged in the center of memory block MB in the column direction. placed along the

Word line shunt regions WSR are provided in the column direction between adjacent column blocks. This word line shunt region WSR is a region for making contact between a word line formed of relatively high resistance polysilicon and a low resistance aluminum wiring. This word line shunt region will be briefly explained below.

FIG. 17 is a diagram schematically showing a cross-sectional structure of a selection transistor Q0 (see FIG. 3) included in a DRAM cell. In FIG. 17, the selection transistor Q0 is connected to an impurity region IP formed on the surface of the semiconductor substrate SUB.
R and a bit line B connected to one impurity region IPR.
L, and a polysilicon layer PL formed on the surface of the semiconductor substrate between these two impurity regions IPR. By transmitting a word line drive signal DWL (indicated by the same reference numeral as a signal line and a signal transmitted thereon) to this polysilicon layer PL, a channel is formed on the surface of the semiconductor substrate between this impurity region IPR. The selection transistor Q0 is turned on. Polysilicon has a relatively high resistance. If the resistance of the word line DWL becomes long, a signal delay occurs due to the resistance of polysilicon. In order to make the word line DWL low resistance, a low resistance aluminum wiring AL is provided in parallel with the polysilicon layer PL. Aluminum wiring A
By periodically connecting L and the polysilicon layer PL, the resistance of this word line DWL is lowered. Aluminum wiring AL is formed in the upper layer of bit line BL. Therefore, the area for making contact between the polysilicon layer PL and the aluminum wiring AL is this bit line BL (/
It is necessary to set it in an area where there is no BL), that is, an area where no memory cells are arranged. For this reason, word line shunt regions are provided between column blocks. This connection mode is shown in FIG.

In FIG. 18, a low-resistance aluminum wiring AL is arranged parallel to a relatively high-resistance polysilicon layer PL, which serves as a word line. A word line drive signal DWL is transmitted to this aluminum wiring AL. The aluminum wiring AL and the polysilicon layer PL form a word line shunt region W.
They are periodically connected in the SR by contact layers CNT. By periodically forming contacts between the aluminum wiring AL and the polysilicon layer PL through the contact regions CNT, the resistance of the polysilicon layer PL can be effectively reduced. Thereby, even if the length of one word line becomes long, the word line drive signal WL can be transmitted to the end of the word line at high speed.

FIG. 19 schematically shows the layout of global I/O lines and column selection lines CSL. In FIG. 19, only these layouts for two memory blocks MB are shown. In Figure 19, global I/
O line pair GIO is arranged in word line shunt region WSR. DRAM word line DWL is arranged in a direction perpendicular to global I/O line pair GIO. In FIG. 19, the aluminum wiring AL and the polysilicon layer PL are arranged parallel to each other, and since they overlap in this plan view, they are shown as the same word line DWL. Also,
A column selection line CSL transmitting a column selection signal from a DRAM column decoder is arranged in a direction perpendicular to this DRAM word line DWL.

Although the DRAM bit line pair DBL is not shown in this layout, this column selection line CSL
placed parallel to the The aluminum wiring AL (see FIG. 18) for the DRAM word line DWL is constituted by a first layer aluminum wiring. The column selection line CSL is the second
Consists of layered aluminum wiring. Global I/
The O line is formed of aluminum wiring in the same layer as the column selection line CSL. By arranging the global I/O line pair GIO in this word line shunt region WSR, D
I for connecting the RAM array and the bidirectional transfer gate
Even if the /O line is arranged in a hierarchical structure including local I/O lines and global I/O lines, the chip area does not increase.

FIG. 20 is a diagram schematically showing the configuration of SRAM array block SMA shown in FIG. 15. In FIG. 20, SRAM array block SMA includes 16 bit line pairs SBL and 256 SRAM word lines SWL. SRAM bit line pair SBL and SRAM word line S
An SRAM cell SMC is placed at the intersection with WL. Figure 1
5, in order to make this SRAM array block SMA correspond to a rectangular chip layout,
M bit line pairs SBL are arranged in the row direction of the DRAM array, and SRAM word lines SWL are arranged in the column direction of the DRAM array. This SRAM word line SWL is SR
Connected to AM row decoder SRD.

SRAM bit line pair SBL must be connected to global I/O line pair GIO via bidirectional transfer gate BTG. Therefore, SRAM bit line pair SB
L needs to be connected to the bidirectional transfer gate BTG provided in the lower direction of FIG. 20 (or the upper direction of FIG. 20: this is determined by the arrangement of the memory array). Therefore, in the configuration shown in FIG. 20, the SRAM word line SW
An SRAM bit line lead-out wiring SBLT is arranged in parallel with L. SRAM bit line extraction wiring SBLT is SRA
The same number of bit line pairs SBL of M array block SMA are provided, and each is connected to a corresponding SRAM bit line pair SBL. If this SRAM bit line lead-out wiring SBLT is formed of the same wiring layer as the SRAM word line SWL, there is no need to provide an additional wiring layer formed in a separate manufacturing process, and this SRAM bit line lead-out wiring SBLT can be easily taken out. Wiring SBLT can be realized.

[0141] The SRAM row decoder SRD decodes the SRAM row address from the outside and stores these 256 SRAM row addresses.
One of the RAM word lines SWL is selected. The 16-bit SRAM cell SMC connected to this selected SRAM word line SWL corresponds to the corresponding SRAM bit line pair SBL and SRAM bit line take-out wiring SBL.
Connected to T. During data transfer, bit line take-out wiring SBLT is connected to global I/O line pair GIO via bidirectional transfer gate BTG.

By using the layouts shown in FIGS. 16 and 20, the DRA
The M array is divided into the upper and lower parts of the diagram, and the upper and lower DRA
The SRAM array is arranged centrally between the M array blocks, and the input/output buffer circuit IOB is provided near the SRAM array in the center of the semiconductor memory device (chip).
A structure in which IOBs 1 to IOB4 are provided can be realized. Such a structure in which the SRAM array is arranged centrally at the center of the chip and data input/output is performed from near the center of the chip provides advantages that are extremely suitable for CDRAMs, as shown below.

The first requirement for a CDRAM is high-speed access to the cache register. Placing the SRAM array that functions as a cache register close to the input/output buffer that inputs and outputs data to and from the outside of the device can shorten the length of signal wiring between them, allowing data to be input and output at high speed. It is suitable for meeting the demand for high-speed access.

Furthermore, by arranging the SRAM array in a concentrated manner in the center, the address lines for selecting SRAM cells can be shortened. By shortening the address line, the wiring resistance and parasitic capacitance associated with the address line can be reduced, and SRAM cells can be selected at high speed, which is suitable for realizing high-speed access to the cache register.

In the case of the architecture shown in FIG.
There may be a concern that the wiring for connecting the AM array and the SRAM array becomes long, and the data transfer speed between the DRAM array and the SRAM array decreases. However, data transfer between this DRAM array and SRAM array is caused by a cache miss (
In this case, the access speed of a standard DRAM is usually sufficient, and there is often no need to increase the access speed, so no problem arises in practice. Even in this case, data can be written/read at high speed by using a data transfer device to be described later.

FIG. 21 is a diagram showing an example of the pin arrangement of a package housing a CDRAM according to the present invention. In FIG. 21, a 4M bit DR as shown in FIG.
A pin arrangement for a CDRAM in which an AM and a 16K bit SRAM are integrated on the same chip is shown. This CDR
AM has a lead pitch of 0.8mm and a chip length of 18.4mm.
, 44 pin 300mil. It is housed in a Type II TSOP (Thin Small Outline Package). This CDRAM uses D as a data input/output method.
Includes two types: /Q separation and masktorite. D/Q
Separation is a method of inputting and outputting write data D and output data Q through separate pins. The mask write mode is an operation mode in which the write data D and the output read data Q are outputted through the same pin terminal, and data writing can be masked from the outside.

In order to efficiently supply the power supply potential to the CDRAM and to facilitate the layout of the power supply wiring, three pins are provided for each of the power supply potentials Vcc and Gnd. That is, the external power supply potential Vcc is supplied to the pins of pin number 1, pin number 11, and pin number 33. The power supply potential Vcc applied to the pins with pin numbers 1, 11, and 33 may have the same voltage value as the operating power supply potential Vcc shown in FIG. The configuration may be such that the external power supply potential Vcc is internally stepped down to supply the operating power supply potential. Ground potential Gnd is applied to pins with pin numbers 12, 22, and 34.

[0148] Pin numbers 6 to 8, 15 to 17, 2
Addresses Ac0-Ac11 for the SRAM are given to pins 8-30 and 37-39. DRA
Addresses Aa0 to Aa9 for M are pin numbers 2, 3, and 1.
It is applied to pin terminals 9 to 21, 24 to 26 and 42, 43. Command addresses Ar0 and Ar1 for specifying a special mode, which will be explained later, are also given to the pins with pin numbers 2 and 3. A cache inhibition signal CI# indicating cache access inhibition is applied to the pin terminal with pin number 4. When the cache inhibition signal CI# is set to "L", access to the SRAM array is prohibited, and direct access to the DRAM array (array access) is enabled. A write enable signal W# indicating the data write mode is applied to the pin with pin number 5. A chip select signal E# indicating that this chip has been selected is applied to the pin numbered 18.

A command register designation signal CR# for designating a special mode is applied to the pin numbered 23. When command register instruction signal CR# is "L", command addresses Ar0 and Ar1 applied to pins numbered 2 and 3 become valid, and a special mode is set.

A cache hit signal CH# indicating a cache hit is applied to the pin with pin number 27. If this cache hit signal CH# is at "L", the cache (SRAM) can be accessed. An output enable signal G# indicating an output mode is applied to the pin numbered 40. Clock signal K is applied to pin number 41. A refresh instruction signal R that specifies refresh of the DRAM array is sent to the pin with pin number 44.
EF# is given. This refresh instruction signal REF
When # becomes “L”, DRA is internally activated in that cycle.
Auto-refresh of M array is performed.

[0151] Pin numbers 9, 10, 13, 14, 31, 3
The data given to pins 2, 35, and 36 differ depending on two types of operation modes: D/Q separation and masked write. The operation mode of this D/Q separation and masked write is set by a command register (described later).

In the masked write mode, pins numbered 10, 13, 32, and 35 are used as common data input/output terminals for commonly performing data input/output. Mask try instruction data M0, M1, M2, and M3 indicating which input/output pins data to be applied is to be masked are applied to pins with pin numbers 9, 14, 31, 35, and 36, respectively.

[0153] In D/Q separation mode, pin number 9
, 14, 31 and 36 pins write data D0, D
It is used as a pin for inputting 1, D2 and D3. Pins with pin numbers 10, 13, 32 and 35 are used as data output pins for outputting read data Q0, Q1, Q2 and Q3.

SRAM addresses Ac0 to Ac11 are non-multiplexed and row and column addresses are given simultaneously. DRAM address (array address) Aa0 to Aa
9 is given by multiplexing a row address and a column address. In the pin arrangement shown in FIG. 21, standard D
Row address strobe signal /RAS and column address strobe signal /CAS, which are normally used in RAM, are not used. CDRAM according to the invention
Control signals and data are input in response to the rising edge of an external clock K.

FIG. 22 is a block diagram showing the internal structure of the CDRAM chip housed in the package shown in FIG. 21. It should be noted that the block arrangement shown in FIG. 22 is only for functionally showing the internal configuration of the CDRAM, and does not match the actual layout.

In FIG. 22, CDRAM is DRAM
100 and an SRAM 200. The DRAM 100 includes a 4M bit DRAM array 101 and a given DRAM array 101.
A DRAM row decoder block 102 decodes an internal row address for RAM and selects four rows from this DRAM array 101, and a DRAM row decoder block 102 that decodes a given internal column address for DRAM and selects this selected row in normal operation mode (array access). A DRAM column decoder block 103 that selects one column from each of the four rows, and a DRAM column decoder block 103 that detects and amplifies data in memory cells connected to the selected row.
In response to the column selection signal from RAM sense amplifier DSA and block 103, this D
The block 104 includes a selection gate SG that selects 16 bits of the RAM array 101 and selects 4 bits of memory cells in the array access mode.

The SRAM 200 includes an SRAM array 201 having a capacity of 16K bits, an SRAM row decoder block 202 that decodes an internal row address for SRAM and selects four rows from this SRAM array 201, and
Decodes the RAM internal column address, selects one bit from each of the four selected rows, and transfers it to the internal data bus 250.
The column decoder/sense amplifier block 203 includes an SRAM column decoder and an SRAM sense amplifier connected to the SRAM cell and senses and amplifies information of the selected SRAM cell during data reading. DRAM
A bidirectional transfer gate circuit 210 is provided between the SRAM 100 and the SRAM 200. In FIG. 22, the column decoder/sense amplifier block 20 is arranged as shown in FIG.
The gate circuit 210 may be connected to the output (input) of No. 3. However, in FIG. 22, in the array access mode, input/output of data to and from the DRAM 100 is performed via the common data bus 251, so the common data bus 251 is shown coupled to the bidirectional transfer gate circuit 210. It will be done. The common data bus 251 is shown in FIG.
, 9 include write data bus lines DBW and *DBW.

[0158] The CDRAM according to the present invention further receives control signals G#, W#, E#, CH#, C
Internal control signal G upon receiving I#, REF#, and CR#
, W, E, CH, CI, REF and CR, and internal address int-Aa for DRAM and internal address int for SRAM.
-Ac, and a clock buffer 254 that buffers an externally applied clock signal K. Control clock buffer 250 takes in the applied control signal in response to the rise of the internal clock from clock buffer 254 and generates an internal control signal. The output of this clock buffer 254 is also provided to address buffer 252. Address buffer 252 outputs internal chip enable signal E at the rising edge of clock K from clock buffer 254.
When int-Aa and int-
Generates Ac.

The CDRAM according to the present invention further has a DR which is activated in response to an internal refresh instruction signal REF.
The refresh address from this counter circuit 256 and the refresh address from the address buffer 252 are controlled by a counter circuit 293 that generates a refresh address for the AM array and a switching signal MUX from a refresh control circuit 292 that is driven in response to an internal refresh instruction signal REF. Address multiplex circuit 258 that provides one of the internal row addresses to DRAM row decoder block 102
including. Refresh control circuit 292 is driven by a refresh request from auto-refresh mode detection circuit 291. This refresh operation will be explained later.

[0160] The CDRAM further receives each internal control signal E,
Transfer operations of the DRAM array drive circuit 260, which generates various control signals for driving the DRAM 100 in response to CH, CI, and REF, and the bidirectional transfer gate control circuit 210, in response to internal control signals E, CH, and CI. , and an SRAM array drive circuit 264 that generates various control signals for driving the SRAM 200 in response to an internal chip select signal E.

The CDRAM according to the present invention is further activated in response to an internal control signal CR, and specifies the operation mode of the CDRAM in response to an external write enable signal W# and a command address Ar (Ar0 and Ar1). a command register 270 that generates a command CM for
and a data input/output control circuit 272 that controls data input/output according to the special mode command CM, and a data input/output control circuit 272 that controls data input/output between the common data bus 251 and the outside of the device under the control of the data input/output control circuit 272. It includes an input/output circuit 274 consisting of an input/output buffer and an output register for processing. The reason why the input/output circuit 274 is provided with an output register is to realize a latch output mode and a register output mode, which are special modes of this CDRAM. The data input/output control circuit 272 not only sets the data input/output timing but also sets the data input/output mode according to the mode specified by the special mode command CM. FIG. 22 shows an example of the data input/output pins in the masked write mode.

FIG. 23 is a diagram showing another layout of the semiconductor memory device shown in FIG. 22. In the configuration shown in FIG. 22, internal data transmission line 251 is connected to SRAM bit line pair SBL by SRAM column decoder 22. Furthermore, the data of the selected column of the DRAM array 1 transmitted via the bidirectional transfer gate circuit 3 is further selected and connected to the internal data transmission line 251 by a column selection signal from the DRAM column decoder 15. In this configuration, the SRAM row decoder 21 and column decoder 2
The internal address int-Ac given to 2 and the DRAM
The internal address int-Aa given to row decoder 14 and column decoder 15 is given through independent paths, respectively. Therefore, this configuration also allows the memory cells of SRAM array 2 and DRAM array 1 to be addressed independently.

In the configuration shown in FIG. 22, an SRAM column decoder 22 is provided between the bidirectional transfer gate circuit 3 and the SRAM array 2; It may also be a configuration provided between. Also, D.R.
DRAM from I/O line pair 16a, 16b of AM array 1
The SRAM bit line pair SBL is selected by the column decoder 15 output and connected to the internal common data bus 251, and the SRAM column decoder 22 connects the SRAM bit line pair SBL to the internal data transmission line 25.
It may be configured to connect to 1.

FIG. 24 is a diagram showing an example of a connection between the bidirectional transfer gate circuit 210 shown in FIG. 22 and the internal common data line 251. In FIG. 24, the SRAM input/output gate 301 connects the SRAM sense amplifier SSA and the SRA
Activated when data is written to M array, data on internal data line 251a is transferred to corresponding SRAM bit line pair SB.
It includes a write circuit WRI for transmitting onto L. S.R.A.
M bit line pair SBL is connected to internal data line 251a via SRAM sense amplifier SSA and SRAM column selection gate 302. An SRAM column selection signal SYL from an SRAM column decoder block 203 is applied to each SRAM selection gate 302 . Thereby,
Only one SRAM column bit line pair SBL is connected to internal data line 251a. Here, the internal data line 251 shown in FIG. 23 transfers 4 bits of data, of which only the internal data line for 1 bit is shown in FIG.

In FIG. 24, in order to further enable array access, this CDRAM connects the global I/O line pair GIO to the internal data line in response to an AND signal of the cache inhibit signal CI and the DRAM column selection signal DY. 251
includes an access switching circuit 310 connected to a. The access switching circuit 310 and the bidirectional transfer gate BTG are included in the transfer gate circuit block 305.

Column selection signal DYi of this DRAM is generated by decoding, for example, the lower four bits of the column address. In other words, the global I/O line pair GIO is one D
Sixteen pairs are provided for a RAM memory mat (capacity 1 Mbit). In the case of array access, it is necessary to select only one of these pairs. Therefore, the column selection signal DYi is generated by decoding the lower 4 bits of the DRAM column address. This access switching circuit 310 simply connects the global I/O line pair GIO to the internal data line 251.
a, and connections to corresponding signal lines are made within the bidirectional transfer gate BTG. Note that when realizing array access, such an access switching circuit 310 may not be provided, and the global I/O line pair GIO may be connected to the internal data line 251a via the SRAM sense amplifier SSA. At this time, the column selection signal applied to the SRAM selection gate 302 becomes a selection signal based on the column address applied to the DRAM. This can be realized by a circuit that multiplexes the column selection signal with the signal CI. This multiplex circuit applies a DRAM column selection signal to the SRAM selection gate when signal CI is active.

Note that in the SRAM, an SRAM sense amplifier S is connected to each SRAM bit line pair SBL.
SA is provided, but this is like a normal SRAM where one SRAM bit line pair for one block is provided.
A configuration in which only a RAM sense amplifier is provided may be used. However, if an SRAM sense amplifier is provided for each SRAM bit line pair SBL in this way, data can be output more reliably and at high speed. Also, SRA
If the M sense amplifier SSA has the same configuration as the DRAM sense amplifier, there is no particular need to provide the write circuit WRI.

Further, the transfer gate circuit block 305 may use the transfer gate circuits shown in FIGS. 8, 9, 12, and 13.

FIG. 25 shows the D/Q in the input/output circuit 274.
FIG. 3 is a diagram showing a configuration for realizing separation. In FIG. 25, the input/output circuit 274 is activated in response to the internal output enable signal G, and the input/output circuit 274 is activated on the internal data line 251a.
Output buffer 3 that generates output data Q from the above data
20, activated in response to an internal write instruction signal W;
An input buffer 322 that generates internal write data from external write data D and transmits it onto the internal data line 251a, and D/Q from the command register 270 (see FIG. 22).
It includes a switch circuit 324 that shorts the output of output buffer 320 and the input of input buffer 322 in response to separation instruction bit CMa. This D/Q separation instruction bit CMa is included in the special mode designation command CM generated from the command register 270. When this switch circuit 324 becomes conductive, data is input and output through the same pin. When the switch circuit 324 is turned off, data is input and output through separate pins. Note that FIG. 25 also representatively shows only the configuration related to input/output of 1-bit data.

FIG. 26 is a diagram showing a data input/output circuit and other connection configurations. In FIG. 26, the output buffer circuit 3
20 receives selected memory cell data of the SRAM sense amplifier or DRAM array and transmits it to external output pin Q. The first input buffer circuit 322a is connected to an external pin terminal Q, and the second input buffer circuit 322b is connected to an external data input pin terminal D. The outputs of the first and second input buffer circuits 322a and 322b are connected to internal data buses DBW and DBW via an OR circuit 322c.
*Transmitted to DBW (251a). Enabling/disabling of the first and second input buffer circuits 322a and 322b is performed in response to an instruction bit CM from a command register (see FIG. 22). If the command register indicates D/Q separation mode, the first
The input buffer circuit 322a is disabled, and the input buffer circuit 322b is enabled. When the instruction bit CM indicates the D/Q common masked write mode, the first input buffer circuit 32
2a is enabled and the second input buffer circuit 3
22b is disabled.

Note that in the configuration shown in FIG. 26, data from the SRAM sense amplifier is transmitted to the output buffer circuit 320, which means that the data in the selected memory cell of the DRAM array is transmitted to the column line of the SRAM array. This is because it shows a case where the signal is further transmitted to the internal data bus via the sense amplifier of the SRAM. That is, in the configuration of FIG. 24 in which the gate 310 is not provided, the column selection signals SYLi and SYLj applied to the gate 302 are the DRAM column decoder output D.
An example is shown in which it is shared with Yi and DYj. This configuration will be explained later.

FIG. 27 is a diagram showing still another configuration of the input/output circuit. In FIG. 27, the output buffer circuit 320
and the input buffer circuit 322, an instruction bit CMa
A transistor 324a is provided which turns on in response to the input buffer circuit 322 and the data input pin terminal D.
A transistor gate 324b that is turned on in response to complementary instruction bit /CMa is provided between the transistor gate 324b and the transistor gate 324b. In this configuration, when instruction bit CMa indicates the D/Q separation mode, transistor gate 324a is turned off and transistor gate 324b is turned on. Conversely, when the D/Q shared mask try mode is indicated, the transistor gate 324a is in the on state and the transistor gate 324b is in the off state.

With this configuration, the input buffer circuit 322
can be selectively connected to data output pin terminal Q or data input pin terminal D, and D/Q separation mode and D/Q sharing mode can be set.

FIG. 28 is a diagram showing an example of how addresses are connected to DRAM and SRAM. In the configuration shown in FIG. 28, access to the DRAM array is from the SR
This is done via the bit line pair SBL or bidirectional transfer gate circuit to the AM array. In this configuration, SRAM
The column selection signal CD from the column decoder 22 is applied to the DRAM
The structure is shared by the column selection signal of the array and the column selection signal of the SRAM array. In FIG. 28, a DRAM address buffer 252a receives DRAM addresses Aa0 to Aa9 from the outside, and receives internal addresses int. Generates Aa. The DRAM row decoder 14 uses this internal address int. Decode the internal row address of Aa,
A word line drive signal DWL is generated to select a word line from the DRAM array. The DRAM column decoder 15 is
It receives a portion of the internal column address from DRAM address buffer 252a and generates a signal CSL for selecting a column selection line from the DRAM array. The remaining part of the internal column address from DRAM address buffer 252a is given to buffer 29. Buffer 29 receives the internal column address from SRAM buffer 252b and transmits it to SRAM column decoder 22. As will be explained in detail later, D
When accessing the RAM array, no internal column address is generated from SRAM buffer 252b. In this case, the buffer 29 is the DRAM address buffer 25
It receives the internal column address from 2a and transmits it to the SRAM column decoder 22.

[0175] The SRAM row decoder 21 receives the internal row address from the SRAM buffer 252b and decodes the SRAM row address.
SRAM word line drive signal S to select one row from the array
Generate WL. According to the configuration shown in FIG. 28, the column decoder output CD applied to the bidirectional transfer gate circuit shown in FIGS. 8 and 9 becomes the SRAM decoder output. Furthermore, according to the configuration shown in FIG. 28, in the data input/output configuration shown in FIG.
, DYj and the SRAM column selection signals SYLi, SYLj are equivalent.

FIG. 29 is a diagram showing another example of the structure of the address input/output section. In the configuration shown in FIG.
In place of the buffer 29 shown in FIG. 3, either the internal column address from the DRAM address buffer 252a or the internal column address from the SRAM address buffer 252b is passed through in response to the cache hit instruction signal CH and the DRAM array access instruction signal CI. multiplexer 3
0 is set. Cache signal CH and DRAM array access instruction signal CI will be explained in detail later, but when cache hit instruction signal CH is generated, SRA
Access to the M array is permitted, and data writing/reading by accessing the DRAM is prohibited. DRA
When M array access instruction signal CI is generated, DR
Data writing/reading by accessing memory cells of the AM array is permitted. Therefore, when signal CH is generated, multiplexer 30 selects the internal column address from SRAM address buffer 252b to
It is transmitted to the AM column decoder 22. Further, when the DRAM array access instruction signal CI is generated, the multiplexer 30 selects an internal column address from the DRAM address buffer 252a and sends the SRAM column decoder 22
Communicate to. Also in the configuration shown in FIG. 29, SRA
The M column decoder 22 performs column selection and SR of the DRAM array.
This configuration is used for both column selection and AM array column selection.

[0177] The address distribution configuration shown in FIGS. 28 and 29 is just an example, and each address is
AM array internal column address decoding and SRAM
A configuration may also be used in which internal column addresses of the array are decoded.

FIG. 30 shows the internal data transmission line pair and SRAM
FIG. 7 is a diagram illustrating another configuration example of a connection form with an array. Figure 2
In the configuration shown in 4, the SRAM sense amplifier SSA
is provided for each SRAM bit line pair SBL. In the configuration shown in FIG. 30, the SRAM sense amplifier SSA has multiple SRAM bit line pairs SBL, *SBL.
One piece is provided for each. Each SRAM bit line pair SBL
, *SBL, a selection gate circuit 302 is provided. A column selection signal CD is applied to this selection gate circuit 302. This column selection signal CD is given the column selection signal from the SRAM column decoder shown in FIGS. 28 and 29. The internal data line pair includes an internal write data line 251a' for transmitting write data and a read data transmission line 251b' for transmitting read data to the output buffer circuit.
including. Internal write data transmission line 251a' includes a complementary data line pair DBW, *DBW. Complementary data from the input buffer circuit is transmitted to internal data lines DBW and *DBW. This internal write data line 251a'
is connected to write circuit 303.

The write circuit 303 includes cross-connected n-channel MOS transistors T301, T302, and T30.
3, including T304. Transistors T302 and T3
The gate of 03 is connected to internal data line DBW. The gates of transistors T301 and T304 are connected to internal data line *DBW. Complementary write data from write circuit 303 is transmitted to each selection gate circuit 302 via data lines DBWa and *DBW. transistor T3
01 and T302 transmit power supply potential Vcc when in the on state. Transistors T303 and T304 transmit ground potential Vss when in the on state. For example, consider a case where "H" data is transmitted to internal data line DBW. At this time, "L" data is transmitted to internal data line *DBW. At this time, transistors T302 and T303 are turned on. Therefore, write circuit 3
From 03, "H" data is transmitted to internal data line DBWa via transistor T302, and "L" data is transmitted to the other internal data line *DBWa via transistor T303.
” data is transmitted.

When reading data, "L" data is transmitted from the input buffer circuit to internal write data lines DBW and *DBW, so that the output of write circuit 303 becomes a high impedance state. At this time, the sense amplifier SSA is activated and the internal data lines DBWa, * are connected via the selected selection gate circuit 302.
The data transmitted to DBWa is amplified by sense amplifier SSA and then transmitted to the output buffer circuit via internal read data transmission line 251b'.

As shown in FIG. 30, internal data line 2
By separately providing the write data transmission line 251a' and the read data transmission line 251b' as 51, the layout of the input/output circuit can be designed more easily than a configuration in which data writing/reading is performed via a common internal data bus. It becomes easier.

A DRAM array is composed of dynamic memory cells, and it is necessary to refresh its stored data periodically or within a predetermined period. Next, the refresh operation of this cache built-in semiconductor memory device will be explained.

Referring to FIG. 22, refresh instruction signal REF# is applied from the outside. This semiconductor memory device automatically refreshes internally when external refresh instruction signal REF# is set to the active state of "L" at the rise of internal clock K.

In FIG. 22, the circuit configuration for performing refresh includes an auto-refresh mode detection circuit 291 that detects that auto-refresh is specified in response to internal refresh instruction signal REF from control clock buffer 250; Refresh control circuit 292 generates various control signals in response to refresh requests from auto-refresh mode detection circuit 291 and supplies them to counter 293 and multiplexer circuit 258.
including. Counter circuit 293 responds to a refresh instruction signal from refresh control circuit 292 and provides the count value stored therein to multiplexer circuit 258 as a refresh row address indicating the row to be refreshed. Multiplexer circuit 258 selects a refresh row address from counter circuit 293 in response to switching control signal MUX from refresh control circuit 292 and provides it to DRAM row decoder 102 . This internal refresh instruction signal REF is also applied to DRAM array drive circuit 260. DRAM array drive circuit 250 becomes active when internal refresh instruction signal REF is applied, and performs operations related to row selection in DRAM array 101.

Refresh control circuit 292 increments the count value of counter circuit 293 by 1 each time refresh instruction signal REF is applied upon completion of refresh. Further, the refresh control circuit 292 deactivates the switching control signal MUX when the refresh is completed, and the multiplexer circuit 258 thereby receives the internal address int for the internal DRAM from the address buffer circuit 252.
-Aa is selected and transmitted to the DRAM row decoder 102.

FIG. 31 is a diagram functionally showing the transfer gate control circuit 262. Transfer gate control circuit 262 generates signals φTDS and φTSD that control the transfer operation of bidirectional transfer gate circuit 210 (3, BTG) in response to internal control signals E, CI, W, and CH. The transfer gate control circuit 262 does not generate the transfer control signals φTDS and φTSD when the cache hit signal CH is active, but when the array access instruction (cache inhibit) signal CI becomes active, the write enable signal at that time is generated. Control signals φTDS and φTSD are sequentially generated according to the state of W. At this time, internal refresh instruction signal REF may be applied to transfer gate control circuit 262, and transfer gate control circuit 262 may be inactivated when internal refresh instruction signal REF is applied. However, since the refresh instruction signal REF# is applied from the outside, if the external specifications are set so that the array access instruction signal CI is not generated at that time, the transfer gate control circuit 262 can specifically receive the refresh instruction signal REF. There's no need. However, when the DRAM array is being refreshed, it is necessary to ensure that the SRAM array and the DRAM array are electrically isolated, and the transfer gate control circuit 262 is disabled in response to the internal refresh instruction signal REF. If such a configuration is provided, the SRAM array and the DRAM array will be reliably electrically separated during the refresh operation, and the SRAM array will be accessible from the outside.

The configuration of the transfer gate control circuit 262 is such that the transfer gate control circuit 262 is disabled when either the cache hit signal CH or the refresh instruction signal REF becomes active. That's fine. More preferably, chip enable signal E is in an inactive state, or cache hit signal CH and refresh instruction signal R
It is sufficient to provide a gate circuit that disables the selection gate control circuit 262 when any one of F is in an active state. In other cases, transfer control signals φTDS and φTSD are generated at predetermined timings according to control signals CI and W.

FIG. 32 is a diagram showing the functional configuration of DRAM array drive circuit 260 shown in FIG. 22. The DRAM array drive circuit 260 includes a row selection system drive circuit 260a that drives circuits related to row selection of the DRAM array, and a DRAM.
It includes a column selection drive circuit 260b that drives circuits related to column selection of M array 1. Row selection system drive circuit 260a generates various control signals φEQ, /φSAPE, φSANE, and DWL at predetermined timings in response to internal control signals E, CH, CI, and REF. Column selection drive circuit 260b generates signal CDA for driving DRAM column decoder 15 at predetermined timing in response to control signals E, CH, CI, and REF. This column selection drive circuit 260b includes the row selection drive circuit 2
If refresh instruction signal REF is inactive when 60a becomes active, column decoder activation signal CDA is generated at a predetermined timing. Column selection related drive circuit 260b is disabled when refresh instruction signal REF is activated. This inhibits column selection operations in the DRAM.

With this configuration, refresh instruction signal R
When EF is activated, refresh operations in the DRAM array can be performed independently of operations in the SRAM array.

Further, the auto-refresh mode detection circuit 291, refresh control circuit 292 and counter circuit 293 shown in FIG.
The command register 270 operates independently of the command register 270. Therefore, command register 2
DRAM array 101 can be refreshed in parallel with setting the command mode to 70. That is, the command register 270 only generates command data CM and applies it to the data input/output control circuit 272 and the input/output buffer + output register block 274, and the data held therein has no effect on the memory cell selection operation in the DRAM array 101. This is because it does not affect

At this time, data setting to the command register 270 is completed in one cycle of the external clock signal K, as will be explained in detail later using a timing diagram. On the other hand, a refresh operation in a DRAM array requires n cycles. This is because the operating speed of the DRAM 100 is slower than the clock K speed. Therefore, in this case, one clock cycle is simply utilized effectively. However, if the period of the external clock K is delayed according to its operation mode, and if the period is equivalent to one memory cycle of the DRAM 100, the external clock K can be used in parallel with setting data to the command register 270 and refreshing the DRAM array 101. It becomes possible to do so. Such a change in the period of the external clock K can be made, for example, when the DRAM is in a standby state or when this storage device is not required to operate at high speed but rather requires low power consumption. If the operating speed of the semiconductor memory device is reduced by increasing the length, the current consumption can be reduced in accordance with the reduction in the operating speed. The period of the external clock K may be lengthened when only the DRAM is being accessed.

By adopting the above-described configuration, a CDRAM having the following features can be realized.

(1) The CDRAM according to the present invention integrates a DRAM memory array as a main memory and an SRAM array as a cache memory on one chip, and uses an internal common data bus and a dedicated data transfer bus between the two memories. are connected via an internal bus. As a result, block transfer between the DRAM array and the SRAM array (cache) is completed in one clock cycle. In the following explanation, when simply referred to as an array, it is referred to as DR.
Let AM array be shown. As a result, the conventional standard D
System performance can be significantly improved compared to a cache memory system using RAM and standard SRAM.

(2) DRAM memory array and SRA
Each of the M arrays can be accessed by a separate address. Therefore, it is possible to support various mapping methods such as a direct mapping method, a set associative method, and a fully associative method.

(3) This CDRAM operates synchronously using an external clock K. Therefore, compared to a method in which an internal clock signal is generated using an address change detection circuit, it is possible to prevent cycle time delays caused by address skew, etc., and to perform accurate control.

(4) Array addresses (DRAM addresses) Aa0 to Aa9 and cache address (SR
AM address) Ac0 to Ac11, data input/output D
0 to D3 or DQ0 to DQ3, write enable signal W#, cache hit signal CH#, chip select signal E#, refresh signal REF#, cache inhibit signal CI#, command register signal CR#, and other externally applied signals ( or data) are all captured on the rising edge of external clock K.

(5) Since the array address is taken in by multiplexing, the number of pins for the array address can be reduced, and the packaging density of the CDRAM can be increased.

(6) The array and cache addresses are independent, and when a cache hit occurs, only the cache is accessed, making it possible to achieve high-speed cache hit access.

(7) Data can be read out at any timing by output enable signal G# regardless of the timing of external clock K, and thereby asynchronous bus control can be executed in the system.

(8) The command register 270 allows the user to arbitrarily specify output specifications (transparent, latch, register; these will be described later) and I/O configuration (input/output pin separation, masked write). As will be explained later, if the register output method is used, the output data of the address specified in the previous cycle appears at the rising edge of the external clock K. Such data output mode is suitable for pipeline applications. Furthermore, in the latch output method, at the timing when invalid data is output, the output data of the address specified in the previous cycle is output during that period. As a result, no invalid data is output, and only valid output data is always obtained. This latch output mode allows a sufficient period of time for the CPU to capture output data.

(9) The data write operation is started by the rising edge of the external clock K, but this write is automatically terminated internally by a timer or the like. Therefore, there is no need to set the end of the write operation using, for example, an external write enable signal W#, which facilitates system timing setting.

(10) Refresh instruction signal REF# specifying auto-refresh can be applied from outside. This allows the DRAM array to be easily auto-refreshed at desired timing.

(11) Also, as mentioned above, the 44-pin 300mil. The CDRAM of the present invention can be housed in a type II TSOP package. This T.S.O.
Type II of the P package is an extremely thin rectangular package and can construct a system with high packaging density.

FIG. 33 is a diagram showing a list of operation modes included in the CDRAM of the present invention and the states of control signals for specifying each operation mode. The operation mode of CDRAM is external control signal E#, CH#, CI#, CR#, W#
It is set by a combination of the states of REF# and REF#. In FIG. 33, “H” indicates a high level signal potential, and “L”
” indicates a low level signal potential, and “X” indicates arbitrary (don't care DC). As shown in Figure 33, the CDRAM operation modes include standby mode, which puts the CDRAM in a standby state, and auto mode of the DRAM array. Array refresh mode for refreshing, data transfer mode between the CPU (Central Processing Unit) and cache (SRAM), data transfer mode between the CPU and the array, and data block transfer mode between the cache and the array. transfer,
There is a special mode setting mode for the command register. The combination of signal states and timing for setting each operation mode will be described in detail later with reference to operation waveform diagrams. Note that in FIG. 33, the write enable signal W# is shown as "H/L" during data transfer between the CPU and the command register in this operation mode.
is set to “H” or “L”, and this “H” and “
L” indicates that both states are used to specify a special mode.

FIGS. 34 and 35 are diagrams showing the contents of command register 270 shown in FIG. 22 and a method for selecting the contents. Command register 270 includes eight registers RR0-RR3 and WR0-WR3. A combination of write enable signal W# and 2-bit command addresses Ar0 and Ar1 is used to select this register. By setting external write enable signal W# to "H" at the rising edge of external clock K, one of registers RR0 to RR3 is selected. Register R
R0 sets both command addresses Ar0 and Ar1 as “
0".Register RR1
is selected by setting command address bit Ar0 to "1" and command address bit Ar1 to "0". If register RR0 is selected, it indicates that masked write mode has been set (this masked write mode is also the default). register RR
If 1 is selected, it indicates that the D/Q separation mode is set.

Register WR0 is selected by setting write enable signal W# to "L" at the rising edge of external clock K and setting both command addresses Ar0 and Ar1 to "0". This register WR0 is shown in Figure 35.
As shown in , the data input terminal DQ0 (D0) at that time
The output mode is set to transparent, latch, or register depending on the combination of data from DQ3 to DQ3 (D3). Details of each of these output modes will be explained later. When this register WR0 is selected, input data D2 and D3 (DQ2 and DQ3)
Both are set to “0”. In this state, if the input data D0 is set to "0" and the input data D1 is set to an arbitrary value, the transparent output mode is set. The latch output mode is selected by setting input data D0 to "1" and input data D1 to "0". Input data D
If both 0 and D1 are set to "1", the register output mode is selected. The remaining registers are available for optional extensions.

FIG. 36 shows a CDRAM 600 according to the present invention.
FIG. 2 is a block diagram showing the configuration of a system when a direct mapping type cache system is configured using the following. In Figure 36, this cache system is
In addition to the RAM 600, a controller 650 for controlling access to the CDRAM 600;
600 and a CPU for inputting and outputting data and performing desired data processing. In FIG. 36, only the structure of the address at the time of a cache access request output from the CPU is shown. This CPU is assumed to be 32 bits. This cache system further includes CDRAM60
An address multiplexing circuit 700 is provided for multiplexing and providing a row address and a column address to an array of zeros. In the CDRAM 600, only the portion related to cache access is representatively shown.

The controller 650 includes a decoder 652 that decodes set addresses A6 to A13 from the CPU, a valid bit memory 654 that indicates which tag is valid in response to the output of the decoder 652, and an SRAM 200.
includes a tag memory 656 for storing tag addresses of data stored in the memory. The SRAM 200 has a 4K×4 bit configuration and has 256 tags. Therefore, the tag memory 656 has a configuration of 8 bits x 256 bits. The valid bit memory 654 has a 1 bit x 256 configuration to indicate which of the 256 tags (sets) are valid. The decoder 652 decodes set addresses A6 to A13, and the valid bit memory 655 decodes the set addresses A6 to A13.
Enable any bit of 4.

The controller 650 further includes a decoder 670 that receives addresses A22 to A31 from the CPU as chip selection signals and determines whether the corresponding CDRAM 600 is designated, and a decoder 670 that activates in response to the output of the decoder 670. The tag address from the tag memory 656 and the tag addresses A14 to A21 from the CPU are
A comparator 658 determines a cache hit/miss by comparing the cache hits/misses, and a multiplex circuit selects either the tag address from the tag memory 656 or the tag addresses A14 to A21 from the CPU depending on the cache hit/miss. 700 . The selector 672 also stores the tag address given from the CPU in the corresponding location of the tag memory 656 when there is a cache miss.

Next, the operation will be briefly explained. CPU
When a requester wishes to access CDRAM 600, it generates addresses A2-A31 onto data bus 620. Of the 30-bit addresses on this common data bus 620,
Addresses A22 to A31 are applied as chip select signals to decoder 670 within controller 650. The decoder 670 decodes the addresses A22 to A31 as the chip select signal and selects the corresponding CDRAM.
Determine whether access is requested. This CD
If it is determined that access is requested to the RAM 600, a chip select signal E# is generated from the decoder 670 and applied to the CDRAM 600. Comparator 658 is also activated by the chip select signal from decoder 670.

[0211] Decoder 6 included in controller 650
52 takes in addresses A6 to A13 from among the addresses transmitted from the CPU onto the address bus 620 as set addresses and decodes them. The decoder 652 that decodes this 8-bit set address sets the corresponding bit in the valid bit memory 654 to a valid state in order to select one tag out of 256 tags. An 8-bit address indicating the tag corresponding to the valid bit of valid bit memory 654 is read from tag memory 656 and applied to comparator 658. A comparator 658 connects the tag address from the tag memory 656 with the C
The tag addresses A14 to A21 output from the PU are compared. If the two match, the comparator 658 outputs a cache hit signal CH to indicate a cache hit.
Drop # to “L” and apply to CDRAM 600. On the other hand, if the two do not match, the comparator 658 generates a cache hit signal CH# of "H" to indicate a cache miss (mishit).

[0212] In case of cache hit, CDRAM6
At 00, the following operations are performed. Operation control at this time is performed by control signals from control clock buffer 250 and SRAM array drive circuit 264 (see FIG. 23). SRAM row decoder 202 selects one set out of 256 sets in response to addresses A6 to A13 from the CPU. That is, one row (each SR
4 in total) are selected one by one in the AM array block. As a result, a 16-bit SRAM cell is selected in each SRAM array block of the SRAM 200. The SRAM column decoder SCD203 decodes block addresses A2-A5 from the CPU and
One bit is selected from among the bit memory cells and connected to the data input/output terminal. FIG. 36 shows output data Q at the time of hit read.

[0213] Next, the operation when a mishit occurs will be explained. In this case, the SRAM 200 does not store data that the CPU requests access to. In controller 650 , selector 672 responds to the miss-instruction signal from comparator 658 and provides the corresponding tag address stored in tag memory 656 to multiplex circuit 700 . At this time, the selector 672 also selects CP.
8-bit tag address A14 given by U
A21 is stored in the corresponding location of the tag memory 656 as a new tag address.

In the CDRAM 600, in this cycle, copyback is performed, that is, DR from the SRAM 200.
A batch transfer of 16 bits to AM100 is performed. S
Address A6- from this CPU in RAM200
SRAM row decoder (SRD) 202 according to A13
The 16 bits x 4 data selected by is sent to addresses A6-A13 and selector 67 output from the CPU
DR according to the 8-bit tag address output from 2.
A row and column selection operation is performed in AM 100 and stored in the corresponding position of the selected 16 bits x 4 DRAM cell.

[0215] In the next operation cycle, CDRAM60
0 is the address A6-A21 output from this CPU
16 bits x 4 DR in DRAM100 according to
AM cell is selected, and this 16-bit x 4 data is also sent to the SR selected by the SRAM row decoder (SRD) 202 according to addresses A6-A13 from the CPU.
Write to the corresponding 16 bit x 4 memory cells of AM200.

As mentioned above, for SRAM, addresses A2 to A5 are block addresses, addresses A6 to A13 are set addresses, and addresses A14 to A21 are tag addresses, and for DRAM, addresses A6 to A11 are column addresses. By using addresses A12 to A21 as row addresses, a direct mapping method between the DRAM 100 and the SRAM 200 can be realized.

FIG. 37 is a block diagram showing the configuration of a 4-way set associative system using the CDRAM of the present invention. The CDRAM 600 has a configuration similar to that shown in FIG.
M100 and a clock control circuit 250'. The clock control circuit 250' includes a control clock buffer 250, an SRAM array drive circuit 264, and a DRA shown in FIG.
Includes an M array drive circuit 260. In order to simplify the drawing, a circuit configuration for controlling data input/output is not shown.

[0218] The controller 750 includes a decoder 752,
Valid bit memory 754, tag address memory 756,
Comparator 758, decoder 770 and selector 7
72 included. To support 4-way, the effective bit memory 754 includes four memory planes each having a 1 bit x 64 configuration, and the tag address memory 75
6 also has four memory planes, each with an 8 bit x 64 configuration. Similarly, one comparator 758 is provided for each memory plane of the tag address memory 756 in order to select one of the four ways, and a total of four comparators 758 are provided. In this 4-way set associative method, the 256 rows of the SRAM 200 are divided into 4 ways, so the number of sets is 64.

[0219] An address having the following configuration is transmitted from the CPU onto the address bus 620. Address A22
or A31 is the chip select address, address A
14 to A21 are tag addresses, addresses A12 and A13 are way addresses, and addresses A6 to A11.
is the set address, and addresses A2 to A5 are the block addresses. Addresses A6 to A11 and addresses A12 to A21 are used as column and row addresses, respectively, for DRAM 100. Further, the DRAM 100 of the CDRAM 600 is provided with a multiplex circuit 700 for multiplexing row addresses and column addresses. Next, the operation will be explained.

Addresses A6-A11 from the CPU are given to decoder 752 as set addresses, and addresses A22-A31 are given to decoder 770 as chip select addresses. Decoder 752 decodes this set address A6-A11 and sets the valid bit associated with the corresponding set to a valid state in valid bit memory 754. As a result, one set (4 ways) is selected. The decoder 770 decodes the chip select addresses A22-A31 and
It is determined whether an access request to 00 has been issued. When the CDRAM 600 is requested to be accessed, the decoder 770 activates the chip select signal E# of "L" and activates the comparator 758. Comparator 758 is a valid bit memory 75
Referring to the valid bit of 4, the tag address memory 756
Read the corresponding 4-way tag address from , and use this read tag address and addresses A14-A2 from the CPU.
Compare 1. When a match is found, the comparator 758 outputs way addresses W0 and W1 indicating the way in which this match was found, and lowers the cache hit signal CH# indicating a cache hit to "L". . If no match is found in comparator 758, cache hit signal CH# is set to "H" indicating a miss.

In the case of a cache hit, way addresses W0 and W1 from the controller 750 and addresses A6-A11 from the CPU are sent to the SRAM row decoder 202.
16 bits×4 SRAM cells are selected in the SRAM array 201. Block address A
2-A5 is decoded by the SRAM column decoder 203, and among the selected 16 bits x 4 SRAM cells, 1 bit x 4 is selected and connected to the data output terminal Q (or data input terminal D).

[0222] In the case of a mishit, the selector 772 selects one of these four ways of tag addresses according to, for example, LRU logic (logic that selects the oldest way) and selects the area in which the tag address should be rewritten. do. The tag address selected by the selector 772 is applied as an array address to the DRAM row decoder DRD of the DRAM 100 via the multiplex circuit 700. In addition, the selector 772 selects the tag address to be rewritten from the address A14-A2 given by the CPU.
Replace with 1.

[0223] Within the CDRAM 600, this cycle is in copyback mode. In this copyback mode, under the control of the selector 772, way addresses W0 and W1 indicating the way to be rewritten are also used.
is output. In the SRAM 200, addresses A6-A11 from the CPU and way addresses W0 and W1 from the controller 750 are decoded, and a 16-bit×4 SRAM cell is selected. On the other hand, DRAM10
0, the 8-bit tag address output from the selector 772 and the address A6- output from the CPU.
According to A13, 16 bits x 4 DRAM cells are selected. Then the selected 16 bits x 4 SR
Data transfer from the AM cell to the selected 16 bits×4 DRAM cell is performed.

In the next operation cycle, 16 bits×4 DRAM cells are selected in DRAM 100 according to addresses A6-A21 from the CPU. This newly selected 16 bits x 4 DRAM cell data is transferred all at once to the 16 bits x 4 SRAM cell selected according to addresses A6-A11 and way addresses W0 and W1.

[0225] With the above configuration, CDRAM
Both the direct mapping method and the set associative mapping method can be implemented without changing the internal configuration of 600. Although not shown in the figure, a fully associative mapping method is of course also possible. In this case, controller 750
In , the address of the SRAM cache and the DRAM
A tag address memory is required to store 100 corresponding addresses. Next, the timing relationships and state transitions of signals in various operation cycles of this CDRAM will be explained.

As described above, control signals other than output enable signal G# and addresses Aa and Ac are latched at the rising edge of external clock signal K. The state of each signal is arbitrary (D.C.) except that setup and hold times are required before and after the rising edge of external clock K, respectively. According to this external clock synchronization method, there is no need to consider cycle time margins caused by skew of address signals, etc., the cycle time can be reduced, and a CDRAM that operates at high speed can be obtained.

Output enable signal G# is shown in FIG.
Controls the output states of the output buffer and output register included in the input/output circuit 274 shown in FIG. When the output enable signal G# is "H", the output data is in a high impedance state (Hi-Z). When the output enable signal G# is in the active state "L", some data is output. The operation modes of the CDRAM are listed in FIG. 33, and each operation mode will be explained below along with its timing diagram.

During standby, at the rising edge of external clock signal K, chip select signal E# and refresh instruction signal REF# are both set to "H", and the remaining control signals CH#, CI#, CR# and W# are set to "H". is an arbitrary state. During this standby mode, the CD
No memory operations are performed in the RAM.

[0229] No. 1: Cache hit write cycle FIG. 38 is a diagram showing the timing of each signal during the cache hit write cycle. External clock signal K
has a cycle time tk. The cycle time tk is the H pulse width tKH when the external clock signal K is in the "H" state and the L pulse width when the external clock signal K is in the "L" state.
Includes pulse width tKL. A cache hit write cycle is a cycle for writing data to the SRAM cache. When this state is selected, at the rising edge of external clock signal K, chip select signal E# is set to "L", cache hit signal CH# is set to "L", cache inhibit signal CI# is set to "H", and command register signal CR# is set to "L". “H”
, sets the write enable signal W# to "L" and the output enable signal G# to "H".

In this state, the address for SRAM 200 is latched as valid, and access to SRAM is performed in accordance with this SRAM address Ac. At this time, address A for DRAM
a is arbitrary (D.C.). Input data D is made valid at the rising edge of external clock signal K, and this valid write data is written into the SRAM cell selected by SRAM address Ac. Cache memory S
Since access to RAM is fast, writing is completed in one clock cycle of external clock signal K, as shown in FIG. That is, the time required for this cache hit write is the clock cycle time tK.

In FIG. 38, output data Q changes in response to an arbitrary state of output enable signal G#, but this is due to the "H" and "L" levels of output enable signal G#. This shows that output data appears accordingly. Also, in this FIG. 38,
The setup time and hold time of each control signal and address signal are also shown. The setup time is the time required to ensure that each control signal or address is set to a defined state by the rising edge of external clock signal K. The hold time is the time required to hold the external clock signal K for a certain period of time from the rising edge of the signal to ensure reliable operation. Each setup time and hold time will be briefly explained.

Chip select signal E# has a setup time tELS required when transitioning to "L", a setup time tEHS required when transitioning to "H", and a hold required when transitioning to "L". It includes time tELH and hold time tEHH required when transitioning to "H".

[0233] Cache hit signal CH# is “L”
Setup time tCHLS required during migration;
Setup time tCHH required when transitioning to “H”
S and the hold time tCH required when transitioning to “L”
LH and the hold time tC required when transitioning to “H”
HHH is set.

Cache inhibit signal CI# has setup times tCILS and tCIHS required when transitioning to "L" and "H", respectively, and hold times required when transitioning to "L" and "H", respectively. Includes times tCILH and tCIHH.

Command register signal CR# has setup times tCRLS and tCRHS required when transitioning to "L" and "H", respectively, and hold times required when transitioning to "L" and "H", respectively. Includes times tCRLH and tCRHH.

Refresh signal REF# has setup times tRLS and tRHS required when transitioning to "L" and "H", respectively, and hold times required when transitioning to "L" and "H", respectively. t
Includes RLH and tRHH.

Write enable signal W# has setup times tWLS and tWHS required when transitioning to "L" and "H", respectively, and hold times required when transitioning to "L" and "H", respectively. time t
Includes WLH and tWHH. Address A for SRAM
c includes a setup time tACS required for the state to be determined to be valid (Valid) and a hold time tACH required when the state is valid.

DRAM address Aa includes a setup time tAAS required until it is determined to be valid (rising edge of external clock signal K) and a hold time tAAH required after it is determined to be valid. .

For write data D, a setup time tDS required for valid data and a hold time tDH required for valid data are required.

For the output enable signal G#, the time tGHD required from the output disable state until the data input pin is activated, and the time tGHD required from the data input pin to the high impedance state. The delay time tGLD required until the signal G# transitions to “L”, the time tGLQ required until the output pin is activated after transition to “L”, and the output after transition to “H” The time tGHQ required for the pin to enter a high impedance state is set.

[0241] The access time is the access time tGLA from when the output enable signal G# becomes "L" until valid data is output, and the access time from when the external clock signal K becomes "L" until valid data is output. The access time tKLA required until the data is output, the access time tKHA required from when the external clock signal K becomes “H” until valid data is output, and when the external clock signal K is “H” in the register output mode. The access time tKHAR from when the external clock signal K becomes "H" until valid data is output, and the array access required from when the external clock signal K becomes "H" until accessing the DRAM and outputting valid data. A time tKHAA is set.

In FIG. 38, write data D is deemed invalid (Inv) after time tGHD has elapsed from the rising edge of output enable signal G#.

[0243] The cycle time of the CDRAM of the present invention is set, for example, to 10 nS to 20 nS. The array access time tKHAA is set to 70 to 80 nS. Each setup and hold time is set to a few nanoseconds.

[0244]NO. 2T: Cache hit read cycle (transparent output mode) FIG. 39 shows a timing diagram of the cache hit read cycle in this transparent output mode. As described above, the output modes include transparent output mode, latch output mode, and registered output mode. This output mode is specified by a command register. In FIG. 39, when setting a cache hit read cycle, chip select signal E# and cache instruction signal CH# are both set to "L" at the rising edge of external clock signal K, and cache inhibit signal CI# and refresh Instruction signal REF#, command register signal CR# and write enable signal W# are set to "H".

In this state, the address Ac for the SRAM is made valid at the rising edge of the external clock signal K, and the SRAM cell selection operation is performed in accordance with this valid address Ac. In transparent output mode, the SRAM specified by this effective address Ac
The cell's data is output in this clock cycle. In this transparent output mode, valid output data Q is output at the later timing of time tKHA after the rising edge of external clock signal K or time tGLA after the falling edge of output enable signal G#. Ru.

[0246] When output enable signal G# falls to "L" before time tKHA, invalid data (IN
V. ) is output until time tKHA has elapsed. In this cache hit read cycle, the write data is set to a high impedance state (Hi-Z),
Further, since the address Aa for the DRAM is never used, it is in an arbitrary state.

[0247]No. 2L: Cache hit read cycle (latch output mode) FIG. 40 shows a timing diagram of a cache hit read cycle in latch output mode. The difference between the latch output mode and the transparent output mode is that when the output enable signal G# is brought down to "L" before the access time tKHA, the SRAM cell selected in the previous cycle is data (Pre.Valid) is output. The timing of other signals is similar to the transparent output mode shown in FIG. If you follow this latch output mode, invalid data (INV) will not be output,
Only valid data is always output.

[0248]No. 2R: Cache hit read cycle (register output mode) FIG. 41 shows a timing diagram of a cache hit read cycle in register output mode. The timing of external control signals in the cache hit read cycle in this register output mode is similar to that in the transparent output mode and latch output mode shown in FIGS. 39 and 40. In this register output mode, the valid data of the previous cycle (Pre. Valid ) is output. In this register output mode, invalid data is not output. This register output mode is suitable for pipeline operation.

The above-mentioned output mode switching is realized by controlling the operation of the output register included in the input/output circuit 274 shown in FIG. 22.

[0250]No. 3: Copy back cycle Figure 42 shows the timing of each signal in the copy back cycle. This copy-back cycle is a cycle for transferring data from the cache (SRAM) to the array (DRAM), and is performed in the first cycle in the case of a miss. In the copyback cycle, at the rising edge of external clock signal K, chip select signal E# and write enable signal W# are both set to "L", and cache hit signal CH# and cache inhibit signal CI# are set to "L".
, refresh instruction signal REF#, command register signal CR# and output enable signal G# are set to “H”.
”. In this copyback cycle,
In a DRAM as well, it is necessary to input an array address Aa to select a memory cell. array address A
a is given by multiplexing a row address (Row) and a column address (Col). The first rising edge of external clock signal K latches the array row address, and the second rising edge of external clock signal K latches the array column address. External clock signal K-2
At the second rising edge, cache hit instruction signal CH#, cache inhibit signal CI#, write enable signal W#, and cache address (address for SRAM) Ac are arbitrary.

Write enable signal W# is set to "L" at the first rising edge of external clock signal K, and external input data D changes from a high impedance state to an arbitrary state. External output data Q is in a high impedance state because output enable signal G# is at "H".

[0252]No. 4: Block Transfer Cycle In the block transfer cycle shown in FIG. 43, data blocks are collectively transferred from the array to the cache (SRAM) after a copy-back operation or the like. This block transfer cycle satisfies the same timing conditions as the copy back cycle shown in FIG. 42, except that write enable signal W# is set to "H" at the first rising edge of external clock signal K.

[0253] That is, cache miss (mishit)
If the write enable signal W# is set to "L" at the first rising edge of the external clock signal K, the copyback cycle is activated, while if the write enable signal W# is set to "H", the array A block transfer cycle to the cache is set.

[0254]No. 5: Array Write Cycle The array write cycle shown in FIG. 44 is a cycle in which the CPU sets a mode in which the CPU directly accesses the array and writes data. A DRAM cell in the array is selected by array address Aa. At this time, as shown in FIG. 24, the data may be written via the access switching circuit 310 of the bidirectional transfer gate circuit 305, or the data may be written in as shown in FIGS. , 12 and 13, data may be written via the SRAM bit line pair SBL, bidirectional transfer gate BTG, and global I/O line pair GIO. S
In the case of a configuration in which data is written via the SRAM bit line pair SBL of the RAM array, the lower bits of the array address Aa may be given as a block address to the column decoder SCD of the SRAM, and the column selection signal is also sent from the DRAM column decoder. It may also be applied to an SRAM selection gate.

The array write cycle is specified at the first rising edge of the external clock signal K as shown in FIG.
This is done by setting I# and write enable signal W# to "L" and setting refresh instruction signal REF# and output enable signal G# to "H". The state of cache instruction signal CH# is arbitrary. In this array write cycle, at the first rising edge of external clock signal K, array address Aa is
is latched as a row address (Row), and on the second rising edge of external clock signal K, array address A is latched as a row address (Row).
a is latched as a column address (Col). Since the cache is not accessed at this time, the state of the cache address Ac is arbitrary. External write data D is latched at the first rising edge of external clock signal K. External output data Q becomes a high impedance state.

In the cache systems shown in FIGS. 36 and 37, only a 16-bit address is given to the DRAM 100, and S
A column selection operation within a block in a RAM is performed. The configurations shown in FIGS. 36 and 37 show the configuration for a cache system, and do not show the configuration for array access. However, when the cache inhibit signal CI# becomes "L" during array access, A configuration may be adopted in which a 4-bit block address is used as a column selection address of the DRAM 100.

[0257]No. 6: Array Read Cycle The array read cycle shown in FIG. 45 is a cycle for setting a mode in which the CPU directly accesses the array and reads data. This array read cycle is specified by setting the chip select signal E# and the cache inhibit signal CI# to "L" at the first rising edge of the external clock signal K, and then setting the refresh instruction signal REF# and command register signal C to "L".
This is done by setting R#, write enable signal W#, and output enable signal G# to "H". At the second rising edge of external clock signal K, chip select signal E# and refresh instruction signal RE are activated.
F# and command register signal CR# are set to "H", and the states of cache inhibit signal CI# and write enable signal W are arbitrary. The cache hit instruction signal CH# is in any state during the array read cycle, and the output enable signal G# is “H”.
At the first rising edge of external clock signal K, array address Aa is latched as a row address, and at the second rising edge of external clock signal K, array address Aa is latched as a column address. The state of external input data D is arbitrary,
External output data Q is set to a high impedance state.

Here, the array access cycle (array write cycle and array read cycle) is set by setting cache signal CI# to "L" at the first rising edge of external clock signal K.
This array access cycle is a cycle for setting a mode in which the CPU directly accesses the array.
Data is not actually read/written within this array write cycle and array read cycle.

[0259] Read/write array data, such as copyback operations, block transfer operations, and array access operations.
Operations requiring writing require selection of a word line in the DRAM array, detection amplification of selected cell data by a sense amplifier, data restoration operation, RAS precharge, and the like. Therefore, operations requiring reading/writing data in these arrays require several clock cycles. DRAM cycle time is ta,
m= where the cycle time of external clock signal K is tK
ta/tK external clock cycles are required for array access. These m cycles become a waiting time for the CPU. The timing when the CPU is weighted in cell selection and data read/write in such an array will be described next.

[0260]No. 7: Array active cycle diagram 4
In the array active cycle shown in 6, a row selection operation, a column selection operation, and data writing/reading are performed according to the applied array address Aa. In this array active cycle, at the rising edge of external clock signal K, chip select signal E#, refresh instruction signal REF#, and command register signal CR# are set to "H", and output enable signal G# is set to "H" in this cycle. It is fixed at medium “H”. The states of cache hit signal CH#, cache inhibit signal CI#, and write enable signal W# are arbitrary. In this array active cycle, the state of external input data D is arbitrary, but the external output data Q becomes high impedance.

[0261]No. 7QT: Array active cycle with transparent output mode In specifying the array active cycle in the transparent output mode shown in FIG. 47, each control signal E#, CH#, CI#, REF#, CR# and W
# is set similarly to the array active cycle shown in FIG. In the array active cycle in the transparent output mode, the output buffer is activated by setting the output enable signal G# to "L", and valid data is output. In the array active cycle in this transparent output mode, the DRAM corresponding to the array address Aa set in the array read cycle shown in FIG.
Cell data is output.

[0262]No. 7QL: Array active cycle in latch output mode The timing states of each control signal in the array active cycle in latch output mode shown in FIG. 48 are the same as those shown in FIG. 47. In the array active cycle in latch output mode, when the output enable signal G#, which had been held at "H" until then, falls to "L", the output enable signal G#, which had been held at "H" until then, falls to "L", first, the output enable signal G#, which has been held at "H" until then, falls to "L". The data (latched in the output register) read in the current array access cycle is output first, followed by the data read in the current array access cycle.

[0263]No. 7QR: Array active cycle in register output mode The states of each control signal in the array active cycle in register output mode shown in FIG. 49 are the same as those shown in FIGS. 47 and 48. In the array active cycle in this latch output mode, the
When output enable signal G#, which has been held at ", falls to "L", external write data D becomes a high impedance state, and the data read in the previous access cycle is output as external output data Q. In this array access cycle in latch output mode, when output enable signal G# is lowered from "H" to "L" in the next clock cycle, the data read in the current array access cycle is output.

By combining the cycles shown in FIGS. 45 to 49, output data Q according to the external address can be obtained from the array.

FIG. 50 is a diagram showing the entire cycle executed when reading data from the array in transparent output mode. In FIG. 50, the numbers circled above the timing diagram represent the numbers assigned in the explanation of each cycle described above.

First, in the array read operation in the transparent output mode, the array read cycle (No. 6) shown in FIG. 45 is executed. This cycle No. 6, array address Aa is sequentially taken in as a row address and a column address at the rising edge of external clock signal K, respectively. Next, the array active cycle shown in FIG. 46 is executed a predetermined number of times, and row and column selection operations in the DRAM array are performed. Finally, cycle No. shown in FIG. By executing 7QT and lowering the output enable signal G# to "L", valid data is output after invalid data is output. The access time tKHAA in this case is comparable to the access time of a normal DRAM.

FIG. 51 is a diagram showing the entire cycle performed when reading data from the array in the latch output mode. In the array read operation in this latch output mode, similarly to the array read operation in the transparent output mode shown in FIG. 50, the array read cycle (No. 6) shown in FIG. Settings are made. After the array address Aa is latched by this array read cycle (cycle No. 6), the array active cycle (cycle No. 7) shown in FIG. 46 is performed a predetermined number of times. After this array active cycle (cycle No. 7), an array active cycle (cycle No. 7QL) in the latch output mode shown in FIG.
) is carried out. This cycle No. In 7QL, when the output enable signal G#, which had been set to "H", falls to "L", an access request is made in the current array read cycle after the data read in the previous access has been output. The data of the memory cell is output. The access time tKHAA at this time is the time required from the first rising edge of the external clock signal K until the memory cell data (Valid) requested to be accessed in the current array access cycle is output.

FIG. 52 is a diagram showing the entire cycle performed when reading data from the array in register output mode. In FIG. 52, first, cycle No.
．． By executing step 6, the array read mode is set, and array address Aa is time-divisionally latched as a row address and a column address, respectively, at the rising edge of external clock signal K. Next, cycle no.
After array active cycle No. 7 is performed a predetermined number of times, cycle No. 7 is performed a predetermined number of times. An array active cycle of 7QR is performed. This cycle No. After the output enable signal G# falls to "L" and the external clock signal K rises at 7QR, the data read in the previous cycle is read out at the later timing after time tKHA or time tGLA has elapsed. It is output as output data Q. The access time tKHAA at this time is the cycle number. 6 is the time from the first rising edge of the external clock signal K until valid data is output.

[0269] DRAM cells need to be refreshed periodically. Setting of this refresh operation is performed by an external refresh instruction signal REF#. During this refresh, in the CDRAM, a refresh address is generated from a refresh address counter (see counter circuit 293 in FIG. 22) in response to this refresh instruction signal REF#, and the DRAM cells are automatically refreshed according to this refresh address. will be carried out. DRAMs having such an auto-refresh function have been known in the DRAM field. The timing of signals for performing this refresh will be explained below.

[0270]No. 8: Refresh Cycle FIG. 53 is a diagram showing the signal timing of the refresh cycle. As shown in FIG. 53, the refresh mode of the DRAM is set by setting chip select signal E# and refresh instruction signal REF# to "H" and "L", respectively, at the rising edge of external clock signal K. At the rising edge of external clock signal K, chip select signal E# is set to “H” and refresh instruction signal REF# is set to “H”.
If this is set to "H", refreshing of this DRAM is stopped. In this auto-refresh cycle, the states of other control signals CH#, CI#, CR#, and W# are arbitrary, and output enable signal G# is set to "H". Therefore, at this time, the states of cache address Ac and array address Aa are arbitrary, the state of external input data D is also arbitrary, and external output data Q is set to a high impedance state.

[0271] Refresh operation is performed only on DRAM. SRAM does not need to be refreshed at all. Therefore, it is possible to access the cache during this refresh period.

[0272] The timing of the cycle in which refresh and cache access are performed simultaneously will be explained below.

[0273]No. 8W: Refresh cycle with cache hit write This cycle No. In 8W, data is written to the corresponding SRAM cell when a cache hit occurs in parallel with refresh in the DRAM. As shown in FIG. 54, this refresh cycle with cache hit write is set when the chip select signal E is set at the rising edge of the external clock signal K.
#, cache hit signal CH#, refresh instruction signal REF#, and write enable signal W# are set to "L", and cache inhibit signal CI# and output enable signal G# are set to "H". . This sets a cache hit write cycle and also sets a refresh cycle.

In the cache (SRAM), in response to the active states of cache hit instruction signal CH# and write enable signal W#, write data D from the outside is taken in at the rising edge of external clock signal K and the corresponding SRAM is Write to cell location. In the DRAM, an internal refresh address counter is activated by refresh instruction signal REF#, and refresh is performed according to the refresh address from this counter.

If refresh instruction signal REF# is set to "H" at the rising edge of external clock signal K, a cache hit write cycle (
Cycle no. 1) is performed, and the DRAM
refresh is stopped.

[0276]No. 8RT: Refresh cycle with cache hit read in transparent output mode This cycle No. In 8RT, cache hit read is performed according to the transparent output mode, and auto-refresh is performed in the DRAM. This cycle No. The settings for 8 are shown in Figure 55.
As shown in , at the rising edge of external clock signal K, chip select signal E# and cache hit signal CH
This is done by setting # and refresh instruction signal REF# to "L" and setting cache inhibit signal CI#, command register signal CR# and write enable signal W# to "H". In the SRAM cache, in response to this cache hit read instruction, the cache address Ac is fetched at the rising edge of the external clock signal K and the corresponding SRAM cell is selected. When output enable signal G# falls to "L", valid output data Q is output after a predetermined time has elapsed.

[0277] In the DRAM, auto-refresh is performed in response to refresh instruction signal REF#. If refresh instruction signal REF# is set to "H" at the rising edge of external clock signal K in a refresh cycle involving this cache hit read, auto-refresh performed in response to refresh instruction signal REF# is stopped. Therefore, in this case, cycle No. shown in FIG. A cache hit read cycle in the same transparent output mode as in 2T is performed.

[0278]No. 8RL: Refresh cycle with cache hit read in latch output mode Cycle No. 8RL shown in FIG. In 8RL, cache hit read is performed in the latch output mode, and auto-refresh of the DRAM is performed. The timing conditions for each control signal are similar to those shown in FIGS. 54 and 55. In this latch output mode,
When a cache hit occurs, after output enable signal G# falls to "L", first the data accessed in the previous cycle is output, followed by the data accessed in the current cycle.

[0279]No. 8RR: Refresh cycle with cache hit read cycle in register output mode Cycle No. 8RR shown in FIG. In 8RR, data is read according to the cache hit read cycle in register output mode, and the DRA
Auto-refresh is also performed in M. Timing conditions for each control signal are similar to those shown in FIGS. 55 and 56, and hit read and auto-refresh are performed. This cycle No. In 8RR, when the output enable signal G# falls to "L", the output data selected in the previous cycle is output. After this, output enable signal G# is set to “H”
When the output enable signal G# is raised to "L" and subsequently lowered to "L" in the next clock cycle, the data of the SRAM cell selected in this cycle is output.

The CDRAM's transparent output mode, latch output mode, register output mode, masked write mode, and D/Q separation mode are realized by setting a command for setting a desired special function in the command register. Next, an operation cycle for setting a command in this command register will be explained.

[0281]No. 9: Command register set cycle Figure 58 shows the command register set cycle (cycle N
o. 9) is a diagram showing the timing of each signal in FIG. This command register set cycle occurs at the rising edge of external clock signal K, chip select signal E#,
Cache inhibit signal CI#, command register signal CR
This is achieved by setting # and write enable signal W# to "L". At this time, as shown in FIG. 34, four registers WR0 to WR0 of the command registers
One of WR3 is selected. In setting the output mode, command register WR0 is selected, and the contents of the output mode are selected based on the combination of input data D at that time. Therefore, at the rising edge of external clock signal K, command address Ar and external write data D are validated and latched. 2 bits A of command address Ar
Command register WR0 is selected when r0 and Ar1 are both 0 (“L”). Upper 2 bits D2 (DQ2) and D3 of the 4-bit external write data D
(DQ3) is “0” (“L”), and the least significant bit D
If 0 (DQ0) is "0", transparent output mode is set.

In the latch output mode, external write data D0 and D are output at the rising edge of external clock signal K.
1 is set as "1"("H") and "0", respectively, and the remaining 2 bits of external write data D2 and D3 are both set as "0". In register output mode, command addresses Ar0 and Ar1 are both set to "0" at the rising edge of external clock signal K, external write data D0 and D1 (DQ0 and DQ1) are both set to "1", and external write data is Both D2 and D3 (DQ2 and DQ3) are “0”
” is selected.

In the configuration of the command register shown in FIG. 34, eight registers are provided, and eight types of special modes can be set. In order to select the command register RR0 for setting the masked write mode and the register RR1 for setting the D/Q separation mode, the write enable signal is activated at the rising edge of the external clock signal K in the timing diagram shown in FIG. Set W# to “H”. A desired mode is selected depending on the value of the command address Ar at this time.

Next, a specific configuration for setting the data output mode to transparent mode, latch mode, and register mode in accordance with the data set by the command register will be described. FIG. 59 is a diagram showing a circuit configuration related to data output mode setting. Figure 5
9, the command register 270 outputs a command register mode detection signal (internal command register signal) CR.
It includes a command register mode selector 279 that decodes a write enable signal W# and command data Ar0, Ar1 in response to the write enable signal W#, registers WR0 to WR3, and a flip-flop FF1. The command register consists of eight registers RR0 to RR3 as shown in FIG.
and WR0 to WR3. However, in FIG. 59, registers RR2 and RR3 are not shown. Registers WR0 to WR3 are each 4-bit registers. Registers RR0 and RR1 share one flip-flop FF1. Register RR0
When is selected, flip-flop FF1 is set to masked write mode. When register RR1 is selected, flip-flop FF1 is set to D/Q separation mode. The input control circuit 272b controls the input circuits 274b and 274b according to the setting data of the flip-flop FF1.
74c.

Data setting in any of registers WR0 to WR3 is performed by decoding command data Ar0 and Ar1. Write enable signal W#
is in an active state, 4-bit data D0 to D3 (or DQ0 to DQ3) are set to the corresponding register via the input circuit 274b or 274c selected by the input control circuit 272b. Since register WR0 is related to the data output mode, the setting of this data output mode will be explained. The output control circuit 272b is set to one of transparent, latch, and register output modes according to the data of the lower two bits of the register WR0, and the output circuit 274a is selectively activated according to the set output mode. Signal φ1, /φ
1 and φ2.

FIG. 60 is a diagram showing an example of a specific configuration of the output circuit 274a. In FIG. 60, the output circuit 274
a is a first output latch 981 for latching data on read data buses DB, *DB in response to control signals φ1, /φ1, and a first output latch 981 for latching data on read data buses DB, *DB in response to control signals φ1, /φ1; or data bus DB, *DB
It includes a second output latch 982 that passes the above data, and an output buffer 983 that receives data from the output latch 982 and transmits it as output data to an external pin terminal DQ in response to a control signal G#.

First output latch 981 includes clocked inverters ICV1 and ICV2 activated in response to clock signals φ1 and /φ1. The input and output of clocked inverter ICV1 are connected to the output and input of clocked inverter ICV2, respectively. This output latch 981 is in a latched state when the clock signal φ1 is "H". That is, clocked inverter I
CV1 and ICV2 are activated when clock signal φ1 is "H" and function as an inverter. When clock signal φ1 is “L”, clocked inverter ICV
1 and ICV2 are disabled and latch 981 does not perform a latching operation.

[0288] When the clock signal φ2 is "L", the second output latch 982 latches the data applied to its inputs A and *A, and outputs it from outputs Q and *Q. When the clock signal φ2 is “H”, the output latch 982 outputs the data latched when the clock signal φ2 is “L” from the outputs Q, *Q, regardless of the signal states of its inputs A, *A. . A clock signal φ1, which controls this latch operation,
/φ1 and φ2 are signals synchronized with an external clock K, and their generation timings are made different by the output control circuit 272b.

Output buffer 983 is activated when output enable signal G# becomes active, and output latch 982
The output data from the terminal is transmitted to the terminal DQ.

FIG. 61 is a diagram showing an example of a specific configuration of second output latch 982. In FIG. 61, second output latch 982 includes a D-type flip-flop DFF that receives input A (*A) at its D input and receives clock signal φ2 at its clock input CLK. From the output Q of the flip-flop DFF to the output Q of the output latch 982 (*Q)
is obtained. This D-type flip-flop DFF is a down edge trigger type, and takes in input A at the timing when the clock signal φ2 falls to L, and the clock signal φ2 is “
During “L”, input A is output as is. Clock signal φ2
When is "H", the previously latched data is output regardless of the state of input A applied to input terminal D. This results in an output latch 982 that achieves the desired functionality. A D-type flip-flop DFF is provided for input A and input *A, respectively. This output latch 9
82 may have another configuration, and may have any circuit configuration as long as it can realize a latch state and a through state in response to the clock signal φ2.

FIG. 62 is a diagram showing an example of a specific configuration of the output control circuit 272b. The output control circuit 272b includes a delay circuit 991a that delays an external clock by a predetermined time.
991b, 991c, a one-shot pulse generation circuit 992a that generates a one-shot pulse signal having a predetermined pulse width in response to the output of the delay circuit 991a, and a one-shot pulse generation circuit 992a that generates a one-shot pulse signal having a predetermined pulse width in response to the output of the delay circuit 991b. A one-shot pulse generating circuit 992b generates a one-shot pulse signal having a predetermined pulse width, and a one-shot pulse generating circuit 992c generates a one-shot pulse signal having a predetermined pulse width in response to the output of a delay circuit 991c. Clock signals φ1 and /φ1 are generated from one-shot pulse generation circuit 992a.

[0292] The outputs of the one-shot pulse generation circuit 992b and the one-shot pulse generation circuit 992c are output from the OR circuit 9.
Given to 93. Clock signal φ from OR circuit 993
2 is generated. The delay time of delay circuit 991b is shorter than the delay time of delay circuit 991c. Enabling/disabling of the one-shot pulse generating circuits 992a to 992c is set by 2-bit command data WR0. When the 2-bit command data WR0 indicates latch mode, the one-shot pulse generation circuit 99
2a and 992c are enabled, and one-shot pulse generation circuit 992b is disabled. Next, the operations of the command register and data output circuit shown in FIGS. 59 to 62 will be explained.

First, explanation will be given with reference to the operational waveform diagram of the latch operation shown in FIG. 63. The latch output mode of the data output mode is set by setting the lower two bits of command data register WR0 to (01). At this time, one shot pulse generation circuits 992a and 99
2c is enabled. It is now assumed that the output enable signal G# is in an active state of "L" indicating data output. At this time, external address An is taken into the address buffer at the rising edge of clock K, the corresponding SRAM word line SWLn is selected, and data RDn appears on SRAM bit line pair SBL. At this time, the one-shot pulse generation circuit 992a outputs the external clock K.
In response to the rising edge of , a one-shot pulse is generated at a predetermined timing and becomes "L" for a predetermined period. When the clock signal φ1 falls to "L", the output latch 981 is inhibited from latch operation. At this time, the clock signal φ2 is at "H" and maintains the latched state.
Data Qn-1 read in the previous cycle is latched and output. 64 selected by this external address
Of the data RDn on the SRAM bit line pair SBL of bits, 4 bits of data further selected according to the external address are transmitted to internal output data buses DB, *DB. With data DBn on data buses DB and *DB fixed, clock signal φ1 rises to "H". As a result, the output latch 981 performs a latch operation and latches the final data DBn.

Next, the one-shot pulse generation circuit 99
A one-shot pulse is generated from 2c, and the signal φ2 becomes “L”.
This causes the output latch 982 to newly take in this latched data DBn and transmit it to the output terminal DQ via the output buffer 983.The generation of this clock signal φ2 is synchronized with the falling edge of the clock K. The data selected in this cycle in response to the falling edge of the external clock K is output from QDBn to the output data Qn.
is output as Clock signal φ2 rises to "H" by the time external clock K rises next. This results in
Output latch 982 connects internal output data buses DB, *DB
The final data DBn is continuously output regardless of the data.

Subsequently, the clock signal φ1 is lowered to "L" to release the latched state of the output latch 981 and prepare for the next cycle, that is, the next definite data latching operation. As a result, in response to the rise of external clock K, the data read in the previous cycle is sequentially output as definite data.

Next, the register mode will be explained with reference to FIG. The register mode is set by setting the lower two bits of command data WR0 to (11). In this register output mode, one-shot pulse generation circuit 992b is enabled and one-shot pulse generation circuit 992c is disabled. In this case, in response to the rise of external clock K, one-shot pulse generation circuit 992b
A one-shot pulse is generated which falls from 0 to 0 to "L". At this time, since the clock signal φ1 is at "H", the output latch 982 latches the data DBn-1 read in the previous cycle.

In the register output mode, the falling timing of the clock signal φ2 to “L” is determined by the external clock K.
is determined in response to the rising edge of . In this case, in response to the (n+1)th cycle of external clock K, read data DBn in the nth clock cycle is outputted to output pin terminal DQ as output data Qn. Therefore, the latch output mode and the register output mode differ only in the generation timing of the clock signal φ2, that is, the transition timing to "L". This allows a latch output mode in which the data of the previous cycle is output, followed by the data read in the current cycle, and a register output in which the data read in the n-th cycle is output in the (n+1)th cycle. mode is realized.

Next, the transparent mode will be explained with reference to FIGS. 65 and 66. First, the first transparent output mode will be explained with reference to FIG. This transparent output mode is performed by setting the lower two bits of register WR0 to X0 as described above. The first transparent output mode and the second transparent output mode are selected by setting the bit value of this X to 0 or 1. At this time, which value is used to select either the first transparent output mode or the second transparent output mode is arbitrary. In the first transparent output mode, both clock signals φ1 and φ2 remain at "L". At this time, the output latch 981 is released from the latch operation, and the output latch 982 is also in the through state. Therefore, in this case, the output data Qn is DBn transmitted on the internal data buses DB, *DB.
will be output as is. That is, if the data on SRAM bit line pair SBL or global I/O line pair GIO is invalid data (INVALID DATA), in response, invalid data IN is also sent to output pin DQ.
V appears.

In the second transparent output mode shown in FIG. 66, clock signal φ1 is generated. While the clock signal φ1 is “H”, the first output latch 98
1 performs a latch operation, the SRAM bit line pair SB
Even if the L data RDn becomes invalid, the data bus D
The data of B, *DB is latched as valid data by the latch circuit 981, and for a predetermined period (“H” of clock signal φ1
”), the period during which the invalid data INV is output is shortened. Also in this second transparent output mode, the clock signal φ2 remains at “L”.

In the above configuration, a down edge trigger type D flip-flop is used as the second output latch 982, but it is also possible to use an up edge trigger type latch circuit by changing the polarity of the clock signal φ2. A similar effect can be obtained. Further, the configuration of the output latch 981 can also be realized using other latch circuits.

The characteristics of the output mode set by this command register are summarized as follows.

(1) Transparent output mode: This mode is a mode in which data on internal data buses DB, *DB is directly transmitted to the output buffer. In this mode, valid data of output data DQ (Q) appears later, either after time tKHA has elapsed from the rising edge of external clock K or after time tGLA has elapsed from the falling edge of output enable signal G#. When output enable signal G# falls before time tKHA, invalid data (inv) is output until time tKHA. This is because if the falling timing of the output enable signal G# is fast, the internal data buses DB, *D
This is because no valid data appears in B. Therefore, in this mode, the period in which output data is valid is limited to the period in which valid data appears on the internal bus.

(2) Latch output mode: In this mode, an output latch circuit is provided between internal data buses DB, *DB and the output buffer. In this latch output mode, data is latched by the output latch circuit while the external clock K is “H”, so the time t
When the output enable signal G# falls before KHA, the read data of the previous cycle is output. Therefore, even during a period when invalid data appears on internal data buses DB and *DB, invalid data is not output to the outside. In other words, it is possible to obtain the effect that a sufficient period can be taken for the CPU to acquire output data.

(3) Register output mode: This mode is a mode in which an output register is provided between the internal data bus and the output buffer. In this register output mode, output data is output after time tKHAR from the rising edge of external clock K or after time tG from the falling edge of output enable signal G#.
Valid data in the previous cycle is output later after LA has elapsed. In this register mode, invalid data is not output for the same reason as in the latch mode. When data is output continuously in this register mode, the data appears to be output at a very high speed when viewed from the rise of the external clock K. Such an operation is generally called a pipeline operation, and the apparent access time can be further reduced than the cycle time.

[0305] By allowing the above-described output mode to be set using the command register, the user can select an output mode that is appropriate for the system.

The functions of the remaining command registers are not specified, but they can be applied to any purpose. Next, the state transition of this CDRAM will be explained with reference to a state transition diagram.

FIG. 67 is a diagram showing the state transition of the CDRAM at the time of a cache miss (mishit). Figure 67(A)
67(B) shows a state transition flow, and FIG. 67(B) shows a state transition between cycles. In FIG. 67, each cycle is indicated by a cycle number.

In FIG. 67, when a cache miss occurs, the copy back cycle (cycle No. 3) shown in FIG. 42 is first performed. This allows D
The data transfer mode to RAM is set. Then figure 4
Array access cycle shown in 6 (cycle No. 7)
is repeated n (n=(ta/tk)-1) times. Here, ta is the cycle time of the DRAM, and tk is the cycle time of the external clock K. This cycle No. By repeating step 7 n times, the batch transfer of data blocks from SRAM to DRAM is completed. Next, a block transfer cycle (cycle No. 4) shown in FIG. 43 is performed. This sets the data transfer mode from DRAM to SRAM. This cycle No. Following cycle no. SR from DRAM by repeating step 7 n times.
Transfer of data blocks to AM takes place. After this,
The DRAM is placed in a state where it can receive the next access. This state is called block transfer mode, and the CPU can access both SRAM and DRAM thereafter.

Cycle No. 4, the array active cycle (cycle No. 7) is set to n'(n' = (ta
/2·tK)-1) times, the DRAM cannot receive the next access because the restore operation and RAS precharge to the memory cell have not yet been completed. However, in this state, the SRAM has already received block data transfer from the DRAM, so there is no need to restore it, and the data on the SRAM bit line pair is in a fixed state, and the CPU accesses the SRAM in this state. can do. This state is called a cache fill state. In this cache fill state, the CPU can only access the SRAM. What is performed after this cache fill is a cache hit write cycle (cycle No. 1) shown in FIG. 38 or a cache hit read cycle (cycle No. 2) shown in FIGS. 39 to 41. Here, this cache hit read cycle (cycle No. 2) may be in any of transparent output mode, latch output mode, and register output mode. Hit writes can be performed successively in each clock cycle, and hit read cycles can also be performed continuously in each clock cycle. It is also possible to transition from a hit read cycle to a hit write cycle.

FIG. 68 is a diagram showing state transition during array access. FIG. 68(A) shows a state transition flow in array access, and FIG. 68(B) shows a state transition diagram between each cycle. Array access includes array write, which writes data to the array, and array read, which reads data from the array. In the array write, first the array write cycle (cycle No. 5) shown in FIG.
) is carried out. This cycle No. 5, followed by cycle no. Data can be written into the DRAM array by repeating the 7 array active cycles n times.

During array read, the array read cycle (cycle No. 6) shown in FIG. 45 is performed.
DRAM is made accessible. This cycle No.
After performing the array read cycle No. 6, the array active cycle (cycle No. 7) shown in FIG.
Repeat times. In this state, data cannot yet be read from the DRAM. This cycle No. Following No. 7, the array active cycle (cycle No. 7Q) for data output shown in FIGS. 47 to 49 is repeated n'+1 times. Here cycle no. 7Q may be any of an array active cycle for transparent output, an array active cycle with latch output, and an array active cycle with register output. This cycle No. Data can be read from the array by setting output enable signal G# to "L" in the last cycle in 7Q. The cycle times for array write and array read seem to be different at first glance, but n=n
'+1, and data can be read/written to the array in the same clock cycle. After performing the array write operation or the array read operation, the array write or array read operation can be performed again.

FIG. 69 is a diagram showing state transition during refresh. FIG. 69(A) shows a flow of state transition during refresh, and FIG. 69(B) shows state transition between each cycle during refresh.

[0313] In normal refresh in which only auto-refresh of DRAM is performed and no access to SRAM is performed, a refresh cycle (cycle No. 8) shown in FIG. 53 is first performed. This is followed by an array active cycle (cycle No. 46) shown in FIG.
7) is repeated n times. This completes one auto-refresh operation according to the refresh address from the refresh counter built into the CDRAM.

[0314] During refresh with hit write, a refresh cycle (cycle No. 8W) with cache hit write shown in FIG. 54 is first performed. Following this, auto-refresh of the DRAM is performed for n clock cycles. During this time, the CPU can execute the cache hit write cycle shown in FIG. 38 n times.

[0315] During the refresh cycle with hit read, the refresh cycle with cache hit read shown in FIGS. 55 to 57 (cycle No. 8R)
will be carried out. This activates auto-refresh of the DRAM, and auto-refresh is performed in the DRAM for n clock cycles. The CPU can perform hit read for these n clock cycles. Here cycle no. The output mode of 8R may be any of transparent output mode, latch output mode, and register output mode.

Various explanations have been given regarding the configuration and operation of the CDRAM according to the present invention.
The configuration of the DRAM is not limited to that of the above-mentioned embodiment, and its capacity is not limited to the configuration of 4M bit CDRAM, that is, 4M bit DRAM and 16K bit SRAM, but DRAM and SRAM of arbitrary storage capacity can be used. May be used. Further, even if the array layout is modified according to the shape of the package, the same effects as in the above embodiment can be obtained.

Finally, data transfer is performed between the DRAM array and S
Still another embodiment of the method for communicating with the RAM array will be described.

FIGS. 70(A) to 72(B) are diagrams schematically showing the copy-back and block transfer operations performed in the event of a cache miss, which were previously explained with reference to the timing diagrams of FIGS. 41 and 42. be. First, normal copyback and block transfer operations will be explained.

In FIG. 69(A), consider the case where data D2 to which the CPU requests access is not stored in the corresponding location in the SRAM. Data D1' is stored in the corresponding location of the SRAM, that is, the cache. When this SRAM cache miss occurs, the DR is still
In AM, it is in a precharge state.

In FIG. 70(B), in response to a cache miss instruction signal, a word line (indicated by hatching in the figure) including an area where data D1' is to be stored is selected in the DRAM. This state is the array active state. In the SRAM, an area of data D1' is selected.

In FIG. 71(A), transfer instruction signal φT
SD is generated, and data D1' of the SRAM is transmitted to a corresponding region of the selected word line of the DRAM. As a result, data D1' is stored in the data area D1 of the DRAM.

In FIG. 71(B), after the transfer of data D' to data area D1 of this DRAM is completed, the DRAM array returns to the precharge state.

In FIG. 72(A), a word line (indicated by hatching in the figure) containing data D2 to which the CPU subsequently requests access is selected in the DRAM.

In FIG. 72(B), data D2 included in the selected word line is transferred to data transfer instruction signal φT.
It is transmitted to the corresponding area of the SRAM array in response to the DS. As a result, data D1 of the SRAM array becomes data D
It will be rewritten in 2. 70(A) to FIG. 71(B) are copy back modes, and FIG. 71(B) to FIG. 72(B) are block transfer modes. The reason why the step in FIG. 71B is included in both cycles is that if both are performed successively, this DRAM precharge period is considered to be included in both cycles.

In this data transfer method, a DRAM array precharge period is interposed, and data transfer is always unidirectional. Therefore, SR at high speed
Data transfer cannot be performed between the AM array and the DRAM array. In this case, FIGS. 8, 9 and 12
If a bidirectional transfer circuit as shown in FIG. 1 is used, data transfer between a DRAM array and an SRAM array can be performed in an overlapping manner. A data transfer operation of a semiconductor memory device that performs this data transfer at a higher speed and satisfies the demand for high-speed operation will be described below.

FIG. 1 is a block diagram schematically showing the configuration of a data transfer device according to an embodiment of the present invention. In the data transfer device shown in FIG. 1, a circuit portion that performs 1-bit data transfer between an SRAM array and a DRAM array is shown. Therefore, the data transfer device includes 16×4 bidirectional transfer gate circuits shown in FIG. Hereinafter, the data transfer device shown in FIG. 1 will be referred to as a bidirectional transfer gate circuit because it transfers 1-bit data.

Referring to FIG. 1, the bidirectional transfer gate circuit includes a gate circuit 1810 that connects SRAM bit line pair SBL, *SBL to latch circuit 1811 in response to transfer control signal φTSL, and a gate circuit 1810 that connects SRAM bit line pair SBL, *SBL to latch circuit 1811 in response to transfer control signal φTLD. A gate circuit 1812 that responds to transmit the latch data of the latch circuit 1811 to the global I/O lines GIO, *GIO;
Write data bus line D in response to RAM write enable signal AWDE and SRAM column decoder output SAY.
Data on BW, *DBW is transferred to global I/O line GIO
, *Includes a gate circuit 1813 for transferring data to GIO. S.R.
The output SAY of the AM column decoder is one of the 16 bits simultaneously selected in the DRAM array block.
Select bits. Therefore, in this case, a configuration in which the lower 4 bits of the column address signal of the DRAM array are applied to the SRAM column decoder is shown as an example.

[0328] The bidirectional transfer gate circuit is further activated in response to the transfer control signal φDTS, and the global I/O
Amplifier circuit 1 that amplifies data on lines GIO, *GIO
814, and the data amplified by the amplifier circuit 1814 in response to the transfer control signal φTDS is transferred to the SRAM bit line pair SB.
It includes a gate circuit 1815 that transmits data to L, *SBL.

Gate circuit 1810 and latch circuit 18
11 constitutes a first transfer means, a gate circuit 1815 and an amplifier circuit 1814 constitute a second transfer means, and a gate circuit 1812 and a gate circuit 1813 constitute a third transfer means.

SRAM write enable signal AWDE is generated when a cache miss occurs during an array access cycle and when the CPU requests data writing. That is, at the rising edge of clock signal K, when chip select signal E# becomes "L", cache hit signal CH# is "H", and write enable signal W# is "L", the transfer shown in FIG. 23 is performed. Generated from gate control circuit 262. DR by gate circuit 1813
When writing data to the AM array, the data is directly written to the global I without going through the SRAM bit line pair SBL, *SBL.
Write data can be transmitted to /O lines GIO and *GIO. This allows data to be written at high speed. Gate circuit 1812 transfers data from the SRAM array to the DRAM array in response to transfer control signal φTLD.
It is used for timing adjustment when data is transferred in batches of 4 bits (in the case of 4MCDRM). Similarly,
The gate circuit 1815 is used for timing adjustment when data is transferred in batches of 64 bits from the DRAM array to the SRAM array.

FIG. 73 is a diagram showing an example of a specific configuration of the bidirectional transfer gate circuit shown in FIG. 1.

Gate circuit 1810 is made conductive in response to transfer control signal φTSL, and N-channel MOS transistors T102 and T103 amplify the signal potential on SRAM bit line pair SBL and *SBL, and transistor T
102, the data amplified by T103 is transferred to the latch circuit 18
N-channel MOS transistor T100 transmitting to 11
, T101. Transistor T102 has its gate connected to SRAM bit line SBL, one conductive terminal connected to ground potential Vss, and the other conductive terminal connected to one conductive terminal of transistor T100. Transistor T103 has its gate connected to the SRAM bit line pair*
SBL, and one conductive terminal is connected to the ground potential Vss.
The other conductive terminal is connected to the transistor T101.
Connected to one continuity terminal.

[0333] The latch circuit 1811 has inverter circuits HA10 and HA1 to which each input is connected to the output of the other.
Contains 1. This inverter circuit HA10 and HA11
constitutes an inverter latch. Latch circuit 1811 further includes inverter circuits HA12 and HA13 that invert the latched data of the inverter latches (inverter circuits HA10 and HA11).

[0334] The gate circuit 1812 is a global I/O
Gate circuit 1812 for transmitting data to line GIO
b, and a gate circuit 1812a for transmitting data to global I/O line *GIO. Gate circuit 181
2a is composed of an n-channel MOS transistor T105, and gate circuit 1812b is composed of an n-channel MOS transistor T106. Transistor T105
Transfer control signal φTLD is applied to the gate of T106.

[0335] The amplifier circuit 1814 is a global I/O
n-channel MOS for amplifying the potential on line *GIO
Transistor T113 and an n-channel MOS that turns on in response to transfer control signal φTDS and transmits data amplified by transistor T113 to node N100.
transistor T112, a p-channel MOS transistor T111 that precharges node N110 to power supply potential Vcc in response to transfer control signal φTDS, and
p-channel MOS transistor T11 connected in parallel with transistor T111 between cc and node N100
Contains 0.

The amplifier circuit 1814 also includes an n-channel MOS transistor T117 for amplifying the signal potential on the global I/O line GIO, and a transfer control signal φTD.
An n-channel MOS transistor T116 is turned on in response to S and transmits the signal potential on the global I/O line GIO amplified by the transistor T117 to the node N110, and an n-channel MOS transistor T116 is turned on in response to the transfer control signal φTDS.
A p-channel MOS transistor T114 that precharges 110 to the power supply potential Vcc, and a power supply Vcc and node N
110 includes a p-channel MOS transistor T115 connected in parallel with a transistor T114.

Transistor T110 has its gate connected to node N110, and transistor T115 has its gate connected to node N100. Transistor T1
10 and transistor T115 constitute a differential amplifier circuit.

The gate circuit 1815 is a gate circuit 1815a for transferring data to the SRAM bit line SBL.
and a gate circuit 1815b for transferring data to the SRAM bit line *SBL. Gate circuit 1815a
includes an n-channel MOS transistor T120 that turns on in response to transfer control signal φTDS and transmits the signal potential on node N100 to SRAM bit line SBL. Gate circuit 1815b is an n-channel MOS that turns on in response to transfer control signal φTDS and transmits the signal potential on node N110 to SRAM bit line *SBL.
Includes transistor T121.

The gate circuit 1813 includes a gate circuit 1813a for transmitting the signal potential on the internal data bus line *DBW onto the global I/O line *GIO, and a gate circuit 1813a for transmitting the signal potential on the internal data bus line *DBW onto the global I/O line *GIO. O line GIO
It includes a gate circuit 1813b for upward transmission. The gate circuit 1813a receives the output S of the SRAM column decoder.
The n-channel MOS transistor T130 turns on in response to AY, and the DRAM write enable signal AWD
It includes an n-channel MOS transistor T131 that turns on in response to E. Transistor T131 and transistor T130 are connected in series between internal write data bus line *DBW and global I/O line *GIO.

Gate circuit 1813b includes an n-channel MOS transistor T132 that is turned on in response to the output SAY of the SRAM column decoder, and an n-channel MOS transistor T133 that is turned on in response to the SRAM write enable signal AWDE. . Transistor T132 and transistor T133 are connected in series between internal data bus line DBW and global I/O line GIO. Next, the operation of this bidirectional transfer gate circuit will be explained.

First, referring to FIG. 74, a data transfer operation during a cache miss write operation will be described. In a cache miss write, at the rising edge of clock signal K, chip select signal E# and write enable W# both become "L", and cache hit signal C
H# becomes "H" (see FIG. 43). In response to this,
Both DRAM and SRAM are activated. At this time, the address given to SRAM and DRAM is CP
This is the address given by U.

At time t1, the DRAM completes the precharge cycle and enters the memory cycle. In response, equalize signal φEQ rises to an inactive state of "L". By the time the DRAM word line DWL is in the selected state in the DRAM, the signal potential on the internal data bus line DBW is determined to a value corresponding to the write data.

When DRAM word line DWL is set to a selected state at time t2 and the signal potential on DRAM bit line pair DBL changes, sense amplifier activation signals φSAN and /φSAP are activated at time t3 and time t4, and each The signal potential on the DRAM bit line pair takes on a value corresponding to the read memory cell data.

On the other hand, in the SRAM, the SRAM word line SWL is selected at time ts1, and the data of the memory cell connected by this selected word line SWL is transferred to the corresponding SRAM.
It is transmitted to RAM bit line SBL (*SBL). S.R.
When the signal potential on the AM bit line SBL (*SBL) is determined, the transfer control signal φTSL rises to "H", the gate circuit 1810 opens, and the SRAM bit lines SBL, *SB
The signal potential on L is transmitted to the latch circuit 1811. That is, in the circuit configuration shown in FIG.
100 and T101 are turned on, one of transistors T102 and T103 is turned on and the other is turned off, and this transistor (T
102 or T103), the "L" potential is transmitted to the latch circuit 1811. The latch circuit 1811 latches this applied "L" signal potential to the corresponding node.

[0345] In DRAM, this latch circuit 18
In parallel with the data latch operation by 11, the column selection line CS
Selection of L is performed (time t5), thereby determining the potential on local I/O line LIO, and then block selection signal φBA changes the potential on local I/O line LIO to global I/O line GIO. (*GIO) is transmitted upward (time t6).

[0346] When the signal potential on global I/O line GIO (*GIO) is determined, DRAM write enable signal AWDE rises to "H". At this time, the output signal SAY from the SRAM column decoder becomes active,
A gate circuit 1813 provided for one global I/O line among the 16 bits is opened. As a result, write data appearing on data bus lines DBW and *DBW is transmitted onto global I/O lines GIO and *GIO via gate circuits 1813b and 1813a.

[0347] At time t7, global I/O line G
When the signal potential on IO (*GIO) reaches a value corresponding to the write data, the transfer control signal φTDS is activated at time t7'.
rises to “H”. In response, transistor T
111 and T114 are turned off, and node N10
0 and N110 are stopped, and transistors T110 and T115 are connected to the global I/O line G transmitted through transistors T112 and T116.
Differentially amplify the signal potentials on IO and *GIO. As a result, the signal potentials at nodes N100 and N110 become potentials that are the inversion of the signal potentials on global I/O lines *GIO and GIO. For example, now global I/O
Signal potential on line GIO is “H”, global I/O line*
Consider the case where the signal potential on GIO is "L". At this time, the transistor T117 is on, and the transistor T1
13 is turned off, and the potential of node N110 becomes “L”
Therefore, the potential of the node N100 becomes "H". The "L" potential of this node N110 is the transistor T1
10 is turned on, and the "H" potential of node N100 turns transistor T115 off. Transistors T110 and T115 differentially amplify and latch the signal potentials at nodes N100 and N110.

In parallel with the amplification operation in amplifier circuit 1814, gate circuits 1815a and 1815b become conductive in response to the rise of transfer control signal φTDS to "H", and the signal potential on node N100 becomes
The signal potential on node N110 to bit line SBL is SR
It is transmitted onto the AM bit line *SBL. At this time, since the transfer control signal φTLD is fixed at "L", the gate circuits 1812a and 1812b are closed, and the data latched by the latch circuit 1811 is transferred to the global I
It is not transmitted to /O lines GIO and *GIO.

On the other hand, in the DRAM array, write data transmitted onto global I/O line GIO is transmitted to DRAM bit lines DBL, *DBL) via local I/O line LIO (*LIO). .

At time t8, the memory cycle of the DRAM is completed, and a precharge period begins, and at time t9, the DRAM enters a standby state waiting for the next cycle.

In the SRAM, the potential of the SRAM word line SWL falls to "L" at time ts2, and
one cycle is completed.

As described above, during a cache miss write operation, write data is written to the corresponding memory cell of the DRAM array, and data changed by this external write data is transmitted to the SRAM array. After the data transfer cycle is completed, writing of data to the memory cell data of the SRAM is completed, and data can be written at high speed even in the event of a cache miss.

The above-described data transfer operation (hereinafter referred to as high-speed copyback mode) is schematically shown in FIGS. 75 to 77. The data transfer operation in the high-speed copyback mode at the time of cache miss write will be described below with reference to FIGS. 75 to 77.

Consider the case where the CPU issues a request to rewrite data D2 to data D. At that time, the SRAM CP
Consider the case where data D1' is stored in the area to which U has requested access, and data D2 is stored in the DRAM array (FIG. 75(A)).

When such a cache miss write occurs, data D1' is first transferred to the latch (latch circuit 1811) in the SRAM. In parallel with this transfer operation, the word line (hatched part) containing data D2 is transferred to the DRAM according to the access from the CPU.
is selected, and the write data D is transmitted to the data D2 storage area connected to this selected word line (see FIG. 75).
B)). As a result, data D2 in the DRAM is rewritten to D2'.

[0356] Next, data D2' rewritten with external write data D in this DRAM is transferred to the area of the SRAM to which the CPU has requested access. As a result, the area of the SRAM that previously stored data D1' is rewritten with data D2' (FIG. 76(A)). As a result, the data rewritten with data D2 is stored in the area of the SRAM to which the CPU has requested access. After this transfer is completed, the DRAM enters a precharge state. SRAM can be accessed in this state (FIG. 76(B))
.

Next, the data D stored in this latch
1' is transferred to area D1 of DRAM. Next, the operation of transferring data D1' latched in this latch to the DRAM array will be described with reference to FIG. 77.

FIG. 77 is a signal waveform diagram showing the data transfer operation from SRAM to DRAM. In FIG. 77, first, at time t1, an array access request is made and an address (for example, output from the tag memory) specifying the area in which data D1' is to be stored is given. Next, from time t1 to time t6, the DRAM word line DWL is selected, the memory cell data connected to the selected word line is sensed and amplified, and the local I/O line and global I/O line are /O line GIO (*GI
O) The above data is confirmed.

At time t7, transfer control signal φTLD is generated, and gate circuit 1812 shown in FIG. 1 is opened. That is, in FIG. 73, the transistor T105
and T106 is turned on, and the latch circuit 1811
The data latched on the global I/O line GIO
and transmitted onto *GIO. This global I/O
The data transmitted onto line GIO (*GIO) is transmitted via local I/O line LIO (*LIO) onto DRAM bit line DBL (DBL) selected by column selection line CSL. As a result, D of data D1 in SRAM is
The transfer operation to RAM is completed.

Transfer operation of data latched by this latch circuit 1811 to DRAM (copy back operation)
Inside, the SRAM can be accessed arbitrarily. That is, at this time, the address given to DRAM and the address given to SRAM are independent addresses (during this copyback transfer,
(16 bits x 4 bits of data are transferred all at once), so the SRAM column decoder is
A selection operation can be performed according to AM address signal Ac. At this time, the gate circuit 1815 transfers the transfer control signal φ
Because TDS is “L” and the transfer control signal φTSL is also “L” and the gate circuit 1810 is in the closed state, DR
The AM array and SRAM array are separated, and the SR
The AM array can be accessed independently without being affected by data transfer operations to the DRAM array.

FIG. 78 is a diagram schematically showing the data transfer operation from this latch circuit to the DRAM. Figure 78(A)
, data D1' is stored in the latch. In the DRAM, a word line (hatched area) including an area for storing data D1 is selected according to an external address (given from a tag memory or the like).

Next, the data D1' latched by this latch circuit is transferred to the area D1 included in the selected word line, and the data in this area changes to D1'. This completes the data transfer from the latch to the DRAM.

Next, the operation at the time of cache miss read will be explained. The behavior at this cache miss read is as follows:
Except that the DRAM write enable signal AWDE is in the "L" state and the gate circuit 1813 is in the closed state.
This is the same operation as the cache miss write shown above. That is, in this case, as shown in the operation waveform diagram of FIG. 79, word lines SWL and DWL are first selected in the SRAM array and DRAM array, and
The data in the M array is latched by the latch circuit 1811, and the data from the DRAM array is transferred to the SR at time t7.
It is transmitted to AM bit line SBL (*SBL). After the data transfer to the SRAM at time t7, the SRAM
Since no precharge operation is required in this step, this transfer data can be read immediately. therefore,
At the time of a cache miss, data write operations and data read operations can be executed in the same cycle time. The data transfer operation from the latch circuit 1811 to the DRAM is the operation at the time of cache miss write shown earlier (FIG. 77).
and FIG. 78).

[0364] Now, the SR specified by the address from the CPU
Data D1' is stored in the AM array area,
Consider a state in which the CPU requests data D2. At this time, the DRAM and SRAM are now in a standby state (FIG. 80(A)).

[0365] When such a cache miss occurs,
First, in the SRAM, an SRAM word line is selected, and data D1' is latched (latch circuit 1811).
will be forwarded to. In parallel with this latch operation, in the DRAM, a word line (hatched area) containing data D2 is selected according to the address from the CPU (
Figure 80(B)).

Next, the data D2 contained in the selected word line of this DRAM is transmitted to the SRAM via the amplifier circuit 1814 and the gate circuit 1815 to the area of the SRAM that previously stored the data D1'. The latch circuit 1811 is in a latched state for this data D1'. S.R.
In AM, data D2 transferred from DRAM can be read immediately.

[0367] After data transfer from DRAM to SRAM,
The DRAM temporarily shifts to a precharge state in order to replace data D1 with data D1'. The area for storing the data D1 is the area where the data D1' stored in the SRAM should be stored (FIG. 81(B)).

After completion of precharging in the DRAM, a word line (hatched area) containing data D1 is selected (FIG. 82(A)). During this word line selection cycle (array active cycle), the SRAM
can be accessed from the outside.

Data D1' latched in the latch (latch circuit 1811) is transferred to the area for storing data D1 included in the selected word line of this DRAM. As a result, the data D1 in the DRAM is rewritten with the data D1' previously stored in the SRAM (Fig. 8
2(B)).

[0370] The address given from the outside is D.
In the RAM, when a word line is selected during data transfer to the SRAM, the address is from the CPU, and when the word line is selected when receiving data from the latch circuit, the address is from an external source, for example, a tag memory.

FIG. 83 is a diagram schematically showing the configuration of a bidirectional data transfer device according to another embodiment of the present invention. Similar to FIG. 1, FIG. 83 shows a bidirectional transfer gate circuit related to transfer of 1-bit data in a bidirectional data transfer device. In FIG. 83, parts corresponding to parts of the circuit shown in FIG. 1 are given the same reference numerals.

Referring to FIG. 83, the bidirectional data transfer circuit has, in addition to the configuration of the bidirectional data transfer circuit shown in FIG.
It includes a gate circuit 1817 provided between SRAM bit line pair SBL, *SBL and internal write data transmission lines DBW, *DBW. This gate circuit 1817 is an SRAM
It becomes open in response to the column decoder output SAY and the SRAM write enable signal SWDE. SRAM write enable signal SWDE is a signal generated when writing data to SRAM, and is generated when write enable signal W# is in the active state of "L" in both cache hit and cache miss.

FIG. 84 is a diagram showing an example of a specific configuration of the bidirectional transfer gate circuit shown in FIG. 83. In FIG. 84, gate circuit 1817 operates on internal write data bus line DB.
A gate circuit 1817a for transmitting write data on W to SRAM bit line SBL and write data bus line *D
It includes a gate circuit 1817b for transmitting write data on BW to SRAM bit line *SBL. Gate circuit 1
817a is an n-channel MOS transistor T that is turned on in response to the output SAY of the SRAM column decoder.
141, and an n-channel MOS transistor T that turns on in response to the SRAM write enable signal SWDE.
140 included. Gate circuit 1817b includes an n-channel MOS transistor T143 that is turned on in response to the output SAY of the SRAM column decoder, and an n-channel MOS transistor T142 that is turned on in response to the SRAM write enable signal SWDE. Gate circuits 1817a and 1817b both transfer data on internal data bus lines DBW and *DBW to SRAM when output SAY of the SRAM column decoder and SRAM write enable signal SWDE are in the active state "H".
It is transmitted onto bit lines SBL and *SBL. The other circuit configuration is similar to the circuit configuration shown in FIG. 73. Next, the data transfer operation from DRAM to SRAM at the time of cache miss write will be explained with reference to FIG. 85, which is an operation waveform diagram.

Until time t7, the same operation as in the case of the bidirectional transfer gate circuit shown in FIGS. 1 and 73 is performed, and data from the SRAM is latched in the latch circuit 1811, and data from the DRAM array is The memory cell data of is transmitted onto the global I/O line GIO (*GIO).

At time t7, transfer control signal φTDS
When GIO rises to “H”, the amplifier circuit 1814 and gate circuit 1815 operate, and the global I/O lines GIO,
*Amplify the signal potential on GIO to connect SRAM bit line pair S
Transmit onto BL, *SBL. In parallel with this transfer operation, the DRAM write enable signal AWDE rises to "H", the gate circuit 1816 becomes open, and the write data on the write data lines DBW, *DBW is transferred to the global I/O.
It is transmitted onto the O lines GIO and *GIO. As a result, the write data is written into the selected memory cell in the DRAM array.

On the other hand, D due to this transfer control signal φTDS
SR in parallel with data transfer operation from RAM to SRAM
AM write enable signal SWDE rises to "H", gate circuit 1817 (1817a, 1817b) becomes open, and write data on write data bus lines DBW, *DBW is transmitted onto SRAM bit lines SBL, *SBL. do. As a result, SRAM bit lines SBL, *SBL
The upper signal potential is determined to be the signal potential corresponding to the value of the write data.

[0377] Here, DRAM write enable signal A
The generation timing of WDE and SRAM write enable signal SWDE is that transfer control signal φTDS is generated and DR
It may be any time after the start of the data transfer operation from AM to SRAM.

According to the configuration of the bidirectional transfer gate circuit shown in FIGS. 83 and 84, write data on the internal write data bus line is directly transferred to the SRAM via the gate circuit 1817.
It is transmitted to bit lines SBL and *SBL. Therefore, when writing data is transferred from the internal data bus lines DBW, *DBW to the DRAM, and rewriting data in the SRAM via a route that transmits the write data from the DRAM to the SRAM, the access time of the DRAM is relatively If the length is shortened, there will be less time to transmit the write data through such a path, and there is a possibility that the data rewritten with the write data cannot be reliably transmitted to the SRAM. In such a case, the gate circuit 1817 is used to directly connect SRA from internal write data bus lines DBW, *DBW.
By adopting a configuration in which data is transmitted to M bit lines SBL and *SBL, it is possible to reliably transmit data rewritten with write data to the SRAM.

FIGS. 86 and 87 are similar to FIGS. 83 and 8.
From DRAM to SRAM of the bidirectional transfer gate circuit shown in 4.
FIG. 2 is a diagram schematically showing a data transfer operation to. This data transfer operation will be briefly explained below with reference to FIGS. 86 and 87.

First, as in FIG. 75(A), consider the case where the CPU wants to write data D2. At this time, both DRAM and SRAM are in a precharge state (FIG. 86(A)).

In FIG. 86(B), the word line (hatched area) containing data D2 is selected in the DRAM, while the data in the area containing data D1' is transmitted to the latch in the SRAM. This data D1' is data that should not be rewritten and is data that should be transferred to the data D1 storage area of the DRAM.

In FIG. 87(A), during the transfer operation of data D2 in the DRAM to the corresponding memory cell in the SRAM,
Write data D is transferred to the data D2 storage area of this DRAM and then transferred to the data D1 storage area of the SRAM. As a result, both the data D2 in the DRAM and the SRAM become data D2' rewritten with the write data D. That is, in parallel with this data transfer from DRAM to SRAM, write data D is written to SRAM and data is written to DRAM.

In FIG. 87(B), the DRAM returns to the precharge state in order to transfer the latched data D1' to the area storing data D1. In this state, the CPU can access the SRAM.

The operation of transferring the data D1' latched by the latch (latch circuit 1811) to the data D1 storage area of the DRAM is the same as that described earlier with reference to FIG. 78, and the description thereof will not be repeated.

Furthermore, in the bidirectional data transfer circuits shown in FIGS. 83 and 84, both gate circuits 1816 and 1817 are closed during the cache miss write operation, so that both gate circuits 1816 and 1817 are closed as shown in FIGS. This is similar to the data transfer operation described with reference to the forward transfer gate circuit, and only the data transfer operation schematically shown in FIGS. 80 to 82 is performed, and the description thereof will not be repeated.

[0386] By providing the gate circuit 1817 as described above, even if there is no time to transfer data to SRAM after rewriting the data in DRAM with write data D, the data in SRAM will remain as write data D. It can definitely be rewritten.

[0387] By using the above-mentioned bidirectional data transfer device, it is possible to support the so-called "write-through mode." That is, this write-through mode is an operation mode in which data written to the SRAM is also written to the corresponding memory cell of the DRAM at the time of cache access. That is, when there is a cache hit when data exists in the SRAM, write-through is performed by executing the cache miss write operation described above. Furthermore, during a cache miss write operation when no data exists in the cache, the previous cache miss write operation may be executed to directly write data to the DRAM array.

Furthermore, when directly accessing DRAM, data can be written directly to DRAM by activating only the DRAM write enable signal AWDE, and when writing data only to SRAM at the time of a cache hit, the write When there is no need to execute through mode, this SRAM write enable signal S
Only WDE becomes active.

When data is transferred using the data transfer device shown in FIGS. 1 and 73 or 83 and 84, the DRAM requires one precharge period to receive latched data. Therefore, data can be transferred between SRAM and DRAM at high speed. Additionally, in conventional copyback and block transfer mode cycles, SRAM could only be accessed after a block transfer was performed, but with this high-speed copyback mode,
DRAM to SRA in the first data transfer cycle
To realize a semiconductor storage device with a built-in cache that can directly access the SRAM after data is transferred to the SRAM and operates at higher speed, since data is transferred to M and conventional block transfer is performed first. Can be done.

[0390] Furthermore, in this bidirectional data transfer device, since data is rewritten to the SRAM in parallel with data transfer, the cache miss read operation and the cache miss write operation are executed in the same cycle time. can do.

[0391] This high-speed copyback mode is explained by taking as an example a case in which it is applied to data transfer between an SRAM array and a DRAM array at the time of a cache miss in a semiconductor storage device with a built-in cache. However, even when data is transferred between two memory cells such as a normal SRAM array and a DRAM array, data can be exchanged at a similar high speed, greatly improving data transfer efficiency. Can be done. In other words, this bidirectional data transfer device can transfer data between a high-speed memory and a large-capacity memory in not only a semiconductor storage device with a built-in cache shown in FIG. It can be applied as a transfer device.

0392]

[Effects of the Invention] According to the first invention, while latching data from high-speed memory at the time of a cache miss,
When a data write request occurs, the write data is written to the large-capacity memory and then the rewritten data is transferred to the high-speed memory, so data transfer from the large-capacity memory to the high-speed memory is performed at high speed. It can be done with
It is possible to obtain a semiconductor memory device that can write and read data to and from a high-speed memory at high speed even in the event of a cache miss.

[0393] According to the second invention, since a separate path for directly transferring write data to the high-speed memory is provided, the access time to the large-capacity memory is shortened, and there is more time to rewrite data in the large-capacity memory. It is possible to obtain a semiconductor memory device that can reliably transfer data rewritten with write data to a high-speed memory even if the data is reduced, and that can write and read data at high speed in the event of a cache miss.

[Brief explanation of drawings]

FIG. 1 is a block diagram schematically showing the configuration of a data transfer device in a semiconductor memory device that is an embodiment of the present invention.

FIG. 2 is a diagram showing the configuration of a memory array of a semiconductor memory device with a built-in cache to which the present invention is applied.

FIG. 3 is a diagram showing a detailed configuration of a portion related to one memory block of the semiconductor memory device shown in FIG. 2;

FIG. 4 is a diagram showing an example of the configuration of the bidirectional transfer gate shown in FIG. 3;

5 is a signal waveform diagram showing a data transfer operation from a DRAM array to an SRAM array in the semiconductor memory device shown in FIG. 2;

6 is a signal waveform diagram showing a data transfer operation from a DRAM array to an SRAM array in the semiconductor memory device shown in FIG. 2, and an access operation to the SRAM after the data transfer.

7 is a signal waveform diagram showing a data transfer operation from an SRAM array to a DRAM array in the semiconductor memory device shown in FIG. 2; FIG.

FIG. 8 is a diagram schematically showing another configuration of the bidirectional transfer gate shown in FIG. 3;

FIG. 9 is a diagram showing a detailed configuration of the bidirectional transfer gate shown in FIG. 8;

FIG. 10 is a signal waveform diagram showing the operation of the bidirectional transfer gate shown in FIGS. 8 and 9 during data transfer from the SRAM array to the DRAM array.

11 is a signal waveform diagram showing a data transfer operation from the DRAM array to the SRAM array in the bidirectional transfer gate shown in FIGS. 8 and 9; FIG.

12 is a diagram showing still another configuration example of the bidirectional transfer gate shown in FIG. 3. FIG.

FIG. 13 is a diagram showing still another configuration example of the bidirectional transfer gate shown in FIG. 3;

FIG. 14 is a diagram schematically showing an example of application of the bidirectional transfer gate shown in FIGS. 8 to 13 to another configuration.

FIG. 15 is a diagram showing the overall configuration of a semiconductor storage device with a built-in cache, which is another application example of the present invention. .

16 is a diagram showing the arrangement of global I/O lines and local I/O lines in the semiconductor memory device shown in FIG. 15. FIG.

FIG. 17 is a diagram showing a cross-sectional structure of a memory cell transistor portion included in a DRAM cell.

FIG. 18 illustrates the relationship between aluminum-backed polysilicon word lines and word line shunt regions.

FIG. 19 is a plan view showing the layout of global I/O lines, column selection lines, and DRAM word lines in a semiconductor memory device according to the present invention.

20 is a diagram showing the configuration of one block of the SRAM array shown in FIG. 15. FIG.

21 is a diagram showing an example of a pin arrangement of a package that houses the semiconductor memory device shown in FIG. 15; FIG.

22 is a block diagram functionally showing the overall configuration of the semiconductor memory device shown in FIG. 15. FIG.

23 is a diagram showing a configuration example of a memory array section of the semiconductor memory device shown in FIG. 22. FIG.

FIG. 24 is a diagram showing an example of a connection relationship between internal data lines and a DRAM array to enable array access to the DRAM array in a semiconductor memory device to which the present invention is applied.

FIG. 25 is a diagram showing an example of the configuration of a data input/output circuit section for realizing a D/Q separation mode and a masked write mode in a semiconductor memory device to which the present invention is applied.

26 is a diagram showing another configuration example of the data input/output circuit section shown in FIG. 25. FIG.

27 is a diagram showing still another configuration example of the data input/output circuit section shown in FIG. 25. FIG.

FIG. 28 is a diagram showing the correspondence between DRAM addresses and SRAM addresses in a semiconductor memory device to which the present invention is applied.

FIG. 29 is a diagram showing the correspondence between DRAM column addresses and SRAM column addresses.

FIG. 30: SRA in the semiconductor memory device shown in FIG. 15;
FIG. 3 is a diagram showing a connection relationship between M bit line pairs and internal data lines.

31 is a diagram specifically showing the input/output relationship of signals of the transfer gate control circuit shown in FIG. 22; FIG.

32 is a block diagram schematically showing the configuration of the DRAM array drive circuit shown in FIG. 22. FIG.

FIG. 33 is a diagram showing a list of operational modes that can be implemented by a semiconductor memory device with a built-in cache to which the present invention is applied, and timing conditions of control signals for setting the operational modes.

34 is a diagram showing a list of the contents of the command register shown in FIG. 22 and signal conditions for setting the mode of this command register; FIG.

FIG. 35 is a diagram illustrating the correspondence between a selected command register and a special mode selected at that time.

36 is a block diagram of a system configuration when a cache system is configured using a direct mapping method using the semiconductor storage device shown in FIG. 22; FIG.

37 is a block diagram showing a system configuration when a cache system is configured using a 4-way set associative mapping method using the semiconductor storage device shown in FIG. 22; FIG.

38 is a signal waveform diagram showing the timing of control signals during a cache hit write cycle of the semiconductor memory device shown in FIG. 22; FIG.

39 is a signal waveform diagram showing the timing of each external signal for performing a cache hit read cycle in the transparent output mode of the semiconductor memory device shown in FIG. 22; FIG.

40 is a signal waveform diagram showing the timing of each external signal when the semiconductor memory device shown in FIG. 22 is operated in a cache hit read cycle in latch output mode.

41 is a signal waveform diagram showing the timing of various external signals for operating the semiconductor memory device shown in FIG. 22 in a cache hit read cycle in register output mode; FIG.

42 is a signal waveform diagram showing the timing of various external signals for operating the semiconductor memory device shown in FIG. 22 in a copy-back cycle; FIG.

43 is a signal waveform diagram showing the timing of various external signals for operating the semiconductor memory device shown in FIG. 22 in a block transfer cycle; FIG.

44 is a waveform diagram showing the timing of each external signal for setting the array write cycle of the semiconductor memory device shown in FIG. 22. FIG.

45 is a waveform diagram showing the timing of each external control signal when setting an array read cycle of the semiconductor memory device shown in FIG. 22; FIG.

46 is a waveform diagram showing the timing of each external control signal for operating the semiconductor memory device shown in FIG. 22 in an array active cycle; FIG.

47 is a signal waveform diagram showing the timing of various external signals for operating the semiconductor memory device shown in FIG. 22 in an array active cycle in transparent output mode.

48 is a waveform diagram showing the timing of each external signal for operating the semiconductor memory device shown in FIG. 22 in an array active cycle with latch output mode; FIG.

49 is a waveform diagram showing the timing of each external signal for operating the semiconductor memory device shown in FIG. 22 in an array active cycle with latch output mode; FIG.

50 is a waveform diagram showing the timing of each external signal for operating the semiconductor memory device shown in FIG. 22 in an array read cycle in transparent output mode.

51 is a waveform diagram showing the timing of various external signals for operating the semiconductor memory device shown in FIG. 22 in an array read cycle in latch output mode; FIG.

52 is a waveform diagram showing the timing of each external signal for operating the semiconductor memory device shown in FIG. 22 in an array read cycle in register output mode.

53 is a waveform diagram showing the timing of each external signal for performing a refresh cycle of the semiconductor memory device shown in FIG. 22; FIG.

54 is a waveform diagram showing the timing of each external signal for causing the semiconductor memory device shown in FIG. 22 to perform a refresh cycle together with a cache hit write; FIG.

55 is a waveform diagram showing the timing of each external signal for executing a refresh cycle with a cache hit read in the transparent output mode of the semiconductor memory device shown in FIG. 22; FIG.

56 is a waveform diagram showing the timing of each external signal for causing the semiconductor memory device shown in FIG. 22 to perform a cache hit read and a refresh cycle in the latch output mode.

57 is a waveform diagram showing the timing of each external signal for causing the semiconductor memory device shown in FIG. 22 to perform a refresh cycle along with a cache hit read in register output mode; FIG.

58 is a waveform diagram showing the timing of each external signal for setting the command register of the semiconductor memory device shown in FIG. 22; FIG.

FIG. 59 is a diagram showing a circuit configuration for setting a data output mode of a semiconductor memory device using a command register.

60 is a diagram showing an example of the configuration of the data output circuit shown in FIG. 59. FIG.

61 is a diagram showing an example of the configuration of the second output latch shown in FIG. 60. FIG.

62 is a diagram showing an example of the configuration of the output control circuit shown in FIG. 59. FIG.

63 is a signal waveform diagram showing the operation of the circuit shown in FIGS. 59 to 62 when the latch output mode is set; FIG.

FIG. 64 is a signal waveform diagram showing the operation when register output mode is set.

65 is a signal waveform diagram showing the operation of the circuit shown in FIGS. 59 to 62 when the first transparent mode is set; FIG.

66 is a signal waveform diagram showing the operation of the circuit shown in FIGS. 59 to 62 when a second transparent mode is set; FIG.

FIG. 67 is a diagram showing a state transition when a cache miss occurs in a semiconductor memory device to which the present invention is applied.

FIG. 68 is a diagram showing a state transition when an array is active in a semiconductor memory device to which the present invention is applied.

FIG. 69 is a diagram showing a state transition during refreshing of a semiconductor memory device to which the present invention is applied.

70 is a diagram showing mutual data transfer operations between a DRAM array and an SRAM array when using the bidirectional transfer gates shown in FIGS. 3, 8, and 12. FIG.

71 is a diagram illustrating mutual data transfer operations between a DRAM array and an SRAM array when using the bidirectional transfer gates shown in FIGS. 3, 8, and 12; FIG.

72 is a diagram showing mutual data transfer operations between a DRAM array and an SRAM array when using the bidirectional transfer gates shown in FIGS. 3, 8, and 12; FIG.

73 is a diagram showing an example of a specific configuration of the data transfer device shown in FIG. 1. FIG.

74 is a signal waveform diagram showing the operation of the data transfer device shown in FIGS. 1 and 73. FIG.

FIG. 75 is a diagram showing a data transfer operation in a bidirectional data transfer device that is an embodiment of the present invention.

FIG. 76 is a diagram schematically showing a data transfer operation in a data transfer device that is an embodiment of the present invention.

FIG. 77 is a signal waveform diagram showing a transfer operation from SRAM to DRAM in a data transfer device according to an embodiment of the present invention.

FIG. 78 is a diagram schematically showing a data transfer operation from SRAM to DRAM in a data transfer device that is an embodiment of the present invention.

FIG. 79 is a signal waveform diagram showing a data transfer operation at the time of a misread in a data transfer device according to an embodiment of the present invention.

FIG. 80 is a schematic diagram showing a data transfer operation at the time of a misread in a data transfer device according to an embodiment of the present invention.

FIG. 81 is a diagram schematically showing a data transfer operation from DRAM to SRAM in a data transfer device that is an embodiment of the present invention.

FIG. 82 is a diagram schematically showing a data transfer operation from SRAM to DRAM in a data transfer device that is an embodiment of the present invention.

FIG. 83 is a block diagram schematically showing the configuration of a bidirectional data transfer device according to another embodiment of the present invention.

FIG. 84 is a diagram showing an example of a specific configuration of the bidirectional data transfer device shown in FIG. 83;

FIG. 85 is a signal waveform diagram showing the operation of a bidirectional data transfer device according to another embodiment of the present invention.

FIG. 86 is a diagram schematically showing a data transfer operation in a bidirectional data transfer device according to another embodiment of the present invention.

FIG. 87 is a diagram schematically showing a data transfer operation in a bidirectional data transfer device according to another embodiment of the present invention.

FIG. 88 is a diagram showing an array configuration of a conventional 1M bit DRAM.

FIG. 89 is a diagram showing an array arrangement of a conventional semiconductor memory device with a built-in cache.

FIG. 90 is a diagram illustrating a specific arrangement of a conventional 1M bit DRAM array.

FIG. 91 is a diagram showing an array arrangement for realizing a 4-way set associative method in a conventional semiconductor memory device with a built-in cache.

[Explanation of symbols]

1 DRAM array 2 SRAM array 3 Bidirectional transfer gate circuit 13 DRAM sense amplifier + IO gate block 1
4 DRAM row decoder 15 DRAM column decoder 16a, 16b I/O line pair 21 SRAM row decoder 22 SRAM column decoder 23 SRAM sense amplifier circuit GIO Global I/O line pair LIO Local I/O line pair CSL Column selection line IOG I/ O gate CSG Column selection gate SBL SRAM bit line pair DBL DRAM bit line pair MM Memory mat 80, 90 Bidirectional transfer gate 85, 1811 Latch 86, 1815 Amplifier 100 DRAM 101 DRAM array 102 DRAM row decoder 1810 Gate circuit 1811 Latch circuit 1812 Gate circuit 1813 Gate circuit 1814 Amplifier circuit 1815 Gate circuit 1817 Gate circuit

Claims (2)

[Claims] 1. A data transfer device in a semiconductor storage device that accesses a high-speed memory when a cache hit occurs and accesses a large-capacity memory when a cache miss occurs, wherein the high-speed memory and the large-capacity memory are formed on the same semiconductor chip. and when the cache miss occurs,
a first transfer means for transferring data of a memory cell of the high-speed memory selected according to an external address to a corresponding memory cell of the large-capacity memory; provided separately from the first transfer means; , for transferring data in a memory cell of the large capacity memory specified by the external address to a memory cell of the selected high speed memory via a transfer path different from a data transfer path of the first transfer means; In response to a data write instruction signal to the second transfer means and the large-capacity memory, the data transfer operation of the first transfer means is inhibited, and data is written to the designated memory cell of the large-capacity memory. A data transfer device for a semiconductor memory device, the data transfer device comprising: third transfer means for transferring write data and transferring the write data to the selected memory cell of the high speed memory via the second transfer means. 2. A data transfer device in a semiconductor storage device that accesses a high-speed memory when a cache hit occurs and accesses a large-capacity memory when a cache miss occurs, wherein the high-speed memory and the large-capacity memory are formed on the same semiconductor chip. and when the cache miss occurs,
a first transfer means for transferring data in a memory cell of the high-speed memory selected according to an external address to a corresponding memory cell of the large-capacity memory; the first transfer means transfers data transferred from the high-speed memory; , and when the cache miss occurs, the data in the large capacity memory selected according to the external address is transferred to the high speed memory via a path different from the data transfer path of the first transfer means. a second transfer means for transferring write data to the selected memory cell of the large capacity memory in response to a data write instruction signal to the large capacity memory; a third transfer means for transferring the data to the selected memory cell of the large capacity memory by the third transfer means; and a third transfer means for inhibiting the transfer operation of the first transfer means; The second transfer means is activated after the start of transfer of write data, and the second transfer means is activated after the data of the selected memory cell of the high speed memory is latched by the latch means of the first transfer means. 3, which is provided separately from the second transfer means, and transfers the write data to the selected memory cell of the high-speed memory in response to a data write instruction signal to the high-speed memory, bypassing the second transfer means. A data transfer device in a semiconductor memory device, comprising a fourth transfer means.