JP2001273766A - Semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To change a data output mode in accordance with use environment. SOLUTION: An output control circuit (272b) sets the data output timing of an output circuit (274a) conforming to an output mode specifying signal stored in a command register (270).

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and, more particularly, to a large-capacity dynamic random access memory (DRAM) as a main memory and a small-capacity static random access memory (DRAM) as a cache memory. (SRAM) and a semiconductor memory device with a built-in cache integrated on the same semiconductor chip. More specifically, the present invention relates to a configuration of a data output unit of a semiconductor memory device.

[0002]

2. Description of the Related Art Recent 16-bit or 32-bit microprocessing units (MPUs) are operating at very high operating clock frequencies of 25 MHz or more. In data processing systems, standard D
RAM (Dynamic Random Access Memory)
Is often used as a large-capacity main memory because of its low bit unit price. Although the access time of this standard DRAM has been shortened, the speed of the MPU has exceeded that of the standard DRAM. For this reason, a data processing system using a standard DRAM as a main memory must make a sacrifice such as an increase in wait states (waiting states). The problem of the gap between the operating speeds of the MPU and the standard DRAM is essential because the standard DRAM has the following features.

(1) A row address and a column address are multiplexed in a time division manner and supplied to the same address pin terminal. The row address is the row address strobe signal / RAS
Is taken into the inside of the device at the falling edge. The column address is taken into the device at the falling edge of the column address strobe signal / CAS. Row address strobe signal / R
AS defines the start of a memory cycle and activates the row selection system. Column address strobe signal / CAS activates a column selection system. "RAS-CA" from when signal / RAS is activated until signal / CAS is activated.
Since a predetermined time called "S delay time (tRCD)" is required, there is a limitation due to address multiplexing that there is a limit in shortening the access time.

(2) Row address strobe signal / R
When AS is started up once and the DRAM is set to the standby state, the row address strobe signal / RAS becomes R
Only after a lapse of a time called an AS precharge time (tRP) can the voltage fall to "L" again. The RAS precharge time is required to reliably precharge various signal lines of the DRAM to a predetermined potential. Therefore, the cycle time of the DRAM cannot be shortened by the RAS precharge time tRP.
Further, shortening the cycle time of the DRAM requires the DR
Since the number of times the signal line is charged and discharged in the AM increases, the current consumption also increases.

(3) The DRAM is improved by improving the circuit technology and process technology such as higher integration of the circuit and the layout, and by improving the application such as the driving method.
Can be speeded up. However, MPUs have been much faster than DRAMs. ECL
High-speed bipolar RAM using bipolar transistors such as RAM (emitter-coupled RAM) and static RAM and relatively low-speed D using MOS transistors (insulated-gate field-effect transistors)
The operation speed of a semiconductor memory, such as a RAM, has a hierarchical structure. It is very difficult to expect a speed (cycle time) of several tens of nS (nanosecond) in a standard DRAM including a MOS transistor as a component.

Various improvements have been made in application from the viewpoint of filling the speed gap (difference in operation speed) between the MPU and the standard DRAM. The main reasons for such improvements are:
(1) Use high-speed mode and interleave method of DRAM; (2) High-speed cache memory (SRAM)
Is provided outside.

In the case of the above method (1), there are a method using a high-speed mode such as a static column mode or a page mode, and a method combining this high-speed mode and an interleave method. The static mode is a method of sequentially accessing only one row of memory cells by selecting one word line (one row) and then sequentially changing only the column address. The page mode is a method in which, after selecting one word line, a signal / CAS is toggled to sequentially take in a column address and sequentially access memory cells connected to the one word line. In any of these modes, the memory cell can be accessed without including the toggle of the signal / RAS.
It is faster than access using CAS.

The interleave method is a method in which a plurality of memories are provided in parallel on a data bus and accesses to the plurality of memories are alternately or sequentially performed, thereby effectively reducing the access time. The method using the high-speed mode of the DRAM and the method of combining the high-speed mode and the interleave method are conventionally known as a method of using the standard DRAM as the high-speed DRAM simply and relatively efficiently.

The above method (2) is a method widely used in mainframes for a long time. This high-speed cache memory is expensive. However, in the field of personal computers, which are required to have high performance at a low cost, some computers are unavoidably used to improve the operation speed at the expense of a certain amount of cost. Regarding where to provide the high-speed cache memory, there are the following three possibilities.

(A) Built in the MPU itself. (B) Provide outside the MPU.

(C) Instead of separately providing a high-speed cache memory, a high-speed mode built in a standard DRAM is used like a cache (a high-speed mode pseudo cache memory). That is, when a cache hit occurs, the standard DRAM is accessed in the high-speed mode, and when a cache miss occurs, the standard DRAM is accessed in the normal mode. These three methods (a) to (c) have already been adopted in some form in data processing systems.

However, from the viewpoint of price, many M
In the PU system, in order to prevent the RAS precharge time (tRP) unavoidable in the DRAM from being exposed effectively, a method is used in which the memory is configured in a bank and interleaved for each memory bank. According to this method, the cycle time of the DRAM can be substantially reduced to almost half of the specification value (specification value). The interleaving method is effective only when the access to the memory is performed sequentially. That is,
If the same memory bank is accessed continuously, no effect is obtained. Further, this method cannot substantially improve the access time of the DRAM itself. Further, the minimum unit of the memory needs to be at least two banks.

When a high-speed mode such as a page mode or a static column mode is used, the access time can be effectively reduced only when the MPU continuously accesses a certain page (data of one specified row). it can. This method has a certain effect because, when the number of banks is relatively large such as 2 to 4, different rows can be accessed for each bank. A case where there is no data in the memory requested by the MPU in a given page is called a “miss hit”. Usually, a chunk of data is stored at a close address or a sequential address. In the high-speed mode, there is a high probability that a "miss hit" will occur because a row address that is half the address has already been specified. However, when the number of banks is increased to 30 to 40, the data of different pages can be stored in each bank, so that the "miss hit" rate is drastically reduced. However, it is not practical to assume 30 to 40 banks in a data processing system. If a "miss hit" occurs, it is necessary to raise the signal / RAS in order to newly select a row address and return to the DRAM precharge cycle, thereby sacrificing the performance of the bank configuration. Become.

In the case of the above method (2), the MPU and the standard DR
A high-speed cache memory is provided between the AM and the AM. In this case, the standard DRAM may be relatively slow. On the other hand, standard DRAM is 4M (mega) bits, 16
M bits and large storage capacities have appeared. In a small-scale system such as a personal computer, the main memory is a standard DRAM of one chip or several chips.
Can be configured. When a high-speed cache memory is provided outside, it is not effective in a small-scale system in which the main memory can be constituted by, for example, one standard DRAM. When a standard DRAM is used as the main memory,
This is because the data transfer speed between the high-speed cache memory and the main memory is limited by the number of data input / output terminals of the standard DRAM, which is a bottleneck to the speed of the system.

In the case of the pseudo cache memory in the high-speed mode, the operation speed is slower than that of the high-speed cache memory, and it is difficult to realize a desired system performance.

As a method of eliminating the loss of system performance caused by using the above-described interleave method or high-speed operation mode, and constructing a relatively inexpensive and small-scale system, a high-speed cache memory (SRAM) may be replaced with a DR.
It can be built into AM. That is, DRAM
May be considered as a main memory and a one-chip memory having a hierarchical structure including an SRAM as a cache memory. A one-chip memory having such a hierarchical structure is called a cache DRAM (CDRAM). This CD
The RAM will be described below.

FIG. 81 shows a conventional standard 1 Mbit DR.
It is a figure showing composition of an important section of AM. In FIG. 81, D
The RAM is a memory cell array 50 including a plurality of memory cells MC arranged in a matrix of rows and columns.
Contains 0. One row of memory cells is connected to one word line WL. One column of memory cells MC is connected to one column line CL. Usually, this column line CL is composed of a pair of bit lines. One word line WL selects a memory cell located at an intersection with one bit line of the pair of bit lines. In a 1M (mega) DRAM, memory cells MC are arranged in a matrix of 1024 × 1024 columns. That is, this memory cell array 500
24 word lines WL and 1024 column lines CL (102
4 pairs of bit lines).

The DRAM is further connected to a row decoder 502 for decoding an externally applied row address (not shown) and selecting a corresponding row of the memory cell array 500, and a word line selected by the row decoder 502. And a column decoder that decodes an externally applied column address (not shown) and selects a corresponding column of memory cell array 500. In FIG. 81, a sense amplifier and a column decoder are shown by one block 504. When this DRAM has a × 1 bit configuration in which data input / output is performed in 1-bit units, one column line CL (bit line pair) is selected by a column decoder. DRAM
Has a × 4 bit configuration for inputting / outputting data in units of 4 bits, four column lines CL are selected by a column decoder. One sense amplifier of the block 504 is provided for each column line (bit line pair) CL.

At the time of memory access for writing data to memory cell MC in the DRAM or reading data from memory cell MC, the following operation is performed. First, a row address is given to the row decoder 502. The row decoder 502 decodes this row address and raises the potential of one word line WL in the memory cell array 500 to "H". This selected word line WL
Is transmitted to the corresponding column line CL. The data on the column line CL is amplified by the sense amplifier included in the block 504. The selection of a memory cell that receives data writing or reading among the memory cells connected to the selected word line WL is performed by a column selection signal from a column decoder included in block 504.

In the above-described high-speed mode, column addresses are sequentially applied to the column decoders included in block 504. In the static column mode operation, the column decoder decodes a column address given every predetermined time as a new column address, and stores a memory cell connected to the selected word line WL in column line CL.
To choose through. In the page mode, a new column address is applied to the column decoder for each toggle of signal / CAS, and the column decoder decodes the column address and selects a corresponding column line. As described above, by setting one word line WL to the selected state and changing only the column address, one connected to the selected word line WL is changed.
The memory cells MC in a row can be accessed at high speed.

FIG. 82 is a diagram showing a general configuration of a conventional 1 Mbit CDRAM. In FIG. 82, the conventional CDR
AM has the same structure as the standard DRAM shown in FIG.
It includes a RAM 506 and a transfer gate 508 for performing data transfer between one row of the DRAM memory cell array 500 and the SRAM 506. SRAM50
Numeral 6 includes a cache register provided corresponding to each column line CL of the memory cell array 500 so that data of one row of the DRAM memory cell array 500 can be stored at the same time. Accordingly, 1024 cache registers are provided. This cache register is constituted by SRAM cells. In the structure of the CDRAM shown in FIG. 82, when a signal indicating a cache hit is given from the outside, access to this SRAM 506 is performed, and the memory can be accessed at high speed. At the time of a cache miss (miss hit), access is made to the DRAM unit.

A large-capacity DRAM as described above and a high-speed S
A CDRAM in which a RAM and a RAM are integrated on the same chip is disclosed in, for example, JP-A-60-7690 and JP-A-62-273.
No. 8590 discloses this.

[0023]

SUMMARY OF THE INVENTION As described above, the conventional C
In the configuration of the DRAM, column lines (bit line pairs) CL of DRAM memory cell array 500 and column lines (bit line pairs) of SRAM (cache memory) 506 are connected via transfer gate 508 in a one-to-one correspondence. You. That is, in the configuration of the conventional CDRAM described above, the data of the memory cells connected to one word line WL in the DRAM memory cell array 500 and the data of the same number of SRAM cells as one row of the memory cell array 500 are transferred. A configuration in which bidirectional batch transfer is performed via gate 508 is employed. In this configuration,
SRAM 506 is used as a cache memory, and D
RAM is used as a main memory.

In this case, the so-called block size of the cache is considered to be the number of bits whose contents can be rewritten in one data transfer in the SRAM 506. Therefore, this block size is equal to the number of memory cells physically coupled to one word line WL of DRAM memory cell array 500. When 1024 memory cells are physically connected to one word line WL as shown in FIGS. 81 and 82, the block size is 1024.

In general, a larger block size increases a hit ratio. However, in the case of the same cache memory size, the hit rate decreases because the number of sets decreases in inverse proportion to the block size. For example, when the cache size is 4K bits, if the block size is 1024, the number of sets is 4, but if the block size is 32, the number of sets is 128. Therefore, in the case of the configuration of the conventional CDRAM, there arises a problem that the block size becomes unnecessarily large and the cache hit rate cannot be improved so much.

An arrangement for reducing the block size is disclosed, for example, in JP-A-1-146187. In this prior art, a DRAM array and an SRAM array are arranged in a one-to-one correspondence with column lines (bit line pairs), but each is divided into a plurality of blocks in the column direction. The selection of a block is performed by a block decoder. When a cache miss (miss hit) occurs, one block is selected by the block decoder. Selected DRAM
Data transfer is performed only between the block and the SRAM block. According to this configuration, the block size of the cache memory can be reduced to an appropriate size, but the following problems remain as unsolved.

FIG. 83 is a diagram showing a standard array configuration of a 1-Mbit DRAM array. In FIG. 83, DR
The AM array has eight memory blocks DMB1 to DMB8.
Is divided into A row decoder 502 is provided in common to the memory blocks DMB1 to DMB8 on one side in the long side direction of the memory array. Memory blocks DMB1 to DM
For each of B8 (sense amplifier + column decoder)
Blocks 504-1 to 504-8 are provided.

Each of the memory blocks DMB1 to DMB8 has a capacity of 128K bits. In FIG. 83, one memory block DMB has 128 rows and 102 rows.
The case where they are arranged in four rows is shown as an example. One column line CL is constituted by a pair of bit lines BL and / BL.

As shown in FIG. 83, if the DRAM memory cell array is divided into a plurality of blocks, the length of one bit line BL (and / BL) becomes shorter. At the time of data reading, the charge stored in the capacitor in the memory cell (memory cell capacitor) is transmitted to the corresponding bit line BL (or / BL). At this time, the amount of potential change generated on the bit line BL (or / BL) depends on the capacitance Cs of the memory cell capacitor and the capacitance Cb of the bit line BL (or / BL).
, Cs / Cb. As the length of the bit line BL (or / BL) decreases, the bit line capacitance Cb decreases. This makes it possible to increase the amount of potential change generated in the bit line.

In operation, the row decoder 502
Only the sensing operation is performed on the memory block (memory block DMB2 in FIG. 83) including the selected word line WL, and the standby state is maintained in the remaining blocks. As a result, it is possible to reduce the power consumption accompanying the charging and discharging of the bit line during the sensing operation.

When the above-described block-divided CDRAM is applied to the DRAM shown in FIG. 83, the SRA is applied to each of the memory blocks DMB1 to DMB8.
It is necessary to provide an M register and a block decoder. This causes a problem that the chip area is significantly increased.

As described above, the DRAM array and the SR
Bit lines correspond one-to-one with the AM array. When the direct mapping method is adopted as a memory mapping method between the main memory and the cache memory, as shown in FIG. 82, the SRAM 506 includes 1024 cache registers arranged in one row.
In this case, the capacity of the SRAM cache is 1 Kbit.

When the 4-way set associative method is adopted as the mapping method, as shown in FIG.
06a to 506d. One of the four cache registers 506a to 506d is selected by the selector 510 according to the way address. In this case SR
The capacity of the AM cache is 4K bits.

As described above, the method of mapping memory cells between the DRAM array and the cache memory is determined by the internal structure of the chip. When the mapping method is changed, it is necessary to change the cache size as described above.

In any of the above-described structures of the CDRAM, since the bit lines of the DRAM array and the SRAM array correspond one-to-one, the column address of the DRAM array and the column address of the SRAM array are inevitable. In principle, it is impossible to realize a fully associative method of mapping memory cells of a DRAM array to arbitrary positions of an SRAM array.

Another configuration of a semiconductor memory device in which a DRAM and an SRAM are integrated on the same chip is disclosed in JP-A-2-87.
No. 392. In this prior art, a DRAM array and an SRAM array are connected via an internal common data bus. The internal common data bus is connected to an input / output buffer for inputting and outputting data to and from the outside of the device. The selection positions of the DRAM array and the SRAM array can be designated by different addresses. However, in this prior art arrangement, D
Since the data transfer between the RAM array and the SRAM array is performed via an internal common data bus, the number of bits that can be transferred at one time is limited by the number of internal data bus lines, and the cache is operated at high speed. The contents of the memory cannot be rewritten. Therefore, as in the case where the SRAM cache is provided outside the standard DRAM as described above, the data transfer speed between the DRAM array and the SRAM array becomes a bottleneck, and a high-speed cache memory system cannot be constructed.

In this prior art, data is transferred between a DRAM array and an SRAM array via an internal common data bus. Therefore, there arises a problem that an operation generally called "copy back mode" cannot be performed at high speed. That is, the "copy back mode" is a step of transferring the data of the corresponding memory cell of the SRAM array to the original memory cell position of the DRAM array at the time of a cache miss, and the step of transferring the data of the DRAM memory cell requested for access to the SRAM array. To the memory cells of Although the internal common data bus is a bidirectional bus, the direction of data transfer performed at a time is from SRAM to DRAM and DRA.
One direction from M to SRAM. Therefore, in this prior art configuration, selection of a word line in the DRAM array, transfer of data from the SRAM array to the DRAM array, precharging of the DRAM array (setting to the standby state), and setting of another word line of the DRAM array A number of steps are required to select and transfer the data of the corresponding memory cell of the selected word line to the SRAM, which causes a problem that "copy back" cannot be performed at high speed.

In this prior art, data transfer between the DRAM array and the SRAM array is performed via the internal common data bus. Therefore, when a cache miss occurs, data transfer from the DRAM array to the SRAM array is performed. Only after completion and the DRAM array has been set to the standby state can the SRAM array be accessed to read data from the SRAM array. Therefore, there arises a problem that data cannot be read at a high speed at the time of a cache miss or the like.

Further, even in a general CDRAM, D
RAM requires refresh. In a CDRAM in which access to the DRAM array and access to the SRAM array cannot be performed independently, it is not possible to access the SRAM array when the DRAM array is refreshed. Therefore, the CPU cannot use the cache during this time, and the performance of the cache system is impaired.

In the conventional CDRAM, the data output timing is uniquely determined by external control signals (/ CAS and / WE). At this time, invalid data is output until the output data is determined. In application applications such as pipeline applications, it is desirable that only valid data be output at all times. Therefore, the data output timing cannot be made variable depending on the application, and the application is limited.In order to apply the pipeline processing, it is necessary to provide another latch means or the like externally. There is a problem that the scale of the cache system becomes large. When such a latch is provided externally and the latch operation is performed by the system clock, in order to prevent latching of invalid data, the data output from the latch at that time becomes the data of the previous cycle and is accessed in the current cycle. The read data cannot be read, and the application of the data is limited.

An object of the present invention is to provide a semiconductor memory device capable of changing data output timing according to an application.

[0042]

According to the present invention, there is provided a semiconductor memory device, comprising: setting means for setting an external data output mode in response to a designating signal to set a data output mode of the semiconductor memory device; Reading means for reading data of a corresponding memory cell from the cell array; and data read from the memory cell which is activated in response to a data output instruction signal from the outside and which is read by the reading means. Means for outputting at different timings according to the output mode is included.

[0043]

According to the semiconductor memory device of the present invention, the data output timing of the semiconductor memory device is determined according to the data output mode designating signal. Therefore, it is possible to obtain desired data at a desired output timing according to an application.

[0044]

FIG. 1 is a diagram schematically showing a configuration of a memory array section of a semiconductor memory device according to an embodiment of the present invention. In FIG. 1, a semiconductor memory device includes a DRAM array 1 including dynamic memory cells arranged in a matrix composed of rows and columns, and an SRAM array composed of static memory cells arranged in a matrix composed of rows and columns. 2 and this DRAM array 1 and SR
A bidirectional transfer gate circuit 3 for performing data transfer with the AM array 2 is included.

When the storage capacity is 1M bits, DRAM array 1 includes 1024 word lines WL and 1024 pairs of bit lines BL and / BL. However, in the figure, the bit line pair is indicated by DBL. This DRAM array 1 is divided into a plurality of blocks along the row and column directions, respectively. In FIG. 1, DRAM array 1 has eight columns in the column direction.
Blocks MBi1 to MBi8 (i = 1 to 4) and four blocks MB1j to MB4j in the row direction
(J = 1 to 8) is shown as an example in the case of being divided into a total of 32 memory blocks.

The eight blocks M divided in the column direction
Bi1 to MBi8 constitute one row block 11.
Four blocks MB1j to MB4j divided in the row direction
Constitutes the column block 12. The memory blocks MBi1 to MBi8 included in one row block 11 share one word line WL. Memory blocks MB1j to MB4j included in the same column block 12 are
Share SL. Each memory block MB11 to MB48
A sense amplifier + IO block 13 is provided for each. The configuration of this sense amplifier + IO block 13 will be described later. The column selection line CSL simultaneously selects two columns (two pairs of bit lines).

The semiconductor memory device further includes a row decoder 14 for selecting a corresponding row from DRAM array 1 in response to an externally applied address, and one column in response to an externally applied column address. Select line CS
A column decoder 15 for selecting L is included. Row block 1
2 is connected to the bidirectional transfer gate circuit 3 via two pairs of I / O lines 16a and 16b independent of each other.

SRAM array 2 includes 16 bit line pairs SBL connected to 16 I / O lines via bidirectional transfer gate circuit 3 respectively. This SRAM array 2 includes 16 pairs of bit lines and 256 word lines in the case of a 4K-bit capacity. Therefore, this SRA
One row of the M array 2 has 16 bits. This SRAM
An SRAM which decodes an externally applied row address for the array and selects one row of this SRAM array 2
Row decoder 21, an SRAM column decoder 22 that decodes an externally applied column address and selects a corresponding column of SRAM array 2, and an SRAM row decoder 21 and an SRAM column decoder 22 that are selected when reading data. The sense amplifier circuit 23 amplifies and outputs data of the memory cell. This S
The SRAM bit line pair SBL selected by the RAM column decoder 22 is connected to a common data bus, and inputs and outputs data to and from the outside of the device via an input / output buffer (not shown). DRAM row decoder 14 and DRAM
The address given to column decoder 15 and the addresses given to SRAM row decoder 21 and SRAM column decoder 22 are mutually independent addresses, and are given via different address pin terminals. Next, a data transfer operation of the semiconductor memory device shown in FIG. 1 will be schematically described with reference to FIG.

First, the operation of the DRAM will be described. First, a row decoder 14 performs a row selecting operation in accordance with a row address given from the outside, and one word line DW
The potential of L rises to “H”. From the memory cell connected to the selected one word line DWL, a corresponding 102
Data is read onto four bit lines BL (or / BL).

Next, sense amplifiers (included in block 13) included in row block 11 including the selected word line DWL are simultaneously activated, and differentially amplify the potential difference between each bit line pair. The reason why only one of the four row blocks 11 is activated is to reduce the power consumption associated with the charging and discharging of the bit line during the sensing operation (the row block including the selected row). The operation method that activates only the block is called a block division operation method).

Next, DRAM column decoder 15 performs a column selecting operation in accordance with an externally applied column address, and one column selecting line C in each column block 12.
SL is set to the selected state. This one column select line CS
L selects two pairs of bit lines, and connects the two pairs of bit lines to two pairs of I / O lines 16a and 16b provided corresponding to the block. Thereby, a plurality of bits (16 bits in this embodiment) from the DRAM array 1
Is read onto a plurality of I / O line pairs 16a and 16b.

Next, the operation of the SRAM portion will be described. The SRAM row decoder 21 performs a row selecting operation in accordance with a row address given from the outside, and selects one word line from the SRAM array 2. As described above, 16-bit memory cells are connected to one SRAM word line. Therefore, 16 static memory cells (SRAMs) are selected in accordance with the operation of selecting one word line.
Cell) is connected to 16 pairs of bit lines SBL.

I / O line pair 16 for DRAM array 1
After 16-bit data has been transmitted to a and 16b, bidirectional transfer gate circuit 3 is turned on, and 1
Six pairs of I / O line pairs 16a and 16b and 16
The pair of bit lines SBL are connected to each other. As a result, 16 bits already selected in the SRAM array 2
The data transmitted on the 16 pairs of I / O lines 16a and 16b are written into the bit memory cells, respectively.

The sense amplifier circuit 23 and the column decoder 22 provided in the SRAM are used to transfer data between a memory cell in the SRAM array 2 and an internal data line for inputting / outputting external data.

An address for selecting an SRAM cell in the SRAM array 2 can be set completely independently of an address for selecting a dynamic memory cell (DRAM cell) in the DRAM array 1. Therefore, the 16-bit memory cell selected in the DRAM array 1 can exchange data with a memory cell at an arbitrary position (row) in the SRAM array 2, and can perform direct mapping, set associative, and full-memory operations. All of the associative mapping methods can be realized without changing the array arrangement and configuration.

In the above description, the SRA
The operation of the 16-bit batch transfer to M has been described in principle, but the 16-bit batch transfer from the SRAM array 2 to the DRAM array 1 is performed according to the same operation. It just reverses the direction of flow. Next, the configuration and operation of the semiconductor memory device with a built-in cache according to the present invention will be described in detail in order.

FIG. 2 is a diagram showing a specific configuration of a main part of the semiconductor memory device shown in FIG. In FIG. 2, DRA
A portion related to data transfer of one memory block MBij of the M array is representatively shown. In FIG. 2, D
RAM memory block MBij includes a plurality of DRAM cells DMC arranged in a matrix. DRAM cell DMC
Includes one transistor Q0 and one capacitor C0. A constant potential Vgg is applied to one electrode (cell plate) of memory capacitor C0.

This memory block MBij further includes a DRAM word line DWL to which each row of DRAM cells DMC is connected, and a DRAM bit line pair DBL to which each column of DRAM cells is DMC connected. This DRA
M bit line pair DBL includes two bit lines BL and / B
L. Complementary signals are transmitted to bit line BL and bit line / BL. DRAM cell DMC
Is a DRAM word line DWL and a DRAM bit line pair DB
L are arranged at intersections.

Each DRAM bit line pair DBL is provided with a DRAM sense amplifier DSA for detecting and amplifying a potential difference on the corresponding bit line pair. This DR
AM sense amplifier DSA receives sense amplifier activation signal φS
The operation is controlled by a sense amplifier activation circuit SAK which generates sense amplifier drive signals φSAN and / φSAP in response to ANE and / φSAPE. DRAM
Sense amplifier DSA includes a first sense amplifier portion, in which a p-channel MOS transistor is cross-coupled and boosts the bit line potential on the high potential side to operating power supply potential Vcc level in response to signal / φSAP, and an n-channel MOS transistor. MOS
Transistors are cross-coupled and include a second sense amplifier portion that discharges the potential of the low potential side bit line to, for example, a ground potential level Vss in response to signal φSAN.

The sense amplifier activating circuit SAK is turned on in response to the sense amplifier activating signal / φSAPE, and a sense amplifier activating transistor TR1 for activating the first sense amplifier portion of the DRAM sense amplifier DSA; A sense amplifier activating transistor TR2 which is turned on in response to the sense amplifier activating signal φSANE and activates the second sense amplifier portion of the DRAM sense amplifier DSA is included. Transistor TR1 is configured by a p-channel MOS transistor, and transistor TR2 is configured by an n-channel MOS transistor. Transistor TR1 transmits drive signal / φSAP at the operating power supply potential Vcc level to one power supply node of each sense amplifier DSA when turned on. When transistor TR2 is turned on, signal φSAN at the potential Vss level is transmitted to the other power supply node of DRAM sense amplifier DSA.

Signal line / φ for outputting signals / φSAP and φSAN from sense amplifier activation circuit SAK
An equalizing transistor TEQ for equalizing both signal lines in response to the equalizing instruction signal φEQ is provided between the SAP and the signal line φSAN. Thereby, sense amplifier drive signal lines / φSAP and φSAN are precharged to an intermediate potential of (Vcc + Vss) / 2 during standby.

For each DRAM bit line pair DBL,
A precharge / equalize circuit PE, which is activated in response to a precharge / equalize signal φEQ, precharges and equalizes each bit line of a corresponding bit line pair to a predetermined precharge potential Vbl, is provided.

DRAM memory block MBij is further provided for each DRAM bit line pair DBL and is turned on in response to a signal potential on column select line CSL, and connects corresponding DRAM bit line pair DBL to local I / O. Includes column select gate CSG connected to line pair LIO. The column selection line CSL is provided in common for two pairs of DRAM bit lines, whereby two DRAM bit line pairs DBL are simultaneously selected. The local I / O line pairs receive two LIOa so that they can receive data from the two simultaneously selected DRAM bit line pairs.
And LIOb.

Memory block MBij further responds to block activation signal φBA to connect local I / O line pairs LIOa and LIOb to global I / O line pairs GIOa and GIOb, respectively.
a and IOGb. Column select line CSL extends in the row direction over one column block shown in FIG. 1, and global I / O line pairs GIOa and GIOb also extend in the row direction over one column block. Local I /
O line pairs LIOa and LIOb extend in the column direction only in one memory block.

In correspondence with FIG. 1, I / O lines 16a and 16b correspond to local I / O line pairs LIOa and LIOb, and LIO gates IOGa and IOGb, respectively.
And global I / O line pairs GIOa and GIOb.

The SRAM has an SRAM word line SWL connected to one row of SRAM cells SMC, and an SRAM connected to one column of SRAM cells SMC.
It includes a bit line pair SBL and an SRAM sense amplifier SSA provided in each of the SRAM bit line pairs SBL for detecting and amplifying a potential difference between the corresponding bit line pair.

The bidirectional transfer gate circuit 3 includes bidirectional transfer gates BTGa and BTGb provided between the SRAM bit line pair SBL and the global I / O line pair GIO. Both bidirectional transfer gates BTGa and BTGb perform data transfer between SRAM bit line pair SBL and global I / O line pairs GIOa and GIOb in response to data transfer instruction signals φTSD and φTDS. Data transfer instruction signal φTSD instructs data transfer from the SRAM portion to the DRAM portion, and data transfer instruction signal φTDS instructs data transfer from the DRAM portion to the SRAM portion.

FIG. 3 is a diagram showing an example of the configuration of the bidirectional transfer gate BTG. In FIG. 3, the bidirectional transfer gate BT
G (BTGa or BTGb) is activated in response to a data transfer instructing signal φTSD, and the SRAM bit line pair S
Drive circuit DR1 for transmitting data on BL to global I / O line pair GIO, and data transfer instructing signal φTDS
, And a drive circuit DR2 for transmitting data on global I / O line pair GIO to SRAM bit line pair SBL. Drive circuits DR1 and DR
2 is set to an output high impedance state when data transfer instruction signals φTSD and φTDS are inactive.

FIG. 4 is a signal waveform diagram showing an operation during data transfer from the DRAM array to the SRAM array. Hereinafter, the data transfer operation from the DRAM array to the SRAM will be described with reference to FIGS.

Precharge instructing signal φE before time t1
While Q is in the active state “H”, sense amplifier drive signal lines φSAN and / φSAP, local I / O line pair LIO and global I / O line pair GIO are each at Vcc / 2.
At the precharge potential. At this time, the precharge / equalize circuit PE is activated to precharge the DRAM bit line pair DBL to the precharge potential of Vcc / 2 (= Vbl) and equalize the potential of each bit line BL, / BL. .

At time t1, precharge instructing signal φ
When the EQ falls, the precharge / equalize circuit PE
And the equalizing transistor TEQ becomes inactive. As a result, the equalizing operation of sense amplifier drive signal lines φSAN and / φSAP is completed, and the equalizing / precharging operation of DRAM bit line pair DBL is stopped, and DRAM bit line pair DBL and sense amplifier drive signal lines φSAN and / φSAP are stopped. Is the intermediate potential Vcc / 2
(However, Vss = 0 V) in a floating state.

Thereafter, a row selecting operation is performed by row decoder 14 (see FIG. 1) according to an externally applied address, and one word line DWL is selected in DRAM array 1 (see FIG. 1) at time t2. The potential of the selected word line DWL rises to "H". One row of memory cells connected to the selected word line DWL are connected to a corresponding DRAM bit line pair DBL (DRAM bit line BL or / BL), and the potential of each DRAM bit line pair DBL is connected to the memory. It changes according to the cell data. In FIG. 4, DRAM bit line pair DB when a memory cell storing potential "H" is selected.
The potential change of L is shown.

At time t3, sense amplifier activating signal φSANE rises from ground potential Vss to operating power supply potential Vcc level, and transistor TR2 included in sense amplifier activating circuit SAK is turned on. Thereby, the second sense amplifier included in DRAM sense amplifier DSA is activated, and the bit lines on the lower potential side of DRAM bit line pair DBL are discharged to the level of ground potential GND.

At time t4, sense amplifier activating signal / φSAPE falls from potential Vcc to the level of ground potential GND, and transistor TR1 included in sense amplifier activating circuit SAK is turned on. This allows DR
The first sense amplifier portion included in AM sense amplifier DSA is activated, and the potential of the high-potential bit line of DRAM bit line pair DBL is charged to the operating power supply potential Vcc level.

At time t5, one column select line CSL is selected according to a column select signal from DRAM column decoder 15 (see FIG. 1), and the potential of the selected column select line CSL rises to "H". . This gives 2
DRAM bit line pair DBL is connected to local I / O line pair LIO (LIOa and LI) via column select gate CSG.
Ob). As a result, the potential on the selected DRAM bit line pair DBL is transmitted to local I / O line pair LIO, and the potential on the local I / O line pair changes from precharge potential Vcc / 2.

At time t6, block activation signal φB
A rises to "H" only for the selected row block, and I / O gate IOG is turned on. As a result, the signal potential on local I / O line pair LIO is
The signal is transmitted onto the / O line pair GIO. Here, the selected row block indicates a row block including the selected word line DWL. Designation of the selected row block is performed, for example, by decoding upper two bits of a row address used for DRAM word line selection. The current consumption can be reduced by performing the block division operation in this manner.

On the other hand, in the SRAM, a row selecting operation is performed by SRAM row decoder 21 (see FIG. 1) at time ts1, and one SRAM in the SRAM array is operated.
The RAM word line SWL is selected, and the selected SR
The potential of the AM word line SWL rises to "H". DRA
The row selection operation in M and the row selection operation in SRAM are performed asynchronously. The data of the SRAM cell connected to the SRAM word line SWL is stored in the corresponding SRAM.
It is transmitted on bit line pair SBL. Thereby, SRA
The potential of M bit line pair SBL is equal to precharge potential Vcc /
2 to a potential corresponding to the information stored in the corresponding SRAM cell.

At time t7, data transfer instruction signal φT
DS rises to "H" for a certain period. Before this time t7, the data of the DRAM cell has already been transmitted to global I / O line pair GIO, and SRAM bit line pair SB.
SRAM cells are connected to L. In response to data transfer instruction signal φTDS, bidirectional transfer gate BTG is activated to transmit the signal potential on global I / O line pair GIO to the corresponding SRAM bit line pair SBL. Thereby, data transmission from the DRAM cell to the SRAM cell is performed.

Relationship that time t7 at which data transfer instructing signal φTDS is activated is later than both time t6 at which block activation signal φBA rises and time ts1 at which SRAM word line SWL is selected. Is satisfied, the time ts1 and the time t1 to the time t6
The context is arbitrary. In this cycle, data transfer instructing signal φTSD from SRAM to DRAM is maintained at inactive “L”.

At time t8, the potential of the selected DRAM word line DWL falls to "L", and at time ts2
, The potential of the SRAM word line SWL selected falls to "L", and each signal returns to the initial state, thereby completing the data transfer cycle from the DRAM to the SRAM.

As described above, DRAM column decoder 1
5 (see FIG. 1) selects one column selection line CSL in each column block 12. One column selection line C
SL selects two pairs of DRAM bit lines DBL. D
Data transfer from the RAM to the SRAM is performed in parallel with each column block. Therefore, in the embodiment shown in this figure, 16-bit data is transferred collectively. However, this relationship is for a configuration in which eight column blocks are provided and two DRAM bit line pairs are selected from each column block. It changes depending on the number or the number of DRAM bit line pairs selected at a time. As a result, an appropriate block size can be set.

As shown in FIG. 4, when drive signal DWL of the DRAM word line falls to an inactive state substantially at time t8, data transfer instructing signal φTDS also falls to “L”. At the time t8, the local I / O
The line pair LIO and the SRAM bit line pair SBL are disconnected, and the DRAM array and the SRAM array are electrically disconnected. After this time t8, the DRAM unit and the SRAM
The operation independent of the section can be performed. Therefore, as shown in FIG. 5, at time t8 ', data transfer instructing signal .phi.TDS
Is inactive, the word line drive signal DWL is still in the active state of "H" in the DRAM array at this time.
Has been maintained. At this time, the DRAM cannot be newly accessed from outside, but the SRAM array unit can be accessed from outside.

That is, as shown in FIG. 5, at time t8 '
When the data transfer instructing signal φTDS falls to “L” at step, even if the DRAM array is in an active state, the SRAM array can be newly accessed after a predetermined time after shifting to the standby state at time ts2. It becomes possible. Therefore, after this time t8 ',
The SRAM can be accessed regardless of the state of the DRAM. For example, at time t8 ',
Data at the time of a cache miss can also be read from the SRAM array.

Before returning to the standby state of the DRAM, an external address can be newly set to access the SRAM. This is because SRAM is RA like DRAM.
This is because high speed access is possible after returning from the standby state without any need for the S precharge operation.

In FIG. 5, at time t9 ', DR
AM word line drive signal DWL falls to "L", and at time t10, equalize signal φEQ is activated, and D
The equalizing and precharging operation of the RAM bit line pair DBL starts. At this time, the equalizing operation of sense amplifier drive signal lines φSAN and / φSAP is similarly performed. In the DRAM, from time t9 ',
At time t11 after the elapse of n seconds, the circuit returns to the standby state including its peripheral circuits. The DRAM array can be accessed only after a predetermined time RAS precharge time has elapsed. However, in the SRAM array, at time ts2, the SRA
After setting the M word line SWL1 to the non-selected state, at time ts3 several n seconds later, another SRA
The M word line SWL2 is selected, and the selected SRAM
Access (reading or writing of data) to a memory cell connected to word line SWL2 can be performed.

From time ts2 when data transfer instructing signal φTDS falls to the inactive "L" level, the SRA
The time ts at which the M word line SWL2 is activated
3 is set to an appropriate value according to the external specification. As described above, before the DRAM returns from the standby state, the SRA
By enabling access to M, a semiconductor memory device that operates at a high speed, particularly a semiconductor memory device with a built-in cache can be obtained.

The selection period of word line SWL2 of this SRAM is very short because there is no need to perform the column selection operation after the sensing and latching operation of the sense amplifier in the DRAM. At time ts4, this SRAM is sufficient.
Access to is completed. From this time ts3 to time ts
The time of 4 is at most 10n in a normal SRAM.
Seconds, and the SRAM
Access to is completed. Such a configuration of accessing the SRAM before returning to the standby state of the DRAM array can be realized by the semiconductor memory device of the present invention in which the SRAM and the DRAM can be accessed by addressing them by different addresses. Become.

FIG. 6 is a signal waveform diagram showing an operation at the time of data transfer from the SRAM to the DRAM. Hereinafter, the data transfer operation from the SRAM to the DRAM will be described with reference to FIGS. The operation of the DRAM portion is performed from the DRAM shown in FIG.
This is exactly the same as that at the time of data transfer to the RAM. Also, in the operation of the SRAM portion, at time ts1, S
The rise of the potential of the RAM word line SWL to "H" is exactly the same as the waveform diagram shown in FIG.

After time ts1 and time t6, that is, DRAM bit line pair DBL is connected to global I / O line pair GI
O to the SRAM bit line pair SBL.
After the M cell (SMC) is connected, the data transfer instructing signal φTSD is activated for a certain period from time t7 to “H”.
Stand up. In response, the bidirectional transfer gate BTG is activated, and the signals on the SRAM bit line pair SBL are transmitted to the global I / O line pair GIO (GIOa, GIOb) and the local I / O line pair LIO (LIOa, LIOb). Through the DRAM bit line pair DBL via the DRAM. This allows
DR connected to selected DRAM bit line pair DBL
The data of the AM cell is rewritten. That is, S
The data of the RAM cell is transferred to the DRAM cell. During the data transfer cycle from the SRAM array to the DRAM array, data transfer instructing signal φTDS is maintained at inactive “L”.

In the configuration of the bidirectional data transfer circuit shown in FIG. 3, only one of drive circuits DR1 and DR2 is driven in accordance with transfer instruction signals φTDS and φTSD. In this case, DR from the SRAM array
Data transfer to AM array and SRA from DRAM array
Data transfer to the M array cannot be performed at the same time. Therefore, there is a case where it is impossible to cope with a case where it is necessary to transfer data between the SRAM array and the DRAM array at a high speed.

FIG. 7 is a diagram showing another configuration example of the bidirectional data transfer gate. 7, a bidirectional transfer gate circuit 80 corresponds to the transfer gate BTG included in the bidirectional transfer gate circuit 3 shown in FIG. The unit bidirectional data transfer circuit 80 amplifies and holds the data transmitted from the SRAM array via the gate 81 to the first latch 8
5 and the data transferred from the DRAM array to the gate 8
4 and an amplifier 86 for receiving and amplifying the received signal. This amplifier circuit 86 also has a data holding function. Gate 81 transmits data on SRAM bit line pair SBL, * SBL to latch 85 in response to transfer control signal DTL. Gate 82 responds to transfer control signal DTA to transfer the latch data of latch 85 to global I / O lines GIO, *.
Transmit to GIO. The gate 83 transmits the data amplified by the amplifier 86 to a transfer control signal DTS2 (control signal DTS).
To the SRAM bit line pair SBL, * SBL. Gate 84 responds to transfer control signal DTS1 (control signal DTS) to control global I / O lines GIO, * GI
The data on O is transmitted to the amplifier 86. Control signal WDE
Is a control signal generated at the time of an access request to the DRAM array, and includes an internal data bus (write data line pair) D
The data on BW, * DBW is transmitted to the input of gate 81. Transfer control signals DTL and DTA are sequentially generated when data of SRAM bit line pair SBL, * SBL is transmitted to global I / O line pair GIO, * GIO of the DRAM array. The control signals DTS1 and DTS2 are D
Occurs when transferring data from the RAM array to the SRAM array. The control signals DTS1 and DTS2 are substantially the same control signal and are generated at substantially the same timing. Control signals DTL, DTA, DTS1 and DTS2 are generated in the same manner as control signals φTDS and φTSD described above. These control signals are generated from a bidirectional data transfer control circuit, as will be described later. Here, the symbols SBL and GIO indicate one signal line when used in pairs with the symbols * SBL and * GIO.

FIG. 8 is a diagram showing an example of a specific configuration of the unit bidirectional transfer gate circuit 80 shown in FIG. 8, a gate 81 includes a gate circuit 81a coupled to the SRAM bit line SBL and a complementary SRAM bit line * SBL
, And a gate circuit 81b coupled thereto. Gate circuit 81
a includes an n-channel MOS transistor 811a having a gate connected to the SRAM bit line SBL, and an n-channel MOS transistor 812a having a gate supplied with a transfer control signal DTL. Gate circuit 81b includes an n-channel MOS transistor 811b having a gate coupled to SRAM bit line * SBL, and an n-channel MOS transistor 812b having a gate supplied with transfer control signal DTL. Transistors 811a and 81
1b is connected to ground potential Vss. Gate circuits 81a and 81b invert data of corresponding SRAM bit lines SBL and * SBL in response to control signal DTL and transmit the inverted data to latch circuit 85.

Latch circuit 85 includes an inverter latch for latching data of gate circuits 81a and 81b.
This inverter latch includes inverter circuits IVL1 and IVL2. This latch circuit 85 is an inverter circuit IVL3 for inverting and transmitting an inverter output.
And IVL4. Inverter circuit IVL3
Inverts the data from the gate circuit 81a. Inverter circuit IVL4 inverts the output of gate circuit 81b.
Gate 82 is turned on in response to transfer control signal DTA, and outputs the output of latch circuit 85 to global I / O line G.
IO, * GIO and n channel MOS transistors 82a and 82b transmitting to the input of gate 84.

Gate 84 is turned on in response to n-channel MOS transistor 841a receiving data on global I / O line GIO and the output of gate 82a at its gate, and data transfer control signal DTS1, and turns on the output of transistor 841a. N transmitted to the input of the amplifier 86
Channel MOS transistor 842 and transfer control signal D
The transistor 842 is turned on in response to TS1.
a and n channel M transmitting one output of amplifier 86
OS transistor 843a is included.

Gate circuit 84b is, like gate circuit 84a, an n-channel MOS receiving at its gate the data on global I / O line * GIO and the output of gate 82b.
It includes a transistor 841b and an n-channel MOS transistor 843b which is turned on in response to the transfer control signal DTS1 and transmits the output of the transistor 842b.

The amplifier 86 is connected to p
Channel MOS transistors TM1a, TM1b and p-channel MOS transistor T connected in parallel with each other.
M2a and TM2b. The transfer control signal DTS1 is applied to the gate of the transistor TM1a, and the gate of the transistor TM1b is connected to the transistors TM2a and TM2b.
Are connected. One conductive terminal of transistors TM1a and TM1b is connected to the gate of transistor TM2a. Transfer control signal DTS1 is applied to the gate of transistor TM2b. Transistor TM1
The other conduction terminals of a, TM1b and TM2a, TM2b are connected to the power supply potential (Vcc).

Gate 83 is turned on in response to transfer control signal DTS2, and includes an n-channel MOS transistor 83a transmitting data from transistor 843a to SRAM bit line * SBL and gate 87a.
This gate 83 is turned on in response to the transfer control signal DTS2, and outputs the output of the transistor 843b to the SR
It includes an AM bit line SBL and an n-channel MOS transistor 83b transmitting to gate circuit 87b.

The gate 87 is connected to the data line DBW and the SRAM
A gate circuit 87a connecting the bit line * SBL and a gate circuit 87b connecting the data line * DBW and the SRAM bit line SBL are included. The gate circuit 87a is a DRAM
A MOS transistor 871a which is turned on in response to an output CD of a column decoder (which may be shared with an output of an SRAM column decoder), and which is turned on in response to an access instruction signal WED to a DRAM array; Includes n-channel MOS transistor 872a connecting internal data line DBW to transistor 871a. Gate circuit 87b includes MOS transistor 871b which is turned on in response to SRAM column decoder output CD.
And an n-channel MOS transistor 87 connecting internal data line * DBW to transistor 871b in response to DRAM array access instruction signal WDE.
2b.

The control signal WDE will be described later.
This is a control signal generated at the time of accessing the DRAM array of the semiconductor memory device from the outside (particularly at the time of data writing). The instruction to access the DRAM array is generated in response to an external control signal (CI #, W #; described later). Internal data lines DBW and * DBW are data lines for transmitting write data, and are connected to an input circuit (described later) included in the input / output circuit. Next, the operation of the bidirectional data transfer gate circuit shown in FIGS. 7 and 8 will be described with reference to the operation waveform diagrams of FIGS.

First, the data transfer operation from the SRAM array to the DRAM array will be described with reference to FIG.

First, at time t1, a word line is selected in the SRAM array, and SRAM bit line pair S is selected.
The data on the BL is determined according to the data of the memory cell connected thereto.

Subsequently, in response to a data transfer instruction from the SRAM array to the DRAM array, first, at time t2, a data transfer instruction signal DTL is generated. In response, transistors 812a and 812b shown in FIG. 8 are turned on, and SRAM bit lines SBL and * SB
The data of L is inverted and transmitted to the latch 85. Latch 85 converts this data into inverter latches IVL1, IVL.
Latch at 2. The latched data is inverted by inverter circuits IVL3 and IVL4 to form a gate circuit 8
2a and 82b. Therefore, at time t2
When a data transfer instructing signal DTL is generated, the latch data of the latch 85 is changed to the corresponding SRAM bit line SBL.
* Value corresponding to the content of SBL.

When the latch data in latch 85 is determined, transfer control signal DTA is generated at time t3. In response, gate circuits 82a and 82a
b is turned on, and the latch data of latch 85 is transmitted to global I / O lines GIO and * GIO, respectively.

At this time, since data transfer from the DRAM array to the SRAM array is not performed, control signal DTS
(DTS1, DTS2) and the DRAM array access instruction signal WDE are in an inactive "L" state. Therefore, transistors 842a and 842b and gate circuits 83a and 83b are all off. The amplifier 86 is also in a non-operating state.

Next, the data transfer operation from the DRAM array to the SRAM array will be described with reference to FIG.

Before the time t1 shown in FIG.
A word line selecting operation in the M array is performed, and data of the selected memory cell is stored in global I / O line pair GIO.
It is transmitted upward and is fixed at time t1.

Subsequently, at time t2, control signals DTS (DTS1, DTS2) for instructing data transfer from the DRAM array to the SRAM array are generated. In response, transistors 842a, 842b, 83a, 83
b is turned on, and the gate 84 and the gate 83 are turned on. In the amplifier 86, the control signal DTS
When (DTS1) is "L", the transistors TM1a and TM2b are on,
The potential of one node of 2a and 842b is held at "H". When control signal DTS is generated at time t2, transistors TM1a and TM2b are turned off. The on / off state of the transistors TM1a and TM2b is set to D through transistors 842a and 842b.
It changes according to the data transmitted from the global I / O lines GIO and * GIO lines of the RAM array. Control signal DT
When S is not generated, the input / output node of amplifier 86 is charged to power supply potential Vcc. Global I / O line G
When the data to the IO is “H”, the transistor 841 a
Are on, and the transistor 841b is off.
In this state, when the transfer control signal DTS1 is generated, the transistors 842a and 842b are turned on,
The transistors TM1a and TM2b are turned off. Therefore, the potential of the input / output node of transistors TM1b and TM1a is discharged to ground potential Vss via transistors 842a and 841a. On the other hand, since the transistor 841b is off, the transistor TM2
a, TM2b is an input / output node of the transistor TM2a.
Is maintained at "H" by being turned on. As a result, the data on global I / O line GIO is inverted through transistors 843a and 83a and SRAM
Transmitted on bit line * SBL and global I / O
The data on line * GIO is the output of transistors 843b and 8
The signal is inverted and transmitted to the SRAM bit line SBL via 3b.

At this time, since data transfer from the SRAM array to the DRAM array is not performed, control signal DTA
And DTL are at "L". This transfer control signal DTS
Is the transfer control signal φ shown in FIGS. 3, 4, 5, and 6.
It becomes a signal equivalent to TDS.

According to the configuration shown in FIGS. 7 and 8,
The data on the SRAM bit lines SBL and * SBL is gate 8
1, global I through latch 85 and gate 82
/ O line GIO, * GIO. The data of global I / O lines GIO and * GIO are transferred to SRAM bit line SB via gate 84, amplifier 86 and gate 83.
L, * SBL. Therefore, according to this configuration, the data transfer paths are different from each other, and the latch 85
And the function of the amplifier 86, D
Data transfer to RAM array and SR from DRAM array
It is possible to execute the data overlapping with the data transfer to the AM array, so that the data transfer between the two arrays can be performed at a high speed.

In particular, according to this configuration, write data is transferred to gates 87a and 87b via data lines DBW and * DBW.
Through the gate 81, the latch 85, and the gate 82 to the global I / O lines GIO, * GIO. Therefore, the common write data line DB
W, * DBW can be used to selectively write to the DRAM array and the SRAM array. In this case, it is possible to write to both, or only to write to one. The instruction to write data to the DRAM array is given by a signal WD.
Performed by E.

Therefore, even if the configuration shown in FIGS. 7 and 8 is used to write data to the DRAM array via SRAM bit lines SBL and * SBL, the word line selection signal in the SRAM array can be used. On the other hand, it is not necessary to add a signal for instructing access to the DRAM array as a condition signal, and write data of a selected memory cell of the high-speed SRAM array to the write data bus DBW, DBW.
* It is not necessary to add a DRAM array access instruction signal as a condition signal to the signal connected to DBW, so that data can be written to the SRAM array at high speed and data can be written to the DRAM array at high speed. Becomes

FIG. 11 is a diagram showing another configuration example of the bidirectional transfer gate circuit. The unit bidirectional transfer gate circuit 90 shown in FIG. 11 has the structure shown in FIG. 7 and additionally transfers data on the internal write data buses DBW and * DBW to the transfer control signal WD.
Includes a gate 88 that communicates to latch 85 in response to E1. The control signals WDE0 and WDE1 correspond to the control signal WDE shown in FIG. 7, and the output of the DRAM column decoder is conditioned. That is, control signal WDE0 applied to gate 87 is not generated when data is written to the DRAM array, and gate 87 is turned off. At this time, only control signal WDE1 is generated, gate 88 is turned on, and data on write data transmission lines DBW, * DBW is transmitted to latch 85. As described above, data is written to both the SRAM array and the DRAM array,
By selectively generating the write control signals WDE0 and WDE1 in accordance with whether data is written only to the RAM array, data can be efficiently written to a large-capacity DRAM at high speed.

FIG. 12 is a diagram showing a configuration of still another bidirectional transfer gate circuit. In this configuration, the gate 8
8 is turned on in response to the gate GT1 which is turned on in response to the data write instruction signal WDE to the DRAM array and the output CD of the column decoder (this is an output for selecting a column of the DRAM array). Includes gate GT2.
In this configuration, the gate 88 connects the write data lines DBW and * DBW directly to the latch 85. The configuration of the other circuit blocks is the same as the configuration of the bidirectional transfer gate circuit shown in FIG. According to this configuration, the transfer control signals WDE0 and WDE1 (these control signals are substantially the same) are eventually conditioned (ANDed) by the column decoder output. The operation of the gate 88 is controlled.

Note that FIG. 7, FIG. 11, and FIG.
The bidirectional transfer gate circuit shown in FIG.
Data transfer between L, * SBL and global I / O lines GIO, * GIO is performed. However, the configuration of the bidirectional transfer gate circuit can be applied to a general semiconductor memory device as shown in FIG. That is, in FIG. 13, the semiconductor memory device 95 includes a large-capacity memory (generally, a DRAM array) 93 and a high-speed memory (generally, an SRAM array) 94. When data transfer such as "copy back" is performed between memory 93 and memory 94, FIG. 7, FIG. 11 and FIG.
With the configuration shown in FIG. 2, the first latch 91 and the second latch 92 can be provided and the respective data transfer paths can be set independently, and the large-capacity memory 93 composed of DRAM and the high-speed memory composed of SRAM can be used. The data transfer in the opposite direction can be performed while transferring the data to 94. In this case, the independent data transfer path means that data transfer from the large-capacity memory 93 to the latch 91 and data transfer from the high-speed memory 94 to the latch 92 can be performed independently. Data transfer to the high-speed memory 94 and the DRAM from the latch 92
This means that data transfer to the large-capacity memory 93 can be performed independently and in parallel. Therefore, no problem occurs even if the data transfer within the memories 93 and 94 is performed via the common bus. Thus, as shown in FIG.
The data transfer can be performed at a high speed by activating the latch 92 and the latch 92 at the same time or simultaneously activating them.

FIG. 14 is a diagram showing a layout of an array of a semiconductor memory device according to another embodiment of the present invention. FIG.
The CDRAM shown in FIG. 4 is a 4-Mbit DRAM array and 1
6K bit SRAM array. That is, FIG.
The four CDRAMs include the four CDRAMs shown in FIG. In FIG. 14, the CDRAM includes four memory mats MM1, MM2, MM3 and MM4 each having a capacity of 1 Mbit. DRAM memory mats MM1-MM
Each of 4 includes a memory cell arrangement of 1024 rows (word lines) and 512 columns (bit line pairs). Each of the DRAM memory mats MM1 to MM4 is divided into 32 memory blocks MB each having a configuration of 128 columns (bit line pairs) × 256 rows (word lines).

In one memory mat MM, the memory mat is divided into four memory blocks in the row direction and into eight blocks in the column direction. As shown in FIG. 14, unlike the arrangement of the DRAM shown in FIG. 1, the 1M-bit memory mat is divided into eight in the column direction and four in the row direction.
This is for storing in a rectangular package to be described later. DR is placed at the center of each memory block MB in the column direction.
An AM sense amplifier DSA and a column select gate CSG are arranged corresponding to each bit line pair DBL. The memory block MB is divided into an upper memory block UMB and a lower memory block LMB with the sense amplifier DSA and the column selection gate CSG at the center. In operation, one of the upper and lower memory blocks UMB and LMB is connected to sense amplifier DSA and column select gate CSG. This sense amplifier DSA and column select gate C
Which of the upper and lower memory blocks UMB and LMB is connected to the SG is determined by the address. Such a configuration in which one memory block MB is divided into upper and lower two memory blocks UMB and LMB and only one of them is connected to sense amplifier DSA and column select gate CSG is commonly used in a DRAM having a shared sense amplifier configuration of 4 Mbits or more, for example. Used.

One memory mat MM includes two activation sections AS. In this activation section AS, one word line is selected. That is, in the configuration shown in FIG. 14, unlike the configuration shown in FIG. 1, one word line is divided into two and divided into respective activation sections. Therefore, selecting one word line in one memory mat MM is equivalent to selecting one word line in each activation section AS.

This semiconductor device (CDRAM) further comprises four DRAM memory mats MM1 to MM4.
In order to select one word line, four DRAM row decoders DRD1, DRD2, DRD3 and DRD4 are provided. The DRAM row decoders DRD1 to DRD4
Selects one word line from each of the memory mats MM1 to MM4. Therefore, in the CDRAM shown in FIG. 14, four word lines are selected at a time. DRA
M row decoder DRD1 includes memory mats MM1 and M
One row is selected from the corresponding activation section AS of M2. DR
The AM row decoder DRD2 selects one row from the lower activation section AS of the memory mats MM1 and MM2. DRAM row decoders DRD3 and DRD4 have D
One row is selected from each of the upper activation section AS and the lower activation section AS of the RAM memory mats MM3 and MM4.

The CDRAM further includes a DRAM column decoder DCD for selecting two columns (bit line pairs) from each column block of the memory mats MM1 to MM4 of the DRAM. The column select signal from DRAM column decoder DCD is transmitted to column select line CSL shown in FIG. The column selection line CSL extends so as to be shared by the upper activation section AS and the lower activation section AS. Therefore, in the configuration shown in FIG. 14, four columns from one column block (in FIG. 14, a block composed of eight memory blocks MB divided in the column direction) are supplied by a column selection signal from DRAM column decoder DCD. Select

The columns selected by column decoder DCD are connected to corresponding global I / O line pairs GIO. The global I / O line pairs GIO extend in the column direction by two pairs for each column block in one activation section AS. The connection configuration between the global I / O line pair GIO and the local I / O line pair LIO in each column block will be described later in detail.

The CDRAM shown in FIG.
SRAM comprising SRAM cells having K-bit capacity
Array blocks SMA1 to SMA4 are included. Two SRs
Row decoders SRD1 and SRD2 for SRAM are provided at the center of both so as to be shared by the AM array blocks. SRAM row decoder SRD1 is shared by SRAM array blocks SMA1 and SMA3. SRAM row decoder SRD2 is shared by SRAM array blocks SM2 and SMA4. Details of the configuration of the SRAM array block SMA will be described later in detail.

This CDRAM has four input / output buffer circuits I / O for inputting / outputting data in 4-bit units.
Includes OB1, IOB2, IOB3 and IOB4. The input / output buffer circuits IOB1 to IOB4 are respectively connected to a block SC of a sense amplifier and a column decoder for an SRAM via a common data bus (internal data bus).
Connected to DA. In the configuration shown in FIG.
Although data input / output is shown to be performed via a sense amplifier for SRAM and a column decoder block SCDA, it is configured so that data input / output is performed from a portion of bidirectional transfer gate BTG. Is also good.

In operation, one word line is selected in each activation section AS. Only the row block including the selected word line is activated. The remaining row blocks maintain the precharge state. In the selected row block, only small block UMB (or LMB) including the selected word line is connected to DRAM sense amplifier DSA and column select gate CSG, and the other small memory block LMB (or UMB) is connected to DRAM. Of the sense amplifier DSA and the column select gate CSG. Therefore, activation (charge / discharge) of 1/8 bit lines is performed as a whole. By performing the division operation in this manner, power consumption due to charging and discharging of the bit line can be reduced. One memory block MB is divided into an upper memory block UMB and a lower memory block LM.
B, and by arranging the sense amplifier DSA in the central portion, the length of the bit line is shortened, and the ratio of the bit line capacitance Cb to the memory capacitor capacitance Cs, Cb / C
s can be reduced, and a sufficient read voltage can be obtained at high speed.

In each activation section AS, a sensing operation is performed on four small blocks UMB (or LMB) in the row direction. In each activation section AS, two pairs of bit lines are selected in one column block by a column selection signal from DRAM column decoder DCD. The global I / O line pair GIO extends in the column direction so as to be shared by the column blocks of each activation section AS. In each activation section AS, two pairs of bit lines are selected from each column block and connected to corresponding two pairs of global I / O lines GIO. 4 pairs of global I to bidirectional transfer gate BTG
/ O line pair GIO is connected. One memory mat MM
, Four bidirectional transfer gates BTG are provided.
Therefore, from one memory mat MM, 16 pairs of global I / O lines GIO are connected to the SR of the corresponding SRAM array.
It can be connected to the AM bit line pair SBL. Next, the layout of this global I / O line will be described.

FIG. 15 shows an arrangement of global I / O lines for one memory mat. In FIG. 15, global I / O line pair GIO is provided for upper activation section UAS, and upper global I / O line pair UGIO is provided.
And lower global I / O line pair LGIO provided for lower activation section LAS. The upper global I / O line pair UGIO and the lower global I / O line pair LGI
O are arranged in parallel. Lower global I / O line pair LG
IO passes through the upper activation section UAS, but is not connected to the local I / O line pair LIO in the upper activation section UAS. The global I / O line pair GIO and the local I / O line pair LIO are IOs which are block selection switches.
Connected via gate IOG. This IO gate IO
Only the G provided in the row block including the selected word line is turned on by the block selection signal φBA, and connects the corresponding local I / O line pair LIO to the corresponding global I / O line pair GIO. I do.

Since local I / line pair LIO has DRAM sense amplifier DSA and column select gate CSG arranged at the center of memory block MB in the column direction, it has a row direction at the center of memory block MB in the column direction. It is arranged along.

A word line shunt region WSR is provided between adjacent column blocks in the column direction. The word line shunt region WSR is a region for making contact between a word line formed of relatively high-resistance polysilicon and a low-resistance aluminum interconnection. The word line shunt region will be briefly described below.

FIG. 16 is a diagram schematically showing a sectional structure of a select transistor Q0 (see FIG. 2) included in a DRAM cell. In FIG. 16, the selection transistor Q0
Are the impurity regions I formed on the surface of the semiconductor substrate SUB.
PR, a bit line BL connected to one impurity region IPR, and a polysilicon layer PL formed on the surface of the semiconductor substrate between the two impurity regions IPR. A word line drive signal DWL (indicated by the same reference numeral as a signal line and a signal transmitted thereon) is applied to the polysilicon layer PL.
Is transmitted, a channel is formed on the surface of the semiconductor substrate between impurity regions IPR, and select transistor Q0 is turned on. Polysilicon has a relatively high resistance. If the resistance of the word line DWL increases, a signal delay occurs due to the resistance of the polysilicon. Word line DWL
, A low-resistance aluminum interconnection AL is provided in parallel with the polysilicon layer PL. By periodically connecting aluminum interconnection AL and polysilicon layer PL, the resistance of word line DWL is reduced. Aluminum interconnection AL is formed above bit line BL. Therefore, polysilicon layer PL and aluminum interconnection AL
The region for making contact with the bit line BL
It is necessary to set an area where (/ BL) does not exist, that is, an area where no memory cell is arranged. For this reason,
A word line shunt region is provided between column blocks. This connection mode is shown in FIG.

In FIG. 17, a low-resistance aluminum interconnection AL is arranged in parallel with a relatively high-resistance polysilicon layer PL serving as a word line. Word line drive signal DWL is transmitted to aluminum interconnection AL. Aluminum interconnection AL and polysilicon layer PL are connected to word line shunt region W.
In SR, they are periodically connected by a contact layer CNT. By periodically forming a contact through aluminum interconnection AL, polysilicon layer PL and contact region CNT, the resistance of polysilicon layer PL can be effectively reduced. Thus, even if the length of one word line is increased, the word line drive signal WL can be transmitted to the word line end at high speed.

FIG. 18 schematically shows a layout of global I / O lines and column select lines CSL. FIG. 18 shows only these layouts for two memory blocks MB. In FIG. 18, the global I /
O line pair GIO is arranged in word line shunt region WSR. DRAM word line DWL is arranged in a direction orthogonal to global I / O line pair GIO. In FIG. 18, aluminum interconnection AL and polysilicon layer PL are arranged in parallel with each other, and are shown as the same word line DWL in this plan view because they overlap. Also,
Column select line CSL for transmitting a column select signal from a DRAM column decoder is arranged in a direction orthogonal to DRAM word line DWL.

In this layout, the bit line pair DBL of the DRAM is not shown, but this column selection line CBL is not shown.
It is arranged in parallel with SL. Aluminum wiring AL (see FIG. 17) for DRAM word line DWL is formed of a first layer aluminum wiring. Column select line CSL is formed of a second layer aluminum interconnection. Global I / O lines are formed of aluminum wiring in the same layer as column select line CSL. This word line shunt region WS
By arranging the global I / O line pair GIO in R, the I / O line for connecting the DRAM array and the bidirectional transfer gate can be formed as a local I / O line, a global I / O line, and a hierarchical structure. No increase in chip area occurs.

FIG. 19 schematically shows a structure of SRAM array block SMA shown in FIG. In FIG. 19, an SRAM array block SMA includes 16 pairs of bit lines SBL and 256 SRAM word lines SWL. SRAM bit line pair SBL and SRAM word line S
An SRAM cell SMC is arranged at the intersection with WL. FIG.
As shown in FIG. 4, this SRAM array block SMA
In order to correspond to the rectangular chip layout
AM bit line pair SBL is arranged in the row direction of the DRAM array, and SRAM word line SWL is arranged in the column direction of the DRAM array. This SRAM word line SWL is S
Connected to RAM row decoder SRD.

The SRAM bit line pair SBL needs to be connected to the global I / O line pair GIO via the bidirectional transfer gate BTG. Therefore, SRAM bit line pair SB
L must be connected to a bidirectional transfer gate BTG provided in the downward direction of FIG. 19 (or the upward direction of FIG. 19: this is determined by the arrangement of the memory array). For this reason, in the configuration shown in FIG.
An SRAM bit line lead-out line SBLT is arranged in parallel with WL. SRAM bit line extraction wiring SBLT is SR
The same number of bit line pairs SBL of the AM array block SMA are provided, and each is connected to the corresponding SRAM bit line pair SBL. This SRAM bit line extraction wiring SBLT
If the SRAM bit line SWL is formed of the same wiring layer as the SRAM word line SWL, there is no need to provide an additional wiring layer newly formed in another manufacturing process, and the SRAM bit line extraction wiring SBLT can be easily realized. it can.

The SRAM row decoder SRD decodes an external SRAM row address and selects one of the 256 SRAM word lines SWL. The 16-bit SRAM cell SMC connected to the selected SRAM word line SWL includes a corresponding SRAM bit line pair SBL and SRAM bit line extraction wiring SB.
Connected to LT. At the time of data transfer, this bit line extraction wiring SBLT is connected to global I / O line pair GIO via bidirectional transfer gate BTG.

By using the layouts shown in FIGS. 15 and 19, the DRA as shown in FIG.
The M array is divided and arranged at the top and bottom of the figure,
An SRAM array is intensively arranged between M array blocks, and an input / output buffer circuit IOB is provided near an SRAM array provided in the center of the semiconductor memory device (chip).
1 to 4 can be realized. Such a structure in which the SRAM array is intensively arranged in the central portion of the chip and data is input / output from the vicinity of the central portion of the chip provides an advantage very suitable for a CDRAM as described below.

The first requirement in the CDRAM is a high-speed access to the cache register. By disposing an SRAM array functioning as a cache register close to an input / output buffer for inputting / outputting data to / from the outside of the device, the length of signal wiring therebetween can be reduced, and data input / output can be performed at high speed. It is suitable for meeting the demand for high-speed access.

By arranging the SRAM array intensively at the center, the address line for selecting the SRAM cell can be shortened. If the address line is shortened, the wiring resistance and the parasitic capacitance associated with the address line can be reduced, and the SRAM cell can be selected at high speed, which is suitable for realizing high-speed access to the cache register.

In the case of the architecture shown in FIG.
The wiring for connecting the AM array and the SRAM array may become longer, and there may be a concern that the data transfer speed between the DRAM array and the SRAM array is reduced.
However, data is transferred between the DRAM array and the SRAM array when a cache miss (miss hit) occurs. In this case, the access speed of the standard DRAM is sufficient, and the Since no speed increase is required, there is no practical problem.

FIG. 20 is a diagram showing an example of the pin arrangement of a package accommodating a CDRAM according to the present invention. In FIG. 20, 4M bit DR as shown in FIG.
The pin layout for a CDRAM in which an AM and a 16K bit SRAM are integrated on the same chip is shown. This CDR
AM has a lead pitch of 0.8 mm and a chip length of 18.4 m
m, 44 pins 300 mil. It is stored in TSOP (Thin Small Outline Package) Type II. This CDRAM is used as a data input / output method.
Includes two types: D / Q separation and masked light. D /
The Q separation is a method in which write data D and output data Q are input / output via separate pins. Masked light is
This is an operation mode in which the write data D and the output read data Q are output via the same pin terminal, and the writing of data from the outside can be masked.

In order to efficiently supply the power supply potential to the CDRAM and to facilitate the layout of the power supply wiring, three pins are provided for each of the power supply potentials Vcc and Gnd. That is, the power supply potential Vcc from the outside is supplied to the pins having the pin numbers 1, 11, and 33. Power supply potential Vcc applied to pins 1, 11 and 33 may have the same voltage value as operating power supply potential Vcc shown in FIG. 2, or applied to pins 1, 11 and 33. The configuration may be such that the external power supply potential Vcc is internally stepped down to supply the operation power supply potential.
The ground potential Gnd is applied to pins of pin numbers 12, 22, and 34.

Pin numbers 6 to 8, 15 to 17, 2
Addresses Ac0 to Ac11 for the SRAM are provided to pins 8 to 30 and 37 to 39. DRA
Addresses Aa0 to Aa9 for M are assigned to pin numbers 2, 3, 1
9 to 21, 24 to 26 and 42, 43. Command addresses Ar0 and Ar1 for designating a special mode, which will be described later, are also applied to the pins of pin numbers 2 and 3. A cache inhibition signal CI # indicating cache access inhibition is applied to the pin terminal of pin number 4. When the cache inhibit signal CI # is set to "L", access to the SRAM array is inhibited, and direct access (array access) to the DRAM array becomes possible. A write enable signal W # indicating a data write mode is applied to the pin No. 5. A chip select signal E # indicating that this chip has been selected is supplied to the pin No. 18.

A command register designating signal CR # for designating a special mode is applied to the pin 23. When the command register designating signal CR # is "L", the command addresses Ar0 and Ar1 given to the pins of the pin numbers 2 and 3 become valid, and the special mode is set.

A cache hit signal CH # indicating a cache hit is applied to the pin of pin number 27. If the cache hit signal CH # is at "L", the cache (SRAM) can be accessed. An output enable signal G # indicating the output mode is applied to the pin 40. The clock signal K is supplied to the pin having the pin number 41. A refresh instruction signal R designating the refresh of the DRAM array is supplied to the pin 44.
EF # is provided. This refresh instruction signal REF
# Becomes "L", DRA is internally performed in that cycle.
Auto-refresh of the M array is performed.

Pin Nos. 9, 10, 13, 14, 31, 3
2, 35 and 36 are provided with different data according to two types of operation modes of D / Q separation and masked write. The operation mode of the D / Q separation and mask write is set by a command register (described later).

In the masked write mode, pins with pin numbers 10, 13, 32, and 35 are used as common data input / output terminals for commonly performing data input / output. To the pins of pin numbers 9, 14, 31, 35 and 36, masked write instruction data M0, M1, M2 and M3 indicating which input / output pin is to be masked are applied, respectively.

In the D / Q separation mode, the pins of pin numbers 9, 14, 31, and 36 are connected to the write data D0,
Used as pins for inputting D1, D2 and D3. Pins with pin numbers 10, 13, 32 and 35 are used as data output pins for outputting read data Q0, Q1, Q2 and Q3.

As for the SRAM addresses Ac0 to Ac11, row and column addresses are given simultaneously in a non-multiplexed manner. DRAM addresses (array addresses) Aa0 to Aa
9 is given by multiplexing a row address and a column address. In the pin arrangement shown in FIG.
The row address strobe signal / RAS and column address strobe signal / CAS which are usually used in the RAM are not used. CDRAM according to the present invention
, Control signals and data are input in response to the rising edge of clock K from the outside.

FIG. 21 is a block diagram showing a configuration inside a CDRAM chip housed in the package shown in FIG. It should be noted that the block arrangement shown in FIG. 21 is only for functionally showing the internal configuration of the CDRAM, and does not match the actual layout.

In FIG. 21, the CDRAM is a DRAM.
100 and an SRAM 200. DRAM 100
Decodes a 4-Mbit DRAM array 101 and a given DRAM internal row address, and
A DRAM row decoder block 102 for selecting four rows from the array 101 and a DRAM for decoding a given internal column address for DRAM and selecting one column each from the selected four rows in a normal operation mode (array access). A column decoder block 103, a DRAM sense amplifier DSA for detecting and amplifying data of a memory cell connected to a selected row, and a DRAM array 101 in a data transfer mode in response to a column selection signal from block 103. A block 104 including a selection gate SG for selecting 16 bits and selecting a 4-bit memory cell in the array access mode is included.

The SRAM 200 has an SRAM array 201 having a capacity of 16K bits, an SRAM row decoder block 202 for decoding an SRAM internal row address and selecting four rows from the SRAM array 201,
The internal column address for the RAM is decoded, and one bit is selected from each of the selected four rows to form an internal data bus 250.
And a column decoder / sense amplifier block 203 comprising an SRAM column decoder and an SRAM sense amplifier for detecting and amplifying information of the selected SRAM cell at the time of data reading. DRAM
A bidirectional transfer gate circuit 210 is provided between 100 and SRAM 200. In FIG. 21, column decoder / sense amplifier block 20 is arranged as shown in FIG.
The gate circuit 210 may be connected to the output (input) of the third circuit. However, in FIG. 21, in the array access mode, input / output of data to / from DRAM 100 is performed via common data bus 251, so that common data bus 251 is coupled to bidirectional transfer gate circuit 210. Is shown. The common data bus 251 includes the write data bus lines DBW and * DBW shown in FIGS.

The CDRAM according to the present invention further includes control signals G #, W #, E #, CH #, C
A control clock buffer 250 that receives I #, REF #, and CR # and generates internal control signals G, W, E, CH, CI, REF, and CR; an internal address int-Aa for DRAM and an internal for SRAM Address in
An address buffer 252 for generating t-Ac and a clock buffer 254 for buffering an externally applied clock signal K are included. Control clock buffer 250
Receives a given control signal and generates an internal control signal in response to the rise of an internal clock from clock buffer 254. The output of clock buffer 254 is also provided to address buffer 252. Address buffer 252 takes in external addresses Aa and Ac applied when internal chip enable signal E is active at the rising edge of clock K from clock buffer 254, and takes in internal addresses int-Aa and in.
Generates t-Ac.

The CDRAM according to the present invention is further activated in response to internal refresh designating signal REF, and
The refresh address from the counter circuit 256 and the switching signal MUX from the refresh control circuit 292 driven in response to the internal refresh instruction signal REF and the address from the address buffer 252 are generated by the counter circuit 293 that generates the refresh address of the AM array. Address multiplexing circuit 258 for providing one of internal row addresses to DRAM row decoder block 102
including. The refresh control circuit 292 is driven by a refresh request from the auto refresh mode detection circuit 291. This refresh operation will be described later.

The CDRAM further includes internal control signals E,
DRAM array drive circuit 260 for generating various control signals for driving DRAM 100 in response to CH, CI and REF, and transfer operation of bidirectional transfer gate control circuit 210 in response to internal control signals E, CH and CI , And an SRAM array drive circuit 264 that generates various control signals for driving the SRAM 200 in response to the internal chip select signal E.

The CDRAM according to the present invention is further activated in response to internal control signal CR and designates an operation mode of the CDRAM in response to an external write enable signal W # and command addresses Ar (Ar0 and Ar1). A command register 270 for generating a command CM for performing the internal control signals G, E, CH, CI and W
And a data input / output control circuit 272 for controlling data input / output in accordance with the special mode command CM. Data input / output between the common data bus 251 and the outside of the device is controlled by the data input / output control circuit 272. And an input / output circuit 274 including an input / output buffer and an output register. The reason why the input / output circuit 274 is provided with an output register is to realize a latch output mode and a register output mode which are special modes of the CDRAM. The data input / output control circuit 272 sets not only the data input / output timing but also the data input / output mode according to the mode specified by the special mode command CM.
FIG. 21 shows an example of the mode of the data input / output pins in the masked write mode.

FIG. 22 is a diagram showing another layout of the semiconductor memory device shown in FIG. In the configuration shown in FIG. 22, internal data transmission line 251 is connected to SRAM bit line pair SBL by SRAM column decoder 22. Further, to the internal data transmission line 251, the data of the selected column of the DRAM array 1 transmitted through the bidirectional transfer gate circuit 3 by the column selection signal from the DRAM column decoder 15 is further selected and connected. In this configuration,
SRAM row decoder 21 and column decoder 22
The internal address int-Ac applied to the DRAM and the internal address int-Aa applied to the row decoder 14 and the column decoder 15 of the DRAM are applied via independent paths. Therefore, with this configuration, SR
The memory cells of the AM array 2 and the DRAM array 1 can be independently addressed.

In the structure shown in FIG. 21, an SRAM column decoder 22 is provided between the bidirectional transfer gate circuit 3 and the SRAM array 2, and the SRAM column decoder 22 includes the bidirectional transfer gate circuit 3 and the DRAM array 1 And a configuration provided between the two. Also, DR
From the I / O line pair 16a, 16b of the AM array 1 to the DRAM
Selected by the output of column decoder 15 and connected to internal common data bus 251, and SRAM column decoder 22 connects SRAM bit line pair SBL to internal data transmission line 25.
1 may be connected.

FIG. 23 is a diagram showing an example of a connection mode between the bidirectional transfer gate circuit 210 and the internal common data line 251 shown in FIG. In FIG. 23, an SRAM input / output gate 301 includes an SRAM sense amplifier SSA and an SRA
M is activated when data is written to the M array, and the data on the internal data line 251a is transferred to the corresponding SRAM bit line pair SB.
L includes a write circuit WRI for transmission on L. SRA
M bit line pair SBL is connected to internal data line 251a via SRAM column select gate 302 via SRAM sense amplifier SSA. The SRAM column selection signal SYL from the SRAM column decoder block 203 is applied to the SRAM selection gates 302, respectively. Thereby,
Only one pair of SRAM column bit lines SBL is connected to internal data line 251a. Here, the internal data line 251 shown in FIG. 21 transfers 4-bit data, and only the internal data line corresponding to one bit is shown in FIG.

Referring to FIG. 23, this CDRAM responds to a logical product signal of cache inhibit signal CI and DRAM column select signal DY to connect global I / O line pair GIO to internal data line in order to further enable array access. 251
a access switching circuit 310 connected to a. The access switching circuit 310 and the bidirectional transfer gate BTG are included in the transfer gate circuit block 305.

Column select signal DYi of the DRAM is generated, for example, by decoding the lower 4 bits of a column address. That is, the global I / O line pair GIO is one D
Sixteen pairs are provided for the RAM memory mat (capacity: 1 Mbit). In the case of array access, only one pair must be selected. Therefore, a column address for the DRAM of the lower 4 bits is decoded to generate a column selection signal DYi. This access switching circuit 310 simply connects global I / O line pair GIO to internal data line 251.
a, and is connected to the corresponding signal line in the bidirectional transfer gate BTG. When array access is realized, the global I / O line pair GIO may be connected to the internal data line 251a via the SRAM sense amplifier SSA without providing such an access switching circuit 310.
At this time, a column selection signal applied to SRAM selection gate 302 is a selection signal based on a column address applied to DRAM. This can be realized by a circuit that multiplexes the column selection signal with the signal CI. This multiplex circuit supplies a column selection signal for DRAM to the SRAM selection gate when signal CI is active.

In the SRAM, an SRAM sense amplifier S is provided for each SRAM bit line pair SBL.
An SA is provided, which is a single SRAM for one block of SRAM bit line pairs like a normal SRAM.
A configuration in which only the RAM sense amplifier is provided may be employed.
However, if an SRAM sense amplifier is provided for each of the SRAM bit line pairs SBL, data can be output more reliably and at high speed. Also, SRA
If the M sense amplifier SSA has the same configuration as the DRAM sense amplifier, there is no need to provide the write circuit WRI.

The transfer gate circuit block 305 may use the transfer gate circuit shown in FIGS. 7, 8, 11 and 12.

FIG. 24 shows D / Q in input / output circuit 274.
FIG. 3 is a diagram illustrating a configuration for realizing separation. In FIG. 24, input / output circuit 274 is activated in response to internal output enable signal G to generate internal data line 251a.
Output buffer 3 for generating output data Q from the above data
20 and is activated in response to the internal write instruction signal W,
An input buffer 322 for generating internal write data from external write data D and transmitting it to internal data line 251a
And D / from the command register 270 (see FIG. 21).
Output buffer 320 in response to Q separation instruction bit CMa
And a switch circuit 324 for short-circuiting the output of the input buffer 322 and the input of the input buffer 322. This D / Q separation instruction bit CMa
Is included in the special mode designation command CM generated from the command register 270. When switch circuit 324 is rendered conductive, data input / output is performed via the same pin. When switch circuit 324 is turned off, data input / output is performed via separate pins. In addition,
FIG. 24 also representatively shows only a configuration related to input / output of 1-bit data.

FIG. 25 is a diagram showing a data input / output circuit and another connection configuration. In FIG. 25, output buffer circuit 3
Numeral 20 receives selected memory cell data of an SRAM sense amplifier or a DRAM array and transmits it to an external output pin Q. The first input buffer circuit 322a is connected to an external pin terminal Q, and the second input buffer circuit 322b is connected to an external data input pin terminal D. Outputs of the first and second input buffer circuits 322a and 322b are connected to an internal data bus DBW, via an OR circuit 322c.
* Transmitted to DBW (251a). The enable and disable of the first and second input buffer circuits 322a and 322b are performed in response to an instruction bit CM from a command register (see FIG. 21). When the command register indicates the D / Q separation mode, the first input buffer circuit 322a is disabled and the input buffer circuit 322b is enabled. If the instruction bit CM indicates a masked write mode common to D / Q, the first input buffer circuit 32
2a is enabled and the second input buffer circuit 3
22b is disabled.

In the structure shown in FIG. 25, data from the SRAM sense amplifier is transmitted to output buffer circuit 320. This is because data of a selected memory cell of the DRAM array is connected to a column line of the SRAM array. This is because the signal is transmitted to the internal data bus via the sense amplifier of the SRAM. That is, the case where column select signals SYLi and SYLj applied to gate 302 are shared with DRAM column decoder outputs DYi and DYj in the configuration in which gate 310 is not provided in the configuration of FIG. 23 is shown as an example. This configuration will be described later.

FIG. 26 is a diagram showing still another configuration of the input / output circuit. 26, an output buffer circuit 320
Between the input buffer circuit 322 and the
324a, which is turned on in response to the input buffer circuit 322 and the data input pin terminal D
And a transistor gate 324b which is turned on in response to the complementary instruction bit / CMa is provided. In the case of this configuration, when the instruction bit CMa indicates the D / Q separation mode, the transistor gate 324a is turned off and the transistor gate 324b is turned on. Conversely, when the D / Q shared masked write mode is indicated, the transistor gate 324a is turned on and the transistor gate 324b is turned off.

With this configuration, input buffer circuit 322
Can be selectively connected to the data output pin terminal Q or the data input pin terminal D, and the D / Q separation mode and the D / Q sharing mode can be set.

FIG. 27 is a diagram showing an example of a mode of connecting addresses to the DRAM and the SRAM. In the structure shown in FIG. 27, access to the DRAM
This is performed via a bit line pair SBL to the AM array or a bidirectional transfer gate circuit. In the case of this configuration, the SRAM
The column selection signal CD from the column decoder 22 is
The configuration is shared by the column selection signal of the array and the column selection signal of the SRAM array. In FIG. 27, DRAM address buffer 252a receives external DRAM addresses Aa0-Aa9 and receives internal address int. Aa is generated. DRAM row decoder 14 receives the internal address int. Decode the internal row address of Aa,
A word line drive signal DWL for selecting a word line from the DRAM array is generated. The DRAM column decoder 15
Receiving part of the internal column address from DRAM address buffer 252a, it generates signal CSL for selecting a column selection line from the DRAM array. The remaining part of the internal column address from DRAM address buffer 252a is applied to buffer 29. Buffer 29 receives the internal column address from SRAM buffer 252b and transmits it to SRAM column decoder 22. As will be described in detail later, D
When accessing the RAM array, no internal column address is generated from SRAM buffer 252b. In this case, the buffer 29 is the DRAM address buffer 25
Receiving the internal column address from 2a and transmitting it to SRAM column decoder 22.

SRAM row decoder 21 receives the internal row address from SRAM buffer 252b,
SRAM word line drive signal S for selecting one row from the array
Generate WL. According to the configuration shown in FIG. 27, the column decoder output CD previously applied to the bidirectional transfer gate circuits shown in FIGS. 7 and 8 becomes an SRAM decoder output. According to the configuration shown in FIG. 27, in the configuration of data input / output shown in FIG.
i, DYj and the SRAM column selection signals SYLi, SYLj are equivalent.

FIG. 28 is a diagram showing another example of the configuration of the address input / output unit. In the configuration shown in FIG.
In response to a cache hit instruction signal CH and a DRAM array access instruction signal CI, one of the internal column address from the DRAM address buffer 252a and the internal column address from the SRAM address buffer 252b. A multiplexer 30 for passing is provided. Cache signals CH and DRA
The M array access instructing signal CI will be described later in detail, but when the cache hit instructing signal CH is generated,
Access to the SRAM array is permitted, and writing / reading of data by accessing the DRAM is prohibited.
When DRAM array access instruction signal CI is generated, writing / reading of data by accessing a memory cell of the DRAM array is permitted. Therefore, when signal CH is generated, multiplexer 30
The internal column address from address buffer 252b is selected and transmitted to SRAM column decoder 22. Multiplexer 30 also provides DRAM array access instruction signal C
I occurs, the DRAM address buffer 252
The internal column address from a is selected and transmitted to the SRAM column decoder 22. Also in the configuration shown in FIG. 28, SRAM column decoder 22 is configured to be used for both column selection of the DRAM array and column selection of the SRAM array.

The configuration of address distribution shown in FIGS. 27 and 28 is merely an example, and DR allocation is independent of each other.
Decoding of internal column address of AM array and SRAM
A configuration in which decoding of an internal column address of the array may be performed.

FIG. 29 shows an internal data transmission line pair and an SRAM.
FIG. 9 is a diagram illustrating another configuration example of a connection mode with an array. FIG.
In the configuration shown in FIG. 3, the SRAM sense amplifier SSA
Are provided for each SRAM bit line pair SBL. In the configuration shown in FIG. 29, SRAM sense amplifier SSA includes a plurality of SRAM bit line pairs SBL, * SB
One is provided for L. Each SRAM bit line pair SB
A selection gate circuit 302 is provided for L and * SBL. Column select signal CD is applied to select gate circuit 302. As column selection signal CD, a column selection signal from the SRAM column decoder shown in FIGS. 27 and 28 is applied. The internal data line pair includes an internal write data line 251a 'for transmitting write data and a read data transmission line 251b' for transmitting read data to an output buffer circuit. This internal write data transmission line 251
a 'includes complementary data line pairs DBW and * DBW. Complementary data from the input buffer circuit is transmitted to internal data lines DBW and * DBW. This internal write data line 251a 'is connected to write circuit 303. Write circuit 303 includes cross-connected n-channel MOS transistors T301, T302, T303, and T304. Gates of transistors T302 and T303 are connected to internal data line DBW. Transistor T301
And the gate of T304 is connected to internal data line * DBW. Complementary write data from write circuit 303 is supplied to each select gate circuit 3 via data lines DBWa and * DBW.
02. Transistors T301 and T30
2 transmits the power supply potential Vcc when in the ON state. Transistors T303 and T304 transmit ground potential Vss when turned on. For example, consider a case where data of "H" is transmitted to internal data line DBW. At this time, "L" data is transmitted to internal data line * DBW.
At this time, the transistors T302 and T303 are turned on. Therefore, "H" data is transmitted from write circuit 303 to internal data line DBWa via transistor T302, and "L" data is transmitted to other internal data line * DBWa via transistor T303.

At the time of data reading, data of "L" is transmitted from input buffer circuit to both internal write data lines DBW and * DBW, whereby the output of write circuit 303 enters a high impedance state. At this time, the sense amplifier SSA is activated, and the internal data lines DBWa, *
After the data transmitted to DBWa is amplified by sense amplifier SSA, it is transmitted to the output buffer circuit via internal read data transmission line 251b '.

As shown in FIG. 29, internal data line 2
By separately providing the write data transmission line 251a 'and the read data transmission line 251b' as 51, the layout design of the input / output circuit can be simplified as compared with the configuration in which data writing / reading is performed via a common internal data bus. It will be easier.

A DRAM array has dynamic memory cells as constituent elements, and its stored data needs to be refreshed periodically or within a predetermined period. Next, the refresh operation of the semiconductor memory device with a built-in cache will be described.

Referring to FIG. 21, a refresh instruction signal REF # is externally applied. This semiconductor memory device automatically refreshes internally when an external refresh instructing signal REF # is set to an active state of "L" at the rising of internal clock K.

Referring to FIG. 21, a circuit configuration for performing refresh includes an auto refresh mode detecting circuit 291 for detecting that auto refresh has been designated in response to an internal refresh instruction signal REF from control clock buffer 250. A refresh control circuit 292 which generates various control signals in response to a refresh request from the auto refresh mode detection circuit 291 and supplies the control signals to the counter 293 and the multiplexer circuit 258.
including. In response to the refresh instruction signal from refresh control circuit 292, counter circuit 293 supplies the count value stored therein to multiplexer circuit 258 as a refresh row address indicating the row to be refreshed. The multiplexer circuit 258 selects a refresh row address from the counter circuit 293 in response to the switching control signal MUX from the refresh control circuit 292, and supplies the refresh row address to the DRAM row decoder 102. This internal refresh instruction signal REF is also applied to DRAM array drive circuit 260. DRAM array drive circuit 250 is activated when internal refresh instruction signal REF is applied, and performs an operation related to row selection in DRAM array 101.

Refresh control circuit 292 increments the count value of counter circuit 293 by one at the completion of refresh every time refresh instruction signal REF is applied. Refresh control circuit 292 renders switching control signal MUX inactive at the completion of refreshing, and multiplexer circuit 258 causes internal buffer int for internal DRAM from address buffer circuit 252 to output.
-Aa is selected and transmitted to the DRAM row decoder 102.

FIG. 30 is a diagram functionally showing the transfer gate control circuit 262. Transfer gate control circuit 262 generates signals φTDS and φTSD for controlling the transfer operation of bidirectional transfer gate circuit 210 (3, BTG) in response to internal control signals E, CI, W and CH. Transfer cache control circuit 262 does not generate transfer control signals φTDS and φTSD when cache hit signal CH is active. However, when array access instruction (cache inhibit) signal CI is active, write enable signal at that time is activated. Control signals φTDS and φTSD are sequentially generated according to the state of W. At this time, the transfer gate control circuit 262
, An internal refresh instructing signal REF may be applied. When internal refresh instructing signal REF is applied, transfer gate control circuit 262 may be rendered inactive. However, since refresh instructing signal REF # is externally applied, transfer gate control circuit 262 receives refresh instructing signal REF particularly if an external specification is set so that array access instructing signal CI is not generated at that time. No need. However, when the refresh operation is performed in the DRAM array, it is necessary to reliably electrically separate the SRAM array from the DRAM array, and the transfer gate control circuit 262 is disabled in response to the internal refresh instruction signal REF. By providing such a configuration, during the refresh operation, the SRAM array and the DRAM array are surely electrically separated from each other, and the SRAM array can be accessed from the outside.

As a configuration of such a transfer gate control circuit 262, a configuration is provided in which when one of the cache hit signal CH and the refresh instruction signal REF is activated, the transfer gate control circuit 262 is disabled. Just do it. More preferably, chip enable signal E is inactive, or cache hit signal CH and refresh instruction signal R
What is necessary is just to provide a gate circuit in which the selection gate control circuit 262 is disabled when any of F is in the active state. In other cases, transfer control signals φTDS and φTSD are generated at predetermined timings in accordance with control signals CI and W.

FIG. 31 shows a functional configuration of DRAM array drive circuit 260 shown in FIG. The DRAM array drive circuit 260 includes a row selection system drive circuit 260a for driving circuits related to row selection of the DRAM array,
A column selection system driving circuit 260b for driving a circuit related to column selection of the AM array 1 is included. Row selection system driving circuit 260a
Generates various control signals φEQ, / φSAPE, φSANE, and DWL at predetermined timings in response to internal control signals E, CH, CI, and REF. The column selection driving circuit 260b generates a signal CDA for driving the DRAM column decoder 15 at a predetermined timing in response to the control signals E, CH, CI and REF. If refresh instruction signal REF is inactive when row selection drive circuit 260a is activated, column selection drive circuit 260b generates column decoder activation signal CDA at a predetermined timing. Column selection related drive circuit 260b is disabled when refresh instruction signal REF is activated.
Thereby, the column selecting operation in the DRAM is prohibited.

With this configuration, refresh instructing signal R
When the EF is activated, the refresh operation in the DRAM array can be executed independently of the operation of the SRAM array.

Auto refresh mode detecting circuit 291, refresh control circuit 292 and counter circuit 293 shown in FIG.
, And its operation is independent of that of the command register 270. Therefore, the command register 2
The refresh of the DRAM array 101 can be performed in parallel with the command mode setting to 70. That is, command register 270 only generates command data CM and provides it to data input / output control circuit 272 and input / output buffer + output register block 274.
This is because the held data does not affect the memory cell selecting operation in the DRAM array 101 at all.

At this time, data setting in command register 270 is completed in one cycle of external clock signal K, as will be described later in detail with reference to a timing chart.
On the other hand, the refresh operation in the DRAM array requires n cycles. This is because the operation speed of the DRAM 100 is lower than the speed of the clock K. Thus, in this case, one clock cycle is simply effectively utilized. However, in the case where the cycle of the external clock K is delayed according to the operation mode, if the cycle is equivalent to one memory cycle of the DRAM 100, the data setting to the command register 270 and the refresh of the DRAM array 101 are performed in parallel. Can be performed. Such a change in the cycle of the external clock K is performed, for example, when the DRAM is in a standby state and when the storage device does not require high-speed operation but rather requires low power consumption. If the operation speed of the semiconductor memory device is reduced by increasing the length, the current consumption can be reduced in accordance with the decrease in the operation speed. The period of the external clock K may be lengthened when only the DRAM is accessed.

With the above configuration, a CDRAM having the following features can be realized.

(1) In a CDRAM according to the present invention, a DRAM memory array as a main memory and an SRAM array as a cache memory are integrated on one chip.
The two memories are connected via an internal bus dedicated to data transfer different from the internal common data bus. As a result, the block transfer between the DRAM array and the SRAM array (cache) is completed in one clock cycle. In the following description, when simply called an array, DRA
Assume an M array. With this, the conventional standard DR
The performance of the system can be greatly improved as compared with a cache memory system using the AM and the standard SRAM.

(2) DRAM memory array and SRAM
Each array can be accessed by a different address. Therefore, it is possible to support various mapping methods such as a direct mapping method, a set associative method, and a full associative method.

(3) This CDRAM uses the external clock K
Are operated synchronously. Therefore, it is possible to prevent a cycle time delay due to an address skew or the like as compared with a method of generating an internal clock signal using an address change detection circuit, and to execute accurate control.

(4) Array addresses (addresses for DRAM) Aa0 to Aa9 and cache addresses (SRA)
M address) Ac0 to Ac11, data input / output D0
To D3 or DQ0 to DQ3, write enable signal W
#, A cache hit signal CH #, a chip select signal E #, a refresh signal REF #, a cache inhibit signal CI #, a command register signal CR #, and other externally applied signals (or data) are all external clocks K.
Captured at the rising edge of

(5) Since the array address is taken in by the multiplex method, the number of pins for the array address can be reduced, and the mounting density of the CDRAM can be increased.

(6) The addresses of the array and the cache are independent. At the time of a cache hit, only access to the cache is performed, and high-speed cache hit access can be realized.

(7) Regardless of the timing of the external clock K, data can be read at an arbitrary timing by the output enable signal G #, thereby enabling asynchronous bus control in the system.

(8) The user can arbitrarily specify the output specifications (transparent, latch, register; these will be described later) and the I / O configuration (input / output pin separation, masked write) by the command register 270. If the register output method is used as described later, the output data of the address specified in the previous cycle appears at the rising edge of the external clock K. Such a data output mode is suitable for pipeline applications. In the latch output method, the output data of the address specified in the previous cycle is output during the period when invalid data is output. As a result, no invalid data is output, and only valid output data is always obtained. In this latch output mode, a period sufficient for the CPU to take in output data can be taken.

(9) The data write operation is started by the rising edge of the external clock K, and the end of the write is automatically terminated internally by a timer or the like.
Therefore, the end of the write operation does not need to be set by, for example, an external write enable signal W #, and the timing of the system can be easily set.

(10) A refresh instruction signal REF # designating auto-refresh can be externally provided. Thereby, the DRAM array can be easily auto-refreshed at a desired timing.

(11) Also, as described above, 44-pin 300 mil. The CDRAM of the present invention can be accommodated in a TSOP package type II. This TSOP
The package type II is an extremely thin rectangular package, and a system with a high mounting density can be constructed.

FIG. 32 is a table showing a list of operation modes provided in the CDRAM of the present invention and the state of control signals for designating each operation mode. The operation modes of the CDRAM are external control signals E #, CH #, CI #, CR #, W #.
And REF #. In FIG. 32, “H” indicates a high level signal potential,
“L” indicates a low-level signal potential, and “X” indicates arbitrary (don't care DC). As shown in FIG.
The operation modes of M include a standby mode in which a CDRAM is in a standby state, an array refresh in which a DRAM array is automatically refreshed, a transfer of data between a CPU (Central Processing Unit) and a cache (SRAM), and a CPU and an array. Transfer of data between the cache and the array, transfer of a data block between the cache and the array, setting of a special mode to the command register, and the like. Combinations of signal states and timings for setting each operation mode will be described later in detail with reference to operation waveform diagrams. In FIG. 32, the write enable signal W # is indicated as "H / L" at the time of data transfer between the CPU and the command register because the write enable signal W # is "H" or "H" in this operation mode. It is set to “L”, indicating that both the “H” and “L” states are used to designate a certain special mode.

FIGS. 33 and 34 show the contents of command register 270 shown in FIG. 21 and a method of selecting the contents. Command register 270 includes eight registers RR0-RR3 and WR0-WR3. In selecting this register, a combination of the write enable signal W # and the 2-bit command addresses Ar0 and Ar1 is used. By setting the external write enable signal W # to "H" at the rising edge of the external clock K, one of the registers RR0 to RR3 is selected. Register R
R0 is selected by setting both command addresses Ar0 and Ar1 to "0". Register RR
1 is selected by setting the command address bit Ar0 to "1" and setting the command address bit Ar1 to "0". If register RR0 is selected, it indicates that the masked write mode has been set (this masked write mode is also the default). Register R
When R1 is selected, it indicates that the D / Q separation mode has been set.

When the write enable signal W # is set to "L" at the rising edge of the external clock K and the command addresses Ar0 and Ar1 are both set to "0", the register WR0 is selected. This register WR0 is shown in FIG.
At that time, the data input terminal DQ0 (D0)
The output mode is set to one of transparent, latch, and register according to the combination of data of DQ3 (D3). Details of each of the output modes will be described later. When register WR0 is selected, input data D2 and D3 (DQ2 and DQ3)
Are both set to “0”. In this state, if the input data D0 is set to "0" and the input data D1 is set to an arbitrary value, the transparent output mode is set.
If the input data D0 is set to "1" and the input data D1 is set to "0", the latch output mode is selected. Input data D
If both 0 and D1 are set to "1", the register output mode is selected. The remaining registers are used for any extended functions.

FIG. 35 shows a CDRAM 600 according to the present invention.
FIG. 2 is a block diagram showing a configuration of a system when a direct mapping type cache system is configured by using FIG. In FIG. 35, this cache system is a CD
A controller 650 for controlling access to the CDRAM 600 in addition to the RAM 600;
And a CPU for inputting and outputting data and performing desired data processing. FIG. 35 shows only the configuration of an address at the time of a cache access request output from the CPU. This CPU assumes 32 bits. The cache system further includes a CDRAM 60
An address multiplexing circuit 700 for multiplexing row addresses and column addresses to an array of 0s is provided. CDRAM 600 representatively shows only a portion related to cache access.

A controller 650 is a decoder 652 for decoding set addresses A6 to A13 from the CPU.
A valid bit memory 654 indicating which tag is valid in response to the output of the decoder 652, and the SRAM 20
A tag memory 656 for storing a tag address of data stored in 0 is included. The SRAM 200 has a 4K × 4 bit configuration, and has 256 tags. For this reason, the tag memory 656 has an 8-bit × 256 configuration. The valid bit memory 654 has a structure of 1 bit × 256 to indicate which of the 256 tags (sets) is valid. The decoder 652 decodes the set addresses A6 to A13 and makes any one of the bits in the valid bit memory 654 valid.

Controller 650 further receives addresses A22 to A31 from the CPU as a chip selection signal, determines whether or not the corresponding CDRAM 600 is designated, and activates in response to the output of decoder 670. The tag address from the tag memory 656 and the tag addresses A14 to A2 from the CPU
1 and a comparator 658 which determines a cache hit / miss by comparing the tag address from the tag memory 656 and any one of the tag addresses A14 to A21 from the CPU according to the cache hit / miss. A selector 672 provided to the circuit 700 is included.
The selector 672 also stores the tag address given from the CPU at a corresponding position in the tag memory 656 upon a cache miss.

Next, the operation will be briefly described. CPU
Generates an address A2 to A31 on the data bus 620 when the user wants to access the CDRAM 600. Of the 30-bit address on the common data bus 620,
Addresses A22 to A31 are provided as a chip select signal to decoder 670 in controller 650. The decoder 670 decodes the addresses A22 to A31 as the chip select signal, and
It is determined whether M has been requested to access. This C
When it is determined that an access request has been made to DRAM 600, a chip select signal E # is generated from decoder 670 and applied to CDRAM 600. The comparator 658 is activated by the chip select signal from the decoder 670.

The decoder 6 included in the controller 650
52 receives and decodes the addresses A6 to A13 among the addresses transmitted from the CPU onto the address bus 620 as set addresses. The decoder 652 that decodes the 8-bit set address sets the corresponding bit of the valid bit memory 654 to a valid state in order to select one of the 256 tags. From the tag memory 656, an 8-bit address indicating a tag corresponding to a valid bit of the valid bit memory 654 is read and applied to the comparator 658. The comparator 658 compares the tag address from the tag memory 656 with the tag addresses A14 to A21 output from the CPU. If they match, the comparator 658
Is a cache hit signal C to indicate a cache hit.
H # falls to “L” and is applied to CDRAM 600. On the other hand, if they do not match, comparator 658 generates a cache hit signal CH # of "H" to indicate a cache miss (miss hit).

In a cache hit, CDRAM6
At 00, the following operation is performed. Operation control at this time is performed by a control signal from control clock buffer 250 and SRAM array drive circuit 264 (see FIG. 21). The SRAM row decoder 202 selects one of the 256 sets in response to addresses A6 to A13 from the CPU. That is, one row (each SR
(A total of four lines are selected for each AM array block). Thus, a 16-bit SRAM cell is selected in each SRAM array block of the SRAM 200. The SRAM column decoder SCD203 decodes the block addresses A2-A5 from the CPU,
One bit is selected from the bit memory cells and connected to the data input / output terminal. FIG. 35 shows output data Q at the time of hit read.

The operation at the time of a mishit will be described below. In this case, the SRAM 200 does not store data requested by the CPU to access. Controller 650
In, the selector 672 gives the corresponding tag address stored in the tag memory 656 to the multiplex circuit 700 in response to the mishit instruction signal from the comparator 658. The selector 672 then sets C
8-bit tag address A14 given from PU
To A21 as new tag addresses in the tag memory 656.
Is stored in the corresponding position.

In CDRAM 600, in this cycle, copy back, that is, DR from SRAM 200 is performed.
Batch transfer of 16 bits to AM 100 is performed. S
In RAM 200, the address A6-
The data of 16 bits × 4 selected by the SRAM row decoder SRD 202 according to A13 is stored in the DRAM according to the address A6-A13 output from the CPU and the 8-bit tag address output from the selector 672.
At 100, a row and column selection operation is performed, and the data is stored in the corresponding position of the selected 16-bit × 4 DRAM cell.

In the next operation cycle, CDRAM 60
0 is the address A6-A21 output from this CPU.
16 bits × 4 DR in the DRAM 100
An AM cell is selected, and this 16-bit × 4 data is again stored in the SRAM 200 selected by the SRAM row decoder SRD according to the address A6-A13 from the CPU.
Is written to the corresponding 16-bit × 4 memory cell.

As described above, for the SRAM, addresses A2 to A5 are set as block addresses, addresses A6 to A13 are set addresses and addresses A14 to A21 are set as tag addresses, and for DRAMs, addresses A6 to A11 are set as column addresses. By using the addresses A12 to A21 as the row addresses, a direct mapping method between the DRAM 100 and the SRAM 200 can be realized.

FIG. 36 is a block diagram showing the configuration of a 4-way set associative system using the CDRAM of the present invention. The CDRAM 600 has the same configuration as that shown in FIG.
The AM 100 includes a clock control circuit 250 '. The clock control circuit 250 'includes the control clock buffer 250, the SRAM array driving circuit 264, and the DR
An AM array driving circuit 260 is included. A circuit configuration for controlling data input / output is not shown to simplify the drawing.

The controller 750 includes a decoder 752,
Valid bit memory 754, tag address memory 756,
Comparator 758, decoder 770 and selector 7
72. In order to support 4 ways, the effective bit memory 754 includes four memory planes each having a configuration of 1 bit × 64, and a tag address memory 754.
6 also comprises four memory planes each having an 8 bit × 64 configuration. Similarly, one comparator 758 is provided for each memory plane of the tag address memory 756 to select one of the four ways, for a total of four comparators. In the four-way set associative method, 256 rows of the SRAM 200 are divided into four ways, so that the number of sets is 64.

An address having the following structure is transmitted from CPU to address bus 620. Address A22
To A31 are chip select addresses, address A
14 to A21 are tag addresses, addresses A12 and A13 are way addresses, addresses A6 to A11.
Are set addresses, and addresses A2 to A5 are block addresses. Addresses A6 to A11 and addresses A12 to A21 are used as column addresses and row addresses for DRAM 100, respectively. A multiplex circuit 700 for multiplexing a row address and a column address is provided for the DRAM 100 of the CDRAM 600. Next, the operation will be described.

Addresses A6-A11 from the CPU are provided to decoder 752 as set addresses, and addresses A22-A31 are provided to decoder 770 as chip select addresses. The decoder 752 decodes the set addresses A6-A11, and sets a valid bit related to the corresponding set in the valid bit memory 754 to a valid state. Thereby, one set (4 ways) is selected. The decoder 770 decodes the chip select addresses A22-A31,
It is determined whether an access request to 00 has been issued. When the CDRAM 600 is requested to access, the decoder 770 activates the chip select signal E # to “L” and activates the comparator 758. The comparator 758 is provided in the valid bit memory 7
The tag address memory 75 is referred to
6, the corresponding 4-way tag address is read, and the read tag address and the address A14-A from the CPU are read.
Compare 21. When a match is found, comparator 758 outputs way addresses W0 and W1 indicating the way in which the match was found, and lowers cache hit signal CH # indicating a cache hit to "L". . If no match is found in comparator 758, cache hit signal CH # is set to "H" indicating a mishit.

In the case of a cache hit, the way addresses W0 and W1 from the controller 750 and the addresses A6-A11 from the CPU are stored in the SRAM row decoder 202.
And a 16-bit × 4 SRAM cell is selected in the SRAM array 201. Block address A
2-A5 is decoded by the SRAM column decoder 203, and 1 bit × 4 is selected from the selected 16-bit × 4 SRAM cells and connected to the data output terminal Q (or data input terminal D).

In the case of a mishit, the selector 772
Selects one of the four-way tag addresses according to the LRU logic (logic for selecting the oldest way) and selects an area in which the tag address is to be rewritten.
The tag address selected by the selector 772 is provided to the DRAM row decoder DRD of the DRAM 100 via the multiplex circuit 700 as an array address. The selector 772 stores the tag address to be rewritten in the address A14-A2 given from the CPU.
Replace with 1.

In CDRAM 600, this cycle is a copy back mode. In this copy-back mode, under the control of selector 772, way addresses W0 and W1 indicating the way to be rewritten.
Is output. In the SRAM 200, the addresses A6-A11 from the CPU and the way addresses W0 and W1 from the controller 750 are decoded, and a 16-bit × 4 SRAM cell is selected. On the other hand, DRAM 10
0, the 8-bit tag address output from the selector 772 and the address A6-
A 16-bit × 4 DRAM cell is selected according to A13. Then, the selected 16-bit × 4 SR
Data transfer from the AM cell to the selected 16-bit × 4 DRAM cell is performed.

In the next operation cycle, a DRAM cell of 16 bits × 4 is selected in DRAM 100 in accordance with addresses A6-A21 from the CPU. The newly selected 16-bit × 4 DRAM cell data is collectively transferred to the 16-bit × 4 SRAM cell selected according to the addresses A6-A11 and the way addresses W0, W1.

With the above configuration, the CDRAM
Both the direct mapping method and the set associative method can be implemented without changing the internal configuration of the 600 at all. Although not shown in the figure, a full associative mapping method is of course also possible. In this case, the controller 75
0, the SRAM cache address and DRA
A tag address memory for storing the corresponding address of M100 is required. Next, signal timing relationships and state transitions in various operation cycles of the CDRAM will be described.

As described above, the control signals except for the output enable signal G # and the addresses Aa and Ac are latched at the rising edge of the external clock signal K. The state of each signal is arbitrary (DC) except that a setup time and a hold time are required before and after the rising edge of the external clock K, respectively. According to the external clock synchronization method, it is not necessary to consider a margin of a cycle time due to a skew of an address signal and the like, and a cycle time can be reduced and a CDRAM that operates at a high speed can be obtained.

The output enable signal G # is shown in FIG.
Controls the output state of the output buffer and output register included in the input / output circuit 274 shown in FIG. When the output enable signal G # is "H", the output data is in a high impedance state (Hi-Z). When the output enable signal G # becomes "L" in an active state, some data is output. The operation modes of the CDRAM are listed in FIG. 32. Each operation mode will be described below with reference to its timing chart.

In the standby state, chip select signal E # and refresh instruction signal REF # are both set to "H" at the rising edge of external clock signal K, and the remaining control signals CH #, CI #, CR # and W # are set.
Is an arbitrary state. In this standby mode, C
No memory operation is performed in the DRAM.

[0222] No. 1: Cache hit write cycle FIG. 37 is a diagram showing the timing of each signal in a cache hit write cycle. The external clock signal K has a cycle time tk. Cycle time tk
Includes an H pulse width tKH when the external clock signal K is in the “H” state and an L pulse width tKL when the external clock signal K is in the “L” state. The cache hit write cycle is a cycle for writing data to the SRAM cache. When this state is selected, the chip select signal E # is set to "L" at the rising edge of the external clock signal K, the cache hit signal CH # is set to "L", the cache inhibit signal CI # is set to "H", and the command register signal CR # is set to "H". "H", the write enable signal W # is set to "L", and the output enable signal G # is set to "H".

In this state, the address for SRAM 200 is latched as valid (Valid), and the SRAM is accessed according to this SRAM address Ac. At this time, the address A for the DRAM
a is arbitrary (DC). The input data D is made valid at the rising edge of the external clock signal K, and this valid write data is written to the SRAM cell selected by the SRAM address Ac. Cache memory S
Since the access to the RAM is fast, the writing is completed in one clock cycle of the external clock signal K as shown in FIG. That is, the time required for the cache hit write is the clock cycle time tK.

In FIG. 37, output data Q changes in response to an arbitrary state of output enable signal G #, which changes to the "H" and "L" levels of output enable signal G #. This indicates that output data appears in response. In FIG. 37,
The setup time and hold time of each control signal and address signal are also shown. The setup time is a time required to surely set each control signal or address to a defined state by the rising edge of the external clock signal K. The hold time is a time required from the rising edge of the external clock signal K to hold the signal for a certain period of time to perform a reliable operation. The setup time and the hold time will be briefly described.

The chip select signal E # has a setup time tELS required when shifting to “L” and a setup time tEHS required when shifting to “H”.
And hold time tELH required at the time of transition to “L”
And hold time tEHH required at the time of transition to “H”
including.

The cache hit signal CH # has "L"
A setup time tCHLS required at the time of transition;
Setup time tCHH required at "H" transition
S and the hold time tCH required when shifting to “L”
LH and hold time tC required at the time of transition to “H”
HHH is set.

The cache inhibit signal CI # includes the setup times tCILS and tCIHS required at the time of transition to “L” and “H”, and the hold required at the time of transition to “L” and “H”, respectively. Includes times tCILH and tCIHH.

Command register signal CR # includes setup times tCRLS and tCRHS required at the time of transition to “L” and “H”, and a hold required at the time of transition to “L” and “H”, respectively. Includes times tCRLH and tCRHH.

The refresh signal REF # includes the setup times tRLS and tRHS required at the time of transition to “L” and “H”, and the hold time required at the time of transition to “L” and “H”, respectively. t
Includes RLH and tRHH.

The write enable signal W # includes the setup times tWLS and tWHS required when transitioning to "L" and "H", and the hold required when transitioning to "L" and "H", respectively. Time t
WLH and tWHH. Address A for SRAM
c includes a setup time tACS required for the state to be determined to be valid (Valid) and a hold time tACH required when the state is valid.

The address Aa for the DRAM includes a setup time tAAS required until it is determined to be valid (rising edge of the external clock signal K) and a hold time tAAH required after it is determined to be valid. .

For write data D, setup time tDS required for valid data and hold time tDH required for valid data are required.

In response to output enable signal G #, time tGHD required from the output disable state to the activation of the data input pin.
And a delay time tGLD required until the signal G # transitions to "L" after the data input pin goes into a high impedance state, and a delay time tGLD required until the output pin is activated after the transition to "L". And a time tGHQ required until the output pin goes into a high impedance state after the transition to “H”.

As the access time, the access time tGLA from when the output enable signal G # goes "L" to when valid data is output, and the valid time after the external clock signal K goes "L". The access time tKLA required until the output is performed, the access time tKHA required until the valid data is output after the external clock signal K becomes “H”, and the external clock signal K is “ Access time tKHAR from the time of “H” until valid data is output
And the DRAM after the external clock signal K becomes "H".
, An array access time tKHAA required until valid data is output after access is set.

In FIG. 37, after a lapse of time tGHD from the rising edge of output enable signal G #, write data D is regarded as invalid (Inv).

The cycle time of the CDRAM of the present invention is set to, for example, 10 ns to 20 ns. The array access time tKHAA is set to 70 to 80 ns. Each setup and hold time is set to a few nanoseconds.

NO. 2T: Cache hit read cycle (transparent output mode) FIG. 38 shows a timing chart of the cache hit read cycle in the transparent output mode. As described above, the output mode includes the transparent output mode, the latch output mode, and the register output mode. This output mode is designated by a command register. In FIG. 38, when a cache hit read cycle is set, chip select signal E # and cache instruction signal CH # are both set to "L" at the rising edge of external clock signal K, and cache inhibit signal CI # and refresh Instruction signal REF #, command register signal CR #, and write enable signal W # are set to "H".

In this state, address Ac for SRAM is made valid at the rising edge of external clock signal K, and the operation of selecting an SRAM cell according to this effective address Ac is performed. In the transparent output mode, the SRAM designated by the effective address Ac
Cell data is output in this clock cycle. In the transparent output mode, valid output data Q is output at a later timing after a lapse of time tKHA from the rising edge of external clock signal K or after a lapse of time tGLA from the falling edge of output enable signal G #. You.

If output enable signal G # falls to "L" before time tKHA, invalid data (IN
V. ) Is output until the time tKHA elapses. In this cache hit read cycle, the write data is set in a high impedance state (Hi-Z), and the address Aa for the DRAM is not used, so that it is in an arbitrary state.

[0239] No. 2L: Cache hit read cycle (latch output mode) FIG. 39 shows a timing chart of the cache hit read cycle in the latch output mode. The difference between the latch output mode and the transparent output mode is that when the output enable signal G # falls to "L" before the access time tKHA, first, the SRAM cell selected in the previous cycle Vali data (Pre.Vali
d) is output. The timing of other signals is the same as in the transparent output mode shown in FIG. According to this latch output mode, invalid data (IN
V) is not output, and only valid data is always output.

[0240] No. 2R: Cache Hit Read Cycle (Register Output Mode) FIG. 40 shows a timing chart of the cache hit read cycle in the register output mode. The timing of the external control signal in the cache hit read cycle in the register output mode is the same as that in the transparent output mode and the latch output mode shown in FIGS. In this register output mode, the valid data (Pre. Vali
d) is output. In this register output mode, no invalid data is output. This register output mode is suitable for pipeline operation.

The switching of the output mode is realized by controlling the operation of an output register included in input / output circuit 274 shown in FIG.

[0242] No. 3: Copyback cycle FIG. 41 shows the timing of each signal in the copyback cycle. This copy back cycle is performed in the cache (SRA
This is a cycle for transferring data from M) to the array (DRAM), and is performed in the first cycle in the case of a mishit. In the copy back cycle, at the rising edge of external clock signal K, both chip select signal E # and write enable signal W # are set to "L", and cache hit signal CH #, cache inhibit signal CI #, refresh instruction The signal REF #, the command register signal CR #, and the output enable signal G # are set to "H". In this copy back cycle, it is necessary to input an array address Aa in order to select a memory cell also in a DRAM. The array address Aa has a row address (Row) and a column address (C
ol) is given as a multiplex. The array row address is latched at the first rising edge of external clock signal K, and the array column address is latched at the second rising edge of external clock signal K. At the second rising edge of external clock signal K, cache hit instruction signal CH #, cache inhibit signal CI #, write enable signal W # and cache address (S
The address (Ac) for the RAM is arbitrary.

Write enable signal W # is set to "L" at the first rising edge of external clock signal K, and external input data D changes from a high impedance state to an arbitrary state. The external output data Q is in a high impedance state because the output enable signal G # is at "H".

[0244] No. 4: Block transfer cycle In the block transfer cycle shown in FIG. 42, the cache (SRA)
The data blocks are collectively transferred to M). This block transfer cycle satisfies the same timing conditions as the copy back cycle shown in FIG. 41 except that write enable signal W # is set to "H" at the first rising edge of external clock signal K.

That is, a cache miss (miss hit)
When the write enable signal W # is set to "L" at the first rising edge of the external clock signal K, a copy-back cycle is started, while when the write enable signal W # is set to "H", the copy-back cycle starts. A block transfer cycle to the cache is set.

[0246] No. 5: Array Write Cycle The array write cycle shown in FIG. 43 is a cycle for setting a mode in which the CPU directly accesses the array and writes data. DRA of array by array address Aa
Select M cell. At this time, as shown in FIG. 23, the access switching circuit 310 of the bidirectional transfer gate circuit 305
, And without providing such an access switching circuit 310, FIG.
As shown in FIGS. 11 and 12, the SRAM bit line pair SB
L and bidirectional transfer gate BTG and global I
Data may be written via the / O line pair GIO. In the case of a configuration in which data is written via the SRAM bit line pair SBL of the SRAM array, the lower bits of the array address Aa may be given to the column decoder SCD of the SRAM as a block address. It may be provided to the SRAM selection gate.

The array write cycle is specified by the chip select signal E # and the cache inhibit signal C at the first rising edge of the external clock signal K as shown in FIG.
This is performed by setting I # and write enable signal W # to "L", and setting refresh instruction signal REF # and output enable signal G # to "H". The state of the cache instruction signal CH # is arbitrary. In this array write cycle, the array address A is output at the first rising edge of the external clock signal K.
a is latched as a row address (Row), and the array address Aa is latched as a column address (Col) at the second rising edge of the external clock signal K. Since access to the cache is not performed at this time, the state of the cache address Ac is arbitrary. External write data D is latched at the first rising edge of external clock signal K. The external output data Q enters a high impedance state.

In the cache system shown in FIGS. 35 and 36, only a 16-bit address is applied to DRAM 100, and S
A column selection operation inside a block in the RAM is performed. The configuration shown in FIGS. 35 and 36 shows the configuration at the time of the cache system, and does not show the configuration of the array access. However, when the cache inhibition signal CI # becomes "L" at the time of the array access, the configuration shown in FIG. The configuration may be such that a 4-bit block address is used as a column selection address of the DRAM 100.

[0249] No. 6: Array Read Cycle The array read cycle shown in FIG. 44 is a cycle for setting a mode in which the CPU directly accesses the array and reads data. The array read cycle is designated by setting the chip select signal E # and the cache inhibit signal CI # to "L" at the first rising edge of the external clock signal K.
This is performed by setting the refresh instruction signal REF #, the command register signal CR #, the write enable signal W #, and the output enable signal G # to "H". At the second rising edge of the external clock signal K, the chip select signal E #, the refresh instruction signal REF #, and the command register signal CR # are set to "H", and the states of the cache inhibit signal CI # and the write enable signal W are changed to "H". Optional. The cache hit instruction signal CH # can be in any state in the array read cycle, and the output enable signal G # maintains the state of "H". At the first rising edge of external clock signal K, array address Aa is latched as a row address, and at the second rising edge of external clock signal K, array address Aa is latched as a column address. The state of external input data D is arbitrary, and external output data Q is set to a high impedance state.

The array access cycle (array write cycle and array read cycle) is set by setting cache signal CI # to "L" at the first rising edge of external clock signal K.
This array access cycle is a cycle for setting a mode in which the CPU directly accesses the array,
Data read / write is not actually performed in the array write cycle and array read cycle.

Read / write of array data such as copy-back operation, block transfer operation and array access operation
Operations requiring a write require selection of a word line of the DRAM array, detection and amplification of selected cell data by a sense amplifier, data restore operation, RAS precharge, and the like. Therefore, an operation requiring reading / writing of data in these arrays requires several clock cycles. The cycle time of the DRAM is ta,
When the cycle time of the external clock signal K is tK, m =
Only ta / tK external clock cycles are required for array access. These m cycles are waiting time for the CPU. The timing when a wait is applied to the CPU in cell selection and data read / write in such an array will be described below.

[0252] No. 7: Array Active Cycle In the array active cycle shown in FIG. 45, a row selecting operation and a column selecting operation and data writing / reading are performed according to applied array address Aa. In this array active cycle, the chip select signals E #,
Refresh instruction signal REF # and command register signal CR # are set to "H", and output enable signal G # is fixed to "H" during this cycle. Cache hit signal CH #, cache inhibit signal CI #,
The state of the write enable signal W # is arbitrary. In this array active cycle, external input data D
Is arbitrary, but the external output data Q becomes high impedance.

[0253] No. 7QT: Array Active Cycle with Transparent Output Mode In designating the array active cycle in the transparent output mode shown in FIG. 46, each control signal E #, CH #, CI #, REF #, CR #, and W
# Is set similarly to the array active cycle shown in FIG. In the array active cycle in the transparent output mode, the output buffer is activated by setting the output enable signal G # to "L", and valid data is output. In the array active cycle in the transparent output mode, the DRAM corresponding to the array address Aa set in the array read cycle shown in FIG.
The cell data is output.

[0254] No. 7QL: Array Active Cycle in Latch Output Mode The timing state of each control signal in the array active cycle in the latch output mode shown in FIG. 47 is the same as that shown in FIG. In the array active cycle in the latch output mode, when the output enable signal G # which has been held at "H" falls to "L", first, the previous access cycle (the array access cycle even in the cache access cycle) is performed. ) Is first output, and then the data read in the current array access cycle is output.

[0255] No. 7QR: Array active cycle in register output mode The state of each control signal in the array active cycle in the register output mode shown in FIG. 48 is the same as that shown in FIGS. 46 and 47. In the array active cycle in this latch output mode, "H"
Falls to "L", the external write data D enters a high impedance state, and the data read in the previous access cycle is output as the external output data Q. In this array access cycle in the latch output mode,
In the next clock cycle, the output enable signal G
When # falls from "H" to "L", data read in the current array access cycle is output.

By combining the cycles shown in FIGS. 44 to 48, output data Q according to the external address is obtained from the array.

FIG. 49 shows the entire cycle executed when data is read from the array in the transparent output mode. In FIG. 49, the numbers indicated by circles on the timing chart represent the numbers given in the description of each cycle described above.

First, in the array read operation in the transparent output mode, an array read cycle (No. 6) shown in FIG. 44 is executed. This cycle No. 6, the array address Aa is sequentially taken in as a row address and a column address at the rising edge of the external clock signal K, respectively. Then, the array active cycle shown in FIG. 45 is executed a predetermined number of times, and a row and column selecting operation in the DRAM array is performed. Finally, the cycle No. shown in FIG. By executing 7QT and lowering the output enable signal G # to "L", valid data is output after invalid data is output. In this case, the access time tKHAA is substantially equal to the access time of a normal DRAM.

FIG. 50 shows an entire cycle performed when data is read from the array in the latch output mode. In the array read operation in the latch output mode, similarly to the array read operation in the transparent output mode shown in FIG. 49, first, an array read cycle (No. 6) shown in FIG. The settings are made. After the array address Aa is latched by the array read cycle (cycle No. 6), the array active cycle (cycle No. 7) shown in FIG. 45 is performed a predetermined number of times. After this array active cycle (cycle No. 7), the array active cycle (cycle No. 7Q) in the latch output mode shown in FIG.
L) is performed. This cycle No. When the output enable signal G # previously set to "H" at 7QL falls to "L", an access is requested in the current array read cycle after the data read by the previous access is output. The data of the memory cell is output. The access time tKHAA at this time is a time required from the first rising edge of the external clock signal K to outputting the memory cell data (Valid) requested to be accessed in the current array access cycle.

FIG. 51 shows an entire cycle performed when data is read from the array in the register output mode. In FIG. 51, first, cycle N
o. By executing step 6, the array read mode is set, and at the rising edge of external clock signal K, array address Aa is latched in a time-division manner as a row address and a column address, respectively. Then, cycle N
o. After the array active cycle of No. 7 has been performed a predetermined number of times, cycle No. 7 An array active cycle of 7QR is performed. This cycle No. In 7QR, after the output enable signal G # falls to "L" and the external clock signal K rises, the data read in the previous cycle at the later timing after the lapse of the time tKHA or the lapse of the time tGLA Output as output data Q. The access time tKHAA at this time is the cycle No. 6, the time from the first rising edge of the external clock signal K to the output of valid data.

DRAM cells need to be periodically refreshed. The setting of this refresh operation is performed by an external refresh instruction signal REF #. At the time of this refresh, in the CDRAM, a refresh address is generated from a refresh address counter (see counter circuit 293 in FIG. 21) in response to refresh instruction signal REF #, and the DRAM cells are automatically refreshed in accordance with the refresh address. Is performed. A DRAM having such an auto-refresh function has been conventionally known in the DRAM field. Hereinafter, the timing of the signal for performing the refresh will be described.

[0262] No. 8: Refresh Cycle FIG. 52 is a diagram showing signal timing of the refresh cycle. As shown in FIG. 52, at the rising edge of external clock signal K, chip select signal E # and refresh instruction signal REF # are changed to "H" and "L", respectively.
By setting, the refresh mode of the DRAM is set. If the chip select signal E # is set to "H" and the refresh instruction signal REF # is set to "H" at the rising edge of the external clock signal K, the refresh of the DRAM is stopped. In this auto refresh cycle, other control signals CH #, CI #, CR #, W
The state of # is arbitrary, and the output enable signal G # is set to "H". Therefore, at this time, the state of cache address Ac and array address Aa is arbitrary, the state of external input data D is also arbitrary, and external output data Q is set to a high impedance state.

The refresh operation is performed only for the DRAM. SRAM does not need to be refreshed at all. Therefore, it is possible to access the cache during this refresh period.

The timing of a cycle for simultaneously performing the refresh and the cache access will be described below.

[0265] No. 8W: Refresh cycle with cache hit write This cycle No. In 8W, data is written to the corresponding SRAM cell when a cache hit occurs, in parallel with the refresh in the DRAM. As shown in FIG. 53, the refresh cycle accompanied by the cache hit write is set at the rising edge of the external clock signal K at the chip select signal E
#, The cache hit signal CH #, the refresh instruction signal REF #, and the write enable signal W # are set to "L", and the cache inhibit signal CI # and the output enable signal G # are set to "H". . As a result, a cache hit write cycle and a refresh cycle are set. In the cache (SRAM), in response to the active state of cache hit instruction signal CH # and write enable signal W #, external write data D is taken in at the rising edge of external clock signal K to the corresponding SRAM cell position. Write. In a DRAM, refresh instructing signal R
The internal refresh address counter is activated by EF #, and refresh is performed according to the refresh address from this counter.

If refresh instruction signal REF # is set to "H" at the rising edge of external clock signal K, the cache hit write cycle (cycle No. 1) shown in FIG. 37 is merely performed, and DRA is performed.
The refresh of M is stopped.

[0267] No. 8RT: Refresh cycle with cache hit read in transparent output mode In 8RT, cache hit read is performed in accordance with the transparent output mode, and auto refresh is performed in the DRAM. This cycle No. The setting of FIG.
As shown in the figure, at the rising edge of the external clock signal K, the chip select signal E # and the cache hit signal C
H # and refresh instruction signal REF # are set to "L", and cache inhibit signal CI #, command register signal CR # and write enable signal W # are set to "H".
This is done by setting In the SRAM cache, the cache address Ac is taken in at the rising edge of the external clock signal K and the corresponding SRAM cell is selected in response to the cache hit read instruction.
When output enable signal G # falls to "L", valid output data Q is output after a predetermined time has elapsed.

In the DRAM, auto refresh is performed in response to refresh instructing signal REF #. If the refresh instruction signal REF # is set to “H” at the rising edge of the external clock signal K in the refresh cycle involving the cache hit read,
Auto-refresh performed in response to refresh instruction signal REF # is stopped. Therefore, in this case, the cycle No. shown in FIG. A cache hit read cycle in the same transparent output mode as 2T is performed.

[0269] No. 8RL: Refresh cycle with cache hit read in latch output mode Cycle No. 8 shown in FIG. In 8RL, cache hit read is performed in the latch output mode and DRAM auto-refresh is performed. The timing conditions of each control signal are the same as those shown in FIGS. In this latch output mode, when a cache hit occurs, after the output enable signal G # falls to "L", first the data accessed in the previous cycle is output, and subsequently the data is accessed in the current cycle. Data is output.

[0270] No. 8RR: Refresh cycle with cache hit read cycle in register output mode Cycle No. 8 shown in FIG. In 8RR, data is read according to a cache hit read cycle in the register output mode, and DRA
Auto refresh is also performed in M. The timing conditions of each control signal are the same as those shown in FIGS. 54 and 55, and heat read and auto refresh are performed. This cycle No. In 8RR, when the output enable signal G # falls to "L", the output data selected in the previous cycle is output. Thereafter, once the output enable signal G # is raised to "H" and subsequently the output enable signal G # is lowered to "L" in the next clock cycle, the data of the SRAM cell selected in the current cycle is obtained. Is output.

The transparent output mode, latch output mode, register output mode, masked write mode, and D / Q separation mode of the CDRAM are realized by setting a command for setting a desired special function in the command register. Next, an operation cycle for setting a command in the command register will be described.

[0272] No. 9: Command register set cycle FIG. 57 shows a command register set cycle (cycle N).
o. It is a figure which shows the timing of each signal in 9).
The command register set cycle includes a chip select signal E #,
Cache inhibit signal CI #, command register signal CR
# And the write enable signal W # are set to “L”. At this time, as shown in FIG. 33, four registers WR0 to WR0 of the command registers
One of WR3 is selected. In setting the output mode, the command register WR0 is selected, and the contents of the output mode are selected by the combination of the input data D at that time. Therefore, the command address Ar and the external write data D are validated and latched at the rising edge of the external clock signal K. 2 bits A of command address Ar
When both r0 and Ar1 are 0 (“L”), the command register WR0 is selected. Upper two bits D2 (DQ2) and D3 of 4-bit external write data D
(DQ3) is “0” (“L”) and the least significant bit D
If 0 (DQ0) is "0", the mode is set to the transparent output mode.

In the latch output mode, external write data D0 and D0 are output at the rising edge of external clock signal K.
1 is set to "1"("H") and "0", respectively, and the remaining two bits of external write data D2 and D3 are both set to "0". In the register output mode, the command addresses Ar0 and Ar1 are both set to "0" at the rising edge of the external clock signal K, the external write data D0 and D1 (DQ0 and DQ1) are both set to "1", and the external write data is set. The selection is made by setting both D2 and D3 (DQ2 and DQ3) to “0”.

In the configuration of the command register shown in FIG. 33, eight registers are provided, and eight kinds of special modes can be set. In order to select the command register RR0 for setting the masked write mode and the register RR1 for setting the D / Q separation mode, the write enable signal is set at the rising edge of the external clock signal K in the timing chart shown in FIG. Set W # to "H". A desired mode is selected according to the value of the command address Ar at this time.

Next, a specific configuration for setting the data output mode to the transparent mode, the latch mode, and the register mode according to the setting data by the command register will be described. FIG. 58 is a diagram showing a circuit configuration related to data output mode setting. FIG.
8, the command register 270 outputs a command register mode detection signal (internal command register signal) CR
, A command register mode selector 279 for decoding the write enable signal W # and the command data Ar0 and Ar1, a register WR0-WR3 and a flip-flop FF1. The command register includes eight registers RR0 to RR3 as shown in FIG.
And WR0 to WR3. However, in FIG. 58, the registers RR2 and RR3 are not shown. Each of the registers WR0 to WR3 is a 4-bit register. Registers RR0 and RR1 share one flip-flop FF1. Register RR0
Is selected, the flip-flop FF1 is set to the masked write mode. When the register RR1 is selected, the flip-flop FF1 is set to the D / Q separation mode. The input control circuit 272b controls the input circuits 274b and 2 according to the setting data of the flip-flop FF1.
74c is selected.

Data setting to any of registers WR0 to WR3 is performed by decoding command data Ar0 and Ar1. Write enable signal W #
Is active, 4-bit data D0-D3 (or DQ0-DQ3) is set in the corresponding register via input circuit 274b or 274c selected by input control circuit 272b. Since the register WR0 is related to the data output mode, the setting of the data output mode will be described. The output control circuit 272b is set to one of the transparent, latch, and register output modes in accordance with the lower 2 bits of data of the register WR0, and selectively activates the output circuit 274a according to the set output mode. Signal φ1, / φ
1 and φ2.

FIG. 59 shows an example of a specific configuration of output circuit 274a. In FIG. 59, the output circuit 274
a is a first output latch 981 for latching data on read data buses DB and * DB in response to control signals φ1 and / φ1, and latch data of output latch 1 in response to clock signal φ2. Or data bus DB, * DB
A second output latch 982 for passing the above data and an output buffer 983 for receiving data from the output latch 982 and transmitting the output data to the external pin terminal DQ in response to the control signal G #.

First output latch 981 includes clocked inverters ICV1 and ICV2 activated in response to clock signals φ1 and / φ1. The input and output of clocked inverter ICV1 are connected to the output and input of clocked inverter ICV2, respectively. This output latch 981 enters a latch state when clock signal φ1 is at “H”. That is, the clocked inverter I
CV1 and ICV2 are activated when clock signal φ1 is at "H" and function as inverters. When the clock signal φ1 is “L”, the clocked inverter ICV
1 and ICV2 are disabled, and latch 981 does not perform a latch operation.

The second output latch 982 latches the data applied to its inputs A and * A when the clock signal φ2 is "L", and outputs the data from the outputs Q and * Q. The output latch 982 outputs the latched data from the outputs Q and * Q when the clock signal φ2 is “L” when the clock signal φ2 is “H”, regardless of the signal states of the inputs A and * A. . Clock signals φ1,
/ Φ1 and φ2 are signals synchronized with an external clock K, and their generation timings are made different by the output control circuit 272b.

Output buffer 983 is activated when output enable signal G # attains an active state, and output latch 982 is activated.
Is transmitted to the terminal DQ.

FIG. 60 shows an example of a specific structure of second output latch 982. Referring to FIG. In FIG. 60, second output latch 982 includes a D-type flip-flop DFF receiving input A (* A) at its D input and receiving clock signal φ2 at its clock input CLK. From the output Q of the flip-flop DFF to the output Q of the output latch 982 (*
Q) is obtained. This D-type flip-flop DFF is of a down-edge trigger type, takes in the input A at the timing when the clock signal φ2 falls to L, and outputs the clock signal φ2.
Output the input A as it is while is "L". When the clock signal φ2 is “H”, the latched data is output regardless of the state of the input A applied to the input terminal D. As a result, the output latch 98 that realizes a desired function is provided.
2 is obtained. D-type flip-flops DFF are provided for input A and input * A, respectively. The output latch 982 may have another configuration, and the clock signal φ
2, any circuit configuration can be used as long as the circuit configuration can realize the latch state and the through state.

FIG. 61 is a diagram showing an example of a specific structure of the output control circuit 272b. The output control circuit 272b includes a delay circuit 991a for delaying the external clock for a predetermined time,
991b and 991c, a one-shot pulse generation circuit 992a for generating a one-shot pulse signal having a predetermined pulse width in response to the output of the delay circuit 991a, and a predetermined pulse width in response to the output of the delay circuit 991b. And a one-shot pulse generation circuit 992c for generating a one-shot pulse signal having a predetermined pulse width in response to the output of delay circuit 991c. Clock signals φ1 and / φ1 are generated from one-shot pulse generation circuit 992a.

The outputs of one-shot pulse generation circuit 992b and one-shot pulse generation circuit 992c are OR circuit 9
93. The clock signal φ from the OR circuit 993
2 is generated. The delay time of delay circuit 991b is shorter than the delay time of delay circuit 991c. The enable / disable of one-shot pulse generation circuits 992a to 992c is set by 2-bit command data WR0. When 2-bit command data WR0 indicates the latch mode, one-shot pulse generation circuit 99
2a and 992c are enabled, and one-shot pulse generation circuit 992b is disabled. Next, the operation of the command register and data output circuit shown in FIGS. 58 to 61 will be described.

First, description will be made with reference to the operation waveform diagram of the latch operation shown in FIG. The setting of the latch output mode in the data output mode is performed by setting the lower two bits of the command data register WR0 to (01). At this time, one-shot pulse generation circuits 992a and 992a
2c is enabled. Now, it is assumed that output enable signal G # is in an active state "L" indicating data output. At this time, external address An is taken into the address buffer at the rising edge of clock K, the corresponding SRAM word line SWLn is selected, and data RDn appears on SRAM bit line pair SBL. At this time, the one-shot pulse generation circuit 992a outputs the external clock K
In response to the rising edge of the signal, a one-shot pulse is generated at a predetermined timing, and is set to "L" for a predetermined period. When the clock signal φ1 falls to "L", the latch operation of the output latch 981 is prohibited. At this time, the clock signal φ2 is at “H” and maintains the latch state.
The data Qn-1 read in the previous cycle is latched and output. 64 selected by this external address
Four bits of data RDn on SRAM bit line pair SBL of bits selected in accordance with an external address are transmitted to internal output data buses DB and * DB. The clock signal φ1 rises to "H" in a state where the data DBn on the data buses DB and * DB are determined. As a result, the output latch 981 performs a latch operation, and latches the determined data DBn.

Subsequently, one-shot pulse generation circuit 99
A one-shot pulse is generated from 2c, and signal φ2 falls to "L". As a result, output latch 982 newly fetches the latched data DBn, and output terminal D
The signal is transmitted to Q via the output buffer 983. The generation of clock signal φ2 is performed in synchronization with the falling of clock K, and the data selected in this cycle is output as output data Qn in response to the falling of external clock K. The clock signal φ2 rises to “H” before the next rise of the external clock K. Thereby, output latch 982 is connected to internal output data bus DB, *
The fixed data DBn is continuously output irrespective of the data of the DB.

Then, the clock signal φ1 falls to "L" to release the latch state of the output latch 981, and prepares for the next cycle, ie, the operation of latching the next fixed data. Thus, data read in the previous cycle is sequentially output as fixed data in response to the rising of external clock K.

Next, the register mode will be described with reference to FIG. The setting of the register mode is performed by setting the lower two bits of the command data WR0 to (11). In this register output mode, one-shot pulse generation circuit 992b is enabled and one-shot pulse generation circuit 992c is disabled. In this case, one-shot pulse generation circuit 992b responds to the rising of external clock K.
, A one-shot pulse falling to "L" is generated. At this time, since clock signal φ1 is at “H”, output latch 982 latches data DBn−1 read in the previous cycle.

In the register output mode, the falling timing of clock signal φ2 to "L" is controlled by external clock K.
Is determined in response to the rise of In this case, in response to the (n + 1) th cycle of the external clock K, the read data DBn in the nth clock cycle is output to the output pin terminal DQ as the output data Qn. Therefore, in the latch output mode and the register output mode, the generation timing of clock signal φ2, that is, “L”
The only difference is the timing of the transition to. Thus, a latch output mode in which data of the cycle before the cycle is output and subsequently data read in the current cycle is output, and a register output in which the read data in the nth cycle is output in the (n + 1) th cycle Mode is realized.

Next, the transparent mode will be described with reference to FIG. 64 and FIG. First, the first transparent output mode will be described with reference to FIG. This transparent output mode is performed by setting the lower two bits of the register WR0 to X0 as described above. The first transparent output mode and the second transparent output mode are selected by setting the bit value of X to 0 or 1. At this time, which of the first transparent output mode and the second transparent output mode is selected by which value is arbitrary.
In the first transparent output mode, clock signals φ1 and φ2 both remain “L”.
At this time, the output latch 981 is released from the latch operation, and the output latch 982 is also in the through state. Therefore, in this case, output data Qn is DBn transmitted on internal data buses DB and * DB.
Is output as it is. That is, when the data of the SRAM bit line pair SBL or the global I / O line pair GIO is invalid data (INVALID DATA), the invalid data INV is also applied to the output pin DQ in response to this.
Appears.

In the second transparent output mode shown in FIG. 65, clock signal φ1 is generated.
First output latch 98 while clock signal φ1 is "H"
1 performs a latch operation, so that SRAM bit line pair SB
Even if the data RDn of L becomes invalid, the data bus D
Since the valid data is latched by the latch circuit 981 for the data of B and * DB and output for a predetermined period (while the clock signal φ1 is “H”), the period during which the invalid data INV is output is reduced. Also in the second transparent output mode, the clock signal φ2 remains “L”.

In the above configuration, a D-type flip-flop of the down-edge trigger type is used as the second output latch 982. However, if the polarity of the clock signal φ2 is changed, a latch circuit of the up-edge trigger type may be used. Similar effects can be obtained. Further, the configuration of the output latch 981 can also be realized by using another latch circuit.

The features of the output mode set by this command register are summarized as follows.

(1) Transparent output mode:
In this mode, data on the internal data buses DB and * DB is transmitted directly to the output buffer. In this mode, output data DQ (Q) is applied to external clock K
After the elapse of time tKHA from the rising edge of the output enable signal G # or the time tKHA from the falling edge of the output enable signal G #.
Valid data appears later after GLA. Time t
When the output enable signal G # falls before the KHA, invalid data (inv) is output until time tKHA. This is because if the fall timing of the output enable signal G # is fast, the internal data buses DB and * DB
Is because no valid data appears. Therefore, in this mode, the period during which the output data is valid is limited to the period during which the valid data appears on the internal bus.

(2) Latch output mode: In this mode, an output latch circuit is provided between the internal data buses DB and * DB and the output buffer. In this latch output mode, while the external clock K is "H", data is latched by the output latch circuit.
That is, when the output enable signal G # falls before the HA, the read data of the previous cycle is output. Therefore, even during a period in which invalid data appears on the internal data buses DB and * DB, no invalid data is output to the outside. That is, it is possible to obtain an effect that a sufficient period for the CPU to capture the output data can be obtained.

(3) Register output mode: In this mode, an output register is provided between the internal data bus and the output buffer. In this register output mode, the output data is a time tGL after the elapse of time tKHAR from the rising edge of external clock K or a time tGL from the falling edge of output enable signal G #.
The valid data in the previous cycle is output later after the lapse of A. In this register mode, invalid data is not output for the same reason as in the latch mode.
When data is continuously output in this register mode, it appears that data is being output at a very high speed from the rising edge of the external clock K. Such an operation is generally called a pipeline operation, and can be further reduced from the apparent access time cycle time.

The output mode as described above can be set by the command register, so that the user can select an output mode according to the system.

Although the function of the remaining command registers is not specified, it can be applied to any use. Next, a state transition of the CDRAM will be described with reference to a state transition diagram.

FIG. 66 is a diagram showing a state transition of the CDRAM at the time of a cache miss (miss hit). FIG. 66 (A)
FIG. 66 shows a state transition flow, and FIG. 66 (B) shows a state transition between cycles. In FIG. 66, each cycle is indicated by a cycle number.

Referring to FIG. 66, when a cache miss occurs, first, a copy back cycle (cycle No. 3) shown in FIG. 41 is performed. With this, from SRAM to D
The data transfer mode to the RAM is set. Then Figure 4
Array access cycle shown in No. 5 (cycle No. 7)
Is repeated n (n = (ta / tk) -1) times. Here, ta is the cycle time of the DRAM, and tk is the cycle time of the external clock K. This cycle No. By repeating Step 7 n times, the batch transfer of the data blocks from the SRAM to the DRAM is completed. Next, a block transfer cycle (cycle No. 4) shown in FIG. 42 is performed. Thereby, a data transfer mode from the DRAM to the SRAM is set. This cycle No. Following the cycle No. 4 7 by repeating n times
The transfer of the data block to the RAM is performed. Thereafter, the DRAM is brought into a state where it can receive the next access. This state is called a block transfer mode,
U can then access both SRAM and DRAM.

Cycle No. Subsequently to the array active cycle (cycle No. 7), n ′ (n ′ = (ta)
/ 2 · tK) -1) times, the DRAM still has a restore operation to its memory cells and a RAS
Precharge has not been completed and the next access cannot be received. However, in the SRAM, the block data has already been transferred from the DRAM in this state, there is no need to restore anything, and the data on the SRAM bit line pair is in a defined state, and the CPU accesses the SRAM in this state. I can do it. This state is called a cache fill state. In this cache fill state, the CPU can access only the SRAM. The cache hit write cycle (cycle No. 1) shown in FIG. 37 or the cache hit read cycle (cycle No. 2) shown in FIGS. 38 to 40 is performed after this cache fill. Here, this cache hit read cycle (cycle No. 2) may be any of the transparent output mode, the latch output mode, and the register output mode. Hit write can be performed continuously for each clock cycle, and hit read cycle can be continuously performed for each clock cycle. Also, the transition from the hit read cycle to the hit write cycle can be made.

FIG. 67 is a diagram showing a state transition at the time of array access. FIG. 67A shows a state transition flow in array access, and FIG. 67B shows a state transition diagram between cycles. The array access includes an array write for writing data to the array and an array read for reading data from the array. In the array write, first, an array write cycle shown in FIG.
5) is performed. This cycle No. After cycle No. 5, cycle no. Data can be written into the DRAM array by repeating the 7 array active cycles n times.

At the time of array read, an array read cycle (cycle No. 6) shown in FIG. 44 is performed.
The DRAM is made accessible. This cycle No.
After performing the array read cycle of No. 6, the array active cycle (cycle No. 7) shown in FIG.
Repeat several times. In this state, data cannot be read from the DRAM yet. This cycle No. 7, the array active cycle (cycle No. 7Q) for data output shown in FIGS. 46 to 48 is repeated n '+ 1 times. Here, the cycle No. 7Q may be any of an array active cycle for a transparent output, an array active cycle with a latch output, and an array active cycle with a register output. This cycle No. Data can be read from the array by setting output enable signal G # to "L" in the last cycle in 7Q.
In this array write and array read, the cycle time appears to be different at first glance, but n =
n ′ + 1, and data can be read / written to / from the array in the same clock cycle. After performing the array write operation or array read operation, array write or array read can be performed again subsequently.

FIG. 68 shows a state transition at the time of refresh. FIG. 68A shows a flow of state transition at the time of refreshing, and FIG. 68B shows a state transition between cycles at the time of refreshing.

In normal refresh in which only DRAM auto-refresh is performed and access to SRAM is not performed, first, a refresh cycle (cycle No. 8) shown in FIG. 52 is performed. Following this, the array active cycle shown in FIG.
7) is repeated n times. This completes one auto-refresh according to the refresh address from the refresh counter built in the CDRAM.

At the time of refresh with hit write, a refresh cycle with cache hit write (cycle No. 8W) shown in FIG. 53 is first performed. Subsequently, the DRAM is automatically refreshed for n clock cycles. During this time, the CPU can execute the cache hit write cycle shown in FIG. 37 n times.

In a refresh cycle involving a hit read, a refresh cycle involving a cache hit read shown in FIGS. 54 to 56 (cycle No. 8R)
Is performed. Thereby, the auto-refresh of the DRAM is started, and the auto-refresh is performed in the DRAM for n clock cycles. The CPU can perform a hit read for n clock cycles.
Here, the cycle No. The output mode of the 8R may be any of a transparent output mode, a latch output mode, and a register output mode.

The structure and operation of the CDRAM according to the present invention have been described in various ways.
The configuration of the DRAM is not limited to that of the above-described embodiment, and its capacity is a 4 Mbit CDRAM, that is, a 4 Mbit DRAM.
The configuration is not limited to a RAM and a 16K-bit SRAM, and a DRAM and an SRAM having an arbitrary storage capacity may be used. Also, in the array layout, the same effect as in the above embodiment can be obtained even if the array layout is modified according to the shape of the package.

Finally, data transfer is performed between the DRAM array and the S
Still another embodiment of a method for performing communication with a RAM array will be described.

FIGS. 69 (A) to 71 (B) are schematic diagrams showing copy back and block transfer operations performed at the time of a cache miss described above. First, normal copyback and block transfer operations will be described.

Referring to FIG. 69A, a case is considered where data D2 requested by the CPU for access is not stored in the corresponding position in the SRAM. Data D1 'is stored in the corresponding position of the SRAM, that is, the cache. When a cache miss to this SRAM occurs, the DR
AM is in a precharge state.

In FIG. 69B, in response to a cache miss instruction signal, a word line (indicated by hatching in the figure) including an area where data D1 'is to be stored is selected in the DRAM. This state is an array active state. In the SRAM, the area of the data D1 'is selected.

Referring to FIG. 70A, transfer instruction signal φT
SD is generated, and SRAM data D1 'is transmitted to a corresponding region of a selected word line of the DRAM.
As a result, the data D1 'is stored in the data area D1 of the DRAM.

In FIG. 70 (B), after the transfer of data D 'to data area D1 of the DRAM is completed, the DRAM array returns to the precharge state.

In FIG. 71A, a word line (indicated by hatching in the figure) containing data D2 requested by the CPU to access is selected in the DRAM.

In FIG. 71B, data D2 included in the selected word line is supplied with data transfer instruction signal φT.
The signal is transmitted to the corresponding area of the SRAM array in response to DS. As a result, the data D1 of the SRAM array becomes the data D
2 will be rewritten. FIGS. 69 (A) to 70 (B) show the copy back, and FIGS. 70 (B) to 71 (B) show the block transfer mode. The reason why the step of FIG. 70B is included in both cycles is that if both are performed subsequently, the precharge period of the DRAM is considered to be included in both.

In the case of this data transfer method, the precharge period of the DRAM array is interposed, and data transfer is always in one direction. Therefore, the SR
Data cannot be transferred between the AM array and the DRAM array. In this case, FIGS. 7, 8 and 11
The data transfer between the two-way transfer DRAM array and the SRAM array as shown in FIG. This data transfer is performed even faster,
The data transfer operation of the semiconductor memory device that satisfies the demand for high-speed operation will be described below.

FIG. 72 is a block diagram showing a circuit configuration for performing bidirectional data transfer according to an embodiment of the present invention. In FIG. 72, a bidirectional transfer gate circuit responds to a transfer control signal φTSL to generate an SRAM bit line pair SB.
L, * SBL to the latch circuit 1811, and the latch data of the latch circuit 1811 in response to the transfer control signal φTLD to the global I / O line GI
A gate 1812 connecting to O, * GIO and a gate 18 connecting the output of the latch 1811 to the global I / O lines GIO, * GIO in response to the DRAM write enable signal AWDE and the SRAM column decoder output SAY.
13 inclusive. Here, SRAM column decoder output SAY
Writes data to one of the 16 bits simultaneously selected in the DRAM array. Therefore SRAM
As the column decoder output SAY, a configuration in the case where a column address in the DRAM is commonly applied to the SRAM column decoder is shown.

The bidirectional data transfer circuit is further turned on in response to the transfer control signal φTDS,
/ O line GIO, * GIO to gate 1816 connecting to amplifier 1815, and output of amplifier 1815 in response to transfer control signal φTDS to SRAM bit line pair SBL, * SB
L includes a gate 1814 that communicates to L. This bidirectional data transfer circuit, when writing data to a DRAM array,
It has a gate 1813 for transmitting directly to the global I / O lines GIO, * GIO without passing through the bit line pairs SBL, * SBL of the RAM. This enables high speed DRAM
Data can be transmitted to the array. Gate 181
2 are 64 bits (4M) selected simultaneously between the SRAM array and the DRAM in response to the transfer control signal φTLD.
(In the case of a CDRAM).

FIG. 73 shows an example of a specific configuration of the bidirectional data transfer circuit shown in FIG. 72. In FIG. 71, a gate 1810 includes a pair of transistors T100 and T10 which are turned on in response to a transfer control signal φTSL.
Including 1. Gate 1810 (transistors T100, T100
101) are SRAM bit lines SBL and * SBL, respectively.
Transistors T102b and T1 that amplify the data of
02a. Transistors T102a, T10
2b inverts and amplifies data on the bit lines * SBL and SBL and transmits them.

The latch 1811 is connected to the inverter 1830a
And 1830b. The latch data of the latch 1811 is stored in the inverter circuit 1
Gates 1812a, 822a and 1822b,
1812b and 1812a, 1813b. Gate 812 is turned on in response to control signal φTLD, and transistor T103a transmitting the output of inverter circuit 1822a to global I / O line * GIO
including. The gate circuit 1812b receives the transfer control signal φTL
And a transistor T103b which is turned on in response to D.

Transistor T103b transmits the output of inverter circuit 1822b to global I / O line GIO in response to transfer control signal φTLD.

Gate 1813 includes gates 1813a and 1813b. The gate circuit 1813a has a DRA
It includes a transistor T104a that is turned on in response to the M write enable signal AWDE and a transistor T105b that is turned on in response to the SRAM column decoder output SAY. The gate circuit 1813a sets the control signal AWDE and the record signal SAY to both "H".
, The output of the inverter circuit 1822a is transmitted to the global I / O line * GIO. Gate circuit 1813
b denotes a transistor T105b which is turned on in response to an SRAM column decoder output SAY output;
A transistor T104b that is turned on in response to the write enable signal AWDE is included. Gate circuit 1813
b transmits the output of the inverter circuit 1822b to the global I / O line GIO when both the decoder output SAY and the write enable signal AWDE are activated.

The gate 1816 is connected to the gate circuit 1816a.
And 1816b. Gate circuit 1816a includes a transistor T106a which is turned on in response to transfer control signal φTDS. The transistor T106a is connected to the global I / O via the inverting amplification transistor 1821a.
Connected to line * GIO and to amplifier 1815. Gate circuit 1816b includes a transistor T106b which is turned on in response to transfer control signal φTDS. Transistor T106b is connected to global I / O line GIO via inverting amplification transistor 821b.

Amplifier 1815 includes p-channel MOS transistors TM11 and TM10 and TM20 and TM21. Transistor TM11 and transistor TM10
Are connected in parallel with each other. Transistor TM20 and transistor TM21 are connected in parallel with each other. Transistor TM11 has a transfer control signal φTDS at its gate.
Receive. Transistor TM10 receives at its gate the output of transistor T106b (gate circuit 1816b). Transistor TM20 receives at its gate the output of transistor T106a (gate circuit 1816a). Transistor TM21 receives transfer control signal φTDS at its gate. Transistors TM10, TM11,
TM20 and TM21 are at power supply potential V when turned on.
Transmit cc.

Gate 1814 includes gate circuits 1814a and 1814b. Gate circuit 1814a includes a transistor T107a that is turned on in response to transfer control signal φTDS. The transistor T107a is the amplifier 1
The output of 815 is transmitted to SRAM bit line SBL. Gate circuit 1814b is turned on in response to transfer signal φTDS and outputs the output of amplifier 1815 to the SRAM bit line *.
Includes transistor T107b for transmitting to SBL. The operation of the bidirectional data transfer circuit shown in FIGS. 72 and 73 will now be described with reference to the operation waveform diagrams of FIGS. 74 and 75.

First, the data transfer operation from the DRAM array to the SRAM array will be described with reference to FIG. In this case, an array active cycle is performed according to array access (cache inhibit) signal CI, and D
Selection of a word line DWL in a RAM array, detection and amplification of memory cell data connected to the selected word line DWL, selection of a column selection line CSL, transmission of data to a local I / O line, and then localization by a block selection signal φBA. The connection between the I / O line and the global G / O line is made.

On the other hand, in the SRAM array, the SRAM
The word line SWL is selected, and the selected word line SWL is selected.
The memory cell connected to WL is an SRAM bit line pair SB
L. At time t7, global I / O
When the data on line GIO and SRAM bit line pair SBL is determined, data transfer control signal φTDS is generated.
At this time, control signals φTLD and φTSL both maintain “L”.

When control signal φTDS attains "H", gate circuits 1814a and 1814b are turned on, and gate circuits 1816a and 1816b are turned on. Thus, after the data on global I / O line GIO is inverted by transistor 1821b, gate circuit 181
SRAM bit line * SB via 6b and 1814b
L. On the other hand, the data on global I / O line * GIO is transmitted to SRAM bit line SBL via gate circuits 1816a and 1814a after being inverted by transistor 1821a.

After the completion of this data transfer, DR at time t9
The AM array enters the equalize / precharge state and shifts to the standby state, while the SRAM array shifts to the precharge / equalize state at time ts2. The data transfer timing shown in FIG. 74 is almost the same as that shown in FIG. At this time, the transfer control signal φT
LD and φTSL correspond to transfer control signal φTSD.

Referring to FIG. 75, the operation of transferring data from the SRAM to the DRAM array will be described. in this case,
Operations substantially similar to the data transfer operation shown in FIG. 6 are performed, however, since control signals φTSD and φTSL are generated, the data transfer at this time is slightly different. In the data transfer shown in FIG. , The potential of the selected word line SWL rises to “H” and the SRAM
After the data of bit line pair SBL is determined, transfer control signal φTSL is first generated. This transfer control signal φTSL
, The gate 1810 is turned on, the data of the SRAM bit lines SBL and * SBL from the transistors T102a and T102b are inverted, and the latch 181 is turned on.
1 is transmitted. Thus, the latch data in the latch 1811 corresponds to the selected memory cell of the SRAM.

Next, at time t7, data transfer control signal φTSD shown in FIG.
Is generated at substantially the same timing as. As a result, the gate 1812 is turned on, and the data latched by the latch 1811 is transferred to the inverter circuits 1822a and 1822.
After being inverted at 22b, it is transmitted onto global I / O lines * GIO and GIO. This global I / O line GI
The data of O and * GIO is transmitted onto DRAM bit line pair DBL via local I / O line LIO. This completes the data transfer from the SRAM array to the DRAM array.

When data is directly written to the DRAM array, data transfer control signals φTLD, φTDS, and φ
No TSL is generated and gate circuits 1813a and 1813a
At 13b, data is written through the gate circuit selected by the SRAM column decoder output SAY.

As shown in FIGS. 72 and 73, if a structure is provided in which a latch 1811 and an amplifier 1815 are provided and data transfer is performed through separate paths, DR
It is also possible to perform data transfer between the AM array and the SRAM array at a higher speed. Next, such an operation mode will be described.

FIGS. 76 and 77 are signal waveform diagrams showing the data transfer operation in the high-speed copy back mode.
Here, the "high-speed copy back" mode includes both a copy back mode in which data is transferred from the SRAM array to the DRAM array and a block transfer mode in which block transfer is performed from the DRAM array to the SRAM array.
First, the data transfer operation from the DRAM to the SRAM will be described with reference to FIG.

In this operation mode, at time ts1
When the selected memory cell data is determined in the SRAM array, a transfer control signal φTSL is generated. As a result, data from the SRAM bit line pair SBL is latched by the latch 1811 via the gate 1810.

On the other hand, selection of DRAM word line DWL and DR performed in parallel in the DRAM array are performed.
An operation of selecting AM column selection line CSL is performed. Latch 1
At time t7 after the completion of the data latch in 811, data transfer control signal φTDS is generated. As a result, the gates 1814 and 1816 are turned on, and the global I / O line GI
The data of O, * GIO is transmitted onto SRAM bit line pair SBL. In the latch 1811, data to be transferred from the SRAM to the DRAM array has already been latched. As shown in FIG. 76, by providing a latch 1811 and an amplifier 1815 in separate systems,
DRA in parallel with transfer of data from array to latch
Data can be transferred from the M array to the SRAM array.

The timing at which transfer control signal φTSL is generated may be any time after time ts1. The transfer control signal φTDS may be generated at a timing when the latch operation in the latch 1811 is completed and the data on the global I / O line GIO is determined. With this configuration, the data in the SRAM can be read immediately after the control signal φTDS is generated and the data on the SRAM bit line pair SBL is determined, and the SRAM array can be accessed at a higher speed.

Next, the data latched by latch 1811 is transferred to the DRAM array.

In FIG. 77, after data transfer to the SRAM array is completed, a word line selecting operation is performed according to another DRAM address. At time t7, when the data on global I / O line pair GIO is determined, data transfer control signal φTLD is generated, gate 1812 is turned on, and the data latched by latch 1811 is transmitted to global I / O line pair GIO. You. This Global I
Data transmitted to / O line pair GIO is transmitted to DRAM bit line pair DBL via local I / O line pair LIO.

The SRAM array shown in FIG.
In transferring data to the array, the data latched by latch 1811 is merely transmitted to the DRAM array. Therefore, in this case, the SRAM array can be accessed in parallel with the data transfer from the SRAM array to the DRAM array, and a higher-speed semiconductor memory device can be obtained. The operation in the high-speed copy back mode shown in FIGS. 76 and 77 is schematically shown in FIGS. Hereinafter, this high-speed copy back mode will be described more specifically with reference to FIGS.

It is assumed that data D1 'is stored in the area accessed to the SRAM array and data D2 requested to be accessed is not stored. In this case, access is made to the SRAM array, and DR
AM is in a precharge state in a standby state (FIG. 7)
8 (A)).

When such a cache miss occurs,
First, in the SRAM, data D1 'is transferred to the latch. In parallel with the data transfer operation to this latch, D
In the RAM, a word line (hatched portion) including data DRAM 2 is selected (FIG. 78).
(B)).

Next, data D2 included in the selected word line of this DRAM is transmitted via an amplifier to the area of SRAM where data D1 'was stored earlier. At this time, the data D1 'is latched in the latch (FIG. 7).
9 (A)).

After data transfer from DRAM to SRAM, D
The RAM temporarily shifts to the precharge state to select the word line including the data D1 again. Data D1 is S
This is the area where the data D1 'stored in the RAM should be stored (FIG. 79 (B)).

After the precharge is completed in the DRAM, a word line (hatched area) including data D1 is selected (FIG. 80 (A)).

Next, the data D latched in the data area D1 included in the selected word line of the DRAM
1 'is transferred. As a result, the data D1 in the DRAM
Is rewritten with the data D1 '(FIG. 80 (B)).

Here, the external address is given in the SRAM
Is the same as in the previous cache miss,
In M, the address is first from the CPU and then from the tag memory.

Comparing the high-speed copy back mode shown in FIGS. 78 to 80 with the data transfer operation shown in FIGS. 69 to 71, the DRAM requires one precharge period during high-speed copying. And data can be transferred between the SRAM and the DRAM at a high speed. In a cycle including the conventional copy back and block transfer modes, the SRAM can be accessed only after the block transfer has been performed.
The data transfer to the RAM is performed, and the block transfer is performed first, so that the SRAM can be directly accessed, and a semiconductor memory device with a cache that operates at higher speed can be obtained.

In the high-speed copy back mode, data transfer between the SRAM array and the DRAM array at the time of a cache miss in a semiconductor memory device with a built-in cache is shown as an example. Similarly, when data is transferred between two memory cell arrays, data can be exchanged at a high speed, and the data transfer efficiency can be greatly improved.

This high-speed copy-back mode shows an example of data transfer between the SRAM array and the DRAM array at the time of a cache miss in a semiconductor memory device with a built-in cache. Even when data is mutually transferred between two memory cell arrays such as an array and a DRAM array, data can be exchanged at a high speed, and the data transfer efficiency can be greatly improved.

[0351]

As described above, according to the present invention, the data output mode can be selected, and the data output timing can be changed according to each data output mode. A highly versatile semiconductor memory device capable of obtaining an output can be obtained.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a memory array of a semiconductor memory device with a built-in cache according to an embodiment of the present invention.

FIG. 2 is a diagram showing a detailed configuration of a portion related to one memory block of the semiconductor memory device shown in FIG. 1;

FIG. 3 is a diagram illustrating an example of a configuration of a bidirectional transfer gate illustrated in FIG. 2;

FIG. 4 is a DRAM in the semiconductor memory device shown in FIG.
FIG. 4 is a signal waveform diagram showing an operation of transferring data from an array to an SRAM.

FIG. 5 is a DRAM in the semiconductor memory device shown in FIG. 1;
FIG. 9 is a signal waveform diagram showing an operation of transferring data from the array to the SRAM array and an operation of accessing the SRAM after the data transfer.

FIG. 6 is an SRAM in the semiconductor memory device shown in FIG.
FIG. 4 is a signal waveform diagram showing an operation of transferring data from an array to a DRAM array.

FIG. 7 is a diagram schematically showing another configuration of the bidirectional transfer gate shown in FIG. 2;

FIG. 8 is a diagram showing a detailed configuration of a bidirectional transfer gate shown in FIG. 7;

FIG. 9 is a signal waveform diagram showing an operation of the bidirectional transfer gate shown in FIGS. 7 and 8 at the time of data transfer from the SRAM array to the DRAM array.

FIG. 10 is a signal waveform diagram showing an operation of transferring data from the DRAM array to the SRAM array in the bidirectional transfer gates shown in FIGS. 7 and 8;

11 is a diagram showing still another configuration example of the bidirectional transfer gate shown in FIG.

12 is a diagram showing still another configuration example of the bidirectional transfer gate shown in FIG.

FIG. 13 is a diagram schematically showing an application example of the bidirectional transfer gate shown in FIGS. 7 to 12 to another configuration.

FIG. 14 is a diagram showing an entire configuration of a semiconductor memory device with a built-in cache according to another embodiment of the present invention.

15 is a diagram showing an arrangement of global I / O lines and local I / O lines in the semiconductor memory device shown in FIG.

FIG. 16 is a diagram showing a cross-sectional structure of a memory cell transistor portion included in a DRAM cell.

FIG. 17 is a diagram showing a relationship between a polysilicon word line lined with aluminum and a word line shunt region.

FIG. 18 is a plan view showing a layout of global I / O lines, column select lines and DRAM word lines in a semiconductor memory device according to the present invention.

19 is a diagram showing a configuration of one block of the SRAM array shown in FIG.

20 is a diagram illustrating an example of a pin arrangement of a package accommodating the semiconductor memory device illustrated in FIG. 14;

21 is a block diagram functionally showing the overall configuration of the semiconductor memory device shown in FIG.

FIG. 22 is a diagram illustrating a configuration example of a memory array unit of the semiconductor memory device illustrated in FIG. 21;

FIG. 23 illustrates a semiconductor memory device according to the present invention;
FIG. 4 is a diagram showing an example of a connection relationship between an internal data line for enabling an array access to a RAM array and a DRAM array.

FIG. 24 shows a diagram of a semiconductor memory device according to the present invention;
FIG. 3 is a diagram showing an example of a configuration of a data input / output circuit unit for realizing a / Q separation mode and a masked write mode.

FIG. 25 is a diagram illustrating another configuration example of the data input / output circuit unit illustrated in FIG. 24;

26 is a diagram showing still another configuration example of the data input / output circuit unit shown in FIG.

FIG. 27 shows D in the semiconductor memory device according to the present invention.
FIG. 4 is a diagram illustrating a correspondence between a RAM address and an SRAM address.

FIG. 28 is a diagram showing a correspondence relationship between a column address of a DRAM and a column address of an SRAM.

FIG. 29 shows an SR in the semiconductor memory device shown in FIG. 14;
FIG. 3 is a diagram showing a connection relationship between an AM bit line pair and an internal data line.

30 is a diagram specifically showing an input / output relationship of signals of the transfer gate control circuit shown in FIG. 21.

FIG. 31 is a block diagram schematically showing a configuration of a DRAM array drive circuit shown in FIG. 21.

FIG. 32 is a table showing a list of operation modes that can be implemented by the semiconductor memory device with a built-in cache according to the present invention and timing conditions of control signals for setting the operation modes.

FIG. 33 is a diagram showing a list of the contents of the command register shown in FIG. 21 and signal conditions for setting the mode of the command register;

FIG. 34 is a diagram exemplifying a correspondence relationship between a selected command register and a special mode selected at that time.

FIG. 35 is a block diagram of a system configuration when a cache system is configured by a direct mapping method using the semiconductor memory device according to the present invention.

FIG. 36 shows an example of using the semiconductor memory device according to the present invention.
It is a block diagram which shows the system structure at the time of comprising a cache system by the mapping system of a way set associative system.

FIG. 37 is a signal waveform diagram representing a timing of a control signal in a cache hit write cycle of the semiconductor memory device according to the present invention.

FIG. 38 is a signal waveform diagram representing the timing of each external signal for performing a cache hit read cycle in the transparent output mode of the semiconductor memory device according to the present invention.

FIG. 39 is a signal waveform diagram showing the timing of each external signal when the semiconductor memory device according to the present invention is operated in a cache hit read cycle in the latch output mode.

FIG. 40 is a signal waveform diagram representing the timing of various external signals for operating the semiconductor memory device according to the present invention in a cache hit read cycle in the register output mode.

FIG. 41 is a signal waveform diagram representing the timing of various external signals for operating the semiconductor memory device according to the present invention in a copy back cycle.

FIG. 42 is a signal waveform diagram representing the timing of various external signals for operating the semiconductor memory device according to the present invention in a block transfer cycle.

FIG. 43 is a waveform chart showing a timing of each external signal for setting an array write cycle of the semiconductor memory device according to the present invention.

FIG. 44 is a waveform chart showing the timing of each external control signal when an array read cycle is set in the semiconductor memory device according to the present invention.

FIG. 45 is a waveform chart showing the timing of each external control signal for operating the semiconductor memory device according to the present invention in an array active cycle.

FIG. 46 is a signal waveform diagram representing the timing of various external signals for operating the semiconductor memory device according to the present invention in an array active cycle in a transparent output mode.

FIG. 47 is a waveform chart showing the timing of each external signal for operating the semiconductor memory device according to the present invention in an array active cycle with a latch output mode.

FIG. 48 is a waveform chart showing the timing of each external signal for operating the semiconductor memory device according to the present invention in an array active cycle with a latch output mode.

FIG. 49 is a waveform chart showing the timing of each external signal for operating the semiconductor memory device according to the present invention in an array read cycle in a transparent output mode.

FIG. 50 is a waveform chart showing timings of various external signals for operating the semiconductor memory device according to the present invention in an array read cycle in a latch output mode.

FIG. 51 is a waveform chart showing the timing of each external signal for operating the semiconductor memory device according to the present invention in an array read cycle in the register output mode.

FIG. 52 is a waveform chart representing the timing of each external signal for causing a refresh cycle of the semiconductor memory device according to the present invention to be performed.

FIG. 53 is a waveform chart showing the timing of each external signal for causing the semiconductor memory device according to the present invention to perform a refresh cycle together with a cache hit write.

FIG. 54 is a waveform chart showing timing of each external signal for executing a refresh cycle together with a cache hit read in the transparent output mode of the semiconductor memory device according to the present invention.

FIG. 55 is a waveform chart showing the timing of each external signal for causing the semiconductor memory device according to the present invention to perform a refresh cycle together with a cache hit read in the latch output mode.

FIG. 56 is a waveform chart showing the timing of each external signal for causing the semiconductor memory device according to the present invention to perform a refresh cycle together with a cache hit read in the register output mode.

FIG. 57 is a waveform chart showing the timing of each external signal for setting the command register of the semiconductor memory device according to the present invention.

FIG. 58 is a diagram showing a circuit configuration for setting a data output mode of a semiconductor memory device by a command register.

FIG. 59 illustrates an example of a configuration of the data output circuit illustrated in FIG. 58;

FIG. 60 illustrates an example of a configuration of a second output latch illustrated in FIG. 59;

61 is a diagram illustrating an example of a configuration of the output control circuit illustrated in FIG. 58;

FIG. 62 is a signal waveform diagram representing an operation of the circuits shown in FIGS. 58 to 61 when a latch output mode is set.

FIG. 63 is a signal waveform diagram representing an operation when register output mode is set.

FIG. 64 is a signal waveform diagram representing an operation of the circuits shown in FIGS. 58 to 61 when the first transparent mode is set.

FIG. 65 is a signal waveform diagram representing an operation of the circuits shown in FIGS. 58 to 61 when the second transparent mode is set.

FIG. 66 shows a state transition at the time of a cache miss in the semiconductor memory device according to the present invention.

FIG. 67 shows a state transition at the time of array access of the semiconductor memory device according to the present invention.

FIG. 68 shows a state transition during refresh of the semiconductor memory device according to the present invention.

FIG. 69 is a diagram showing a mutual data transfer operation between the DRAM array and the SRAM array when the bidirectional transfer gates shown in FIGS. 2, 7 and 11 are used.

FIG. 70 is a diagram showing a mutual data transfer operation between the DRAM array and the SRAM array when the bidirectional transfer gates shown in FIGS. 2, 7 and 11 are used.

FIG. 71 is a diagram showing a mutual data transfer operation between the DRAM array and the SRAM array when the bidirectional transfer gates shown in FIGS. 2, 7 and 11 are used.

FIG. 72 is a diagram showing still another example of the configuration of the bidirectional transfer gate for implementing data transfer according to the present invention.

73 is a diagram showing an example of a specific configuration of the bidirectional transfer gate shown in FIG. 72.

FIG. 74 is a signal waveform diagram representing an operation when data is transferred from a DRAM array to an SRAM array using the bidirectional transfer gates shown in FIGS. 72 and 73.

FIG. 75 is a signal waveform diagram representing an operation when data is transferred from the SRAM array to the DRAM array using the bidirectional transfer gates shown in FIGS. 72 and 73.

76. DRAM for performing high-speed copy-back operation using the bidirectional transfer gates shown in FIGS. 72 and 73
FIG. 9 is a signal waveform diagram showing an operation of transferring data from the array to the SRAM array.

FIG. 77. SRAM during high-speed copy-back operation
FIG. 4 is a signal waveform diagram showing an operation of transferring data from an array to a DRAM array.

FIG. 78 is a schematic diagram for explaining a high-speed copy back mode operation.

FIG. 79 is a schematic diagram for describing a high-speed copy back mode operation.

FIG. 80 is a schematic diagram for explaining a high-speed copy back mode operation.

FIG. 81 is a diagram showing an array configuration of a conventional 1M bit DRAM.

FIG. 82 is a diagram showing an array arrangement of a conventional semiconductor memory device with a built-in cache.

FIG. 83 is a view illustrating a specific arrangement of a conventional 1-Mbit DRAM array;

FIG. 84 is a diagram showing an array arrangement for realizing a 4-way set associative method in a conventional semiconductor memory device with a built-in cache.

[Explanation of symbols]

1 DRAM array, 2 SRAM array, 3 bidirectional transfer gate circuit, 13 DRAM sense amplifier + IO gate block, 14 DRAM row decoder, 15 DR
AM column decoder, 16a, 16b I / O line pair, 2
1 SRAM row decoder, 22 SRAM column decoder, 23 SRAM sense amplifier circuit, GIO global I / O line pair, LIO local I / O line pair, CS
L column select line, IOG I / O gate, CSG column select gate, SBL SRAM bit line pair, DBLD
RAM bit line pair, MM memory mat, 80, 90 bidirectional transfer gate, 85, 1811 latch, 86, 18
15 amplifier, 100 DRAM, 101 DRAM array, 102 DRAM row decoder, 270 command register, 272b output control circuit, 274a output circuit, 274b, 274c input circuit, 981, 982 output latch, 983 output buffer.

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Koji Hayano 4-1-1 Mizuhara, Itami-shi, Hyogo Mitsubishi Electric Corporation Inside Kita Itami Works (72) Masaki Kumanoya 4-1-1 Mizuhara, Itami-shi, Hyogo Mitsubishi Electric LSI Research Institute, Inc. (72) Inventor Akira Yamazaki 4-1-1 Mizuhara, Itami-shi, Hyogo Mitsubishi Electric LSL Research Institute Inc. (72) Inventor Hisashi Iwamoto 4-Chome, Mizuhara, Itami-shi, Hyogo No. 1 Mitsubishi Electric Corporation LSI Research Institute

Claims (1)

[Claims] 1. A semiconductor memory device including a memory cell array including a plurality of memory cells, wherein a setting for setting a data output mode of the semiconductor memory device in response to a data output mode designation signal from outside the semiconductor memory device. Means for reading data of a corresponding memory cell in the memory cell array in accordance with an address from outside the semiconductor memory device; and setting means activated in response to a data output instruction signal from outside the semiconductor memory device. And a means for outputting data read by the reading means at different timings according to the data output mode set by the semiconductor memory device.