JP3240161B2 - Semiconductor storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a clock synchronous semiconductor memory device which operates in synchronization with an externally applied clock signal. Specifically, a large-capacity dynamic random access memory (DRAM) as a main memory and a small-capacity static random access memory (SRAM) as a cache memory are integrated on the same semiconductor chip. A semiconductor memory device with a built-in cache.

[0002]

2. Description of the Related Art Recent 16-bit or 32-bit microprocessing units (MPUs) have been operating at very high operating clock frequencies of 25 MHz or more. In a data processing system, a standard DRAM (Dynamic Random Access Memory) is often used as a main memory having a large storage capacity because of a low unit cost per bit. Although the access time of the standard DRAM has been shortened, the speedup of the MPU has exceeded that of the standard DRAM. For this reason, a data processing system using a standard DRAM as a main memory must sacrifice, for example, an increase in wait states (waiting states). The problem of the gap between the operating speeds of the MPU and the standard DRAM is essential because the standard DRAM has the following features.

(1) A row address signal and a column address signal are time-division multiplexed and applied to the same address pin terminal. The row address signal is taken into the device at the falling edge of row address strobe signal / RAS. The column address signal is a column address strobe signal / CAS
Is taken into the inside of the device at the falling edge. Row address strobe signal / RAS defines the start of a memory cycle and activates a row selection system. Column address strobe signal / CAS activates a column selection system. Since a predetermined time called “RAS-CAS delay time (tRCD)” is required from the time when signal / RAS is activated to the time when signal / CAS is activated, reduction in access time is limited. There is a restriction due to address multiplexing.

(2) Row address strobe signal / R
When AS is started up and DRAM is set to the standby state, row address strobe signal / RAS
Only after a lapse of a time called an AS precharge time (tRP) can the voltage fall to "L" again. The RAS precharge time tRP is required to reliably precharge various signal lines of the DRAM to a predetermined potential. Therefore, the RAS precharge time tRP
Therefore, the cycle time of the DRAM cannot be shortened. Also, shortening the cycle time of the DRAM is
In a DRAM, the number of times of charging and discharging of a signal line increases, which leads to an increase in current consumption.

(3) The DRA is improved by improving the circuit technology and process technology such as higher integration and layout of the circuit, or by improving the application such as the driving method.
M can be accelerated. However, MPU
The progress of high speed has greatly exceeded that of DRAM. The operation of a semiconductor memory such as a high-speed bipolar RAM using bipolar transistors such as an ECLRAM (emitter-coupled RAM) and a static RAM and a relatively low-speed DRAM using a MOS transistor (insulated gate field effect transistor) Speed has a hierarchical structure. It is very difficult to expect a speed (cycle time) of several tens of nS (nanosecond) in a standard DRAM including a MOS transistor as a component.

In order to fill the speed gap (difference in operating speed) between the MPU and the standard DRAM, various improvements have been made in application. The main reasons for such improvement are (1) using a high-speed mode and an interleave scheme of a DRAM, and (2) a high-speed cache memory (SRA).
M) is provided outside.

In the case of the above method (1), there are a method using a high-speed mode such as a static column mode or a page mode, and a method combining this high-speed mode and an interleave method. The static mode is a method of sequentially accessing only one row of memory cells by selecting one word line (one row) and then sequentially changing only the column address. The page mode is a method in which after selecting one word line, the signal / CAS is toggled to sequentially fetch the column address signal and sequentially access the memory cells connected to the one word line. In any of these modes, the memory cell can be accessed without including the toggle of the signal / RAS, which is faster than the normal access using the signals / RAS and / CAS.

The interleave system is a system in which a plurality of memory devices are provided in parallel on a data bus and accesses to the plurality of memory devices are alternately or sequentially performed, thereby effectively reducing the access time. The method using the high-speed mode of the DRAM and the method of combining the high-speed mode and the interleave method are conventionally known as a method of using the standard DRAM as the high-speed DRAM simply and relatively efficiently.

The above method (2) is a method widely used in mainframes for a long time. High-speed cache memories are expensive. However, in the field of personal computers, which are required to have high performance at low cost, some of them are unavoidably used to improve the operation speed, at the expense of being somewhat expensive. Regarding where to provide the high-speed cache memory, there are the following three possibilities.

(A) Built in the MPU itself.

(B) Provide outside the MPU.

(C) Instead of providing a separate high-speed cache memory, a high-speed mode built in a standard DRAM is used like a cache (a high-speed mode pseudo cache memory). That is, a standard DRAM is accessed in a high-speed mode when a cache hit occurs, and a standard DRAM is accessed in a normal mode when a cache miss occurs.

The above three methods (a) to (c) have already been adopted in some form in data processing systems. However, from the viewpoint of price, in many MPU systems, in order to prevent the RAS precharge time (tRP) inevitable in the DRAM from appearing effectively, the memory has a bank configuration, and each memory bank has An interleaving method is used. According to this method, the cycle time of the DRAM can be substantially reduced to almost half of the specification value (specification value).

However, the interleaving method is effective only when accesses to the memory device are made sequentially. That is, no effect can be obtained when successively accessing the same memory bank. In addition, this method cannot substantially improve the access time of the DRAM itself. In addition, the minimum unit of the memory needs to be at least two banks.

When a high-speed mode such as a page mode or a static column mode is used, the access time can be effectively reduced only when the MPU continuously accesses a certain page (data of one specified row). it can. This method has a certain effect when the number of banks is relatively large, such as 2 to 4, since different rows can be accessed for each bank. The case where the data of the memory requested by the MPU does not exist in the given page is called “miss hit (cache miss)”. Typically, a chunk of data is stored at an adjacent address or a sequential address. In the high-speed mode, since a row address that is half of the address has already been specified, the probability of occurrence of a “miss hit” is high.

When the number of banks becomes as large as 30 to 40, data of different pages can be stored in each bank, so that the "miss hit" rate is drastically reduced. However, it is not practical to assume 30 to 40 banks in a data processing system. When a "miss hit" occurs, it is necessary to raise the signal / RAS in order to newly select a row address and return to the DRAM precharge cycle, thereby sacrificing the performance of the bank configuration. Become.

In the case of the above method (2), the MPU and the standard D
A high-speed cache memory is provided between the RAM and the RAM.
In this case, the standard DRAM may be relatively slow. On the other hand, the standard DRAM is 4M (mega) bits, 16M
Bits and large storage capacities are emerging. In a small-scale system such as a personal computer, the main memory can be constituted by one or several chips of a standard DRAM. When an external high-speed cache memory is provided, the main memory is, for example, one standard D
It is not effective in a small-scale system that can be constituted by a RAM. When the standard DRAM is used as the main memory, the data transfer speed between the high-speed cache memory and the main memory is limited by the number of data input / output terminals of the standard DRAM, which is a bottleneck to the speed of the system.

In the case of the pseudo cache memory in the high-speed mode, the operation speed is slower than that of the high-speed cache memory, so that it is difficult to realize the desired system performance.

As a method of resolving the sacrifice of the system performance caused by using the above-mentioned interleave method or high-speed operation mode and constructing a relatively inexpensive and small-scale system, a high-speed cache memory (SRAM) may be replaced with a DR.
It can be built into AM. That is, DRAM
May be considered as a main memory and a one-chip memory having a hierarchical structure including an SRAM as a cache memory. Such a one-chip memory having a hierarchical structure is called a cache DRAM (CDRAM). This C
The DRAM will be described below.

FIG. 188 shows a conventional standard 1 Mbit D
FIG. 2 is a diagram illustrating a configuration of a main part of a RAM. In FIG. 188, the DRAM includes a memory cell array 500 including a plurality of memory cells MC arranged in a matrix of rows and columns. One row of memory cells is one word line W
L. One column of memory cells MC is connected to one column line C
L. This column line CL is usually composed of a pair of bit lines. One word line WL selects a memory cell located at the intersection with one of the pair of bit lines. In a 1M (mega) DRAM, memory cells MC are arranged in a matrix of 1024 rows × 1024 columns. That is, the memory cell array 500 includes 1024 word lines WL and 1024 column lines CL (1024 pairs of bit lines).

The DRAM further decodes an externally applied row address signal (not shown) to select a corresponding row of memory cell array 500.
And a sense amplifier for detecting and amplifying data of a memory cell connected to the word line selected by the row decoder 502, and decoding an externally applied column address signal (not shown) to correspond to the memory cell array 500. Including a column decoder for selecting a column. In FIG. 184, a sense amplifier and a column decoder are represented by one block 504. Here, actually, an address buffer is provided, and the address buffer receives an externally applied row address signal and a column address signal to generate an internal row address signal and a column address signal,
Each is applied to a row decoder 502 and a column decoder. Here, this address buffer is not shown.

When the DRAM has a × 1 bit configuration in which data input / output is performed in 1-bit units, one column line (one bit line pair) CL is selected by a column decoder. D
When the RAM has a × 4 bit configuration in which data is input / output in 4-bit units, four column lines CL
Is selected. One sense amplifier included in the block 504 is provided for each column line (bit line pair) CL.

At the time of memory access for writing data to or reading data from memory cell MC in the DRAM, the following operation is performed. First, a row address signal (more precisely, an internal row address signal) is applied to row decoder 502. Row decoder 502 decodes the applied row address signal, and raises the potential of one word line WL in memory cell array 500 to “H”. The data of the 1024-bit memory cell MC connected to the selected word line WL is transmitted onto the corresponding column line CL. Data on the column line CL is amplified by the sense amplifier included in the block 504. Among the memory cells connected to the selected word line WL,
Selection of a memory cell to receive data writing or reading is performed by a column selection signal from a column decoder included in block 504. The column decoder decodes a column address signal (more precisely, an internal column address signal),
A column selection signal for selecting a corresponding column in memory cell array 500 is generated.

In the high-speed mode operation described above, a column address signal is sequentially applied to the column decoder included in block 504. In the static column mode operation, the column decoder decodes a column address signal applied every predetermined time as a new column address signal, and connects a memory cell MC connected to the selected word line WL via the column line CL. select. In the page mode, a new column address signal is applied to the column decoder for each toggle of signal / CAS. The column decoder decodes the applied column address signal and selects a corresponding column line. In this way, by setting one word line WL in the selected state and changing only the column address, it is possible to access the memory cells MC in one row connected to the selected word line WL at high speed.

FIG. 189 is a diagram showing a general configuration of a conventional 1 Mbit CDRAM. In FIG. 189, the conventional CDRAM has a structure for transferring data between SRAM array 506 and one row of DRAM memory cell array 500 and SRAM array 506 in addition to the structure of the standard DRAM shown in FIG. Gate 508
including. SRAM array 506 includes a cache register provided corresponding to each column line CL of memory cell array 500 so that data of one row of DRAM memory cell array 500 can be stored simultaneously. Therefore, 1024 cache registers are provided in SRAM array 506. This cache register is usually constituted by a static memory cell (SRAM cell).

In the case of the configuration of the CDRAM shown in FIG. 189,
When a signal indicating a cache hit is provided from the outside, access to SRAM array 506 is performed, and
Access to memory cells can be performed at high speed.
When a cache miss (miss hit) occurs, the DRAM
Is accessed.

The above-mentioned large-capacity DRAM and high-speed S
A CDRAM in which a RAM and a RAM are integrated on the same chip is disclosed in, for example, JP-A-60-7690 and JP-A-62-273.
No. 8590 discloses this.

In the configuration of the conventional CDRAM as described above, the column lines (bit line pairs) CL and the SRAM (cache memory) array 5 of the DRAM memory cell array 500 are arranged.
06 column lines (bit line pairs) are connected via transfer gates 508 in a one-to-one correspondence. That is,
In the configuration of the conventional CDRAM described above, data of the memory cells connected to one word line WL in the DRAM memory cell array 500 and data of the same number of SRAM cells as one row of the memory cell array 500 are transferred via the transfer gate 508. A configuration is adopted in which bidirectional batch transfer is performed. In this configuration, the SRAM 506 is used as a cache memory, and the DRAM is used as a main memory.

The so-called block size of the cache is
In the SRAM 506, the number of bits whose contents can be rewritten in one data transfer can be considered. Therefore, this block size is equal to the number of memory cells physically coupled to one word line WL of DRAM memory cell array 500. As shown in FIGS. 188 and 189, when 1024 memory cells are physically connected to one word line WL, the block size is 1024.

Generally, when the block size is large, the hit ratio increases. However, in the case of the same cache memory size, the number of sets decreases in inverse proportion to the block size, and consequently the hit rate decreases. For example, when the cache size is 4K bits, if the block size is 1024, the number of sets is 4, but if the block size is 32, the number of sets is 128. Therefore, in the case of the configuration of the CDRAM shown in FIG. 189, there arises a problem that the block size becomes unnecessarily large and the cache hit ratio cannot be improved so much.

[0031]

An arrangement for reducing the block size is disclosed, for example, in Japanese Patent Application Laid-Open No. 1-146187. In this prior art, a DRAM array and an SRAM array are arranged in a one-to-one correspondence with column lines (bit line pairs), but each is divided into a plurality of blocks in the column direction. The selection of a block is performed by a block decoder. When a cache miss (miss hit) occurs, one block is selected by the block decoder. Data transfer is performed only between the selected DRAM block and SRAM block. According to this configuration, the block size of the cache memory can be reduced to an appropriate size, but the following problems remain as unsolved.

FIG. 190 shows a standard array configuration of a 1 Mbit DRAM array. In FIG. 190,
The DRAM array has eight memory blocks DMB1 to DMB.
It is divided into B8. Memory blocks DMB1 to DMB8
, A row decoder 502 is provided on one side in the long side direction of the memory array. Memory block DMB1
To DMB8 are provided with (sense amplifier + column decoder) blocks 504-1 to 504-8.

Each of the memory blocks DMB1 to DMB8 has a capacity of 128K bits. In FIG. 190, one memory block DMB has 128 rows × 10
The case where they are arranged in 24 columns is shown as an example. 1
Each of the column lines CL is constituted by a pair of bit lines BL and / BL.

As shown in FIG. 190, when the DRAM memory cell array is divided into a plurality of blocks, the length of one bit line BL (and / BL) becomes shorter. At the time of data reading, the charge stored in the capacitor in the memory cell (memory cell capacitor) is transmitted to the corresponding bit line BL (or / BL). At this time, the amount of potential change generated on the bit line BL (or / BL) depends on the capacitance Cs of the memory cell capacitor and the capacitance Cb of the bit line BL (or / BL).
And Cs / Cb. As the length of the bit line BL (or / BL) becomes shorter, the bit line capacitance Cb becomes smaller. Thereby, the amount of potential change generated in the bit line can be increased.

In operation, the row decoder 50
Sense operation is performed on a memory block (memory block DMB2 in FIG. 190) including word line WL selected by 2 and the standby state is maintained in the remaining blocks. As a result, it is possible to reduce the power consumption accompanying the charging and discharging of the bit line during the sensing operation.

When the above-described block-divided CDRAM is applied to the DRAM shown in FIG. 190, the SRA is applied to each of the memory blocks DMB1 to DMB8.
It is necessary to provide an M cash register and a block decoder. Therefore, there is a problem that the chip area is significantly increased.

In this configuration, only the SRAM cache register for the selected block operates,
There is also a problem that the use efficiency of the RAM cache register is poor.

As described above, the DRAM array and the SR
Bit lines correspond one-to-one with the AM array. When a direct mapping method is adopted as a memory mapping method between the main memory and the cache memory, as shown in FIG.
It consists of 1024 rows of cash registers arranged in rows. In this case, the capacity of the SRAM cache is 1K bits.

When the 4-way set associative method is adopted as the mapping method, as shown in FIG. 191, the SRAM array 506 includes four rows of cache registers 506a to 506d. One of the four cache registers 506a to 506d is selected by selector 510 according to the way address. This figure 1
In the configuration shown in FIG. 91, the capacity of the SRAM cache is 4
It becomes K bits.

As described above, the method of mapping memory cells between the DRAM array and the cache memory is determined by the internal structure of the chip. When the mapping method is changed, it is necessary to change the cache size as described above.

In any of the above-described configurations of the CDRAM, since the DRAM array and the SRAM array have one-to-one bit lines, the column address of the DRAM array and the column address of the SRAM array are inevitable. In principle, it is impossible in principle to realize a fully associative method of mapping a memory cell of a DRAM array to an arbitrary position of an SRAM array.

Another configuration of a semiconductor memory device in which a DRAM and an SRAM are integrated on the same chip is disclosed in
87392. In this prior art, a DRAM array and an SRAM array are connected via an internal common data bus. The internal common data bus is connected to an input / output buffer for inputting and outputting data to and from the outside of the device. The DRAM array and the SRAM array can each specify a selected position by separate address signals generated independently.

However, in this prior art configuration, data transfer between the DRAM array and the SRAM array is performed via an internal common data bus. The number of bits that can be transferred at one time is limited by the number of internal common data bus lines, and the contents of the cache memory cannot be rewritten at high speed. Therefore, the aforementioned S
As in the case where the RAM cache is provided outside the standard DRAM, the data transfer speed between the DRAM array and the SRAM array becomes a bottleneck, and a high-speed cache memory system cannot be constructed.

In ASICs (application specific ICs) and pipeline applications, the semiconductor memory device operates in synchronization with an external clock signal such as a system clock. The operation mode of the semiconductor memory device is determined by the state of the external control signal at the rising or falling edge of the external clock signal. The external clock signal is applied to the semiconductor memory device regardless of whether the semiconductor memory device is accessed. At this time, an input buffer or the like that receives an external control signal, an address signal, and data operates in response to the external clock signal. From a power consumption perspective,
When there is no access to the semiconductor memory device, it is preferable not to supply an external clock signal to the semiconductor memory device or to lengthen the cycle of the external clock signal.

Generally, a DRAM is supplied with a row address signal and a column address signal in a time division multiplexed manner. The acquisition of the row address signal and the column address signal into the device is performed in synchronization with the external clock signal. Therefore, when a conventional DRAM is operated in synchronization with an external clock signal, it takes a long time to fetch the row address signal and the column address signal. There is a problem that high-speed operation cannot be performed.

When a conventional semiconductor memory device is operated in synchronization with an external clock signal, its operation speed is uniquely determined by the external clock signal. At this time, the conventional clock-synchronous semiconductor memory device cannot cope with an application in which low power consumption is more important than high-speed operation at an operation speed specified by an external clock signal.

In a clock synchronous semiconductor memory device, control signals and address signals are taken in internally in synchronization with a clock signal. The control signal and the address signal are taken in by a buffer circuit. Each buffer circuit is activated in synchronization with a clock signal, and generates an internal signal corresponding to a given external signal. In a standby state or the like, a valid control signal and address signal are not supplied, but an external clock signal is continuously supplied. Therefore, each buffer circuit operates unnecessarily, which is one obstacle to reduction of current consumption during standby. In particular, as the cycle period of the external clock signal becomes shorter, the number of operations of each buffer circuit increases, and the current consumption during standby increases accordingly. This is a major obstacle to realizing low current consumption.

When the semiconductor memory device includes a dynamic memory cell (DRAM cell), the DRA
M cells need to be refreshed periodically. DRA
The M refresh mode generally includes an auto refresh mode and a self refresh mode.

FIG. 1 shows a waveform diagram during the auto refresh operation.
92. In the auto refresh mode, the chip select signal * CE is set to "H", and the external refresh instruction signal * REF is set to "L". Internal control signal int. For driving the row selection system in response to the fall of refresh instruction signal * REF from outside. * RAS falls to "L". This internal control signal int. * RAS
, A word line is selected according to the refresh address generated from the built-in address counter, and the memory cells connected to the selected word line are refreshed. Therefore, in this auto-refresh mode, the refresh timing of the semiconductor memory device is controlled by externally applied refresh instruction signal * REF.
Is determined by Therefore, whether or not the semiconductor memory device is refreshed can be known outside the memory device.

FIG. 193 shows a waveform diagram during the self-refresh operation. In the self-refresh mode, the chip select signal * CE is set to "H" and the external refresh instruction signal * REF is set to "L". When external refresh instruction signal * REF falls to "L", internal control signal int. * RAS is generated, and the word line is selected according to the refresh address from the built-in address counter. Subsequently, the sensing operation and rewriting of the memory cell connected to the selected word line are performed, and
The memory cells connected to the word line WL are refreshed.

The first cycle of the self refresh is the same as the auto refresh. When the chip select signal * CE is at "H" and the refresh instruction signal * REF is set at "L" for a predetermined time TF or longer, a built-in timer generates a refresh request signal. In response, internal control signal int. * RAS is generated to select a word line and refresh the memory cells connected to the selected word line. This operation is repeated while refresh instruction signal * REF is at "L". In the refresh operation in the self refresh, the refresh timing is determined by a timer built in the semiconductor memory device. The refresh timing cannot be known from outside. Normally, in the self-refresh mode, data cannot be accessed from outside. Therefore, self refresh is not performed in the normal mode, and the self refresh mode is generally performed to hold data in the standby mode.

Originally, the upper limit of the refresh cycle required for holding data has a difference between semiconductor chips (for example, see Nikkei Electronics, April 6, 1987, p. 170). Normally, in order to perform self-refresh, a guaranteed value of data retention is measured by a test of a semiconductor memory device, and a timer cycle for defining a self-refresh cycle is programmed in accordance with the guaranteed value. Generally, when the auto-refresh mode and the self-refresh mode are selectively used, it is necessary to measure a guaranteed value of a data retention guarantee time to determine the self-refresh cycle. As can be seen from FIG. 193, in the self-refresh mode, first, an operation similar to the auto-refresh is performed according to external refresh instruction signal * REF, and then a refresh operation by a timer is performed. Therefore, in this case, it can be said that the self-refresh cycle is a cycle in which the auto-refresh is performed accurately, and subsequently, after a predetermined time TF has elapsed. In this self-refresh cycle, the refresh timing is merely determined by the built-in timer as described above, and the refresh timing cannot be known from outside. Therefore, there is a problem that the self-refresh cycle cannot be used as a method such as hidden refresh in the normal mode.

Further, in a semiconductor memory device having a built-in DRAM array and SRAM array, it is desirable to transfer data at a high speed from the DRAM array to the SRAM array from the viewpoint of high-speed operation. From DRAM array to S
At the time of data transfer to the RAM array, selection of a row (word line) in the DRAM array, detection and amplification of data of a memory cell connected to the selected word line, and column selection are performed.

In general, a row address signal and a column address signal are multiplexed and applied to a DRAM array. Therefore, there is a limitation due to the address multiplexing in increasing the speed of data transfer from the DRAM array to the SRAM array. In this case, it is conceivable that the row address signal and the column address signal of the DRAM are simultaneously applied simply according to a non-multiplex system. However, the number of terminals for inputting DRAM addresses is greatly increased. An increase in the number of terminals is not preferable because it increases the chip size and the package size.

Data transfer from the DRAM array to the SRAM array needs to be performed after detection and amplification of the memory cell data by the sense amplifier. For this reason,
There is a problem that data transfer from the DRAM array to the SRAM array cannot be performed at high speed.

Further, some external processing units such as a CPU (central processing unit) have a data transfer mode called a burst mode for performing data transfer at a high speed. The burst mode is a mode in which a block of data blocks is continuously transferred. Data blocks are stored consecutively at adjacent address locations. Since the burst mode is a high-speed data transfer mode, in a semiconductor memory device with a built-in cache, this data block is stored in the cache memory. A semiconductor memory device with a built-in cache that can be easily connected to an external arithmetic processing device having a burst mode function has not been devised yet.

An object of the present invention is to provide a semiconductor memory device capable of performing self-refresh even in a normal mode.

Another object of the present invention is to provide a semiconductor memory device capable of performing high-speed data transfer between a DRAM array and an SRAM array.

Still another object of the present invention is to provide a clock synchronous semiconductor memory device capable of greatly reducing current consumption in a standby mode.

Still another object of the present invention is to provide a semiconductor memory device which can be accessed at a high speed even at the time of a cache miss (miss hit).

It is still another object of the present invention to provide a semiconductor memory device with a built-in cache which can be easily connected to an external processing unit having a burst mode function.

Still another object of the present invention is to provide a semiconductor memory device which does not impair high-speed operation even when the period of an external clock signal is lengthened.

Still another object of the present invention is to provide a clock synchronous semiconductor memory device which operates reliably even when the period of the external clock signal is lengthened or the external clock signal is generated intermittently. That is.

A still further object of the present invention is to provide a semiconductor memory device with a built-in cache which can operate at high speed without erroneous operation with low power consumption.

Still another object of the present invention is to provide a clock synchronous type semiconductor memory device with a built-in cache which can operate at high speed without erroneous operation with low power consumption.

Still another object of the present invention is to provide a semiconductor memory device which can easily cope with both applications where high-speed operation is important and applications where low power consumption is important.

A still further object of the present invention is to provide a semiconductor memory device with a built-in cache which can easily realize both high-speed operation and low power consumption according to the purpose of use.

Still another object of the present invention is to provide a clock-synchronous cache-incorporated semiconductor memory device which can easily realize both high-speed operation and low-power-consumption operation according to the purpose of use. is there.

[0069]

A semiconductor memory device according to claim 1 is a DRAM having dynamic memory cells.
An array, means for generating a refresh address, auto-refresh means for refreshing the DRAM array in response to an external refresh instruction,
Timer means for performing a timing operation and outputting a refresh request at predetermined intervals, self-refresh means for refreshing the DRAM array in response to a refresh request from the timer means, and setting the refresh mode to either auto-refresh or self-refresh. Mode setting means for setting one pin terminal to one of a refresh instruction input terminal and a self-refresh execution instruction output terminal in accordance with the refresh mode set by the refresh mode setting means. Means. The timer means is started when the self-refresh mode is set in the refresh mode setting means.

[0070]

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[0084]

According to the first aspect of the invention, the setting of the self-refresh mode or the auto-refresh mode is performed by the refresh mode setting means. The instruction output terminal is switched by the input / output switching means. Therefore, the refresh timing can be known outside the storage device even in the self-refresh mode,
The self-refresh mode can be used even in the normal mode.

[0085]

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[0090]

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【Example】

"Array Arrangement 1" FIG. 2 schematically shows an example of the configuration of a memory array section of a semiconductor memory device to which the present invention is applied. In FIG. 2, a semiconductor memory device includes a DRAM array 1 including dynamic memory cells arranged in a matrix composed of rows and columns, and an SRAM array composed of static memory cells arranged in a matrix composed of rows and columns. 2 and this DRAM array 1 and S
A bidirectional transfer gate circuit 3 for performing data transfer with the RAM array 2 is included.

When the storage capacity is 1 M bits, DRAM array 1 includes 1024 word lines WL and 1024 pairs of bit lines BL and / BL. However, in the figure, the bit line pair is indicated by DBL. This DRAM array 1 is divided into a plurality of blocks along the row and column directions, respectively. In FIG. 2, DRAM array 1 has eight columns in the column direction.
Blocks MBi1 to MBi8 (i = 1 to 4) and four blocks MB1j to MB4j in the row direction
(J = 1 to 8) is shown as an example in the case of being divided into a total of 32 memory blocks.

The eight blocks M divided in the column direction
Bi1 to MBi8 constitute one row block 11.
Four blocks MB1j to MB4j divided in the row direction
Constitutes the column block 12. The memory blocks MBi1 to MBi8 included in one row block 11 share one word line WL. Memory blocks MB1j to MB4j included in the same column block 12 are
Share SL. Each memory block MB11 to MB48
A sense amplifier + IO block 13 is provided for each. The configuration of this sense amplifier + IO block 13 will be described later. The column selection line CSL simultaneously selects two columns (two pairs of bit lines).

This semiconductor memory device further includes a row decoder 14 for selecting a corresponding row from DRAM array 1 in response to an externally applied address, and one column in response to an externally applied column address. Select line CS
A column decoder 15 for selecting L is included. Row block 1
2 is a pair of independent I / O lines 16a and 16b
To the bidirectional transfer gate circuit 3.

SRAM array 2 includes 16 bit line pairs SBL connected to 16 pairs of I / O lines via bidirectional transfer gate circuit 3 respectively. This SRAM array 2 includes 16 pairs of bit lines and 256 word lines in the case of a 4K-bit capacity. Therefore, this SRA
One row of the M array 2 has 16 bits. This SRAM
An SRAM which decodes an externally applied row address for the array and selects one row of this SRAM array 2
A row decoder 21, an SRAM column decoder 22 for decoding an externally applied column address and selecting a corresponding column of the SRAM array 2, and an SRAM row decoder 21 and an SRAM column decoder 22 selected at the time of data reading. The sense amplifier circuit 23 amplifies and outputs data of the memory cell.

The SRAM bit line pair SBL selected by the SRAM column decoder 22 is connected to a common data bus, and inputs / outputs data from / to the outside of the device via an input / output buffer (not shown). The addresses applied to the DRAM row decoder 14 and the DRAM column decoder 15 and the addresses applied to the SRAM row decoder 21 and the SRAM column decoder 22 are mutually independent addresses, and are applied through different address pin terminals. Next, a data transfer operation of the semiconductor memory device shown in FIG. 2 will be schematically described.

The operation of the DRAM will be described. First, the row decoder 14 performs a row selecting operation in accordance with a row address given from the outside, and raises the potential of one word line DWL to “H”. Data is read from the memory cells connected to the selected one word line DWL to the corresponding 1024 bit lines BL (or / BL).

Next, sense amplifiers (included in block 13) included in row block 11 including the selected word line DWL are simultaneously activated, and differentially amplify the potential difference between each bit line pair. The reason why only one of the four row blocks 11 is activated is to reduce the power consumption associated with the charging and discharging of the bit line during the sensing operation (the row block including the selected row). An operation method that activates only the block is referred to as a block division operation method).

Next, DRAM column decoder 15 performs a column selecting operation according to an externally applied column address. One column selection line C in each column block 12
SL is set to the selected state. This one column select line CS
L selects two pairs of bit lines, and connects the two pairs of bit lines to two pairs of I / O lines 16a and 16b provided corresponding to the column block. As a result, data of a plurality of bits (16 bits in this embodiment) is read from the DRAM array 1 onto the plurality of I / O line pairs 16a and 16b.

Next, the operation of the SRAM portion will be described. The SRAM row decoder 21 performs a row selecting operation in accordance with a row address given from the outside, and selects one word line from the SRAM array 2. As described above, 16-bit memory cells are connected to one SRAM word line. Therefore, according to the operation of selecting one word line, 16 static memory cells (SRAMs) are selected.
Cell) is connected to 16 pairs of bit lines SBL.

I / O line pair 16 for DRAM array 1
After 16-bit data has been transmitted to a and 16b, bidirectional transfer gate circuit 3 is turned on, and 1
Six pairs of I / O line pairs 16a and 16b and 16
The pair of bit lines SBL are connected to each other. As a result, 16 bits already selected in the SRAM array 2
The data transmitted on the 16 pairs of I / O lines 16a and 16b are written into the bit memory cells, respectively.

A sense amplifier circuit 23 and a column decoder 22 provided in the SRAM are used to transfer data between a memory cell in the SRAM array 2 and an internal data line for inputting / outputting external data.

An address for selecting an SRAM cell in the SRAM array 2 can be set completely independently of an address for selecting a dynamic memory cell (DRAM cell) in the DRAM array 1. Therefore, the 16-bit memory cell selected in the DRAM array 1 can exchange data with a memory cell at an arbitrary position (row) in the SRAM array 2, and can perform direct mapping, set associative, and full-memory operations. All of the associative mapping methods can be realized without changing the array arrangement and configuration.

In the above description, the SRA
The operation of the 16-bit batch transfer to M has been described in principle, but the 16-bit batch transfer from the SRAM array 2 to the DRAM array 1 is performed according to the same operation. Only the transfer direction is reversed. Next, the configuration and operation of the semiconductor memory device with a built-in cache according to the present invention will be described in detail in order.

FIG. 3 is a diagram showing a specific configuration of a main part of the semiconductor memory device shown in FIG. In FIG. 3, DRA
A portion related to data transfer of one memory block MBij of the M array is representatively shown. In FIG. 3, D
RAM memory block MBij includes a plurality of DRAM cells DMC arranged in a matrix. DRAM cell DMC
Includes one transistor Q0 and one capacitor C0. A constant potential Vgg is applied to one electrode (cell plate) of memory capacitor C0.

Memory block MBij further includes a DRAM word line DWL connected to one row of DRAM cells DMC, and a DRAM bit line pair DBL connected to one column of DRAM cells DMC. This DRA
M bit line pair DBL includes two bit lines BL and / B
L. Complementary signals are transmitted to bit line BL and bit line / BL. DRAM cell DMC
Is a DRAM word line DWL and a DRAM bit line pair DB
L are arranged at intersections.

A DRAM sense amplifier DSA for detecting and amplifying a potential difference on a corresponding bit line pair is provided for each DRAM bit line pair DBL. This DR
AM sense amplifier DSA receives sense amplifier activation signal φ
The operation is controlled by a sense amplifier activation circuit SAK which generates sense amplifier drive signals φSAN and / φSAP in response to SANE and / φSAPE. DRA
M sense amplifier DSA includes a first sense amplifier portion, in which a p-channel MOS transistor is cross-coupled, boosts the bit line potential on the high potential side to operating power supply potential Vcc level in response to signal / φSAP, and n Channel MO
An S transistor is cross-coupled and includes a second sense amplifier portion for discharging the potential of the lower potential bit line to, for example, a ground potential level Vss in response to signal φSAN.

Sense amplifier activating circuit SAK is turned on in response to sense amplifier activating signal / φSAPE, and sense amplifier activating transistor TR1 for activating the first sense amplifier portion of DRAM sense amplifier DSA is connected to sense amplifier activating transistor SAK. And a sense amplifier activating transistor TR2 which is turned on in response to a sense amplifier activating signal φSANE to activate a second sense amplifier portion of the DRAM sense amplifier DSA. Transistor TR1 is configured by a p-channel MOS transistor, and transistor TR2 is configured by an n-channel MOS transistor. Transistor TR1 transmits drive signal / φSAP at the operating power supply potential Vcc level to one power supply node of each sense amplifier DSA when turned on. When transistor TR2 is turned on, signal φSAN at the potential Vss level is transmitted to the other power supply node of DRAM sense amplifier DSA.

Signal line / φ for transmitting signals / φSAP and φSAN from sense amplifier activation circuit SAK
An equalizing transistor TEQ for equalizing both signal lines in response to equalizing instruction signal φEQ is provided between SAP and signal line φSAN. Thereby, sense amplifier drive signal lines / φSAP and φSAN are precharged to an intermediate potential of (Vcc + Vss) / 2 during standby. Here, the signal lines and the signals thereon are indicated by the same reference numerals.

For each DRAM bit line pair DBL,
A precharge / equalize circuit PE is provided which is activated in response to a precharge / equalize signal φEQ, precharges and equalizes each bit line of a corresponding bit line pair to a predetermined precharge potential Vbl.

DRAM memory block MBij is further provided for each DRAM bit line pair DBL and is turned on in response to a signal potential on column select line CSL, and connects the corresponding DRAM bit line pair DBL to local I / O. Includes column select gate CSG connected to line pair LIO. Column select line CSL is provided in common for two pairs of DRAM bit lines, thereby simultaneously providing two DRAM bit lines.
The bit line pair DBL is selected. The local I / O line pairs receive two LIOs so as to receive data from the two DRAM bit line pairs selected at the same time.
a and LIOb.

Memory block MBij further responds to block activation signal φBA to connect local I / O line pairs LIOa and LIOb to global I / O line pairs GIOa and GIOb, respectively.
a and IOGb. Column select line CSL extends in the row direction over one column block shown in FIG. 2, and global I / O line pairs GIOa and GIOb also extend in the row direction over one column block. Local I /
O line pairs LIOa and LIOb extend in the column direction only in one memory block.

In correspondence with FIG. 2, I / O lines 16a and 16b are connected to local I / O line pairs LIOa and LIOb and LIO gates IOGa and IOGb, respectively.
And global I / O line pairs GIOa and GIOb.

The SRAM has an SRAM word line SWL connected to one row of SRAM cells SMC and an SRAM connected to one column of SRAM cells SMC.
A bit line pair SBL and an SRAM sense amplifier SSA provided for each of the SRAM bit line pairs SBL and detecting and amplifying a potential difference between the corresponding bit line pair are included.

Bidirectional transfer gate circuit 3 includes bidirectional transfer gates BTGa and BTGb provided between SRAM bit line pair SBL and global I / O line pair GIO. Bidirectional transfer gates BTGa and BTGb both perform data transfer between SRAM bit line pair SBL and global I / O line pairs GIOa and GIOb in response to data transfer instruction signals φTSD and φTDS. Data transfer instruction signal φTSD instructs data transfer from the SRAM portion to the DRAM portion, and data transfer instruction signal φTDS instructs data transfer from the DRAM portion to the SRAM portion.

[Array Arrangement 2] FIG. 4 shows another example of the array arrangement. In the configuration of the array arrangement shown in FIG. 4, SRAM column decoder 22 is connected to DRAM array 1
And the SRAM array 2. The input / output buffer 274 is connected to the SRAM via the internal data line 251.
Connected to the column selected by column decoder 22.
In the configuration shown in FIG. 4, a column selected in DRAM array 1 is connected to internal data line 2 via a bidirectional transfer gate.
51. The connection between the DRAM array 1 and the internal data line 251 via the bidirectional transfer gate circuit 3
This may be performed using a column selection gate provided in the bidirectional transfer gate in response to a column selection signal from the column decoder 15 of the DRAM. The connection between the DRAM array 1 and the internal data line 251 and the connection between the SRAM array 2 and the internal data line 251 will be described later in detail.

Address buffer 252 receives an externally applied address signal Aa in response to chip enable signal E, and generates an internal row / column address signal int-Aa for specifying a row / column of DRAM array 1. Address buffer 252 also receives an externally applied address signal Ac in response to chip enable signal E, and
An internal row for specifying a row and a column of the RAM array 2
A column address signal int-Ac is generated. The external address signal Aa for the DRAM array and the address signal Ac for the SRAM array are applied to the address buffer 252 via separate terminals.

In the structure shown in FIG. 4, the internal address int-Ac applied to row decoder 21 and column decoder 22 of the SRAM and the internal address int-Aa applied to row decoder 14 and column decoder 15 of the DRAM are The data is supplied from the address buffer 252 via independent paths. Therefore,
Also in this configuration, SRAM array 2 and DRAM
Each of the memory cells of array 1 can be addressed independently.

In the structure shown in FIG. 4, an SRAM column decoder 22 is provided between bidirectional transfer gate circuit 3 and SRAM array 2. SRAM column decoder 22 is provided between bidirectional transfer gate circuit 3 and DRAM array 1. And a configuration provided between the two. Also, DRAM
The I / O line pair 16a, 16b of the array is selected according to the output of the DRAM column decoder 15, and the selected DR is selected.
Connecting the AMI / O line pair to the internal common data bus 251;
In addition, the SRAM column decoder 22 may be configured to connect the SRAM bit line pair SBL to the internal data transmission line 251.

"Array arrangement 3"

FIG. 5 is a diagram showing a layout of an array of a semiconductor memory device according to another embodiment of the present invention. The CDRAM shown in FIG. 5 has a 4-Mbit DRAM array and 16K bits.
SRAM array of bits. That is, C in FIG.
The DRAM includes four CDRAMs shown in FIG. 2 or FIG. In FIG. 5, the CDRAM has four memory mats MM1, MM2, MM each having a capacity of 1M bits.
3 and MM4. DRAM memory mats MM1 to MM1
Each of MM4 includes a memory cell arrangement of 1024 rows (word lines) and 512 columns (bit line pairs). Each of the DRAM memory mats MM1 to MM4 has a structure of 128 columns (bit line pairs) × 256 rows (word lines), respectively.
It is divided into memory blocks MB.

In one memory mat MM, the memory mat is divided into four memory blocks in the row direction and divided into eight blocks in the column direction. As shown in FIG. 5, unlike the arrangement of the DRAM shown in FIG. 2, the 1M-bit memory mat is divided into eight in the column direction and four in the row direction because it is housed in a rectangular package described later. To do that.

At the center of each memory block MB in the column direction, a sense amplifier DSA for DRAM and a column selection gate C are provided.
SG is arranged corresponding to each bit line pair DBL. The memory block MB is divided into an upper memory block UMB and a lower memory block LMB around the sense amplifier DSA and the column selection gate CSG. In operation, one of the upper and lower memory blocks UMB and LMB is connected to sense amplifier DSA and column select gate C
Connected to SG. Upper and lower memory blocks UMB and LM are connected to sense amplifier DSA and column select gate CSG.
Which of B is to be connected is determined by the address. Such a configuration in which one memory block MB is divided into upper and lower two memory blocks UMB and LMB and only one of them is connected to sense amplifier DSA and column select gate CSG is commonly used in a DRAM having a shared sense amplifier configuration of 4 Mbits or more, for example. Used.

One memory mat MM includes two activation sections AS. In this activation section AS, one word line is selected. That is, in the configuration shown in FIG. 5, unlike the configuration shown in FIG.
And divided into activation sections.
Therefore, selecting one word line in one memory mat MM is equivalent to selecting one word line in each activation section AS.

This semiconductor device (CDRAM) further comprises four DRAM memory mats MM1 to MM4 to 1
In order to select one word line, four DRAM row decoders DRD1, DRD2, DRD3 and DRD4 are provided. The DRAM row decoders DRD1 to DRD4
Selects one word line from each of the memory mats MM1 to MM4. Therefore, in the CDRAM shown in FIG. 5, four word lines are selected at a time. DRAM
Row decoder DRD1 includes memory mats MM1 and MM
One row is selected from the two corresponding activation sections AS. DRA
M row decoder DRD2 selects one row from lower activation section AS of memory mats MM1 and MM2.
DRAM row decoders DRD3 and DRD4 are DRA
One row is selected from each of upper activation section AS and lower activation section AS of M memory mats MM3 and MM4.

The CDRAM further includes a DRAM column decoder DCD for selecting two columns (bit line pairs) from each column block of memory mats MM1 to MM4 of the DRAM. The column select signal from DRAM column decoder DCD is transmitted to column select line CSL shown in FIG. The column selection line CSL extends so as to be shared by the upper activation section AS and the lower activation section AS. Therefore, in the configuration shown in FIG. 5, four columns from one column block (in FIG. 5, a block composed of eight memory blocks divided in the column direction) are provided by a column selection signal from DRAM column decoder DCD. Selected.

The columns selected by column decoder DCD are connected to corresponding global I / O line pairs GIO. The global I / O line pairs GIO extend in the column direction by two pairs for each column block in one activation section AS. The connection configuration between the global I / O line pair GIO and the local I / O line pair LIO in each column block will be described later in detail.

The CDRAM shown in FIG.
SRAM comprising SRAM cells having bit capacity
Array blocks SMA1 to SMA4 are included. Two SRs
Row decoders SRD1 and SRD2 for SRAM are provided at the center of both so as to be shared by the AM array blocks. SRAM row decoder SRD1 is shared by SRAM array blocks SMA1 and SMA3. SRAM row decoder SRD2 is shared by SRAM array blocks SMA2 and SMA4. Details of the configuration of the SRAM array block SMA will be described later.

This CDRAM has four input / output buffer circuits I / O for inputting / outputting data in 4-bit units.
Includes OB1, IOB2, IOB3 and IOB4. The input / output buffer circuits IOB1 to IOB4 are respectively connected to a block SC of a sense amplifier and a column decoder for an SRAM via a common data bus (internal data bus).
Connected to DA. In the configuration shown in FIG. 5, data is input and output through a sense amplifier for SRAM and a column decoder block SCDA. This is because data is input and output from a portion of bidirectional transfer gate BTG. You may comprise so that input and output may be performed.

In operation, one word line is selected in each activation section AS. Only the row block including the selected word line is activated. The remaining row blocks maintain the precharge state. In the selected row block, only small block UMB (or LMB) including the selected word line is connected to DRAM sense amplifier DSA and column select gate CSG, and the other small memory block LMB (or UMB) is used for DRAM. It is separated from sense amplifier DSA and column select gate CSG. Therefore, activation (charge / discharge) of 1/8 bit lines is performed as a whole. By performing the division operation in this manner, power consumption due to charging and discharging of the bit line can be reduced. One memory block MB is divided into an upper memory block UMB and a lower memory block LMB.
By arranging the sense amplifier DSA at the center, the length of the bit line is reduced, and the ratio of the bit line capacitance Cb to the memory capacitor capacitance Cs, Cb / Cs
Can be reduced, and a sufficient read voltage can be obtained at high speed.

In each activation section AS, a sensing operation is performed on four small blocks UMB (or LMB) in the row direction. In each activation section AS, DRA
Two pairs of bit lines are selected in one column block by a column selection signal from M column decoder DCD. The global I / O line pair GIO extends in the column direction so as to be shared by the column blocks of each activation section AS. In each activation section AS, two pairs of bit lines are selected from each column block and connected to corresponding two pairs of global I / O lines GIO. Four pairs of global I / O line pairs GIO are connected to the bidirectional transfer gate BTG. Four bidirectional transfer gates BTG are provided for one memory mat MM. Therefore, from one memory mat MM, 16 pairs of global I / O lines GIO can be connected to SRAM bit line pairs SBL of the corresponding SRAM array.
Next, the layout of this global I / O line will be described.

FIG. 6 is a diagram showing the arrangement of global I / O lines for one memory mat. In FIG. 6, global I / O line pair GIO includes upper global I / O line pair UGIO provided for upper activation section UAS, and lower global I / O line pair provided for lower activation section LAS. Including LGIO. This upper global I / O
The line pair UGIO and the lower global I / O line pair LGIO are arranged in parallel. The lower global I / O line pair LGIO passes through the upper activation section UAS, but is not connected to the local I / O line pair LIO in the upper activation section UAS. Global I / O line pair GIO and local I / O
The line pair LIO is connected via an IO gate IOG which is a block selection switch. This IO gate IOG is
Only those provided in the row block including the selected word line are turned on by the block selection signal φBA,
Corresponding local I / O line pair LIO and corresponding global I
/ O line pair GIO is connected.

Since local I / line pair LIO has DRAM sense amplifier DSA and column select gate CSG arranged at the center of memory block MB in the column direction, it has a row direction at the center of memory block MB in the column direction. It is arranged along.

A word line shunt region WSR is provided between adjacent column blocks in the column direction. The word line shunt region WSR is a region for making contact between a word line formed of relatively high-resistance polysilicon and a low-resistance aluminum interconnection. The word line shunt region will be briefly described below.

FIG. 7 is a diagram schematically showing a sectional structure of a select transistor Q0 (see FIG. 3) included in a DRAM cell. In FIG. 7, a select transistor Q0 includes an impurity region IPR formed on a surface of a semiconductor substrate SUB.
And bit line BL connected to one impurity region IPR
And a polysilicon layer PL formed on the surface of the semiconductor substrate between the two impurity regions IPR. By transmitting word line drive signal DWL (indicated by the same reference numeral as a signal line and a signal transmitted thereon) to polysilicon layer PL, a channel is formed on the surface of the semiconductor substrate between impurity regions IPR. The selection transistor Q0 is turned on. Polysilicon has a relatively high resistance. If the resistance of the word line DWL increases, a signal delay occurs due to the resistance of the polysilicon. In order to lower the resistance of word line DWL, a low-resistance aluminum interconnection AL is provided in parallel with polysilicon layer PL. Aluminum wiring AL
And the polysilicon layer PL are periodically connected to lower the resistance of the word line DWL. Aluminum interconnection AL is formed above bit line BL. Therefore, a region for making contact between polysilicon layer PL and aluminum interconnection AL is formed by bit line BL (/
BL) needs to be set in an area where no memory cell is arranged, that is, an area where no memory cell is arranged. Therefore, a word line shunt region is provided between column blocks. This connection mode is shown in FIG.

In FIG. 8, a low-resistance aluminum interconnection AL is arranged in parallel with a relatively high-resistance polysilicon layer PL serving as a word line. Word line drive signal DWL is transmitted to aluminum interconnection AL. Aluminum wiring A
L and the polysilicon layer PL are connected to the word line shunt region WS
In R, it is periodically connected by the contact layer CNT. By periodically forming contacts through aluminum interconnection AL, polysilicon layer PL, and contact region CNT, the resistance of polysilicon layer PL can be effectively reduced. Thereby, even if the length of one word line is increased, the word line drive signal WL can be transmitted to the end of the word line at a high speed.

FIG. 9 schematically shows a layout of global I / O lines and column select lines CSL. FIG. 9 shows only these layouts for two memory blocks MB. In FIG. 9, global I / O line pair GIO is arranged in word line shunt region WSR. D
The RAM word line DWL is connected to the global I / O line pair GI
It is arranged in a direction orthogonal to O. In FIG. 9,
Aluminum wiring AL and polysilicon layer PL are arranged in parallel with each other, and are shown as the same word line DWL in this plan view because they overlap. Also, DRAM
Column select line CSL for transmitting a column select signal from a column decoder is arranged in a direction orthogonal to DRAM word line DWL.

In this layout, the bit line pair DBL of the DRAM is not shown, but this column select line CSL is not shown.
It is arranged in parallel with. Aluminum interconnection AL (see FIG. 8) for DRAM word line DWL is formed of a first-layer aluminum interconnection. Column select line CSL is formed of a second layer aluminum interconnection. Global I / O
The line is formed by the same layer of aluminum wiring as the column selection line CSL. By arranging global I / O line pair GIO in word line shunt region WSR, DR
I / O for connecting AM array and bidirectional transfer gate
Even if the O line has a local I / O line, a global I / O line, and a hierarchical structure, the chip area does not increase.

FIG. 10 schematically shows a structure of SRAM array block SMA shown in FIG. In FIG. 10, the SRAM array block SMA includes 16 pairs of bit lines SBL and 256 SRAM word lines SWL. SRAM bit line pair SBL and SRAM word line SW
An SRAM cell SMC is arranged at the intersection with L. As shown in FIG. 5, in order to make this SRAM array block SMA correspond to a rectangular chip layout, SRAM bit line pairs SBL are arranged in the row direction of the DRAM array.
In addition, SRAM word lines SWL are arranged in the column direction of the DRAM array. The SRAM word line SWL is connected to the SRAM row decoder SRD.

The SRAM bit line pair SBL needs to be connected to the global I / O line pair GIO via the bidirectional transfer gate BTG. Therefore, SRAM bit line pair SB
L needs to be connected to a bidirectional transfer gate BTG provided in the downward direction of FIG. 10 (or the upward direction of FIG. 10: this is determined by the arrangement of the memory array). For this reason, in the configuration shown in FIG.
An SRAM bit line lead-out line SBLT is arranged in parallel with WL.

The SRAM bit line extraction wiring SBLT is S
The same number as the bit line pairs SBL of the RAM array block SMA are provided, each corresponding to the corresponding SRAM bit line pair SBL.
Connected to. This SRAM bit line extraction wiring SBL
If T is formed of the same wiring layer as the SRAM word line SWL, the SRAM bit line extraction wiring SBLT can be easily realized without providing an additional wiring layer newly formed in another manufacturing process. .

The SRAM row decoder SRD decodes an external SRAM row address and decodes the 256 S rows.
One of the RAM word lines SWL is selected. A 16-bit SRAM cell SMC connected to the selected SRAM word line SWL is provided with a corresponding SRAM bit line pair SBL and SRAM bit line extraction wiring SBL.
Connected to T. At the time of data transfer, this bit line extraction wiring SBLT is connected to global I / O line pair GIO via bidirectional transfer gate BTG.

By using the layouts shown in FIGS. 6 and 10, as shown in FIG. 5, the DRAM array is divided into upper and lower parts of the figure, and the SRAM array is arranged between the upper and lower DRAM array blocks. Intensively arranged,
Further, input / output buffer circuits IOB1 to IOB1
A structure in which the IOB 4 is provided can be realized. Such a structure in which the SRAM array is intensively arranged in the central portion of the chip and data is input / output from the vicinity of the central portion of the chip provides an advantage very suitable for a CDRAM as described below.

The first requirement in the CDRAM is a high-speed access to the cache register. By disposing an SRAM array functioning as a cache register close to an input / output buffer for inputting / outputting data to / from the outside of the device, the length of signal wiring therebetween can be reduced, and data input / output can be performed at high speed. It is suitable for meeting the demand for high-speed access.

By arranging the SRAM array intensively at the center, the address line for selecting the SRAM cell can be shortened. If the address line is shortened, the wiring resistance and the parasitic capacitance associated with the address line can be reduced, and the SRAM cell can be selected at high speed, which is suitable for realizing high-speed access to the cache register.

In the case of the architecture shown in FIG.
The wiring for connecting the M array and the SRAM array may become longer, and the data transfer speed between the DRAM array and the SRAM array may be reduced. However, data is transferred between the DRAM array and the SRAM array when a cache miss (miss hit) occurs. In this case, the access speed of the standard DRAM is usually sufficient, and there is often no need to increase the access speed, so that there is no practical problem. Even in this case, data can be written / read at high speed by using a data transfer device described later.

[Pin Arrangement] FIG. 11 is a diagram showing an example of the pin arrangement of a package accommodating a CDRAM having the array arrangement "array arrangement 3" shown in FIG. This FIG.
As shown in FIG. 5, the CDRAM accommodated in the first embodiment includes a 4M-bit DRAM and a 16K-bit SRAM integrated on the same chip. This CDRAM has a lead pitch of 0.8 mm, a chip length of 18.4 mm, and 44 pin terminals.
300 mil. It is stored in TSOP (Thin Small Outline Package) Type II.

This CDRAM includes two types of data input / output methods: D / Q separation and masked write. The D / Q separation is a method in which write data D and read data Q are input / output via separate pin terminals. The masked write mode is an operation mode in which the write data D and the read data Q are output through the same pin terminal, and the data writing can be masked from the outside.

In order to efficiently supply the power supply potential to the CDRAM and to facilitate the layout of the power supply wiring, three pin terminals are provided for each of the power supply potentials Vcc and Gnd. An external power supply potential Vcc is supplied to the pin terminals of pin numbers 1, 11, and 33. Power supply potential Vcc applied to pin terminals of pin numbers 1, 11, and 33 may have the same voltage value as operating power supply potential Vcc shown in FIG. An external power supply potential Vcc applied to the pin terminals of pin numbers 1, 11 and 33 may be internally stepped down to supply an operating power supply potential. The ground potential Gnd is at pin 1
2, 22, and 34 pin terminals.

Pin numbers 6 to 8, 15 to 17, 2
8 to 30 and 37 to 39 pin terminals
Address signals Ac0 to Ac11 for AM are provided. The address signals Aa0 to Aa9 for the DRAM correspond to the pin numbers 2, 3, 19 to 21, 24 to 26 and 4
2, 43 pin terminals. Pin numbers 2 and 3
Are also supplied with command addresses Ar0 and Ar1 for setting various modes to be described later.

A cache inhibition signal CI # indicating cache access inhibition is applied to the pin terminal of pin number 4. When the cache inhibit signal CI # is set to "L", access to the SRAM array is inhibited and the DRAM
Direct access to the array (array access) becomes possible.

A write enable signal W # indicating the data write mode is applied to the pin terminal of pin number 5. A chip select signal E # indicating that this chip has been selected is supplied to the pin terminal of the pin number 18.

A command register instruction signal CR # for designating a special mode is applied to the pin terminal of pin number 23. When the command register designating signal CR # is "L", the command addresses Ar0 and Ar1 given to the pin terminals of the pin numbers 2 and 3 become valid, and the special mode is set (register selection). The configuration of the command register will be described later. To pin number 23, a burst mode instruction signal BE # for transferring data in accordance with the burst mode by an externally provided arithmetic processing unit is also applied. Burst mode instruction signal BE
When # is activated, the CDRAM internally generates an address signal automatically.

A cache hit signal CH # indicating a cache hit is applied to the pin terminal of pin number 27. If the cache hit signal CH # is at "L", the cache (SRAM array) can be accessed. An output enable signal G # indicating the output mode is applied to the pin terminal of the pin number 40. A clock signal (for example, a system clock) is supplied to the pin 41.
K is given.

A refresh instruction signal R for instructing refresh of the DRAM array is supplied to the pin terminal of pin number 44.
EF # is given. This refresh instruction signal REF
# Goes to “L”, DR is internally set in that cycle.
The AM array is automatically refreshed. CDR
The AM has an auto refresh mode and a self refresh mode. The setting of the refresh mode is determined by the refresh mode setting signal set in the command register. At the time of the auto refresh mode, D in accordance with the above-described refresh instruction signal REF #
The RAM array is refreshed.

When self refresh is designated, the pin terminal of this pin number 44 is switched to an output terminal.
At the time of executing the self-refresh, a signal BUSY # indicating the execution of the self-refresh is output from the pin terminal of the pin number 44. By this signal BUSY #, CDRA
It is possible to know the timing of self-refresh outside M, and self-refresh can be used even in a normal cycle.

Pin numbers 9, 10, 13, 14, 31, 3
The data supplied to the pin terminals 2, 35 and 36 are different depending on the two types of operation modes of D / Q separation and masked write. The operation mode of D / Q separation and masked write is set by a command register (described later).

In the masked light mode, the pin number 1
Pins 0, 13, 32 and 35 are used as data input / output terminals for commonly performing data input / output. Pins 9, 14, 31, 35, and 36 have masked write instruction data M0, M1, M2, and M3 indicating which input / output pin is to be masked.
Are given.

In the D / Q separation mode, the pin terminals of pin numbers 9, 14, 31, and 36 are connected to write data D.
Used as pin terminals for inputting 0, D1, D2 and D3. Pin numbers 10, 13, 32 and 35
Of the read data Q0, Q1, Q2 and Q3
Is used as a data output pin terminal for outputting data.

SRAM addresses Ac0 to Ac11 and D
The RAM addresses (array addresses) Aa0 to Aa9 are
Each is provided independently via a separate pin terminal. In the pin arrangement shown in FIG. 11, external operation control signals usually used in a standard DRAM, that is, row address strobe signal / RAS and column address strobe signal / CAS are not used. This FIG.
CDRAM stored in the package shown in Fig. 5 (see Fig. 5)
, Control signals and data are input in response to a rising edge of clock signal K from the outside.

"Internal Function" FIG. 1 is a block diagram showing the internal structure of a CDRAM chip housed in the package shown in FIG. The block arrangement shown in FIG.
It should be noted that this is only for functionally showing the internal configuration of the RAM, and does not match the actual layout.

In FIG. 1, the CDRAM is a DRAM 1
00 and the SRAM 200. DRAM 100
4M bit DRAM array 101 and given DR
The internal row address for AM is decoded, and a DRAM row decoder block 102 for selecting four rows from the DRAM array 101 and the internal column address for DRAM are decoded. In a normal operation mode (array access), the selected row is selected. D to select one column each from four rows
A RAM column decoder block 103 and a DR for detecting and amplifying data of a memory cell connected to a selected row
In response to a column select signal from block 103 and AM sense amplifier DSA, this DR
The block 104 includes a selection gate SG for selecting 16 bits of the AM array 101 and selecting a 4-bit memory cell in the array access mode.

The SRAM 200 has an SRAM array 201 having a capacity of 16K bits, an SRAM row decoder block 202 for decoding an internal row address for the SRAM and selecting four rows from the SRAM array 201,
The internal column address for the RAM is decoded, and one bit is selected from each of the selected four rows and the internal data bus 251 is selected.
And a column decoder / sense amplifier block 203 comprising an SRAM column decoder and an SRAM sense amplifier for detecting and amplifying information of the selected SRAM cell at the time of data reading. DRAM
A bidirectional transfer gate circuit 210 is provided between 100 and SRAM 200. In FIG. 1, the gate circuit 210 may be connected to the output (input) of the column decoder / sense amplifier block 203 as in the arrangement shown in FIG. However, in FIG. 1, in the array access mode, since input / output of data to / from DRAM 100 is performed via common data bus 251, common data bus 251 is shown coupled to bidirectional transfer gate circuit 210. It is.

The CDRAM further includes externally applied control signals G #, W #, E #, CH #, CI #, REF #
/ BUSY # and CR # / BE # to generate internal control signals G, W, E, CH, CI, REF, and CR, and a DRAM internal address int-Aa and SRAM. An address buffer 252 for generating an internal address int-Ac and a clock buffer 254 for buffering a clock signal K supplied from the outside are included. Control clock buffer 2
Numeral 50 fetches a given control signal in response to the rise of the internal clock from clock buffer 254 and generates an internal control signal. The output of clock buffer 254 is also provided to address buffer 252. Address buffer 252 takes in external addresses Aa and Ac applied when internal chip enable signal E is active at the rising edge of internal clock K from clock buffer 254, and generates internal addresses int-Aa and int-Ac. I do.

The CDRAM further includes a DRAM array 10
A refresh circuit 290 for refreshing memory cells of 0 is included. Refresh circuit 290 is activated in response to internal refresh instruction signal REF, and
A counter circuit 293 for generating a refresh address of the RAM array, a refresh control circuit 292 driven in response to the internal refresh instruction signal REF, and a switching signal MUX from the refresh control circuit 292,
An address multiplexing circuit 258 for providing one of the refresh address from the counter circuit 253 and the internal row address from the address buffer 252 to the DRAM row decoder block 102 is included. The refresh control circuit 292 includes an auto refresh mode detection circuit 29.
1 is driven by a refresh request. This refresh operation will be described later.

The CDRAM further includes internal control signals E,
DRAM array drive circuit 260 for generating various control signals for driving DRAM 100 in response to CH, CI and REF, and transfer operation of bidirectional transfer gate control circuit 210 in response to internal control signals E, CH and CI And an SRAM array drive circuit 264 for generating various control signals for driving the SRAM 200 in response to the internal chip select signal E.

The CDRAM according to the present invention is activated in response to an internal control signal CR and changes the operation mode of the CDRAM in response to an external write enable signal W # and command addresses Ar (Ar0 and Ar1). A command register 270 for generating a command CM for designating, a data input / output control circuit 272 for controlling data input / output according to the internal control signals G, E, CH, CI and W and the special mode command CM; Under the control of control circuit 272, input / output circuit 27 including an input / output buffer and an output register for inputting / outputting data between common data bus 251 and the outside of the device.
4 inclusive. The reason why the input / output circuit 274 is provided with an output register is to realize a latch output mode and a register output mode which are special modes of the CDRAM. The data input / output control circuit 272 sets not only the data input / output timing but also the data input / output mode according to the mode specified by the special mode command CM. FIG. 1 shows an example of the mode of the data input / output pins in the masked write mode.

The CDRAM further includes an additional function control circuit 299 for implementing various functions. The function realized by the additional function control circuit 299 will be described later in detail, and includes, for example, prohibition of internal clock generation during standby, switching between refresh auto-refresh / self-refresh, and switching of address generation source during burst mode. . Next, the configuration of each circuit will be specifically described.

"Input / output circuit" (Connection between DRAM array and SRAM array and internal data line)

FIG. 12 is a diagram showing an example of the connection between the bidirectional transfer gate circuit (BTG) shown in FIG. 2 and the internal common data line 251. 12, an SRAM input / output gate 301 includes an SRAM sense amplifier SSA and an SR sense amplifier SSA.
Activated when data is written to the AM array, the data on internal data line 251a is transferred to corresponding SRAM bit line pair S.
Includes write circuit WRI for transmitting onto BL. SR
AM bit line pair SBL is connected to internal data line 251a via SRAM sense amplifier SSA and SRAM column select gate 302. The SRAM column selection signal SYL from the SRAM column decoder block 203 is applied to the SRAM selection gates 302, respectively. Thereby,
Only one pair of SRAM column bit lines SBL is connected to internal data line 251a. Here, the internal data line 251 shown in FIG. 1 transfers 4-bit data, and only the internal data line corresponding to one bit is shown in FIG.

In FIG. 12, in order to further enable array access, the CDRAM responds to a logical product signal of cache inhibit signal CI and DRAM column select signal DY to connect global I / O line pair GIO to internal data line. 251
a access switching circuit 310 connected to a. The access switching circuit 310 and the bidirectional transfer gate BTG are included in the transfer gate circuit block 305.

The column select signal DYi of the DRAM is generated, for example, by decoding the lower 4 bits of a DRAM column address. That is, 16 pairs of global I / O line pairs GIO are provided for one DRAM memory mat (capacity: 1 Mbit). In the case of array access, only one pair must be selected. Therefore, a column address for the DRAM of the lower 4 bits is decoded to generate a column selection signal DYi.

Access switching circuit 310 merely connects global I / O line pair GIO to internal data line 251a, and is connected to corresponding signal lines in bidirectional transfer gate BTG. When the array access is realized, the SRAM sense amplifier SS is provided without providing such an access switching circuit 310.
The configuration may be such that the global I / O line pair GIO is connected to the internal data line 251a via A. At this time, S
The column selection signal applied to RAM selection gate 302 is DR
It becomes a selection signal based on the column address given to AM. This can be realized by a circuit that multiplexes the column selection signal by the signal CI. This multiplex circuit supplies a column select signal for DRAM to SRA when signal CI is active.
Give to M select gate.

In the SRAM, an SRAM sense amplifier S is provided for each SRAM bit line pair SBL.
An SA is provided, which is a single SRAM for one block of SRAM bit line pairs like a normal SRAM.
A configuration in which only the RAM sense amplifier is provided may be employed.
However, if an SRAM sense amplifier is provided for each of the SRAM bit line pairs SBL, data can be output more reliably and at high speed. Also, SRA
If the M sense amplifier SSA has the same configuration as the DRAM sense amplifier, there is no need to particularly provide the write circuit WRI.

FIG. 13 shows the D / Q in the input / output circuit 274.
FIG. 3 is a diagram illustrating a configuration for realizing separation. In FIG. 13, input / output circuit 274 is activated in response to internal output enable signal G to generate an internal data line 251a.
Output buffer 3 for generating output data Q from the above data
20 and is activated in response to the internal write instruction signal W,
An input buffer 322 for generating internal write data from external write data D and transmitting it to internal data line 251a
And D / Q from command register 270 (see FIG. 1)
A switch circuit 324 for short-circuiting the output of output buffer 320 and the input of input buffer 322 in response to separation instruction bit CMa is included. The D / Q separation instruction bit CMa is included in the special mode designation command CM generated from the command register 270. When switch circuit 324 is rendered conductive, data input / output is performed via the same pin. When switch circuit 324 is turned off, data input / output is performed via separate pins. FIG. 13 also representatively shows only a configuration related to input / output of 1-bit data.

FIG. 14 is a diagram showing another connection configuration of the data input / output circuit. In FIG. 14, the output buffer circuit 3
20 receives the selected memory cell data of the SRAM sense amplifier or the DRAM array and transmits it to the external output pin Q. The first input buffer circuit 322a is connected to an external pin terminal Q, and the second input buffer circuit 322b is connected to an external data input pin terminal D. Outputs of the first and second input buffer circuits 322a and 322b are connected to internal data buses DBW,
* Transmitted to DBW (251a). The enable / disable of the first and second input buffer circuits 322a and 322b is performed in response to an instruction bit CM from a command register (see FIG. 1). When the command register indicates the D / Q separation mode, the first input buffer circuit 322a is disabled and the input buffer circuit 322b is enabled. If the instruction bit CM indicates a masked write mode common to D / Q, the first input buffer circuit 32
2a is enabled and the second input buffer circuit 3
22b is disabled.

In the structure shown in FIG. 14, data from the SRAM sense amplifier is transmitted to output buffer circuit 320. This is because data of a selected memory cell of the DRAM array is connected to a column line of the SRAM array. This is because the signal is transmitted to the internal data bus via the sense amplifier of the SRAM. That is, a case where column select signal lines SYLi and SYLj applied to gate 302 are shared with DRAM column decoder output lines DYi and DYj in the configuration in which gate 310 is not provided in the configuration of FIG. 12 is shown as an example. . This configuration will be described later.

FIG. 15 is a diagram showing still another configuration of the input / output circuit. In FIG. 15, the output buffer circuit 320
Between the input buffer circuit 322 and the
Transistor 324a which is turned on in response to
And a transistor gate 324b that is turned on in response to the complementary instruction bit / CMa is provided between the input buffer circuit 322 and the data input pin terminal D.
In this configuration, when the instruction bit CMa indicates the D / Q separation mode, the transistor gate 324a is turned off and the transistor gate 324b is turned on. Conversely, when the D / Q-shared masked write mode is indicated, the transistor gate 324a is turned on and the transistor gate 324b is turned off.

With this configuration, input buffer circuit 322
Can be selectively connected to the data output pin terminal Q or the data input pin terminal D, and the D / Q separation mode and the D / Q sharing mode can be set.

Next, a circuit configuration for setting the data output mode of the input / output circuit will be described. The data output mode is set by a command register.

The data output mode is set to one of a transparent mode, a latch mode, and a register mode according to the data set by the command register. FIG. 16 is a diagram showing a circuit configuration related to the data output mode setting. In FIG. 16, a command register 270 responds to a command register mode detection signal (internal command register signal) CR in response to an external write enable signal W # and command data Ar0, A.
Command register mode selector 2 for decoding r1
79, and registers WR0 to WR3 and a flip-flop FF1. The command register includes eight registers RR0 to RR3 and WR0 to WR3 as described later. However, the registers RR2 and RR3 are not shown in FIG. Register WR
0 to WR3 are 4-bit registers. Registers RR0 and RR1 have one flip-flop FF
Share one. When the register RR0 is selected, the flip-flop FF1 is set to the masked write mode. When the register RR1 is selected, the flip-flop F
F1 is set to the D / Q separation mode. Input control circuit 2
72b selects one of the input circuits 274b and 274c according to the setting data of the flip-flop FF1.

Which of the registers WR0 to WR3 is to be set is determined by decoding the command data Ar0 and Ar1. Write enable signal W #
Is active, 4-bit data D0-D3 (or DQ0-DQ3) is set in the corresponding register via input circuit 274b or 274c selected by input control circuit 272b. Associated with the data output mode is register WR0. The setting of the data output mode to the register WR0 will be described. Output control circuit 272a is set to one of transparent, latch, and register output modes in accordance with the lower two bits of register WR0, and selectively activates output circuit 274a in accordance with the set output mode. Signals φ1, / φ1 and φ2 are generated.

FIG. 17 is a diagram showing an example of a specific configuration of the output circuit 274a. In FIG. 17, the output circuit 274
a is a first output latch 981 for latching data on read data buses DB and * DB in response to control signals φ1 and / φ1, and latch data of output latch 1 in response to clock signal φ2. Or data bus DB, * DB
A second output latch 982 for passing the above data and an output buffer 983 for receiving data from the output latch 982 and transmitting the output data to the external pin terminal DQ in response to the control signal G #.

First output latch 981 includes clocked inverters ICV1 and ICV2 activated in response to clock signals φ1 and / φ1. The input and output of clocked inverter ICV1 are connected to the output and input of clocked inverter ICV2, respectively. This output latch 981 enters a latch state when clock signal φ1 is at “H”. That is, the clocked inverter I
CV1 and ICV2 are activated when clock signal φ1 is at "H" and function as inverters. When the clock signal φ1 is “L”, the clocked inverter ICV
1 and ICV2 are disabled, and latch 981 does not perform a latch operation.

When clock signal φ2 is at "L", second output latch 982 latches data applied to its inputs A and * A and outputs the same from outputs Q and * Q. The output latch 982 outputs the latched data from the outputs Q and * Q when the clock signal φ2 is “L” when the clock signal φ2 is “H”, regardless of the signal states of the inputs A and * A. . Clock signals φ1,
/ Φ1 and φ2 are signals synchronized with an external clock K, and their generation timings are made different by the output control circuit 272a.

Output buffer 983 is activated when output enable signal G # is activated, and output latch 982 is activated.
Is transmitted to the terminal DQ.

FIG. 18 is a diagram showing an example of a specific configuration of the second output latch 982. In FIG. 18, second output latch 982 includes a D-type flip-flop DFF receiving input A (* A) at its D input and receiving clock signal φ2 at its clock input CLK. From the output Q of the flip-flop DFF to the output Q of the output latch 982 (*
Q) is obtained. This D-type flip-flop DFF is of a down-edge trigger type, takes in the input A at the timing when the clock signal φ2 falls to L, and outputs the clock signal φ2.
Output the input A as it is while is "L". When clock signal φ2 is "H", data latched earlier is output regardless of the state of input A applied to input terminal D. As a result, the output latch 98 that realizes a desired function is provided.
2 is obtained. D-type flip-flops DFF are provided for input A and input * A, respectively. The output latch 982 may have another configuration, and the clock signal φ
2, any circuit configuration can be used as long as the circuit configuration can realize the latch state and the through state.

FIG. 19 is a diagram showing an example of a specific configuration of the output control circuit 272b. The output control circuit 272a includes a delay circuit 991a for delaying the external clock for a predetermined time,
991b and 991c, a one-shot pulse generation circuit 992a for generating a one-shot pulse signal having a predetermined pulse width in response to the output of the delay circuit 991a, and a predetermined pulse width in response to the output of the delay circuit 991b. And a one-shot pulse generation circuit 992c for generating a one-shot pulse signal having a predetermined pulse width in response to the output of delay circuit 991c. Clock signals φ1 and / φ1 are generated from one-shot pulse generation circuit 992a.

The outputs of one-shot pulse generation circuit 992b and one-shot pulse generation circuit 992c are OR circuit 9
93. The clock signal φ from the OR circuit 993
2 is generated. The delay time of delay circuit 991b is shorter than the delay time of delay circuit 991c. The enable / disable of one-shot pulse generation circuits 992a to 992c is set by 2-bit command data WR0. When 2-bit command data WR0 indicates the latch mode, one-shot pulse generation circuit 99
2a and 992c are enabled, and one-shot pulse generation circuit 992b is disabled. Next, the operation of the command register and data output circuit shown in FIGS. 16 to 19 will be described.

First, description will be made with reference to the operation waveform diagram of the latch operation shown in FIG. The setting of the latch output mode in the data output mode is performed by setting the lower two bits of the command data register WR0 to (01). At this time, one-shot pulse generation circuits 992a and 992c are enabled. Now, it is assumed that output enable signal G # is in an active state "L" indicating data output. At this time, external address An is taken into the address buffer at the rising edge of clock K, the corresponding SRAM word line SWLn is selected, and SR
Data RDn appears on AM bit line pair SBL. At this time, the one-shot pulse generation circuit 992a generates a one-shot pulse that becomes “L” for a predetermined period at a predetermined timing in response to the rising of the external clock K.
When this clock signal φ1 falls to "L",
The output latch 981 is prohibited from latching. At this time, the clock signal φ2 is at “H” and the output latch 98
2 maintains the latch state, latches and outputs the data Qn-1 read in the previous cycle. Of the data RDn on the 64-bit SRAM bit line pair SBL selected by the external address, 4-bit data further selected according to the external address is transmitted to the internal output data buses DB and * DB. This data bus DB, *
When the data DBn on DB is determined, the clock signal φ
1 rises to "H". As a result, the output latch 981 performs a latch operation and latches the determined data DBn.

Subsequently, the one-shot pulse generation circuit 99
A one-shot pulse is generated from 2c, and signal φ2 falls to "L". As a result, output latch 982 newly takes in data DBn latched in output latch 981 and transmits it to output terminal DQ via output buffer 983. The generation of clock signal φ2 is performed in synchronization with the falling of clock K, and the data selected in this cycle is output as output data Qn in response to the falling of external clock K. The clock signal φ2 becomes “H” until the next rise of the external clock K.
Stand up. Thus, output latch 982 continuously outputs determined data DBn irrespective of the data on internal output data buses DB and * DB.

Subsequently, the clock signal φ1 falls to "L" to release the latch state of the output latch 981, and prepares for the next cycle, ie, the operation for latching the next fixed data. Thus, data read in the previous cycle is sequentially output as fixed data in response to the rising of external clock K.

Next, the register output mode will be described with reference to FIG. The setting of the register output mode is performed by setting the lower two bits of the command data WR0 to (11). In this register output mode, one-shot pulse generation circuit 992b is enabled and one-shot pulse generation circuit 992c is disabled. In this case, a one-shot pulse falling to "L" is generated from one-shot pulse generation circuit 992b in response to the rising of external clock K. At this time, since clock signal φ1 is at “H”, output latch 982 latches data DBn−1 read in the previous cycle.

In the register output mode, the falling timing of clock signal φ2 to "L" is controlled by external clock K.
Is determined in response to the rise of In this case, in response to the (n + 1) th cycle of the external clock K, the read data DBn in the nth clock cycle is output to the output pin terminal DQ as the output data Qn. Therefore, in the latch output mode and the register output mode, the generation timing of clock signal φ2, that is, “L”
The only difference is the timing of the transition to. Thus, a latch output mode in which data of the cycle before the cycle is output and subsequently data read in the current cycle is output, and a register output in which the read data in the nth cycle is output in the (n + 1) th cycle Mode is realized.

Next, the transparent mode will be described with reference to FIG. First, the first transparent output mode will be described with reference to FIG. This transparent output mode is performed by setting the lower two bits of the register WR0 to (X0) as described above. The first transparent output mode and the second transparent output mode are selected by setting the bit value of X to 0 or 1. At this time, which of the first transparent output mode and the second transparent output mode is selected by which value is arbitrary.
In the first transparent output mode, clock signals φ1 and φ2 both remain “L”.
At this time, the output latch 981 is released from the latch operation, and the output latch 982 is also in the through state. Therefore, in this case, output data Qn is DBn transmitted on internal data buses DB and * DB.
Is output as it is. That is, when the data of the SRAM bit line pair SBL or the global I / O line pair GIO is invalid data (INVALID DATA), the invalid data INV is also applied to the output pin DQ in response to this.
Appears.

In the second transparent output mode shown in FIG. 22B, clock signal φ1 is generated. Since the first output latch 981 performs a latch operation while the clock signal φ1 is at “H”, even if the data RDn of the SRAM bit line pair SBL becomes invalid, the data on the data buses DB and * DB are output from the output latch 981. Latched as valid data for a predetermined period (clock signal φ1
During the "H" period), the period during which the invalid data INV is output is shortened. Also in the second transparent output mode, the clock signal φ2 remains “L”.

In the above-described configuration, a down-edge trigger type D flip-flop is used as the second output latch 982. However, if the polarity of the clock signal φ2 is changed, an up-edge trigger type latch circuit is used. Can obtain the same effect. Also, the output latch 981
Can also be realized by using another latch circuit.

The characteristics of the output mode set by the command register are summarized as follows.

(1) Transparent output mode:
In this mode, data on the internal data buses DB and * DB is transmitted directly to the output buffer. In this mode, output data DQ (Q) is applied to external clock K
After the elapse of time tKHA from the rising edge of the output enable signal G #
Valid data appears later after GLA. Time t
When the output enable signal G # falls before the KHA, invalid data (inv) is output until time tKHA. This is because if the fall timing of the output enable signal G # is fast, the internal data buses DB and * DB
Is because no valid data appears. Therefore, in this mode, the period during which the output data is valid is limited to the period during which the valid data appears on the internal bus.

(2) Latch output mode: In this mode, an output latch circuit is provided between the internal data buses DB and * DB and the output buffer. In this latch output mode, data is latched by the output latch while the external clock K is "H", so that the time tKHA
When the output enable signal G # falls earlier, the read data of the previous cycle is output. Therefore, even during a period in which invalid data appears on the internal data buses DB and * DB, no invalid data is output to the outside. That is, it is possible to obtain an effect that a sufficient period for the CPU to capture the output data can be obtained.

(3) Register output mode: In this mode, an output register is provided between the internal data bus and the output buffer. In this register output mode, the output data is a time tGL after the elapse of time tKHAR from the rising edge of external clock K or a time tGL from the falling edge of output enable signal G #.
The valid data in the previous cycle is output later after the lapse of A. In the register output mode, invalid data is not output for the same reason as in the latch output mode. When data is continuously output in this register mode, it appears that data is being output at a very high speed from the rising edge of the external clock K. Such an operation is generally called a pipeline operation, and the apparent access time can be further reduced than the cycle time.

By allowing the output mode as described above to be set by the command register, the user can select an output mode according to the system.

[Data Transfer between DRAM and SRAM] FIG. 23 is a diagram showing an example of the configuration of the bidirectional transfer gate BTG. In FIG. 23, a bidirectional transfer gate BTG (BTG
a or BTGb) are activated in response to a data transfer instruction signal φTSD, and respond to a data transfer instruction signal φTDS to drive circuit DR1 transmitting data on SRAM bit line pair SBL to global I / O line pair GIO. Drive circuit D for transmitting data on global I / O line pair GIO to SRAM bit line pair SBL
R2. Drive circuits DR1 and DR2 are set to an output high impedance state when data transfer instruction signals φTSD and φTDS are inactive.

FIG. 24 is a signal waveform diagram representing an operation during data transfer from the DRAM array to the SRAM array. Hereinafter, the data transfer operation from the DRAM array to the SRAM will be described with reference to FIGS.

Precharge instructing signal φE before time t1
While Q is in the active state “H”, sense amplifier drive signal lines φSAN and / φSAP, local I / O line pair LIO and global I / O line pair GIO are each at Vcc / 2.
At the precharge potential. At this time, the precharge / equalize circuit PE is activated to precharge the DRAM bit line pair DBL to the precharge potential of Vcc / 2 (= Vbl) and equalize the potential of each bit line BL, / BL. .

At time t1, precharge instructing signal φ
When the EQ falls, the precharge / equalize circuit PE
And the equalizing transistor TEQ becomes inactive. As a result, the equalizing operation of sense amplifier drive signal lines φSAN and / φSAP is completed, and the equalizing / precharging operation of DRAM bit line pair DBL is stopped, and DRAM bit line pair DBL and sense amplifier drive signal lines φSAN and / φSAP are stopped. Is the intermediate potential Vcc / 2
(However, Vss = 0 V) in a floating state.

Thereafter, a row selecting operation is performed by row decoder 14 (see FIG. 2) according to an externally applied address. At time t2, the DRAM array 1 (FIG. 2)
1), one word line DWL is selected, and the potential of the selected word line DWL rises to “H”. One row of memory cells connected to the selected word line DWL are connected to a corresponding DRAM bit line pair DBL (DRAM bit line BL or / BL), and the potential of each DRAM bit line pair DBL is connected to the memory. It changes according to the cell data. FIG. 24 shows a potential change of DRAM bit line pair DBL when a memory cell storing potential "H" is selected.

At time t3, sense amplifier activating signal φSANE rises from ground potential Vss to operating power supply potential Vcc level, and transistor TR2 included in sense amplifier activating circuit SAK is turned on. Thereby, the second sense amplifier included in DRAM sense amplifier DSA is activated, and the bit lines on the lower potential side of DRAM bit line pair DBL are discharged to the level of ground potential GND.

At time t4, sense amplifier activating signal / φSAPE falls from potential Vcc to the level of ground potential GND, and transistor TR1 included in sense amplifier activating circuit SAK is turned on. This allows DR
The first sense amplifier portion included in AM sense amplifier DSA is activated, and the potential of the high-potential bit line of DRAM bit line pair DBL is charged to the operating power supply potential Vcc level.

At time t5, one column select line CSL is selected according to a column select signal from DRAM column decoder 15 (see FIG. 2), and the potential of selected column select line CSL rises to "H". . This gives 2
DRAM bit line pair DBL is connected to local I / O line pair LIO (LIOa and LI) via column select gate CSG.
Ob). Selected DRAM bit line pair D
The potential on BL is transmitted onto local I / O line pair LIO, and the potential on local I / O line pair is precharge potential Vc.
It changes from c / 2.

At time t6, block activation signal φB
A rises to "H" only for the selected row block, and I / O gate IOG is turned on. As a result, the signal potential on local I / O line pair LIO is
The signal is transmitted onto the / O line pair GIO. Here, the selected row block indicates a row block including the selected word line DWL. Designation of the selected row block is performed, for example, by decoding upper two bits of a row address used for DRAM word line selection. The current consumption can be reduced by performing the block division operation in this manner.

On the other hand, in the SRAM, at time ts1, a row selecting operation is performed by SRAM row decoder 21 (see FIG. 2), and one SRAM is selected in the SRAM array.
The RAM word line SWL is selected, and the selected SR
The potential of the AM word line SWL rises to "H". DRA
The row selection operation in M and the row selection operation in SRAM are performed asynchronously. The data of the SRAM cell connected to the SRAM word line SWL is stored in the corresponding SRAM.
It is transmitted on bit line pair SBL. Thereby, SRA
The potential of M bit line pair SBL is equal to precharge potential Vcc /
2 to a potential corresponding to the information stored in the corresponding SRAM cell.

At time t7, data transfer instruction signal φT
DS rises to "H" for a certain period. Before this time t7, the data of the DRAM cell has already been transmitted to global I / O line pair GIO, and SRAM bit line pair SB.
SRAM cells are connected to L. In response to data transfer instruction signal φTDS, bidirectional transfer gate BTG is activated to transmit the signal potential on global I / O line pair GIO onto the corresponding SRAM bit line pair SBL. Thereby, data transmission from the DRAM cell to the SRAM cell is performed.

Time t7 at which data transfer instruction signal φTDS is activated is a time later than both time t6 at which block activation signal φBA rises and time ts1 at which selection of SRAM word line SWL is performed. As long as the relationship is satisfied, time ts1 and time t1 to time t1
6 is arbitrary. In this cycle, data transfer instructing signal φTSD from SRAM to DRAM is maintained at inactive “L”.

At time t8, the potential of the selected DRAM word line DWL falls to "L", and at time ts2
, The potential of the SRAM word line SWL selected falls to "L", and each signal returns to the initial state, thereby completing the data transfer cycle from the DRAM to the SRAM.

As described above, DRAM column decoder 1
5 (see FIG. 2) selects one column selection line CSL in each column block 12. One column selection line C
SL selects two DRAM bit line pairs DBL. D
Data transfer from the RAM to the SRAM is performed in parallel with each column block. Therefore, in the embodiment shown in FIG. 2, 16-bit data is transferred collectively. However, this relationship is for a configuration in which eight column blocks are provided and two DRAM bit line pairs are selected from each column block. The number of bits of data transferred collectively changes according to the number of column blocks or the number of DRAM bit line pairs selected at a time. As a result, an appropriate block size can be set.

As shown in FIG. 24, when drive signal DWL of the DRAM word line falls to an inactive state substantially at time t8, data transfer instruction signal φTDS is accordingly set to “L”.
Is falling. At the time t8, the local I / O
The O line pair LIO and the SRAM bit line pair SBL are disconnected, and the DRAM array and the SRAM array are electrically disconnected. After this time t8, the DRAM unit and the SRA
Operation independent of the M section is enabled. Therefore, FIG.
As shown in FIG. 5, at time t8 ', data transfer instructing signal φT
When DS is made inactive, the word line drive signal DWL still maintains the active state "H" in the DRAM array at this time. At this time, the DRAM cannot be newly accessed from outside, but the SRAM array unit can be accessed from outside.

That is, as shown in FIG.
When the data transfer instruction signal .phi.TDS falls to "L" at 8 ', even if the DRAM array is in the active state, the SRAM array newly accesses after a transition to the standby state at time ts2 after a predetermined time. It becomes possible. Therefore, after this time t8 ',
The SRAM can be accessed regardless of the state of the DRAM. For example, at time t8 ',
Data at the time of a cache miss can also be read from the SRAM array.

It is also possible to access the SRAM by setting a new external address before the DRAM returns from the standby state. This is because SRAM is RA like DRAM.
This is because high speed access is possible after returning from the standby state without any need for the S precharge operation.

In FIG. 25, at time t9 ', D
RAM word line drive signal DWL falls to "L", and at time t10, equalize signal φEQ is activated,
The equalizing and precharging operation of the DRAM bit line pair DBL starts. At this time, the equalizing operation of sense amplifier drive signal lines φSAN and / φSAP is similarly performed. In the DRAM, from time t9 ',
At time t11 after the elapse of 0n seconds, the circuit returns to the standby state including its peripheral circuits. The DRAM array can be accessed only after a predetermined time RAS precharge time has elapsed.
However, in the SRAM array, at time ts2, SR
After setting the AM word line SWL1 to the non-selected state, at time ts3 several n seconds later, another SR
The AM word line SWL2 is selected, and the selected SRA
Access (reading or writing of data) to a memory cell connected to M word line SWL2 can be performed.

From time ts2 when data transfer instruction signal φTDS falls to the inactive "L" state, the SRA
The time ts at which the M word line SWL2 is activated
3 is set to an appropriate value according to the external specification. As described above, before the DRAM returns from the standby state, the SRA
By enabling access to M, a semiconductor memory device that operates at a high speed, particularly a semiconductor memory device with a built-in cache can be obtained.

The selection period of the word line SWL2 of the SRAM is very short because there is no need to perform the column selection operation after the sensing and latching operation of the sense amplifier in the DRAM, and the access to this SRAM at time ts4 is sufficient. Complete. From this time ts3 to time ts4
Is about 10 ns at most in a normal SRAM, and the access to the SRAM is completed when the DRAM is on standby. Such a configuration for accessing the SRAM before the DRAM array returns from the standby state is as follows.
This is made possible by the semiconductor memory device of the present invention, in which the RAM and the DRAM can be accessed by specifying addresses with different addresses.

FIG. 26 is a signal waveform diagram representing an operation during data transfer from the SRAM to the DRAM. The data transfer operation from the SRAM to the DRAM will be described below with reference to FIGS. The operation of the DRAM part
From time t1 to time t6, the DRAM shown in FIG.
Is exactly the same as that at the time of data transfer from the SRAM to the SRAM. Also in the operation of the SRAM portion, the potential of the SRAM word line SWL rises to "H" at the time ts1, which is exactly the same as the waveform diagram shown in FIG.

After time ts1 and time t6, that is, DRAM bit line pair DBL is connected to global I / O line pair GI
O to the SRAM bit line pair SBL.
After the M cell (SMC) is connected, the data transfer instructing signal φTSD is activated for a certain period from time t7 to “H”.
Stand up. In response, the bidirectional transfer gate BTG is activated, and the signal on the SRAM bit line pair SBL is transmitted to the global I / O line pair GIO (GIOa, GIOb) and the local I / O line pair LIO (LIOa, LIOb). Through the DRAM bit line pair DBL via the DRAM. This allows
DR connected to selected DRAM bit line pair DBL
The data of the AM cell is rewritten. That is, S
The data of the RAM cell is transferred to the DRAM cell. During the data transfer cycle from the SRAM array to the DRAM array, data transfer instructing signal φTDS is maintained at inactive “L”.

The data transfer operation shown in FIGS. 24 to 26 is performed when a cache miss occurs when the SRAM array is used as a cache. That is, when the data requested by the CPU as an external processing unit is not stored in the SRAM array, necessary data is transferred from the DRAM array to the SRAM array. At the time of this cache miss, a copy-back operation for transferring data from the SRAM array to the DRAM and a block transfer for transferring desired data from the DRAM array to the SRAM array are performed. The copy back operation and the block transfer operation will be described below.

Referring to FIG. 27A, a case is considered where data D2 requested by the CPU for access is not stored in a corresponding position in the SRAM. Data D1 'is stored in the corresponding position of the SRAM, that is, the cache. When a cache miss to this SRAM occurs, the DR
AM is in a precharge state.

In FIG. 27B, in response to a cache miss instruction signal, a word line (indicated by hatching in the figure) including an area where data D1 'is to be stored is selected in the DRAM. This state is an array active state. In the SRAM, the area of the data D1 'is selected.

In FIG. 28A, transfer instruction signal φT
SD is generated, and SRAM data D1 'is transmitted to a corresponding region of a selected word line of the DRAM.
As a result, the data D1 'is stored in the data area D1 of the DRAM.

In FIG. 28B, after the transfer of data D 'to data area D1 of the DRAM is completed, the DRAM array returns to the precharge state.

In FIG. 29A, a word line (indicated by hatching in the figure) including data D2 requested by the CPU to access is selected in the DRAM.

In FIG. 29B, data D2 included in the selected word line is supplied with data transfer instruction signal φT.
The signal is transmitted to the corresponding area of the SRAM array in response to DS. As a result, the data D1 of the SRAM array becomes the data D
2 will be rewritten. FIGS. 27 (A) to 28 (B) show the copy back, and FIGS. 28 (B) to 29 (B) show the block transfer mode. Here, the reason why the step of FIG. 28B is included in both cycles is that if both are performed subsequently, the DRAM precharge period is considered to be included in both.

In the case of this data transfer method, the precharge period of the DRAM array is interposed, and data transfer is always in one direction. Therefore, the SR
Data cannot be transferred between the AM array and the DRAM array. A data transfer operation in which the data transfer between the DRAM array and the SRAM array is performed at a higher speed by overlapping the data transfer will be described below.

FIG. 30 is a block diagram schematically showing a configuration of a data transfer device according to another embodiment of the present invention. In the data transfer device shown in FIG.
A circuit portion for performing 1-bit data transfer with the AM array is shown. Therefore, the data transfer device shown in FIG.
0 × 16 bidirectional transfer gate circuits are included. Hereinafter, the data transfer device shown in FIG. 30 is referred to as a bidirectional transfer gate circuit for performing 1-bit data transfer.

Referring to FIG. 30, a bidirectional transfer gate circuit includes a gate circuit 1810 connecting SRAM bit line pair SBL, * SBL to latch circuit 1811 in response to transfer control signal φTSL, and a transfer control signal φTLD. In response, the latch data of latch circuit 1811 is changed to global I / O
A gate circuit 1812 for transmitting to the lines GIO, * GIO;
DRAM write enable signal AWDE and SRAM
In response to column decoder output SAY, data on write data bus lines DBW and * DBW are transferred to global I / O line GI
O, * Includes a gate circuit 1813 for transferring to GIO. S
The output SAY of the RAM column decoder selects one of the 16 bits simultaneously selected in the DRAM array block. Therefore, in this case, a configuration in which the lower 4 bits of the column address signal of the DRAM array are applied to the SRAM column decoder is shown as an example.

The bidirectional transfer gate circuit is further activated in response to transfer control signal φDTS, and the global I / O
Amplifier circuit 1 for amplifying data on lines GIO, * GIO
814 and the data amplified by the amplifier circuit 1814 in response to the transfer control signal φTDS.
L, * SBL.

Gate circuit 1810 and latch circuit 18
11 configures a first transfer unit, the gate circuit 1815 and the amplifier circuit 1814 configure a second transfer unit, and the gate circuit 1812 and the gate circuit 1813 configure a third transfer unit.

DRAM write enable signal AWDE
Is generated when a cache miss occurs when an array access cycle and a CPU request data writing. That is, at the rising edge of the clock signal K,
When the chip select signal E # is "L", the cache hit signal CH # is "H", and the write enable signal W # is "L", the transfer gate control circuit 2 shown later
Generated from 62.

When data is written to the DRAM array by gate circuit 1813, SRAM bit line pair SBL,
* Global I / O line GI directly without going through SBL
Write data can be transmitted to O, * GIO. Thus, data can be written at a high speed. Gate circuit 1812 responds to transfer control signal φTLD by
It is used to adjust the timing when data is transferred from the M array to the DRAM array in 64 bits (in the case of 4MCDRM) collectively. Similarly, the gate circuit 1815 connects the DRAM array to the SRAM array from the DRAM array.
It is used for timing adjustment when data transfer is performed collectively for 4 bits. Symbols SBL and GIO indicate one signal line.

FIG. 31 shows an example of a specific configuration of the bidirectional transfer gate circuit shown in FIG.

Gate circuit 1810 is rendered conductive in response to transfer control signal φTSL and N-channel MOS transistors T102 and T103 for amplifying the signal potential on SRAM bit line pair SBL and * SBL.
102, the data amplified at T103 is latched by the latch circuit 18.
N-channel MOS transistor T10 transmitting to transistor 11
0 and T101. Transistor T102 has a gate connected to SRAM bit line SBL, one conductive terminal connected to ground potential Vss, and the other conductive terminal connected to one conductive terminal of transistor T100. The gate of the transistor T103 is an SRAM bit line *
SBL, one of the conduction terminals of which is connected to the ground potential Vss.
And the other conduction terminal is connected to the transistor T101.
Is connected to one of the conductive terminals.

The latch circuit 1811 includes inverter circuits HA10 and HA1 each having an input connected to the other output.
Including 1. The inverter circuits HA10 and HA11
Constitutes an inverter latch. Latch circuit 1811 further includes inverter circuits HA12 and HA13 for inverting latch data of inverter latches (inverter circuits HA10 and HA11).

Gate circuit 1812 has a global I / O
Gate circuit 1812 for transmitting data to line GIO
b and a gate circuit 1812a for transmitting data to global I / O line * GIO. Gate circuit 181
2a is configured by an n-channel MOS transistor T105, and the gate circuit 1812b is configured by an n-channel MOS transistor T106. Transistor T105
And transfer control signal φTLD is applied to the gate of T106.

The amplifier circuit 1814 has a global I / O
N channel MOS for amplifying the potential on line * GIO
Transistor T113 and an n-channel MOS transistor which is turned on in response to transfer control signal φTDS and transmits data amplified by transistor T113 to node N100.
A transistor T112; a p-channel MOS transistor T111 for precharging node N110 to power supply potential Vcc in response to transfer control signal φTDS;
p-channel MOS transistor T11 connected in parallel with transistor T111 between cc and node N100
Contains 0.

Amplifier circuit 1814 further includes an n-channel MOS transistor T117 for amplifying a signal potential on global I / O line GIO, and a transfer control signal φTD.
In response to S, the transistor is turned on, and an n-channel MOS transistor T116 transmitting the signal potential on global I / O line GIO amplified by transistor T117 to node N110, and node N in response to transfer control signal φTDS.
P-channel MOS transistor T114 for precharging 110 to power supply potential Vcc, power supply Vcc and node N
110 includes a p-channel MOS transistor T115 connected in parallel with the transistor T114.

Transistor T110 has its gate connected to node N110, and transistor T115 has its gate connected to node N100. Transistor T1
10 and the transistor T115 constitute a differential amplifier circuit.

Gate circuit 1815 is a gate circuit 1815a for transferring data to SRAM bit line SBL.
And a gate circuit 1815b for transferring data to the SRAM bit line * SBL. Gate circuit 1815a
Includes an n-channel MOS transistor T120 which is turned on in response to transfer control signal φTDS and transmits the signal potential on node N100 to SRAM bit line SBL. Gate circuit 1815b is turned on in response to transfer control signal φTDS, and an n-channel MO transmitting signal potential on node N110 to SRAM bit line * SBL.
Includes S transistor T121.

Gate circuit 1813 includes a gate circuit 1813a for transmitting the signal potential on internal data bus line * DBW to global I / O line * GIO, and a gate circuit 1813a for transmitting the signal potential on internal data bus line DBW to global I / O line * GIO. O line GIO
Includes a gate circuit 1813b for transmitting up. Gate circuit 1813a is connected to output S of the SRAM column decoder.
N-channel MOS transistor T130 which is turned on in response to AY, and DRAM write enable signal AWD
An n-channel MOS transistor T131 which is turned on in response to E is included. Transistors T131 and T130 are connected in series between internal write data bus line * DBW and global I / O line * GIO.

Gate circuit 1813b includes an n-channel MOS transistor T132 turned on in response to the output SAY of the SRAM column decoder, and an n-channel MOS transistor T133 turned on in response to the SRAM write enable signal AWDE. . Transistor T132 and transistor T133 are connected in series between internal data bus line DBW and global I / O line GIO. Next, the operation of the bidirectional transfer gate circuit will be described.

First, a data transfer operation at the time of a cache miss write operation will be described with reference to FIG. In the cache miss write, at the rising edge of the clock signal K, the chip select signal E # and the write enable W # both become "L", and the cache hit signal C
H # becomes "H" (described later). In response, both the DRAM and the SRAM are activated. At this time, the address given to the SRAM and the DRAM is the address given from the CPU.

At time t1, the DRAM completes the precharge cycle and enters the memory cycle. In response, equalize signal φEQ rises to the inactive state of “L”. By the time the DRAM word line DWL is selected in the DRAM, the signal potential on the internal data bus line DBW is determined to a value corresponding to the write data.

When DRAM word line DWL is selected at time t2 and the signal potential on DRAM bit line pair DBL changes, sense amplifier activation signals φSAN and / φSAP are activated at time t3 and time t4, respectively. The signal potential on the DRAM bit line pair has a value corresponding to the read memory cell data.

In the SRAM, at time ts1, SRAM word line SWL is selected, and the data of the memory cell connected by the selected word line SWL is stored in the corresponding SRA.
It is transmitted to M bit line SBL (* SBL). SRAM
When the signal potential on bit line SBL (* SBL) is determined, transfer control signal φTSL rises to “H”, gate circuit 1810 opens, and SRAM bit lines SBL, * SB
The signal potential on L is transmitted to the latch circuit 1811. That is, in the circuit configuration shown in FIG.
100 and T101 are turned on, one of the transistors T102 and T103 is turned on and the other is turned off, and the transistor (T
102 or T103), the “L” potential is transmitted to the latch circuit 1811. Latch circuit 1811 latches the applied "L" signal potential at a corresponding node.

In a DRAM, this latch circuit 18
11 in parallel with the data latch operation by the column selection line CS.
L is selected (time t5), whereby the potential on local I / O line LIO is determined. Then, the potential on local I / O line LIO is transmitted to global I / O line GIO (* GIO) by block select signal φBA (time t6).

When the signal potential on global I / O line GIO (* GIO) is determined, DRAM write enable signal AWDE rises to "H". At this time, the output signal SAY from the SRAM column decoder becomes active,
The gate circuit 1813 provided for one global I / O line of the 16 bits opens. Thereby, the write data appearing on data bus lines DBW and * DBW is transmitted onto global I / O lines GIO and * GIO via gate circuits 1813b and 1813a.

At time t7, global I / O line G
When the signal potential on IO (* GIO) becomes a value corresponding to the write data, transfer control signal φTDS at time t7 '
Rises to “H”. In response, the transistor T
111 and T114 are turned off, and the node N10
0 and N110 are stopped, and transistors T110 and T115 are connected to global I / O line G transmitted through transistors T112 and T116.
The signal potentials on IO and * GIO are differentially amplified.
Thus, the signal potentials of nodes N100 and N110 become potentials obtained by inverting the signal potentials on global I / O lines * GIO and GIO.

For example, now, global I / O line GIO
Consider a case where the upper signal potential is "H" and the signal potential on global I / O line * GIO is "L". At this time, the transistor T117 is turned on, the transistor T113 is turned off, the potential of the node N110 becomes “L”,
The potential of the node N100 becomes “H”. This node N1
The “L” potential of 10 turns on the transistor T110, and the “H” potential of the node N100 turns on the transistor T110.
115 is turned off. Signal potentials at nodes N100 and N110 are differentially amplified and latched by transistors T110 and T115.

In parallel with the amplification operation in amplifier circuit 1814, gate circuits 1815a and 1815b are rendered conductive in response to the rise of transfer control signal φTDS to “H”, and the signal potential on node N100 is set to the level of SRAM.
The signal potential on the node N110 to the bit line SBL is SR
Transmitted onto AM bit line * SBL. At this time, since transfer control signal φTLD is fixed at “L”, gate circuits 1812 a and 1812 b are closed, and the data latched by latch circuit 1811 is
Not transmitted to / O lines GIO, * GIO.

On the other hand, in the DRAM array, write data transmitted on global I / O line GIO is transmitted to DRAM bit line DBL (* DBL) via local I / O line LIO (* LIO). .

At time t8, the memory cycle of the DRAM is completed, a precharge period is started, and at time t9, the DRAM enters a standby state waiting for the next cycle.

In the SRAM, at time ts2, the potential of SRAM word line SWL falls to "L", and
One cycle is completed.

As described above, at the time of cache miss write operation, write data is written to the corresponding memory cell of the DRAM array, and data changed by the external write data is transmitted to the SRAM array. After the completion of the data transfer cycle, the writing of data to the memory cells of the SRAM is completed, and the data can be written at a high speed even in the case of a cache miss.

The operation of the above-described data transfer operation (hereinafter, referred to as a high-speed copy back mode) is schematically shown in FIGS. The data transfer operation in the high-speed copy back mode at the time of this cache miss write will be described below with reference to FIGS.

It is assumed that the CPU issues a request to rewrite data D2 to data D. At that time, the CP of the SRAM
It is assumed that data D1 'is stored in the area requested by U and data D2 is stored in the DRAM array (FIG. 33A).

When such a cache miss write occurs, data D1 'is first transferred to the latch (latch circuit 1811) in the SRAM. In parallel with this transfer operation, in the DRAM, a word line (hatched portion) containing data D2 according to an access from the CPU
Is selected, and write data D is transmitted to data D2 storage area connected to the selected word line (FIG. 33).
(B)). As a result, the data D2 of the DRAM is rewritten to D2 '.

Next, data D2 'rewritten by external write data D in this DRAM is transferred to an area of the SRAM requested by the CPU for access. As a result, the area of the SRAM previously storing the data D1 'is rewritten with the data D2' (FIG. 34A). As a result, the data rewritten by the data D2 is stored in the area of the SRAM requested by the CPU for access. After this transfer is completed, the DRAM enters a precharge state. The SRAM can be accessed in this state (FIG. 34)
(B)).

Next, the data D stored in the latch
1 'is transferred to the area D1 of the DRAM. Next, the operation of transferring data D1 'latched by the latch to the DRAM array will be described.

FIG. 35 is a signal waveform diagram representing a data transfer operation from the SRAM to the DRAM. In FIG. 35, first, at time t1, an array access request is made, and an address (for example, output from a tag memory) designating an area where data D1 'is to be stored is given. Then, from time t1 to time t6, selection of DRAM word line DWL, detection and amplification of memory cell data connected to the selected word line, and local I / O line and global I / O are performed as in the case shown in FIG. / O line GIO (* GI
O) The above data is determined.

At time t7, transfer control signal φTLD is generated, and gate circuit 1812 shown in FIG. 30 is opened. That is, in FIG. 31, the transistor T10
5 and T106 are turned on, and the latch circuit 181 is turned on.
The data latched at 1 is the global I / O line GI
Transmitted on O and * GIO. This global I /
Data transmitted onto O line GIO (* GIO) is applied to column select line CSL via local I / O line LIO (* LIO).
Is transmitted onto the DRAM bit line DBL (* DBL) selected in step (1). As a result, the data D1 in the SRAM
Transfer operation to the DRAM is completed.

During the operation of transferring the data latched by the latch circuit 1811 to the DRAM (copy back operation), the SRAM can be arbitrarily accessed. That is, at this time, the address given to the DRAM and S
The address given to the RAM is an independent address (at the time of this copy-back transfer, data of 16 bits × 4 bits is collectively transferred in the DRAM).
The selecting operation can be performed according to the M address signal Ac. At this time, the gate circuit 1815 outputs the transfer control signal φT.
Since DS is “L” and the transfer control signal φTSL is also “L” and the gate circuit 1810 is closed, DR
The AM array and the SRAM array are separated, and SR
The AM array can be accessed independently without being affected by the data transfer operation to the DRAM array.

FIG. 36 schematically shows a data transfer operation from the latch circuit to the DRAM. FIG. 36 (A)
, The data D1 'is stored in the latch.
In the DRAM, a word line (hatched area) including an area for storing data D1 is selected according to an external address (given from a tag memory or the like).

Next, data D1 'latched by this latch circuit is transferred to region D1 included in the selected word line, and the data in this region changes to D1'. This completes the data transfer from the latch circuit to the DRAM.

Next, the operation at the time of a cache miss read will be described. The operation at the time of this cache miss read is
Except that the DRAM write enable signal AWDE is in the “L” state and the gate circuit 1813 is in the closed state,
This is the same as the operation at the time of cache miss write described above. That is, in this case, as shown in the operation waveform diagram of FIG. 37, first, word lines SWL and DWL are selected in the SRAM array and the DRAM array, and SR
The data of the AM array is latched by the latch circuit 1811 and the data from the DRAM array is
The signal is transmitted to the RAM bit line SBL (* SBL). After the data transfer to the SRAM at time t7, the SRA
Since no precharge operation is required in M,
This transfer data can be read immediately. Therefore, a data write operation and a data read operation can be performed in the same cycle time at the time of a cache miss. The data transfer operation from the latch circuit 1811 to the DRAM is the same as the operation at the time of the cache miss write described above (see FIGS. 35 and 36).

Now, the SR specified by the address from the CPU
Data D1 'is stored in the area of the AM array.
It is assumed that the CPU is requesting data D2. At this time, the DRAM and the SRAM are now in a standby state (FIG. 38A).

When such a cache miss occurs,
First, in the SRAM, an SRAM word line is selected, and data D1 'is latched (latch circuit 1811).
Transferred to In parallel with the latch operation, in the DRAM, a word line (hatched portion) including data D2 is selected according to an address from the CPU (FIG. 38B).

Next, data D2 included in the selected word line of this DRAM is transmitted to the SRAM via amplifier circuit 1814 and gate circuit 1815, to the area where data D1 'was stored earlier in the SRAM. Latch circuit 1811 is in a state of latching data D1 '. SR
In the AM, the data D2 transferred from the DRAM can be immediately read (FIG. 39A).

After data transfer from DRAM to SRAM,
The DRAM temporarily shifts to a precharge state in order to replace data D1 with data D1 '. The area for storing the data D1 is the area for storing the data D1 'stored in the SRAM (FIG. 39B).

After the precharge is completed in the DRAM, a word line (hatched area) including data D1 is selected (FIG. 40A). During this word line selection cycle (array active cycle), the SRAM
Can be accessed from outside.

The data D1 'latched by the latch (latch circuit 1811) is transferred to an area for storing data D1 included in the selected word line of the DRAM. Thus, data D1 in the DRAM is rewritten with data D1 'previously stored in the SRAM (FIG. 4).
0 (B)).

As the address given from the outside, D
In the RAM, when a word line is selected when transferring data to the SRAM, the address is from the CPU, and when the word line is selected when receiving data from the latch circuit, the address is from an external, for example, a tag memory.

FIG. 41 is a diagram schematically showing a configuration of a bidirectional data transfer device according to still another embodiment of the present invention. FIG. 41 shows a bidirectional transfer gate circuit related to the transfer of 1-bit data in the bidirectional data transfer device, as in FIG. 41, portions corresponding to the portions of the circuit shown in FIG. 30 are denoted by the same reference numerals.

Referring to FIG. 41, the bidirectional data transfer circuit has an SRAM bit line pair SBL, * SBL and internal write data transmission lines DBW, * in addition to the structure of the bidirectional data transfer circuit shown in FIG. And a gate circuit 1817 provided between the gate and DBW. This gate circuit 1817 has an SR
Opened in response to the output SAY of the AM column decoder and the SRAM write enable signal SWDE. SRAM
The write enable signal SWDE is a signal generated at the time of writing data to the SRAM, and is generated when the write enable signal W # is in the active state of "L" in both a cache hit and a cache miss.

FIG. 42 shows an example of a specific structure of the bidirectional transfer gate circuit shown in FIG. In FIG. 42, gate circuit 1817 has an internal write data bus line DB
Gate circuit 1817a for transmitting write data on W to SRAM bit line SBL, and write data bus line * D
Includes gate circuit 1817b for transmitting write data on BW to SRAM bit line * SBL. Gate circuit 1
817a is an n-channel MOS transistor T which is turned on in response to the output SAY of the SRAM column decoder.
141 and an n-channel MOS transistor T which is turned on in response to the SRAM write enable signal SWDE.
140.

Gate circuit 1817b includes an n-channel MOS transistor T143 turned on in response to the output SAY of the SRAM column decoder, and an n-channel MOS transistor T142 turned on in response to the SRAM write enable signal SWDE. Gate circuit 1
Both 817a and 1817b transfer data on internal data bus lines DBW and * DBW to SRAM bit lines SBL and * SBL when output SAY of SRAM column decoder and SRAM write enable signal SWDE attain an active state of "H". Communicate to The other circuit configuration is the same as the circuit configuration shown in FIG. Next, a data transfer operation from the DRAM to the SRAM at the time of cache miss write will be described with reference to an operation waveform diagram of FIG.

Until time t7, an operation similar to that of the bidirectional transfer gate circuit shown in FIGS. 30 and 31 is performed, data from SRAM is latched in latch circuit 1811, and data from the DRAM array is read. Is transmitted to the global I / O line GIO (* GIO).

At time t7, transfer control signal φTDS
Rises to "H", amplifier circuit 1814 and gate circuit 1815 operate, and global I / O lines GIO,
* Amplify the signal potential on GIO to generate SRAM bit line pair S
Transmit on BL, * SBL. In parallel with this transfer operation, the DRAM write enable signal AWDE rises to “H”, the gate circuit 1816 is opened, and the write data on the write data lines DBW and * DBW is
/ O line GIO, transmitted to * GIO. This allows
Write data is written to a selected memory cell in the DRAM array.

DRAM using transfer control signal φTDS
SRAM write enable signal SWDE rises to "H" in parallel with the data transfer operation from memory cell to SRAM, gate circuit 1817 (1817a, 1817b) is opened, and write data on write data bus lines DBW, * DBW To the SRAM bit lines SBL, * SBL.
As a result, the signal potential on the SRAM bit lines SBL, * SBL is determined to be the signal potential corresponding to the value of the write data.

Here, DRAM write enable signal A
The timing of generating the WDE and the SRAM write enable signal SWDE is determined by the transfer control signal φTDS
Any time may be used as long as it is a time after the data transfer operation from the AM to the SRAM is started.

According to the structure of the bidirectional transfer gate circuit shown in FIGS. 41 and 42, the write data on the internal write data bus line is directly transferred to SRAM via gate circuit 1817.
It is transmitted to bit lines SBL and * SBL. Therefore, when the write data is transferred from internal data bus lines DBW, * DBW to the DRAM and the write data is transferred from the DRAM to the SRAM, the access time of the DRAM is relatively reduced. When the length is shortened, the time margin for transmitting the write data through such a path is reduced, and the data rewritten by the write data may not be transmitted to the SRAM without fail. In such a case, gate circuit 1817 is used to directly access SRA from internal write data bus lines DBW and * DBW.
By employing a configuration for transmitting data to M bit lines SBL and * SBL, data rewritten with write data can be reliably transmitted to SRAM.

FIGS. 44 and 45 correspond to FIGS.
From the DRAM of the bidirectional transfer gate circuit shown in FIG.
FIG. 4 is a diagram schematically showing an operation of transferring data to a device. Hereinafter, this data transfer operation will be briefly described with reference to FIGS. 44 and 45.

First, as in FIG. 33A, the case where the CPU wants to write data D2 is considered. At this time, both the DRAM and the SRAM are in a precharged state (FIG. 44A).

In FIG. 44B, a word line (hatched area) including data D2 is selected in the DRAM. In the SRAM, data in an area including data D1 'is transmitted to the latch. This data D1 'is data that should not be rewritten and should be transferred to the data D1 storage area of the DRAM.

Referring to FIG. 45A, during the operation of transferring the data D2 of the DRAM to the corresponding memory cell of the SRAM,
Write data D is transferred to data D2 storage area of this DRAM and to data D1 storage area of SRAM. Thereby, the data D2 of the DRAM and the SRAM
Are both data D2 'rewritten with the write data D. That is, the write data D is written to the SRAM in parallel with the data transfer from the DRAM to the SRAM, and the data is written to the DRAM.

In FIG. 45B, in order to transfer the latched data D1 'to the area for storing data D1, the DRAM returns to the precharge state. In this state, the CPU can access the SRAM.

The operation of transferring data D1 'latched by the latch (latch circuit 1811) to the storage area of data D1 of the DRAM is the same as that described above with reference to FIG. 36, and description thereof will not be repeated. .

In the bidirectional data transfer circuit shown in FIGS. 41 and 42, both gate circuits 1816 and 1817 are closed during a cache miss write operation. Similar to the data transfer operation described with reference to the bidirectional transfer gate circuit described above, only the data transfer operation schematically shown in FIGS. 38 to 40 is performed, and description thereof will not be repeated.

By providing gate circuit 1817 as described above, even if there is no time to transfer the data from the DRAM to the SRAM after rewriting it with the write data D, the data in the SRAM can be written with the write data D. Rewritten reliably.

By using the above-described bidirectional data transfer device, it is possible to cope with a so-called “write-through mode”. In the write-through mode, at the time of cache access, the data written in the SRAM is
This is an operation mode in which data is also written to a memory cell corresponding to AM.
In other words, at the time of a cache hit when data exists in the SRAM, the write-through is performed by executing the above-described cache miss write operation. Further, at the time of a cache miss write operation in which no data exists in the cache, the previous cache miss write operation may be directly executed to directly write data to the DRAM array.

For direct access to the DRAM, data can be directly written to the DRAM by activating only the DRAM write enable signal AWDE.
When writing data only to the SRAM at the time of a cache hit, if it is not necessary to execute the write-through mode, only the SRAM write enable signal SWDE is activated.

If data transfer is performed using the data transfer device shown in FIGS. 30 and 31 or FIGS. 41 and 42, in the DRAM, a precharge period is required once to receive latch data. And data can be transferred between the SRAM and the DRAM at a high speed. In the conventional copy-back and block transfer mode cycles, the SRAM can be accessed only after the block transfer has been performed. Using this high-speed copyback mode,
In the first data transfer cycle, DRAM
Data transfer to M is performed, and conventional block transfer is performed first. Therefore, the SRAM can be directly accessed after the data is transferred to the SRAM, and a semiconductor memory device with a built-in cache that operates at higher speed can be realized.

In this bidirectional data transfer device, since data is rewritten to the SRAM in parallel with the data transfer, the cache miss read operation and the cache miss write operation are executed in the same cycle time. can do.

This high-speed copy-back mode is described as an example of a case where the high-speed copy-back mode is applied to data transfer between an SRAM array and a DRAM array at the time of a cache miss in a semiconductor memory device with a built-in cache. However, even when data is mutually transferred between two memory cells such as a normal SRAM array and a DRAM array, data can be exchanged at a high speed similarly, and the data transfer efficiency is greatly improved. Can be. That is, this bidirectional data transfer device is not limited to a semiconductor memory device with a built-in cache as shown in FIG. It can be applied as a transfer device.

[Distribution of Address] FIG. 46 is a diagram showing an example of a mode of connecting addresses to the DRAM and the SRAM. In the structure shown in FIG. 46, access to the DRAM array is performed via bit line pair SBL or a bidirectional transfer gate circuit of the SRAM array. In the case of this configuration, the column selection signal CD from the SRAM column decoder 22 provides a DRAM array column selection signal and a SRAM array column selection signal.

In FIG. 46, a DRAM address buffer 252a stores external DRAM addresses Aa0 to Aa0.
Aa9, and receives the internal address int. Aa is generated.
The DRAM row decoder 14 receives the internal address in
t. Aa, decodes the internal row address, and
Word line drive signal DWL for selecting a word line from the array
Occurs. The DRAM column decoder 15 is a DRAM
A signal C for receiving a part of the internal column address from address buffer 252a and selecting a column selection line from the DRAM array
Generate SL. This DRAM address buffer 252
The remainder of the internal column address from a is provided to buffer 29. The buffer 29 is an SRAM buffer 252
b and transmits the received internal column address to the SRAM column decoder 22. As will be described later in detail, when accessing the DRAM array, the SRAM buffer 25
The internal column address for column selection of the SRAM array is not generated from 2b. In this case, buffer 29 receives the internal column address from DRAM address buffer 252a, and
The signal is transmitted to the RAM column decoder 22.

The SRAM row decoder 21 receives the internal row address from the SRAM buffer 252b,
SRAM word line drive signal S for selecting one row from the array
Generate WL. According to the structure shown in FIG. 46, the column decoder output SAY applied to the bidirectional transfer gate circuits previously shown in FIGS. 31 and 42 becomes the SRAM decoder output CD. According to the configuration shown in FIG. 46, in the data input / output configuration shown in FIG. 12, column selection signals DYi, DYj and SRAM column selection signals SYLi,
This is equivalent to SYLj.

FIG. 47 is a diagram showing another configuration example of the address input / output unit. In the configuration shown in FIG.
In response to a cache hit instruction signal CH and a DRAM array access instruction signal CI instead of the buffer 29 shown in FIG. 19, passes either the internal column address from the DRAM address buffer 252a or the internal column address from the SRAM address buffer 252b. Multiplexer 3
0 is provided. Cache signal CH and DRAM array access instruction signal CI will be described later in detail. Briefly, when the cache hit instruction signal CH is generated, access to the SRAM array is permitted and DR
Data writing / reading by accessing the AM is prohibited. When a DRAM array access instructing signal (cache access inhibit signal) CI is generated, data writing / reading by accessing a memory cell of the DRAM array is performed.
Reading is allowed.

Therefore, multiplexer 30 outputs signal C
H occurs, the SRAM address buffer 252
b to select the internal column address and transmit it to the SRAM column decoder 22. Further, the multiplexer 30 has a DR
When the AM array access instruction signal CI is generated, D
The internal column address from RAM address buffer 252a is selected and transmitted to SRAM column decoder 22. Also in the configuration shown in FIG. 47, SRAM column decoder 22 has a configuration used for both column selection of the DRAM array and column selection of the SRAM array.

The configuration for allocating the addresses shown in FIGS. 46 and 47 is merely an example,
Decoding of internal column address of AM array and SRAM
A structure in which decoding of an internal column address of the array may be performed.

FIG. 48 shows an internal data transmission line pair and an SRAM.
FIG. 9 is a diagram illustrating another configuration example of a connection mode with an array. FIG.
In the configuration shown in FIG. 2, the SRAM sense amplifier SSA
Are provided for each SRAM bit line pair SBL. In the configuration shown in FIG. 48, SRAM sense amplifier SSA includes a plurality of SRAM bit line pairs SBL, * SB
One is provided for L. Each SRAM bit line pair SB
A select gate circuit 302 is provided for L and * SBL. Column select signal CD is applied to select gate circuit 302. This column selection signal CD is supplied from the SRAM column decoder shown in FIGS. 46 and 47. Internal data line pairs include an internal write data line 251a 'for transmitting write data and a read data transmission line 251 for transmitting read data to an output buffer circuit.
b '. Internal write data transmission line 251a 'includes a pair of complementary data lines DBW and * DBW. Complementary data from the input buffer circuit is transmitted to internal data lines DBW and * DBW. This internal write data line 251
a 'is connected to the write circuit 303.

The write circuit 303 includes cross-connected n-channel MOS transistors T301, T302, T30
3, T304. Transistors T302 and T3
03 is connected to the internal data line DBW. Gates of transistors T301 and T304 are connected to internal data line * DBW. Complementary write data from write circuit 303 is transmitted to select gate circuits 302 via data lines DBWa and * DBW. Transistor T3
01 and T302 transmit power supply potential Vcc when in the ON state. Transistors T303 and T304 transmit ground potential Vss when turned on.

For example, consider the case where data of "H" is transmitted to internal data line DBW. At this time, "L" data is transmitted to internal data line * DBW. The transistors T302 and T303 are turned on. Therefore, data of "H" is transmitted from write circuit 303 to internal data line DBWa via transistor T302, and the other internal data line * DBWa is supplied to transistor T302.
“L” data is transmitted via 303.

At the time of data reading, data of "L" is transmitted from input buffer circuit to both internal write data lines DBW and * DBW, whereby the output of write circuit 303 enters a high impedance state. At this time, the sense amplifier SSA is activated, and the internal data lines DBWa, *
After the data transmitted to DBWa is amplified by sense amplifier SSA, it is transmitted to the output buffer circuit via internal read data transmission line 251b '.

As shown in FIG. 48, internal data line 2
By separately providing the write data transmission line 251a 'and the read data transmission line 251b' as 51, the layout design of the input / output circuit can be simplified as compared with the configuration in which data writing / reading is performed via a common internal data bus. It will be easier.

[Refresh Operation] The DRAM array
A dynamic memory cell is a constituent element, and its stored data needs to be refreshed periodically or within a predetermined period. Next, the refresh operation of the semiconductor memory device with a built-in cache will be described.

Referring to FIG. 1, a refresh instruction signal REF # is externally applied. This semiconductor storage device
When the refresh instruction signal REF # from the outside is set to the active state of "L" at the rising of the internal clock K, the refresh is automatically performed internally.

In FIG. 1, a circuit 290 for refreshing includes an auto refresh mode detecting circuit 291 for detecting that auto refresh has been designated in response to an internal refresh instruction signal REF from control clock buffer 250. A refresh control circuit 292 that generates various control signals in response to a refresh request from the auto refresh mode detection circuit 291 and supplies the control signals to the counter 293 and the multiplexer circuit 258.
including. In response to the refresh instruction signal from refresh control circuit 292, counter circuit 293 supplies the count value stored therein to multiplexer circuit 258 as a refresh row address indicating the row to be refreshed.

The multiplexer circuit 258 selects a refresh row address from the counter circuit 293 in response to the switching control signal MUX from the refresh control circuit 292, and supplies it to the DRAM row decoder 102. This internal refresh instruction signal REF is also applied to DRAM array drive circuit 260. DRAM array drive circuit 2
Numeral 50 is activated when internal refresh instruction signal REF is applied, and executes an operation related to row selection in DRAM array 101.

The refresh control circuit 292 increments the count value of the counter circuit 293 by one each time the refresh instruction signal REF is supplied when refresh is completed. Refresh control circuit 292 renders switching control signal MUX inactive at the completion of refreshing, and multiplexer circuit 258 causes internal buffer int for internal DRAM from address buffer circuit 252 to output.
-Aa is selected and transmitted to the DRAM row decoder 102.

FIG. 49 is a diagram functionally showing transfer gate control circuit 262. Transfer gate control circuit 262 generates signals φTDS and φTSD for controlling the transfer operation of bidirectional transfer gate circuit 210 (3, BTG) in response to internal control signals E, CI, W and CH. Transfer cache control circuit 262 does not generate transfer control signals φTDS and φTSD when cache hit signal CH is active. However, when array access instruction (cache inhibit) signal CI is active, write enable signal at that time is activated. Control signals φTDS and φTSD are sequentially generated according to the state of W.

At this time, the transfer gate control circuit 262
Internal refresh instruction signal REF may be applied, and transfer gate control circuit 262 may be rendered inactive when internal refresh instruction signal REF is applied. Since a refresh instruction signal REF # is externally applied, transfer gate control circuit 262 need not particularly receive refresh instruction signal REF if an external specification is set so that array access instruction signal CI is not generated at that time. Absent. However, when the refresh operation is performed in the DRAM array, it is necessary to reliably separate the SRAM array from the DRAM array. If a configuration is provided in which the transfer gate control circuit 262 is disabled in response to the internal refresh instruction signal REF, S
The RAM array and the DRAM array are surely electrically separated, and the SRAM array can be accessed from the outside.

As a configuration of such a transfer gate control circuit 262, a configuration is provided in which, when one of the cache hit signal CH and the refresh instruction signal REF is activated, the transfer gate control circuit 262 is disabled. Just do it. More preferably, chip enable signal E is inactive, or cache hit signal CH and refresh instruction signal R
What is necessary is just to provide a gate circuit in which the selection gate control circuit 262 is disabled when any of F is in an active state. In other cases, transfer control signals φTDS and φTSD are generated at predetermined timings in accordance with control signals CI and W.

FIG. 50 shows a functional configuration of DRAM array drive circuit 260 shown in FIG. The DRAM array driving circuit 260 includes a row selection system driving circuit 260a for driving a circuit related to row selection of the DRAM array and a DRAM.
A column selection system driving circuit 260b for driving a circuit related to column selection of array 1 is included. The row selection driving circuit 260a
Various control signals φEQ, / φSAPE, φSANE, and DWL are generated at predetermined timings in response to the internal control signals E, CH, CI, and REF. At this time, the internal control signal int. * RAS may be generated. The column selection driving circuit 260b controls the control signals E, CH,
DRA at predetermined timing in response to CI and REF
A signal CDA (corresponding to internal control signal int. * CAS) for driving M column decoder 15 is generated.

The column selection driving circuit 260b generates the column decoder activation signal CDA at a predetermined timing if the refresh instruction signal REF is inactive when the row selection driving circuit 260a is activated. I do.
The column selection driving circuit 260b supplies the refresh instruction signal R
When the EF is activated, it is disabled. Thereby, the column selecting operation in the DRAM is prohibited.

With this configuration, when the internal refresh instruction signal REF is activated, the refresh operation in the DRAM array can be executed independently of the operation of the SRAM array.

Auto refresh mode detection circuit 291, refresh control circuit 292 and counter circuit 293 shown in FIG. 1 operate in response to refresh instruction signal REF, and operate independently of command register 270. Therefore, the command register 27
0 in parallel with the command mode setting to 0
01 can be refreshed. That is,
Command register 270 generates command data CM and outputs data input / output control circuit 272 and input / output buffer +
This is because the data is only given to the output register block 274, and the held data has no effect on the memory cell selecting operation in the DRAM array 101.

The data setting in the command register 270 is performed as described later in detail with reference to a timing chart.
It is completed in one cycle of the external clock signal K. On the other hand, D
The refresh operation in the RAM array requires n cycles. This is because the operation speed of the DRAM 100 is lower than the speed of the clock K. Thus, in this case, one clock cycle is simply effectively utilized. However, if the external clock K is
If the cycle is delayed according to the operation mode,
If the cycle is equivalent to one memory cycle of DRAM 100, data setting to command register 270 and DR
Refreshing of the AM array 101 can be performed in parallel. Such a change in the cycle of external clock K is performed, for example, when the DRAM is in a standby state and when the storage device does not require high-speed operation but rather requires low power consumption. If the operation speed of the semiconductor memory device is reduced by increasing the cycle of the clock K, the current consumption can be reduced in accordance with the decrease in the operation speed. The period of the external clock K may be lengthened when only the DRAM is accessed.

With the above configuration, a CDRAM having the following features can be realized.

(1) In the CDRAM according to the present invention, a DRAM memory array as a main memory and an SRAM array as a cache memory are integrated on one chip,
The two memories are connected via an internal bus dedicated to data transfer different from the internal common data bus. As a result, the block transfer between the DRAM array and the SRAM array (cache) is completed in one clock cycle. In the following description, when simply called an array, DRA
Assume that an M array is shown. With this, the conventional standard DR
The performance of the system can be greatly improved as compared with a cache memory system using an AM and a standard SRAM.

(2) DRAM memory array and SRAM
Each array can be accessed by a different address. Therefore, it is possible to support various mapping methods such as a direct mapping method, a set associative method, and a full associative method.

(3) This CDRAM uses the external clock K
Are operating synchronously. Therefore, it is possible to prevent a cycle time delay due to an address skew or the like as compared with a method of generating an internal clock signal using an address change detection circuit, and to execute accurate control.

(4) Array addresses (addresses for DRAM) Aa0 to Aa9 and cache addresses (SRA
M address) Ac0 to Ac11, data input / output D0
To D3 or DQ0 to DQ3, write enable signal W
#, A cache hit signal CH #, a chip select signal E #, a refresh signal REF #, a cache inhibit signal CI #, and a command register signal CR #.
Is captured at the rising edge of

(5) Since the array address is fetched in a multiplex system, the number of pins for the array address can be reduced, and the mounting density of the CDRAM can be increased.

(6) The addresses of the array and the cache are independent, and only access to the cache is performed at the time of a cache hit, so that high-speed cache hit access can be realized.

(7) Regardless of the timing of the external clock K, data can be read at an arbitrary timing by the output enable signal G #, thereby enabling asynchronous bus control in the system.

(8) The command register 270 allows the user to arbitrarily specify the output specifications (transparent, latch, register) and the I / O configuration (input / output pin separation, masked write). If the register output method is used, output data at the address specified in the previous cycle appears at the rising edge of the external clock K.
Such a data output mode is suitable for pipeline applications.

In the latch output method, the output data of the address specified in the previous cycle is output at the timing when invalid data is output. As a result, no invalid data is output, and only valid output data is always obtained. In this latch output mode, C
A sufficient period can be taken for the PU to capture the output data.

(9) The data write operation is started by the rising edge of the external clock K, and the end of this write is automatically terminated internally by a timer or the like.
Therefore, the end of the write operation does not need to be set by, for example, an external write enable signal W #, and the timing of the system can be easily set.

(10) A refresh instruction signal REF # designating auto-refresh can be externally provided. Thus, the DRAM array can be easily auto-refreshed at a desired timing.

(11) Also, as described above, 44-pin 300 mil. The CDRAM of the present invention can be accommodated in a TSOP package type II. This TSOP
The package type II is an extremely thin rectangular package, and a system with a high mounting density can be constructed.

FIG. 51 shows a first preferred CDRA of the present invention.
FIG. 4 is a diagram showing a list of operation modes provided in M and states of control signals for designating each operation mode. CDR
The operation modes of the AM are external control signals E #, CH #, CI
#, CR #, W #, and REF #. In FIG. 51, “H” indicates a high-level signal potential, “L” indicates a low-level signal potential,
“X” indicates arbitrary (don't care DC). As shown in FIG. 51, the operation mode of the CDRAM
Mode in which the DRAM is in a standby state, an array refresh mode in which DRAM arrays are automatically refreshed, a CPU (Central Processing Unit) and a cache (SRA).
M), a data transfer mode between the CPU and the array, a data block transfer between the cache and the array, a special mode setting mode for the command register, and the like. Combinations of signal states and timings for setting each operation mode will be described later in detail with reference to operation waveform diagrams. In FIG. 51, the write enable signal W # is set to “H / H” during data transfer between the CPU and the command register.
In this operation mode, the write enable signal W # is set to "H" or "L", and the "H" or "L" state is designated as "L". It is used for

"Command register" FIGS. 52 and 53
FIG. 3 is a diagram showing the contents of a command register 270 shown in FIG. 1 and a method of selecting the contents. Command register 27
0 is eight registers RR0-RR3 and WR0-WR
3 inclusive. To select this register, the write enable signal W # and the 2-bit command addresses Ar0 and A
The combination of r1 is used. By setting the external write enable signal W # to "H" at the rising edge of the external clock K, one of the registers RR0 to RR3 is selected. The register RR0 is selected by setting both the command addresses Ar0 and Ar1 to "0". The register RR1 is selected by setting the command address bit Ar0 to "1" and setting the command address bit Ar1 to "0". If register RR0 is selected, it indicates that the masked write mode has been set (this masked write mode is also the default). When the register RR1 is selected, it indicates that the D / Q separation mode has been set.

If the write enable signal W # is set to "L" at the rising edge of the external clock K and both the command addresses Ar0 and Ar1 are set to "0", the register WR0 is selected. This register WR0 is
As shown in the figure, the data input terminal DQ0 (D0) at that time
The output mode is set to one of transparent, latch, and register by the combination of data of DQ3 (D3).

The details of each of the output modes have been described above. When register WR0 is selected, input data D2 and D3 (DQ2 and DQ3) are both set to "0". In this state, if the input data D0 is set to "0" and the input data D1 is set to an arbitrary value, the transparent output mode is set. If the input data D0 is set to "1" and the input data D1 is set to "0", the latch output mode is selected. If the input data D0 and D1 are both set to "1", the register output mode is selected. The remaining registers are used for any extended functions.

FIG. 54 shows a CDRAM 600 according to the present invention.
FIG. 2 is a block diagram illustrating a configuration of a system when a direct mapping type cache system is configured by using FIG. In FIG. 54, this cache system
A controller 650 for controlling access to the CDRAM 600 in addition to the DRAM 600;
M600 and a CPU for inputting and outputting data and performing desired data processing. FIG. 54 shows only the configuration of an address at the time of a cache access request output from the CPU. This CPU assumes 32 bits. This cache system further comprises a CDRAM6
Address multiplexing circuit 700 for multiplexing row address and column address to array 00
Is provided. CDRAM 600 representatively shows only a portion related to cache access.

The controller 650 decodes an 8-bit set address A6 to A13 from the CPU, a valid bit memory 654 indicating which tag is valid in response to the output of the decoder 652, and a SR
A tag memory 656 for storing a tag address of data stored in the AM 200 is included. SRAM 200 is 4K ×
It has a 4-bit configuration and has 256 tags. For this reason, the tag memory 656 has an 8-bit × 256 configuration. The effective bit memory 654 stores the 256
A 1-bit × 256 configuration is provided to indicate which of the tags (sets) is valid. Decoder 652
Decodes the set addresses A6 to A13 and makes any bit of the valid bit memory 654 valid.

Controller 650 further receives addresses A22 to A31 from the CPU as a chip select signal, determines whether or not the corresponding CDRAM 600 is designated, and activates in response to the output of decoder 670. The tag address from the tag memory 656 and the tag addresses A14 to A2 from the CPU
1 and a comparator 658 which determines a cache hit / miss by comparing the tag address from the tag memory 656 and any one of the tag addresses A14 to A21 from the CPU according to the cache hit / miss. A selector 672 provided to the circuit 700 is included.
The selector 672 also stores the tag address given from the CPU at a corresponding position in the tag memory 656 upon a cache miss.

Next, the operation will be briefly described. CPU
Generates 30-bit addresses A2 to A31 on the data bus 620 when the user wants to access the CDRAM 600. Of the 30-bit addresses on the common data bus 620, addresses A22 to A31 are used as chip select signals as decoders 670 in the controller 650.
Given to. The decoder 670 decodes the addresses A22 to A31 as the chip select signal, and determines whether or not a corresponding CDRAM is requested to access. When it is determined that an access request has been made to CDRAM 600, chip select signal E # is generated from decoder 670 and applied to CDRAM 600. The comparator 658 is activated by the chip select signal from the decoder 670.

Decoder 6 included in controller 650
52 receives and decodes the addresses A6 to A13 among the addresses transmitted from the CPU onto the address bus 620 as set addresses. The decoder 652 that decodes the 8-bit set address sets the corresponding bit of the valid bit memory 654 to a valid state in order to select one of the 256 tags. From the tag memory 656, an 8-bit address indicating a tag corresponding to a valid bit of the valid bit memory 654 is read and applied to the comparator 658. The comparator 658 stores the tag address from the tag memory 656 and C
The tag addresses A14 to A21 output from the PU are compared. If the two match, the comparator 658 indicates a cache hit, so that the cache hit signal CH
# Is dropped to “L” and given to CDRAM 600. On the other hand, if they do not match, comparator 658 generates a cache hit signal CH # of "H" to indicate a cache miss (miss hit).

In a cache hit, CDRAM6
At 00, the following operation is performed. Operation control at this time is performed by a control signal from control clock buffer 250 and SRAM array drive circuit 264 (see FIG. 1). The SRAM row decoder 202 selects one of 256 sets in response to addresses A6 to A13 from the CPU. That is, one row (each SRA
(A total of four in each of the M array blocks) is selected. Thus, a 16-bit SRAM cell is selected in each SRAM array block of the SRAM 200. The SRAM column decoder SCD203 decodes the block addresses A2-A5 from the CPU,
One bit is selected from the bit memory cells and connected to the data input / output terminal. FIG. 54 shows output data Q at the time of hit read.

The operation at the time of a mishit will be described below. In this case, the SRAM 200 does not store data requested by the CPU to access. Controller 650
In, the selector 672 gives the corresponding tag address stored in the tag memory 656 to the multiplex circuit 700 in response to the mishit instruction signal from the comparator 658. The selector 672 then sets C
8-bit tag address A14 given from PU
To A21 as new tag addresses in the tag memory 656.
Is stored in the corresponding position.

In CDRAM 600, in this cycle, copy back, that is, DR from SRAM 200 is performed.
Batch transfer of 16 bits to AM 100 is performed. S
In RAM 200, the address A6-
SRAM row decoder (SRD) 202 according to A13
The data of 16 bits × 4 selected by the address A6-A13 output from the CPU and the selector 67
DR according to the 8-bit tag address output from 2
The row and column selection operation is performed in AM 100, and the data is stored in the corresponding position of the selected 16-bit × 4 DRAM cell.

In the next operation cycle, CDRAM 60
0 is the address A6-A21 output from this CPU.
16-bit × 4 DR in the DRAM 100
An AM cell is selected, and the 16-bit × 4 data is transferred to the SR row decoder (SRD) 202 selected by the SRAM row decoder (SRD) 202 in accordance with addresses A6-A13 from the CPU.
The data is written into a 16-bit × 4 memory cell corresponding to AM200.

As described above, for the SRAM, addresses A2 to A5 are set as block addresses, addresses A6 to A13 are set addresses and addresses A14 to A21 are set as tag addresses, and for DRAMs, addresses A6 to A11 are set as column addresses. By using the addresses A12 to A21 as row addresses, a direct mapping method between the DRAM 100 and the SRAM 200 can be realized.

FIG. 55 is a block diagram showing the configuration of a 4-way set associative system using the CDRAM of the present invention. CDRAM 600 has the same configuration as that shown in FIG.
M100, and a clock control circuit 250 '. The clock control circuit 250 'includes the control clock buffer 250, the SRAM array drive circuit 264, and the DRAM shown in FIG.
An array drive circuit 260 is included. A circuit configuration for controlling data input / output is not shown to simplify the drawing.

The controller 750 includes a decoder 752,
Valid bit memory 754, tag address memory 756,
Comparator 758, decoder 770 and selector 7
72. To accommodate four ways, the valid bit memory 754 includes four memory planes each having a 1 bit × 64 configuration, and a tag address memory 75
6 also comprises four memory planes each having an 8 bit × 64 configuration. Similarly, one comparator is provided for each memory plane of the tag address memory 756 in order to select one of the four ways, and a total of four comparators are provided. In the 4-way set associative method, 256 rows of the SRAM 200 are divided into 4 ways, so that the number of sets is 64.

An address having the following structure is transmitted onto address bus 620 from the CPU. Address A22
To A31 are chip select addresses, address A
14 to A21 are tag addresses, addresses A12 and A13 are way addresses, addresses A6 to A11.
Are set addresses, and addresses A2 to A5 are block addresses. Addresses A6 to A11 and addresses A12 to A21 are used as column addresses and row addresses for DRAM 100, respectively. A multiplex circuit 700 for multiplexing a row address and a column address is provided for the DRAM 100 of the CDRAM 600. Next, the operation will be described.

Addresses A6-A11 from the CPU are provided to decoder 752 as set addresses, and addresses A22-A31 are provided to decoder 770 as chip select addresses. The decoder 752 decodes the set addresses A6-A11, and sets a valid bit related to the corresponding set in the valid bit memory 754 to a valid state. Thereby, one set (4 ways) is selected. The decoder 770 decodes the chip select addresses A22-A31,
It is determined whether an access request to 00 has been issued. When the CDRAM 600 is requested to access, the decoder 770 activates the chip select signal E # to “L” and activates the comparator 758. The comparator 758 is provided in the valid bit memory 7
The tag address memory 75 is referred to by referring to the 54 effective bits.
6, the corresponding 4-way tag address is read, and the read tag address and the address A14-A from the CPU are read.
Compare 21. When a match is found, comparator 758 outputs way addresses W0 and W1 indicating the way in which the match was found, and sets cache hit signal CH # to "L" to indicate a cache hit.
Fall to If no match is found in comparator 758, cache hit signal CH # is set to "H" indicating a mishit.

In the case of a cache hit, the way addresses W0 and W1 from the controller 750 and the addresses A6-A11 from the CPU are stored in the SRAM row decoder 202.
And a 16-bit × 4 SRAM cell is selected in the SRAM array 201. Block address A
2-A5 is decoded by the SRAM column decoder 203, and 1 bit × 4 is selected from the selected 16-bit × 4 SRAM cells and connected to the data output terminal Q (or data input terminal D).

In the case of a mishit, the selector 772
Selects one of the four-way tag addresses according to the LRU logic (logic for selecting the oldest way) and selects an area in which the tag address is to be rewritten.
The tag address selected by the selector 772 is provided to the DRAM row decoder DRD of the DRAM 100 via the multiplex circuit 700 as an array address. The selector 772 stores the tag address to be rewritten in the address A14-A2 given by the CPU.
Replace with 1.

In CDRAM 600, this cycle is in copy back mode. In this copy back mode, the way addresses W0 and W1 indicating the way to be rewritten are also controlled under the control of the selector 772.
Is output. In the SRAM 200, the addresses A6-A11 from the CPU and the way addresses W0 and W1 from the controller 750 are decoded, and a 16-bit × 4 SRAM cell is selected. On the other hand, DRAM 10
0, the 8-bit tag address output from the selector 772 and the address A6-
A 16-bit × 4 DRAM cell is selected according to A13. Then, the selected 16-bit × 4 SR
Data transfer from the AM cell to the selected 16-bit × 4 DRAM cell is performed.

In the next operation cycle, a DRAM cell of 16 bits × 4 is selected in DRAM 100 in accordance with addresses A6-A21 from the CPU. The newly selected 16-bit × 4 DRAM cell data is collectively transferred to the 16-bit × 4 SRAM cell selected according to the addresses A6-A11 and the way addresses W0, W1.

With the above structure, the CDRAM
Both the direct mapping method and the set associative method can be realized without changing the internal configuration of the 600. Although not shown, a full associative mapping method is of course also possible. In this case, the controller 750
In, the address of the SRAM cache and the DRAM
A tag address memory that stores 100 corresponding addresses is required. Next, signal timing relationships and state transitions in various operation cycles of the CDRAM will be described.

As described above, the control signals except for the output enable signal G # and the addresses Aa and Ac are latched at the rising edge of the external clock signal K. The state of each signal is arbitrary (DC) except that a setup time and a hold time are required before and after the rising edge of the external clock K, respectively. According to the external clock synchronization method, it is not necessary to consider a margin of a cycle time due to a skew of an address signal and the like, and a cycle time can be reduced and a CDRAM that operates at a high speed can be obtained.

Output enable signal G # controls the output state of the output buffer and output register included in input / output circuit 274 shown in FIG. When the output enable signal G # is "H", the output data is in a high impedance state (Hi-Z). When the output enable signal G # becomes "L" in an active state, some data is output. The operation modes of the CDRAM are listed in FIG. 51, and each operation mode will be described below with reference to its timing chart.

In the standby state, chip select signal E # and refresh instruction signal REF # are both set to "H" at the rising edge of external clock signal K, and the remaining control signals CH #, CI #, CR # and W # are set.
Is an arbitrary state. During this standby, C
No memory operation is performed in the DRAM.

[0369] No. 1: Cache hit write cycle FIG. 56 is a diagram showing the timing of each signal in a cache hit write cycle. External clock signal K
Has a cycle time tk. Cycle time tk
Includes an H pulse width tKH when the external clock signal K is in the “H” state and an L pulse width tKL when the external clock signal K is in the “L” state. The cache hit write cycle is a cycle for writing data to the SRAM cache. When this state is selected, the chip select signal E # is set to "L" at the rising edge of the external clock signal K, the cache hit signal CH # is set to "L", the cache inhibit signal CI # is set to "H", and the command register signal CR # is set to "H". "H", the write enable signal W # is set to "L", and the output enable signal G # is set to "H".

In this state, the address for SRAM 200 is latched as valid (Valid), and the SRAM is accessed according to this SRAM address Ac. At this time, the address A for the DRAM
a is arbitrary (DC). The input data D is made valid at the rising edge of the external clock signal K, and this valid write data is written to the SRAM cell selected by the SRAM address Ac. Cache memory S
Since access to the RAM is fast, writing is completed in one clock cycle of the external clock signal K as shown in FIG. That is, the time required for the cache hit write is the clock cycle time tK.

In FIG. 56, output data Q changes in response to an arbitrary state of output enable signal G #, which changes to "H" and "L" levels of output enable signal G #. This indicates that output data appears in response. In FIG. 56,
The setup time and hold time of each control signal and address signal are also shown. The setup time is a time required to surely set each control signal or address to a defined state by the rising edge of the external clock signal K. The hold time is a time required from the rising edge of the external clock signal K to hold the signal for a certain period of time to perform a reliable operation. The setup time and the hold time will be briefly described.

The chip select signal E # has a setup time tELS required when shifting to “L” and a setup time tEHS required when shifting to “H”.
And hold time tELH required at the time of transition to “L”
And hold time tEHH required at the time of transition to “H”
including.

The cache hit signal CH # has "L"
A setup time tCHLS required at the time of transition;
Setup time tCHH required at "H" transition
S and the hold time tCH required when shifting to “L”
LH and hold time tC required at the time of transition to “H”
HHH is set.

The cache inhibit signal CI # includes the setup times tCILS and tCIHS required at the time of transition to “L” and “H”, and the hold required at the time of transition to “L” and “H”, respectively. Includes times tCILH and tCIHH.

The command register signal CR # has the setup times tCRLS and tCRHS required when transitioning to "L" and "H", and the hold required when transitioning to "L" and "H", respectively. Includes times tCRLH and tCRHH.

The refresh signal REF # includes a setup time tRLS and tRHS required at the time of transition to “L” and “H”, respectively, and a hold time required at the time of transition to “L” and “H”. t
Includes RLH and tRHH.

The write enable signal W # includes the setup times tWLS and tWHS required at the time of transition to “L” and “H”, and the hold required at the time of transition to “L” and “H”, respectively. Time t
WLH and tWHH. Address A for SRAM
c includes a setup time tACS required for the state to be determined to be valid (Valid) and a hold time tACH required when the state is valid.

The address Aa for the DRAM includes a setup time tAAS required until it is determined to be valid (rising edge of the external clock signal K) and a hold time tAAH required after it is determined to be valid. .

For write data D, setup time tDS required for valid data and hold time tDH required for valid data are required.

In response to output enable signal G #, time tGHD required from the time when the output disable state is set to the time when the data input pin is activated is set.
And a delay time tGLD required until the signal G # transitions to "L" after the data input pin goes into a high impedance state, and a delay time tGLD required until the output pin is activated after the transition to "L". And a time tGHQ required until the output pin goes into a high impedance state after the transition to “H”.

As access times, the access time tGLA from when the output enable signal G # goes “L” to when valid data is output and the valid data after the external clock signal K goes “L” are set. The access time tKLA required until output, the access time tKHA required from when the external clock signal K changes to “H” to when valid data is output, and the external clock signal K in the register output mode are “ Access time tKHAR from the time of “H” until valid data is output
And the DRAM after the external clock signal K becomes "H".
, An array access time tKHAA required until valid data is output after access is set.

In FIG. 56, after a lapse of time tGHD from the rising edge of output enable signal G #, write data D is regarded as invalid (Inv).

The cycle time of the CDRAM of the present invention is set, for example, from 10 nS (nanosecond) to 20 nS. The array access time tKHAA is 70 to 8
Set to 0 nS. Each setup and hold time is set to a few nanoseconds.

NO. 2T: Cache Hit Read Cycle (Transparent Output Mode) FIG. 57 shows a timing chart of the cache hit read cycle in the transparent output mode. As described above, the output mode includes the transparent output mode, the latch output mode, and the register output mode. This output mode is designated by a command register. In FIG. 57, when a cache hit read cycle is set, chip select signal E # and cache designating signal CH # are both set to "L" at the rising edge of external clock signal K, and cache inhibit signal CI # and refresh Instruction signal REF #, command register signal CR #, and write enable signal W # are set to "H".

In this state, the address Ac for the SRAM is validated at the rising edge of the external clock signal K, and the SRAM cell is selected according to the valid address Ac. In the transparent output mode, the SRAM designated by the effective address Ac
Cell data is output in this clock cycle. In the transparent output mode, valid output data Q is output at a later timing after a lapse of time tKHA from the rising edge of external clock signal K or after a lapse of time tGLA from the falling edge of output enable signal G #. You.

If output enable signal G # falls to "L" before time tKHA, invalid data (IN
V. ) Is output until the time tKHA elapses. In this cache hit read cycle, the write data is set to a high impedance state (Hi-Z),
Since the address Aa for the DRAM is not used, the state is arbitrary.

[0387] No. 2L: Cache hit read cycle (latch output mode) FIG. 58 shows a timing chart of the cache hit read cycle in the latch output mode. The difference between the latch output mode and the transparent output mode is that, in the latch output mode, when the output enable signal G # falls to “L” before the access time tKHA,
First, data (Pre. Valid) of the SRAM cell selected in the previous cycle is output. The timing of other signals is the same as in the transparent output mode shown in FIG. According to the latch output mode, invalid data (INV) is not output, and only valid data is always output.

[0388] No. 2R: Cache Hit Read Cycle (Register Output Mode) FIG. 59 shows a timing chart of the cache hit read cycle in the register output mode. The timing of the external control signal in the cache hit read cycle in the register output mode is the same as that in the transparent output mode and the latch output mode shown in FIGS. In this register output mode, time tK from the rising edge of external clock signal K is applied.
After the lapse of HAR or the output enable signal G #
Valid data (Pre. Valid) of the previous cycle is output at the later time after the elapse of the time tGLA from the falling edge of. In this register output mode, no invalid data is output. This register output mode is suitable for pipeline operation.

The switching of the output mode is realized by controlling the operation of the output register included in input / output circuit 274 shown in FIG. 1 (see FIG. 16 for more details).

[0390] No. 3: Copyback cycle FIG. 60 shows the timing of each signal in the copyback cycle. This copy back cycle is a cycle for transferring data from the cache (SRAM) to the array (DRAM), and is performed in the first cycle in the case of a mishit. In the copy back cycle, the chip select signal E # and the write enable signal W # are both set to "L" at the rising edge of the external clock signal K, and the cache hit signals CH #, CH #,
Cache inhibit signal CI #, refresh instruction signal RE
F #, the command register signal CR #, and the output enable signal G # are set to "H".

In this copy back cycle, D
In a RAM, it is necessary to input an array address Aa in order to select a memory cell. Array address Aa
Is given by multiplexing a row address (Row) and a column address (Col). The array row address is latched on the first rising edge of external clock signal K,
The array column address is latched at the second rising edge of external clock signal K. At the second rising edge of external clock signal K, cache hit instruction signal CH #, cache inhibit signal CI #, write enable signal W #, and cache address (address for SRAM) Ac are arbitrary.

The write enable signal W # is set to "L" at the first rising edge of the external clock signal K, and the external input data D changes from a high impedance state to an arbitrary state. The external output data Q is in a high impedance state because the output enable signal G # is at "H".

No. 4: Block Transfer Cycle In the block transfer cycle shown in FIG. 61, the cache (SRA)
The data blocks are transferred collectively to M). This block transfer cycle satisfies the same timing conditions as the copy back cycle shown in FIG. 60 except that write enable signal W # is set to "H" at the first rising edge of external clock signal K.

That is, a cache miss (miss hit)
When the write enable signal W # is set to "L" at the first rising edge of the external clock signal K, a copy-back cycle is started, while when the write enable signal W # is set to "H", the copy-back cycle starts. A block transfer cycle to the cache is set.

Whether high-speed copy-back, normal copy-back and block transfer, or write-through is performed is determined by transferring command data to a command register.

[0396] No. 5: Array Write Cycle The array write cycle shown in FIG. 62 is a cycle for setting a mode in which the CPU directly accesses the array and writes data. DRA of array by array address Aa
Select M cell. At this time, as shown in FIG. 12, the access switching circuit 310 of the bidirectional transfer gate circuit 305
, And without providing access switching circuit 310, as shown in FIGS. 30 and 41, bit line pair SBL of SRAM and bidirectional transfer gate BTG and global I / O Data may be written via the line pair GIO. S
In the case of writing data via the SRAM bit line pair SBL of the RAM array, the lower bits of the array address Aa may be given as a block address to the column decoder SCD of the SRAM. It may be provided to the SRAM selection gate.

An array write cycle is designated at the first rising edge of external clock signal K by chip select signal E # and cache inhibit signal C as shown in FIG.
This is performed by setting I # and write enable signal W # to "L", and setting refresh instruction signal REF # and output enable signal G # to "H". The state of the cache instruction signal CH # is arbitrary. In this array write cycle, the array address A is output at the first rising edge of the external clock signal K.
a is latched as a row address (Row), and the array address Aa is latched as a column address (Col) at the second rising edge of the external clock signal K. Since access to the cache is not performed at this time, the state of the cache address Ac is arbitrary. External write data D is latched at the first rising edge of external clock signal K. The external output data Q enters a high impedance state.

In the cache system shown in FIGS. 54 and 55, only a 16-bit address is given to DRAM 100, and S
A column selection operation inside a block in the RAM is performed. 54 and 56 show the configuration at the time of the cache system, and do not show the configuration of the array access. However, when the cache inhibition signal CI # becomes "L" at the time of the array access, the configuration shown in FIG. The configuration may be such that a 4-bit block address is used as a column selection address of the DRAM 100.

[0399] No. 6: Array Read Cycle The array read cycle shown in FIG. 63 is a cycle for setting a mode in which the CPU directly accesses the array and reads data. The array read cycle is specified by setting the chip select signal E # and the cache inhibit signal CI # to "L" at the first rising edge of the external clock signal K, refresh instruction signal REF #, command register signal CR #, and write enable signal. This is performed by setting W # and output enable signal G # to "H". At the second rising edge of external clock signal K, chip select signal E #, refresh instruction signal REF #, and command register signal CR
# Is set to "H". The states of the cache inhibit signal CI # and the write enable signal W are arbitrary. The cache hit instruction signal CH # can be in any state in the array read cycle, and the output enable signal G # maintains the state of "H". At the first rising edge of external clock signal K, array address Aa is latched as a row address, and at the second rising edge of external clock signal K, array address Aa is latched as a column address. The state of external input data D is arbitrary, and external output data Q is set to a high impedance state.

Here, the array access cycle (array write cycle and array read cycle) is set by setting cache signal CI # to "L" at the first rising edge of external clock signal K.
This array access cycle is a cycle for setting a mode in which the CPU directly accesses the array.
Data read / write is not actually performed in the array write cycle and the array read cycle.

Read / write of array data such as copy-back operation, block transfer operation and array access operation
Operations requiring a write require selection of a word line of a DRAM array, detection and amplification of selected cell data by a sense amplifier, data restore operation, RAS precharge, and the like. Therefore, an operation requiring reading / writing of data in these arrays requires several clock cycles. The cycle time of the DRAM is ta,
Assuming that the cycle time of the external clock signal K is tK, m =
Only ta / tK external clock cycles are needed for array access. These m cycles are the waiting time for the CPU. The timing when a wait is applied to the CPU in cell selection and data read / write in such an array will be described below.

[0402] No. 7: Array Active Cycle In the array active cycle shown in FIG. 64, a row selecting operation, a column selecting operation, and data writing / reading are performed in the DRAM according to applied array address Aa. In this array active cycle, at the rising edge of external clock signal K, chip select signal E #, refresh instruction signal REF # and command register signal CR # are set to "H", and output enable signal G # is set to the cycle. Medium “H”
Fixed to The states of the cache hit signal CH #, the cache inhibit signal CI #, and the write enable signal W # are arbitrary. In this array active cycle, the state of external input data D is arbitrary, but external output data Q becomes high impedance.

No. 7QT: Array Active Cycle with Transparent Output Mode In the specification of the array active cycle in the transparent output mode shown in FIG. 65, each control signal E #, CH #, CI #, REF #, CR # and W
# Is set similarly to the array active cycle shown in FIG. In the array active cycle in the transparent output mode, the output buffer is activated by setting the output enable signal G # to "L", and valid data is output. In the array active cycle in the transparent output mode, the DRAM corresponding to the array address Aa set in the array read cycle shown in FIG.
The cell data is output.

[0404] No. 7QL: Array active cycle in latch output mode The timing state of each control signal in the array active cycle in the latch output mode shown in FIG. 66 is the same as that shown in FIG. In the array active cycle in the latch output mode, when the output enable signal G #, which has been held at "H", falls to "L", first, the previous access cycle (the array access cycle even in the cache access cycle) is performed. ) Is first output, and then the data read in the current array access cycle is output.

[0405] No. 7QR: Array active cycle in register output mode The state of each control signal in the array active cycle in the register output mode shown in FIG. 67 is the same as that shown in FIGS. 65 and 66. In the array active cycle in the latch output mode, the output enable signal G which has been held at "H" until then is output.
When # goes low, the external write data D enters a high impedance state, and the data read in the previous access cycle is output as the external output data Q.
In the array access cycle in the latch output mode, when output enable signal G # falls from "H" to "L" in the next clock cycle, data read in the current array access cycle is output.

By combining the cycles shown in FIGS. 63 to 67, output data Q according to the external address is obtained from the array.

FIG. 68 shows the entire cycle executed when data is read from the array in the transparent output mode. In FIG. 68, the numbers indicated by circles on the timing chart represent the numbers given in the description of each cycle described above.

First, in the array read operation in the transparent output mode, an array read cycle (No. 6) shown in FIG. 63 is executed. This cycle No. 6, the array address Aa is sequentially taken in as a row address and a column address at the rising edge of the external clock signal K, respectively. Then, the array active cycle shown in FIG. 64 is executed a predetermined number of times, and the row and column selecting operation in the DRAM array is performed. Finally, the cycle No. shown in FIG. By executing 7QT and lowering the output enable signal G # to "L", valid data is output after invalid data is output. In this case, the access time tKHAA is substantially equal to the access time of a normal DRAM.

FIG. 69 shows an entire cycle performed when data is read from the array in the latch output mode. In the array read operation in the latch output mode, similarly to the array read operation in the transparent output mode shown in FIG. 68, first, an array read cycle (No. 6) shown in FIG. The settings are made. After the array address Aa is latched by the array read cycle (cycle No. 6), the array active cycle (cycle No. 7) shown in FIG. 64 is performed a predetermined number of times. After this array active cycle (cycle No. 7), the array active cycle (cycle No. 7Q) in the latch output mode shown in FIG.
L) is performed. This cycle No. In 7QL, when the output enable signal G #, which has been set to "H", falls to "L", an access request is made in the current array read cycle after the data read by the previous access is output. The data of the memory cell is output. The access time tKHAA at this time is a time required from the first rising edge of the external clock signal K to outputting the memory cell data (Valid) requested to be accessed in the current array access cycle.

FIG. 70 shows an entire cycle performed when data is read from the array in the register output mode. In FIG. 70, first, cycle N
o. By executing step 6, the array read mode is set, and at the rising edge of external clock signal K, array address Aa is latched in a time-division manner as a row address and a column address, respectively. Then, cycle N
o. After the array active cycle of No. 7 has been performed a predetermined number of times, cycle No. 7 An array active cycle of 7QR is performed. This cycle No. In 7QR, after the output enable signal G # falls to "L" and the external clock signal K rises, the data read in the previous cycle at the later timing after the lapse of the time tKHA or the lapse of the time tGLA Output as output data Q. The access time tKHAA at this time is the cycle No. 6, the time from the first rising edge of the external clock signal K to the output of valid data.

The DRAM cells need to be refreshed periodically. The setting of this refresh operation is performed by an external refresh instruction signal REF #. At the time of this refresh, in the CDRAM, a refresh address is generated from a refresh address counter (see counter circuit 293 in FIG. 1) in response to refresh instruction signal REF #, and DRAM cells are automatically refreshed in accordance with the refresh address. Is performed. A DRAM having such an auto-refresh function has been conventionally known in the DRAM field. Hereinafter, the timing of the signal for performing the refresh will be described.

[0412] No. 8: Refresh Cycle FIG. 71 is a diagram showing signal timing of the refresh cycle. As shown in FIG. 71, at the rising edge of external clock signal K, chip select signal E # and refresh instruction signal REF # are changed to "H" and "L", respectively.
By setting, the refresh mode of the DRAM is set. If the chip select signal E # is set to "H" and the refresh instruction signal REF # is set to "H" at the rising edge of the external clock signal K, the refresh of the DRAM is stopped. In this auto refresh cycle, other control signals CH #, CI #, CR #, W
The state of # is arbitrary, and the output enable signal G # is set to "H". Therefore, at this time, the state of cache address Ac and array address Aa is arbitrary, the state of external input data D is also arbitrary, and external output data Q is set to a high impedance state.

The refresh operation is performed only for the DRAM. SRAM does not need to be refreshed at all. Therefore, it is possible to access the SRAM cache during this refresh period.

The timing of a cycle for simultaneously performing the refresh and the cache access will be described below.

[0415] No. 8W: Refresh cycle with cache hit write This cycle No. In 8W, data is written to the corresponding SRAM cell when a cache hit occurs, in parallel with the refresh in the DRAM. The refresh cycle with cache hit write is set at the rising edge of external clock signal K as shown in FIG.
#, The cache hit signal CH #, the refresh instruction signal REF #, and the write enable signal W # are set to "L", and the cache inhibit signal CI # and the output enable signal G # are set to "H". . As a result, a cache hit write cycle and a refresh cycle are set.

In the cache (SRAM), in response to the activation state of cache hit instruction signal CH # and write enable signal W #, external write data D is taken in at the rising edge of external clock signal K to handle the corresponding SRAM. Write to cell location. In the DRAM, a refresh instruction signal REF # activates an internal refresh address counter, and refresh is performed according to the refresh address from this counter.

When refresh instruction signal REF # is set to "H" at the rising edge of external clock signal K, the cache hit write cycle (cycle No. 1) shown in FIG. 56 is simply performed, and DRA is performed.
The refresh of M is stopped.

[0418] No. 8RT: Refresh cycle with cache hit read in transparent output mode In 8RT, cache hit read is performed in accordance with the transparent output mode, and auto refresh is performed in the DRAM. This cycle No. The setting of FIG.
As shown in the figure, at the rising edge of the external clock signal K, the chip select signal E # and the cache hit signal C
H # and refresh instruction signal REF # are set to "L", and cache inhibit signal CI #, command register signal CR # and write enable signal W # are set to "H".
This is done by setting In the SRAM cache, the cache address Ac is taken in at the rising edge of the external clock signal K and the corresponding SRAM cell is selected in response to the cache hit read instruction.
When output enable signal G # falls to "L", valid output data Q is output after a predetermined time has elapsed.

In the DRAM, auto refresh is performed in response to refresh instruction signal REF #. If the refresh instruction signal REF # is set to “H” at the rising edge of the external clock signal K in the refresh cycle involving the cache hit read,
Auto-refresh performed in response to refresh instruction signal REF # is stopped. Therefore, in this case, the cycle No. shown in FIG. A cache hit read cycle in the same transparent output mode as 2T is performed.

[0420] No. 8RL: Refresh cycle with cache hit read in latch output mode Cycle No. 8 shown in FIG. In 8RL, cache hit read is performed in the latch output mode and DRAM auto-refresh is performed.
The timing conditions of each control signal are the same as those shown in FIGS. In this latch output mode,
When a cache hit occurs, after the output enable signal G # falls to "L", the data accessed in the previous cycle is output first, followed by the data accessed in the current cycle.

[0421] No. 8RR: Refresh cycle accompanied by cache hit read cycle in register output mode. In 8RR, data is read according to a cache hit read cycle in the register output mode, and DRA
Auto refresh is also performed in M. The timing conditions of each control signal are the same as those shown in FIGS. 72 and 73, and hit read and auto refresh are performed. This cycle No. In 8RR, when the output enable signal G # falls to "L", the output data selected in the previous cycle is output. Thereafter, once the output enable signal G # is raised to "H" and subsequently the output enable signal G # is lowered to "L" in the next clock cycle, the data of the SRAM cell selected in the current cycle is obtained. Is output.

The transparent output mode, latch output mode, register output mode, masked write mode, and D / Q separation mode of the CDRAM are realized by setting a command for setting a desired special function in the command register. Next, an operation cycle for setting a command in the command register will be described.

[0423] No. 9: Command Register Set Cycle FIG. 76 shows a command register set cycle (cycle N).
o. It is a figure which shows the timing of each signal in 9).
The command register set cycle includes a chip select signal E #,
Cache inhibit signal CI #, command register signal CR
# And the write enable signal W # are set to “L”. At this time, as shown in FIG. 52, four registers WR0 of the command registers
One of WR3 is selected. In setting the output mode, the command register WR0 is selected, and the contents of the output mode are selected by the combination of the input data D at that time. Therefore, the command address Ar and the external write data D are validated and latched at the rising edge of the external clock signal K. 2 bits A of command address Ar
When both r0 and Ar1 are 0 (“L”), the command register WR0 is selected. Upper two bits D2 (DQ2) and D3 of 4-bit external write data D
(DQ3) is “0” (“L”) and the least significant bit D
If 0 (DQ0) is "0", the mode is set to the transparent output mode.

In the latch output mode, external write data D0 and D0 are output at the rising edge of external clock signal K.
1 is set to "1"("H") and "0", respectively, and the remaining two bits of external write data D2 and D3 are both set to "0". In the register output mode, the command addresses Ar0 and Ar1 are both set to "0" at the rising edge of the external clock signal K, the external write data D0 and D1 (DQ0 and DQ1) are both set to "1", and the external write data is set. The selection is made by setting both D2 and D3 (DQ2 and DQ3) to “0”.

In the configuration of the command register shown in FIG. 52, eight registers are provided, and eight kinds of special modes can be set. In order to select the command register RR0 for setting the masked write mode and the register RR1 for setting the D / Q separation mode, in the timing chart shown in FIG. Set W # to "H". A desired mode is selected according to the value of the command address Ar at this time.

FIG. 77 shows a state transition of the CDRAM at the time of a cache miss (miss hit). FIG. 77 (A)
FIG. 77B shows a state transition flow, and FIG. 77B shows a state transition between cycles. In FIG. 77, each cycle is indicated by a cycle number.

In FIG. 77, when a cache miss occurs, first, a copy back cycle (cycle No. 3) shown in FIG. 60 is performed. With this, from SRAM to D
The data transfer mode to the RAM is set. Then Figure 6
Array access cycle shown in No. 4 (cycle No. 7)
Is repeated n (n = (ta / tk) -1) times. Here, ta is the cycle time of the DRAM, and tk is the cycle time of the external clock K. This cycle No. By repeating Step 7 n times, the batch transfer of the data blocks from the SRAM to the DRAM is completed. Then, a block transfer cycle (cycle No. 4) shown in FIG. 61 is performed. Thereby, a data transfer mode from the DRAM to the SRAM is set. This cycle No. Following the cycle No. 4 7 by repeating n times
The transfer of the data block to the RAM is performed. Thereafter, the DRAM is brought into a state where it can receive the next access. This state is called a block transfer mode,
U can then access both SRAM and DRAM.

The cycle No. Subsequently to the array active cycle (cycle No. 7), n ′ (n ′ = (ta)
/ 2 · tK) -1) times, the DRAM still has a restore operation to its memory cells and a RAS
Precharge has not been completed and the next access cannot be received. However, in the SRAM, the block data has already been transferred from the DRAM in this state, and there is no need to restore anything, and the data on the SRAM bit line pair is in a defined state. The CPU can access the SRAM in this state. This state is called a cache fill state. In this cache fill state, the CPU can access only the SRAM. After the cache fill, the cache hit write cycle (cycle No. 1) shown in FIG. 56 or the cache hit read cycle (cycle No. 2) shown in FIGS. 57 to 59 is performed. Here, this cache hit read cycle (cycle No. 2) may be any of the transparent output mode, the latch output mode, and the register output mode. Hit write can be performed continuously for each clock cycle, and hit read cycle can be continuously performed for each clock cycle. Also, the transition from the hit read cycle to the hit write cycle can be made.

FIG. 78 is a diagram showing a state transition at the time of array access. FIG. 78A shows a state transition flow in array access, and FIG. 78B shows a state transition diagram between cycles. The array access includes an array write for writing data to the array and an array read for reading data from the array. In the array write, first, an array write cycle shown in FIG.
5) is performed. This cycle No. After cycle No. 5, cycle no. Data can be written into the DRAM array by repeating the 7 array active cycles n times.

At the time of array read, an array read cycle (cycle No. 6) shown in FIG. 63 is performed.
The DRAM is made accessible. This cycle No.
After performing the array read cycle of No. 6, the array active cycle (cycle No. 7) shown in FIG.
Repeat several times. In this state, data cannot be read from the DRAM yet. This cycle No. 7, the array active cycle (cycle No. 7Q) for data output shown in FIGS. 65 to 67 is repeated n '+ 1 times. Here, the cycle No. 7Q may be any of an array active cycle for a transparent output, an array active cycle with a latch output, and an array active cycle with a register output.

This cycle No. Data can be read from the array by setting output enable signal G # to "L" in the last cycle in 7Q. In this array write and array read, the cycle time appears to be different at first glance, but n
= N '+ 1, and data can be read / written to / from the array in the same clock cycle. After performing the array write operation or array read operation, array write or array read can be performed again subsequently.

FIG. 79 is a diagram showing state transition at the time of refresh. FIG. 79A shows a state transition flow at the time of refresh, and FIG. 79B shows a state transition between cycles at the time of refresh.

In normal refresh in which only DRAM auto refresh is performed and access to SRAM is not performed, first, a refresh cycle (cycle No. 8) shown in FIG. 71 is performed. Following this, the array active cycle shown in FIG.
7) is repeated n times. This completes one auto-refresh according to the refresh address from the refresh counter built in the CDRAM.

At the time of refresh with hit write, a refresh cycle with cache hit write (cycle No. 8W) shown in FIG. 72 is first performed. Subsequently, the DRAM is automatically refreshed for n clock cycles. During this time, the CPU can execute the cache hit write cycle shown in FIG. 56 n times.

In a refresh cycle involving a hit read, a refresh cycle involving a cache hit read shown in FIGS. 73 to 75 (cycle No. 8R)
Is performed. Thereby, the auto-refresh of the DRAM is started, and the auto-refresh is performed in the DRAM for n clock cycles. The CPU can perform a hit read for n clock cycles.
Here, the cycle No. The output mode of the 8R may be any of a transparent output mode, a latch output mode, and a register output mode.

[Second Embodiment] In a second embodiment described below, control signal CI # applied to pin number 4
(Cache access prohibition signal) and command set / burst enable signal CR # / BE # are defined as control signals CCI and CC2, respectively. These are simply the names of the signals changed, and the first
It has the same functions as the embodiment.

FIG. 80 shows a CDR according to the second embodiment.
FIG. 2 is a block diagram functionally showing the entire configuration of an AM. In the CDRAM shown in FIG. 80, clock buffer 254 is used instead of address buffer 260 shown in FIG.
Fetches external addresses Ac and Aa according to internal clock signal int-K, internal chip enable signal E and internal cache hit instruction signal / CH from internal address i.
An address generation circuit 360 for generating nt-Ac and int-Aa is provided. This address generating circuit 360
By adjusting the timing of taking in the addresses Ac and Aa, the CDRAM 5000 can be set to operate in either the low power consumption mode or the high speed operation mode.

DRAM Row Decoder 102 and DRA
A DRAM internal address signal int-Aa applied to M column decoder 103 is externally supplied with a row address signal and a column address signal in a time division manner. The operation speed of the DRAM can be adjusted by adjusting the timing of taking in the address signal. Address generation circuit 36
0 is the internal control signal K (int-K), the internal control signal E
The timing for taking in the DRAM address signal Aa from the outside is adjusted according to / CH to generate an internal row address signal and an internal column address signal. FIG. 81 shows an internal address signal i for DRAM in this address generating circuit.
FIG. 9 is a signal waveform diagram illustrating an operation of a circuit related to a portion that generates nt-Aa. Hereinafter, the operation of address generation circuit 360 will be described with reference to FIG.

At time T1, internal control signals E and CH are set to "H" at the rising edge of clock signal K, respectively.
By setting “L” and “L”, an operation mode for performing high-speed operation with low current consumption (hereinafter, referred to as a low power consumption mode) is set. At this time, the address generation circuit 360
Captures external address signal Aa as internal row address signal int.Aar in response to the rising edge of clock signal K. Then, external address signal Aa is taken in response to the falling edge of clock signal K to generate internal column address signal int.Aac. This operation is described in more detail as follows. At time T1, external address signal Aa has already been applied to address generating circuit 360 at the rising edge of the external clock signal. At this time, an internal row address strobe signal / RAS for taking in a row address signal is generated in accordance with a combination of the states of the signal, E and CH, and becomes active state "L".
When internal row address strobe signal / RAS attains an active state of "L", address generating circuit 360 latches external address signal Aa, and thereafter continuously generates internal row address signal int.Aar to generate DRAM row decoder 102. (Time T2).

At time T3, at the falling edge of external clock signal K, internal row address strobe signal / RAS
Is at "L", internal column address strobe signals CAL and / CAL are generated. In response, address generation circuit 360 takes in and latches external address signal Aa as an internal column address signal (time T4),
This is given to the RAM column decoder 103.

If the DRAM row address signal int.Aar and the DRAM column address signal int.Aac are taken in by a single pulse of the clock signal K as shown in FIG. The DRAM can be operated more quickly than in a configuration in which the operation is performed only at the rising edge of the external clock signal as in a synchronous semiconductor memory device.

In other words, as shown in FIG. 82, in the low current consumption mode, at time TA, the DRAM row address signal and column address signal are taken in, and the operation for the DRAM is started from this time.

On the other hand, when all operations are determined at the same timing (rising edge) of clock signal K as in a conventional clock synchronous semiconductor memory device, DRA
The M column address signal is fetched at the next rising edge of clock signal K (time TB), and the DRAM starts operating at the time of fetching the column address signal. Therefore, in order to reduce the power consumption of the CDRAM, even when the period of the clock signal K is lengthened or intermittently generated with emphasis on the power consumption rather than the operation speed of the CDRAM, the normal clock synchronous type is used. Compared with the configuration of the semiconductor memory device, the operation start time of the DRAM can be shortened by the time (TB-TA) between times TB and TA. In other words, a clock synchronous semiconductor memory device that can operate at high speed even in the low power consumption mode can be obtained.

Here, as shown in FIG.
Are controlled by an external control signal, and internal row address strobe signal / RA shown in FIG.
S and internal column address strobe signals CAL, / CA
L is a control signal that determines only the timing of taking in the DRAM address in the address generation circuit 360.

In this case, in a state where the cycle of external clock signal K is lengthened to meet the demand for low power consumption, external clock signal K is intermittently generated to further reduce power consumption. Think. Even in this case, the configuration is such that the fetch operation of address generation circuit 360 is reset using internal row address strobe signal / RAS, so that even if noise occurs during such intermittent operation, malfunction is prevented. Thus, a CDRAM with a sufficient margin can be obtained. Here, the intermittent operation mode corresponds to a case where the cycle of the clock signal K is temporarily lengthened or a case where the cycle of the external clock signal K is made variable. Next, a margin for a noise pulse generated when the cycle of the external clock signal is long will be described.

FIG. 83 is a diagram showing a comparison between the low power consumption mode and the conventional operation mode. In the low power consumption mode, when noise pulse NZ is generated in external clock signal K and external address signal Aa is taken in the CDRAM at time TC, external address signal Aa is taken in as the internal column address signal at the next time TD. Rare, time TD
Then, the DRAM starts operating. However, at this time, the operation of the DRAM is automatically terminated by resetting the address generation circuit 360 after a lapse of a predetermined time, so that a malfunction due to the noise pulse NZ can be prevented. That is, when external clock signal K rises at time TEa, D
The operation of the RAM is completed and returns to the precharge state, and an operation can be performed in accordance with a combination of various control signal states at the rising edge of the external clock signal K. An affordable CDRAM can be obtained.

On the other hand, when the row address signal and the column address signal are fetched only at the rising edge of external clock signal K as in the normal mode, the row address signal is applied in response to the noise pulse at the rising edge time TC of noise pulse NZ. If the data is erroneously taken in, the CD is kept until the next time TEa rises.
The RAM is in a state of waiting for input of a column address signal. At this time, at the time TEa at which the accurate external clock signal K rises, the CDRAM takes in the address signal Aa at that time as a column address signal and starts operation. For this reason, when an accurate external clock signal K is applied, an erroneous operation is performed. In order to meet the demand for low power consumption, the period of the external clock signal K is increased, so that there is a margin for noise. Disappears.

As described above, by resetting the DRAM after a lapse of a predetermined time (for example, a time required until the completion of the sensing operation in the DRAM array) after the address generation circuit 360 fetches the DRAM column address signal, such an external circuit can be obtained. Even when the clock signal K is intermittently applied, noise resistance can be improved.

FIG. 84 shows the address generation circuit 3 shown in FIG.
FIG. 6 is a diagram illustrating an example of a specific configuration of the embodiment. In FIG. 84, address generation circuit 360 includes a row address strobe signal generation circuit 2601 for generating internal row address strobe signal / RAS in response to control signals E and CH and external clock signal K, and a row address strobe signal generation circuit 2601 Row address strobe signal / RA from
A column address strobe signal generating circuit 2602 for generating internal column address strobe signals CAL, / CAL in response to S and clock signal K, and taking in external address signal Aa in response to internal row address strobe signal / RAS Row address latch 26 for generating an address signal
03, an internal row address strobe signal / RAS, a column address latch 2604 for taking in an external address signal Aa and generating an internal column address signal in response to the internal column address strobe signals CAL, / CAL, and an internal row address strobe signal / RAS. And a reset signal generating circuit 2605 for generating a reset signal after a predetermined time elapses (for example, during the active state of the DRAM) and applying the reset signal to row address strobe signal generating circuit 2601. Here, the external clock signal K and the internal clock signal int-K are substantially the same signal, and in the following description, the internal clock signal is simply indicated by the symbol K.

Row address strobe signal generation circuit 260
1 generates the internal row address strobe signal / RAS when the control signal E is at "H" and the control signal CH is at "L" at the rising edge of the (internal) clock signal K. Column address strobe signal generation circuit 2602 generates internal column address strobe signals CAL and / CAL in response to the falling edge of external clock signal K. Column address strobe signal generation circuit 2602 is reset when internal row address strobe signal / RAS rises to an inactive "H" state.

Row address latch 2603 attains a latch state when internal row address strobe signal / RAS attains "L", and continuously outputs a latched signal as an internal row address signal regardless of the state of external address signal Aa. I do.

Column address latch 2604 responds to internal row address strobe signal / RAS to external address A.
a, and column address strobe signals CAL, / CA
The address signal applied in response to L is continuously output as an internal column address signal. The address generation circuit shown in FIG. 84 is a portion related to a DRAM address.
At the time of a cache hit for accessing the SRAM array, a row address signal and a column address signal are simultaneously applied to an SRAM address generation circuit (not shown).
Here, a row address signal and a column address signal are taken in at the same timing of the external clock signal. This FIG.
The operation of the address signal generating circuit shown in FIG. 4 is the same as that described above with reference to the signal waveform diagram shown in FIG. 81, and description thereof will not be repeated. Next, a specific configuration of each circuit shown in FIG. 84 will be described.

FIG. 85 shows a specific structure of the row address strobe signal generation circuit 2601 shown in FIG.
In FIG. 85, row address strobe signal generation circuit 26
01 is the clock signal K, the control signal E and the control signal /
AND circuit 261 receiving CH (inverted signal of signal CH)
0 and an OR circuit 2611 receiving the output of the AND circuit 2610 at one input and receiving the Q output of a flip-flop (FF) 2612 at the other input. Flip-flop 2612 is provided with a set input S receiving the output of OR circuit 2611 and reset signal generating circuit 260 shown in FIG.
5, a reset input R for receiving a reset signal RS from
Includes Q and / Q outputs. The Q output and the / Q output output signals complementary to each other.

An internal row address strobe signal / RAS is generated from the / Q output of flip-flop 2612.
The flip-flop 2612 usually has a circuit configuration in which two NOR circuits are crossed. The flip-flop enters a set state when an “H” signal is applied to the set input S, and outputs an “L” signal from the / Q output.
When a signal of “H” is given to the reset input R, the reset state is set, and the signal from the / Q output becomes “H”. Next, the operation of row address strobe signal generation circuit 2601 shown in FIG. 85 will be described with reference to the operation waveform diagram shown in FIG.

If the control signal E is at “H” and the control signal CH is at “L” when the clock signal K rises to “H”,
The output of the AND circuit 2610 becomes "H". Accordingly, the output of the OR circuit 2611 rises to “H”, and the flip-flop 2612 is set. Flip-flop 2612 is set, and internal row address strobe signal / RAS output from / Q output of flip-flop 2612 falls to "L". At this time, the Q output of the flip-flop 2612 becomes “H”, and the output of the OR circuit 2611 becomes “H”. When a predetermined time elapses after generation of internal row address strobe signal / RAS, reset signal generation circuit 2605 (FIG. 84)
), The flip-flop 2612 is reset, and the row address strobe signal / RAS rises to "H". As a result, row address generating circuit 360 is ready to receive the next address.

In the case where the flip-flop 2612 has a circuit configuration in which a normal NOR gate is crossed, the “H” reset signal RS is supplied when the “H” signal is supplied to the set input S. Normally, at this time, both the Q output and the / Q output become "L". At this time, the Q output of the flip-flop 2612 is
11 is provided to one input of the OR circuit 261.
1 becomes "L". If the reset signal RS has an appropriate pulse width, the flip-flop 2612 enters a stable reset state. At this time, in order to reliably operate the flip-flop 2612, a one-shot pulse signal is generated when the Q output of the flip-flop 2612 becomes “H”, and the one-shot pulse signal is supplied to the OR circuit 2611. It may be configured as follows. Further, a circuit for generating a one-shot pulse having an appropriate pulse width in response to the output of AND circuit 2610 may be provided, and a pulse from this one-shot pulse generation circuit may be applied to the set input of flip-flop 2612. Good.

FIG. 86 shows an example of a specific configuration of column address strobe signal generating circuit 2602 shown in FIG. 86, a column address strobe signal generation circuit 2602 includes an AND circuit 2621 receiving clock signal K at one input thereof, an inverter circuit 2622 receiving internal row address strobe signal / RAS, and
A set input / S receiving the output of the circuit 2621, a reset input / R receiving the output of the inverter circuit 2622,
Flip-flop 262 having Q output and / Q output
3 is included. The / Q output of flip-flop 2623 is applied to the other input of AND circuit 2621. Column address strobe signal / CAL is applied to flip-flop 2623
Column address strobe signal C
AL is generated from inverter circuit 2624 receiving / Q output of flip-flop 2623.

The flip-flop 2623 has two NAs.
An ND circuit is provided, and a set state is provided when an "L" signal is applied to its set input / S, and a reset state is provided when an "L" signal is applied to its reset input / R. Becomes Next, the operation will be described.

The flip-flop 2623 is now in the reset state. At this time, the / Q output of flip-flop 2623 is at "H", and the output of AND circuit 2621 is at "H" in response to the rising of clock signal K. When clock signal K falls to "L", the output of AND circuit 2621 falls to "L", flip-flop 2623 is set, and column address strobe signal / CAL from its / Q output becomes "L". , Inverter circuit 62
4, the column address strobe signal CAL becomes "H". On the other hand, row address strobe signal / RAS goes low in response to the rising of clock signal K, and the output of inverter circuit 622 goes high.

When a predetermined time has elapsed, internal row address strobe signal / RAS rises from "L" to "H",
The output of inverter circuit 2622 falls to "L". As a result, the flip-flop 2623 is reset, and the column address strobe signal / CAL goes "H" and the column address strobe signal CAL goes "L".

At this time, it is conceivable that both the signal to the set input / S and the signal to the reset input / R of the flip-flop 2623 become “L”. However, a configuration in which the / Q output of the flip-flop 2623 is forcibly reset is adopted. Such a state can be prevented if provided. At this time, a circuit configuration for setting the Q output of the flip-flop 2623 together may be provided.

In simplicity, a one-shot pulse signal having a predetermined pulse width is generated in response to the fall of clock signal K to generate flip-flop 2.
Alternatively, a configuration of 623 to the set input / S may be used.
At this time, the generated one-shot pulse signal is a pulse signal that falls from “H” to “L”.

FIG. 87 shows the row address latch 2 shown in FIG.
FIG. 603 is a diagram illustrating an example of a specific configuration of a reference numeral 603. In FIG. 87, row address latch 2603 includes an inverter circuit 2631 receiving external address signal Aa, and a clocked inverter 263 receiving an output of inverter circuit 2631.
2, an inverter circuit 2633 receiving the output of the clocked inverter 2632, and a clocked inverter 2634 receiving the output of the inverter circuit 2633.

The operation of clocked inverter 2632 is controlled by internal row address strobe signals RAS and / RAS. Internal row address strobe signal R
When AS is at "H" and internal row address strobe signal / RAS is at "L", clocked inverter 2
Reference numeral 632 indicates an inactive high output impedance state. Internal row address strobe signal RAS is at "L" and internal row address strobe signal / RAS is at "H".
, Clocked inverter 2632 attains an active state, inverts the output of inverter circuit 2631 and transmits it to node N10.

Clocked inverter 2634 is activated when internal row address strobe signal / RAS is at "L" and internal row address strobe signal RAS is at "H", and functions as an inverter. When internal row address strobe signal RAS is at "L" and internal row address strobe signal / RAS is at "H", clocked inverter 2634 enters an inactive high impedance state. Therefore, when clocked inverter 2634 is activated, inverter circuit 2633 and clocked inverter 2634 form a latch circuit, and continuously output the signal potential appearing at node N10. Node N10 generates an internal row address signal int.Ara. Next, the operation will be described.

When internal row address strobe signal / RAS is inactive "H", clocked inverter 2632 functions as an inverter. On the other hand,
Clocked inverter 2634 is in an output high impedance state. Therefore, at this time, node N10
Is supplied with an external address signal Aa. When internal row address strobe signal / RAS falls to "L", clocked inverter 2632 enters an output high impedance state, and clock toy inverter 2634 is activated to function as an inverter. In this state, the signal potential appearing at node N10 when internal row address strobe signal / RAS is applied is applied to inverter circuit 2633 and clocked inverter 2
634, and the internal row address signal int.
It is continuously output as Ara.

FIG. 88 shows the column address latch 2 shown in FIG.
604 is a figure which shows an example of the specific structure of 604. In FIG. 88, a column address latch 2604 receives an external address signal Aa at one input and receives an internal row address strobe signal / RAS at the other input.
1, a clocked inverter 2642 receiving an output of the NOR circuit 2641, an inverter circuit 2643 receiving an output of the clocked inverter 2642, and an inverter 2
643 includes a clocked inverter 2644 receiving the output of 643.

Clocked inverter 2642 is activated when internal column address strobe signal CAL is at "L" and internal column address strobe signal / CAL is at "H", and functions as an inverter. The internal column address strobe signal CAL is "H" and the internal column address strobe signal / C
When AL is “H”, the clocked inverter 2642 is in an inactive state, and is in an output high impedance state.
Clocked inverter 2644 is activated when internal column address strobe signal / CAL is at "L" and internal column address strobe signal CAL is at "H", and functions as an inverter. Clocked inverter 264
4 is inactive when the internal column address strobe signal CAL is at "L" and the internal column address strobe signal / CAL is at "H", and enters an output high impedance state. When clocked inverter 2644 is in an active state, inverter circuit 2643 and clocked inverter 2644 form a latch circuit, and node N20
Is latched. Internal column address signal int.Arc is generated from node N20. Next, the operation will be described.

When internal row address strobe signal / RAS is at "H", the output of NOR circuit 2641 is at "L". At this time, the internal column address strobe CAL,
Since / CAL is not generated, clocked inverter 2642 functions as an inverter and transmits an "H" signal to node N20.

Internal row address strobe signal / RAS
Falls to "L", NOR circuit 2641 functions as an inverter. At this time, the NOR circuit 2641 outputs a signal obtained by inverting the external address signal Aa. After a predetermined time elapses after the internal row address strobe signal / RAS falls to "L", internal column address strobe signals CAL and / CAL are generated and clocked inverter 2
642 is in an output high impedance state, while clocked inverter 2644 is activated to function as an inverter. Thereby, the signal potential appearing at node N20 when internal column address strobe signals CAL and / CAL are generated is changed to internal column address signal int.A
It is continuously output as rc.

The structure shown in FIGS. 87 and 88 shows the structure of a portion related to one bit of external address signal Aa, and corresponds to each bit of external address signal Aa. A circuit shown at 88 is provided.

A reset signal generating circuit 2 shown in FIG.
The circuit 605 may have any circuit configuration as long as it detects that the internal row address strobe signal / RAS has fallen to "L" and generates a reset pulse RS after a predetermined time has elapsed. The reset signal generation circuit can be easily realized by a circuit for delaying the row address strobe signal / RAS and a circuit configuration for generating a one-shot pulse signal in response to the output of the delay circuit.

The reset signal generation circuit 2605
May be generated from DRAM array drive circuit 260 shown in FIG. At this time, the DRAM array drive circuit 260 has generated a signal for activating circuits in a portion related to the row selection operation of the DRAM array. What is necessary is just to make the circuit configuration that generates. For example,
A configuration in which a reset pulse RS is generated after a predetermined time has elapsed after a sense amplifier activation signal for performing a sensing operation in DRAM array 101 is generated can be used.

Next, a configuration for setting the operation mode of the CDRAM in accordance with the purpose of use, that is, one of a high-speed operation mode and a low power consumption operation mode will be described. A command register is used for mode setting.

As shown in FIG. 89, data input pins DQ3 (D3) and DQ2 when register WR0 is selected.
The operation mode of the CDRAM is set according to the data value of (D2).

When DQ3 (D3) and DQ2 (D2) are both set to "0", the first high-speed mode is designated. D
By setting Q3 (D3) and DQ2 (D2) to "0" and "1", the low power consumption operation mode is designated. If DQ3 (D3) and DQ2 (D2) are set to "1" and "0", the second high-speed operation mode is designated. Here, the input terminal is set to D when register WR0 is set.
What is indicated as Q (D) is that the DQ separation mode is designated by the register RR1 or the register R
This is because the function of the pin differs depending on whether the masked light mode is selected by R0. Next, the data DQ3 (D3) and DQ2 (D2) of the register WR0
The operation mode realized by the data AB given in FIG.

FIG. 90 shows a high speed operation mode of the CDRAM. The first high-speed operation mode is selected by setting both data AB of the upper two bits of the register WR0 to "0". In this state, the row address signal (ROW) is first taken in at the first rising edge of clock signal K (# 1) of clock signal K, and then the rising edge of third clock signal K (# 3) Fetches a column address signal (COL). The operation of the CDRAM is started from the falling edge of the third clock signal # 3.

The second high-speed operation mode is selected by setting upper two bits of data AB of command register WR0 to “1” and “0”. In the second high-speed operation mode, the first clock signal K (#
The row address signal (ROW) is taken in at the rising edge of 1), and the second clock signal K1 (#
The column address signal (COL) is taken in at the rising edge of 2).

Therefore, when accessing the DRAM array at the time of a cache miss of the CDRAM or the like, the operation speed can be set to an optimum value according to the purpose of use. The time required to access the DRAM array can be set to an optimal value according to the processing purpose, and flexible system construction is facilitated.

FIG. 91 is a signal waveform diagram representing an operation for operating the CDRAM in the low power consumption mode. This low power consumption mode is designated by setting upper two bits AB of command register WR0 shown in FIG. 89 to "0" and "1", respectively. In this low power consumption mode, a row address signal (ROW) is taken in at a rising edge of clock signal K, and a column address signal (COL) is taken in at a falling edge of clock signal K. In this case, even if clock signal K is generated intermittently as described above or the period of clock signal K is temporarily lengthened, row and column address signals are taken in with a single pulse. Even when the clock cycle becomes longer, row and column address signals can be taken in with a single clock signal. Since the DRAM operates immediately after the capture of the column address signal, it is possible to obtain a CDRAM that can operate at high speed with low power consumption.

FIG. 92 is a diagram showing a circuit configuration for setting the timing for taking in external address signal Aa according to the operation mode. The circuit configuration shown in FIG.
Is used as a column address strobe signal generation circuit 2602 shown in FIG. That is, the column address strobe signal generation circuit shown in FIG. 92 is used instead of the column address strobe signal generation circuit shown in FIG. The remaining circuits can use the circuits described above. Referring to FIG. 92, a column address strobe signal generation circuit 2602 '
Receives an output of AND circuit 2701 at its set input / S1, receives an internal row address strobe signal / RA
And a flip-flop 2702 receiving S through inverter circuit 2709 at its reset input / R1. The output / Q1 of flip-flop 2702 is connected to AND circuit 270
1 to the other input. Flip-flop 2702
Is set or reset when a signal of "L" is applied to input / S1 or / R1.

Circuit 2602 'also has an OR circuit 2703 receiving clock signal K at one input thereof, an OR circuit 2710 receiving output / Q1 of flip-flop 2702 and internal row address strobe signal / RAS, and an output of OR circuit 2703. Input S2 and OR circuit 27
It includes a flip-flop 2704 having a reset input R2 receiving the output of ten. Output Q2 of flip-flop 2704 is applied to the other input of OR circuit 2703.
Flip-flop 2704 enters the set state when the output of OR circuit 2703 rises to “H”, and enters the reset state when the output of OR circuit 2710 rises to “H”.

The circuit 2602 'further includes a clock signal K
Circuit 2705 receiving at its one input, output Q2 of flip-flop 2704 and inverter circuit 270
And an flip-flop 2 receiving the output of AND circuit 2705 at its set input / S3 and receiving the output of AND circuit 2711 at its reset input / R3.
706. Output Q3 of flip-flop 2706 is applied to the other input of AND circuit 2705. Flip-flop 2706 attains a set state in response to the fall of the signal applied to set input / S3, and enters a reset state in response to the fall of the signal applied to reset input / R3.

Circuit 2602 'also includes an OR circuit 2707 receiving clock signal K at one input thereof, an OR circuit 2712 receiving output / Q3 of flip-flop 2706 and internal row address strobe signal / RAS, and OR circuit 2707. Flip-flop 2708 receives an output at its set input S4 and receives the output of OR circuit 2712 at its reset input R4. Flip-flop 270
The output Q4 of 8 is applied to the other input of the OR circuit 2707. This flip-flop 2708 has a set input S4
To the set state in response to the rising of the signal applied to reset input R4.

Column address strobe signal generating circuit 260
2 'further includes the Q2 output of the flip-flop 2704 and the data B (D in FIG. 89) set in the register WR0.
AND circuit 2715 receiving the output / Q1 of flip-flop 2702, the output of inverter 2713 and register W
Data A set to R0 (data DQ3 shown in FIG. 89)
AND circuit 2714 receiving the AND) and AND circuit 2
OR circuit 27 receiving the output of output 714, the output of AND circuit 2715, and the output Q4 of flip-flop 2708
16 and an inverter circuit 2717 receiving the output of the OR circuit 2716. A column address strobe signal CAL is generated from OR circuit 2716, and inverter circuit 271
7, a column address strobe signal / CAL is generated. Next, the operation will be described with reference to FIG. 93 which is an operation waveform diagram.

First, the case where the low power consumption mode is set will be described. At this time, data A is “0”
(“L”), and the data B is “1” (“H”). In this state, the output of AND circuit 2714 is at "L". In addition, flip-flops 2702, 27
04, 2706 and 2708 are in a reset state.
When the external clock signal K rises for the first time, the output of the AND circuit 2701 becomes "H". At this time, flip-flop 2702 holds the previous reset state only when the signal applied to its set input / S1 rises from "L" to "H". In response to the rising of clock signal K, internal row address strobe signal / RAS is set to "L".
Fall. At this time, since the flip-flop 2702 is in a reset state, this flip-flop 2702
Is at "H", and the output of the OR circuit 2710 also becomes "H".

In response to the rising of clock signal K, OR
Even if the output of circuit 2703 rises to "H", O
By the output from the R circuit 2710, the flip-flop 2
704 is set, and its output Q2 becomes "H". At this time, the output of the AND circuit 2711 is "L" and the output of the OR circuit 2712 is "H" (the output / Q3 of the flip-flop 2703 is "H"), so that the flip-flops 2706 and 2708 are also in the reset state. The state is maintained. Therefore, in this state, the output of AND circuit 2715 is "L",
The output of the circuit 2716 also becomes “L”.

When clock signal K falls to "L", A
The output of ND circuit 2701 falls to "L", flip-flop 2702 is set, and output / Q1 of flip-flop 2702 falls from "H" to "L". In response, the output of inverter circuit 2713 rises to "H". Since data B is at the "H" potential level, the output of AND circuit 2715 rises to "H" in response to the fall of "L" of output / Q1 of flip-flop 2702. As a result, the output of OR circuit 2716 rises, and internal column address signal CAL becomes “H”.
Then, internal column address signal / CAL falls to "L".
This realizes a low power consumption mode in which the row address signal and the column address signal are taken in at the rising edge and the falling edge of one pulse (# 1) of clock signal K, respectively.

Next, a description will be given of a second high-speed operation mode in which a row address signal and a column address signal are taken in at the rising edge of each clock signal. In this case, data A is 1
(“H”), and data B is set to 0 (“L”). In this case, the output of the AND circuit 2715 is “L”
Fixed. In this case, the output of the AND circuit 2714 becomes “H” when the output Q2 of the flip-flop 2704 rises to “H”. The output Q2 of the flip-flop 2704 rises to "H" because the flip-flop 27
04 is released from the reset state, and the output of the OR circuit 2703 rises to "H". More specifically, OR circuit 2703 responds to the rising of clock signal K (# 2) applied after flip-flop 2702 is set and its / Q1 output attains "L".
Becomes "H" when the flip-flop 270
4 is set. Therefore, in the second high-speed operation mode, the column address strobe signal CAL is set to “H” and the internal column address strobe signal / CAL is set to “L” in the second clock signal K (#
This is at the time of the rising edge of 2). Thereby, the second high-speed operation mode is realized.

Next, a column address is fetched at the third rising edge of clock signal K (# 3).
Will be described. In this case, data A and B are both set to “0”. In this state, the outputs of AND circuits 2714 and 2715 both become "L". Output Q of flip-flop 2704
2 rises to "H" in response to the second rising (# 2) of the clock signal K. As a result, the AND circuit 271
1 becomes "H", and the flip-flop 2706 is released from the reset state. In response to the second falling (# 2) of clock signal K, the output of AND circuit 2705 falls to "L", flip-flop 2706 is set, and output / Q3 of flip-flop 2706 is set.
Falls to “L”. When the output / Q3 of flip-flop 2706 falls to "L", OR circuit 271 is output.
2 becomes “L”, and the flip-flop 2708 is released from the reset state. When the output of OR circuit 2707 rises to "H" at the third rising of clock signal K (# 3), flip-flop 2708 enters a set state, and the potential of output Q4 rises to "H". Thus, the output of the OR circuit 2716 becomes “H”. Thus, a first high-speed operation in which a row address signal is taken in at the first rise of clock signal K and a column address signal is taken at the third rise of clock signal K is realized.

In any of the operation cycle modes,
After a predetermined time elapses, internal row address strobe signal / RA
When S rises to "H", flip-flop 2702,
2704, 2706 and 2708 are all in the reset state. These flip-flops 2702, 2704,
2706 and 2708 have the same configuration as the flip-flops 2612 and 2623 previously shown in FIGS.

As described above, by operating the CDRAM synchronously with the external clock signal K, the cycle time delay caused by the address skew and the like can be reduced as compared with the method of generating the internal clock signal using the address change detection circuit. Can be prevented, and accurate control can be performed.

Also, at this time, by arbitrarily setting the timing for taking in the column address of the DRAM in particular, it is possible to flexibly cope with both applications where importance is placed on low power consumption and applications where importance is placed on high-speed operation. CDRAM can be obtained.

In the above-described configuration, the configuration in which the timing for taking in the column address is variable is not limited to the CDRAM. Can be obtained. Further, the configuration may be such that the row address signal and the column address signal are supplied to different pin terminals.

Next, the CD according to the second embodiment of the present invention will be described.
FIG. 94 shows a list of operation modes provided in the RAM and the states of control signals for designating each operation mode. C
The operation modes of the DRAM include a chip select signal E #, a cache hit signal CH #, and a write enable signal W.
#, A refresh instruction signal REF #, and control signals CC1 # and CC2 #. In FIG. 94, “H” indicates a high-level signal potential, and “L” indicates a low-level signal potential. As shown in FIG. 94, the operation modes of the CDRAM include a cache mode TH for accessing an SRAM cache, a command register set mode TG for setting command data in a command register, and a CDRA.
A standby mode TS for setting M to a standby state; a cache miss mode TM for performing an operation upon a cache miss (miss hit); a direct array access mode TD for directly accessing a DRAM array; a refresh mode TR for refreshing a DRAM array; and a DRAM array. Check mode TC for checking a counter that generates a row address for refreshing data
including. Combinations of signal states and timings for setting each operation mode will be described later in detail with reference to operation waveform diagrams. First, an operation at the time of a cache miss will be briefly described.

At the time of a cache miss, that is, a mishit, the data requested by the CPU is not stored in the SRAM cache.
It is necessary to transfer from the M array to the SRAM cache. This transfer is performed by a bidirectional transfer gate circuit (D
TB) 210. The data transfer operation will be described with reference to FIG. Bidirectional transfer gate circuit 210
Represents the data in the DRAM array 101 as the SRAM array 20
1 and a transfer gate DTB1 for latching data from the SRAM array 201 and transferring the data to the DRAM array 101. (FIG. 3
0, see the configuration of the data transfer gate in FIG. 41)

Now, assume that data D2 is stored in area D of SRAM array 201, and the CPU requests data D1 in this area D. In this case, it is a cache miss state. At this time, according to the address output by the CPU, the data D1
And transmits it to the transfer gate DTB2. Concurrently, the data D2 stored in the SRAM array 201 is latched by the transfer gate DTB1. Transfer gate DTB
2 is transferred to the SRAM array 20
1 is transferred to the corresponding area D. Data D2 is latched by transfer gate DTB1. After the data D1 is transferred to the SRAM array 201, the CPU
The RAM array 201 can be accessed. On the other hand, in the DRAM array 101, the transfer gate DT
In order to receive data D2 from B1, it is temporarily set to a precharge state. Next, an address indicating an address where data D2 is to be stored is applied to DRAM array 101 from, for example, a tag memory, and a row selecting operation is performed according to this address (hereinafter, referred to as a miss address). After the row selecting operation is performed, data D2 stored in transfer gate DTB1 is transferred to the corresponding area.

By performing bidirectional data transfer as described above, even in the case of a cache miss, the DRAM array 101 does not wait for return to the precharge state immediately after data transfer from the DRAM array 101 to the SRAM array 201. In addition, the CPU can access the SRAM array 201 to read / write desired data.
The operation in each operation mode (high-speed mode, low power consumption mode) at the time of this data transfer will be described in detail below with reference to the operation waveform diagram shown in FIG.

First, the chip select signal E # is set to "L" at the rising edge of the clock signal K, and the cache hit signal CH # is set to "H" to initialize the cache miss cycle TM (initiate) cycle. TMMI is performed. In this cache miss initialization cycle TMMI, at the rising edge of clock signal K, SRAM address Ac is enabled and taken into the device, and row address signal (R) of DRAM address Aa is taken into the device. . In the low power consumption mode, the column address signal (C) in DRAM array Aa is taken in at the falling edge of clock K. In the second high-speed operation mode, the column address signal (C) is taken in at the rising edge of the third clock signal K.

When clock signal K rises for the second time, array active cycle TMMA is then started.
In this array active cycle TMMA, D
A memory cell selection operation is performed in the RAM array according to the CPU address, and the selected memory cell data is transferred to the SRAM array. From DRAM array to S
After the data is transferred to the RAM array, the SRAM array selects data according to the previously fetched SRAM address, and outputs the selected data Q. At this time, the data transferred from the SRAM array to the transfer gate is still latched by the transfer gate DTB1.
This state completes the array active cycle TMMA. At this time, the time required from when the clock signal K first rises to when the data Q requested by the CPU is output is tKHAA, which is required after the DRAM column address is fetched and the output data Q is output. Time is tCAA.

After completion of array active cycle TMMA, a precharge cycle TMMP for precharging the DRAM is performed. During this precharge period, the SRAM cache can be accessed. S
The chip select signal E # and the cache hit signal CH # are set to "H" or "L" according to the presence or absence of access to the RAM, and data is output according to the state at that time. On the other hand, in the DRAM array, an internal precharge operation is performed, and various signal lines are precharged to a desired potential. After the precharging of the DRAM array is completed, the transfer gate DTB1 is transferred from the SRAM array.
An array write cycle TMA for writing the data transferred to the corresponding position of the DRAM array is performed.

The array write cycle TMA is started by first performing an initialization cycle (initial cycle) TMA. This initialization cycle is set by setting the chip select signal E # to "L" at the rising edge of the clock signal K. Thereby, for example, a miss address given from the tag memory is given to the DRAM array, and the given miss address is taken as a row address signal (R) and a column address signal (C) according to the operation mode in the DRAM array. Put in. After capturing this row and column address signal, DR
An array active cycle and a precharge cycle TMAA of an array write for actually writing data latched in the AM array are performed.

In the array active / precharge cycle TMAA, a corresponding memory cell is selected from the DRAM array according to the applied miss address, and the data already latched in the bidirectional transfer gate DTB1 is stored in the selected memory. Written to the cell. DR
In parallel with the data write cycle in the AM array,
The CPU can independently access the SRAM array.

The cycle time of clock signal K is tK, and the array cycle time of the DRAM (the time required to directly access the DRAM array and read the desired data) is given by ta. The cycle time required for the miss read / write cycle TMM at the time of a cache miss is equal to or longer than the array cycle time ta, and the cycle time of the array write cycle TMA is also equal to or longer than the array cycle time ta.

FIG. 97 is a signal waveform diagram showing a cache hit read operation in the low power consumption mode. This cache hit read operation (LTHR) shows a data output waveform in the transparent output mode. In the cache hit read operation, at the rising edge of the clock signal K, the chip select signal E # is set to "L", the cache hit signal CH # is set to "L", the control signal CC1 # is set to "L", the refresh instruction signal REF #, Signal CC
2 # and the write enable signal W # are set to "H". At this time, the clock signal K
At the rising edge of, the SRAM address (CPU address) Ac is fetched, and the SRAM cache is accessed. By causing output enable signal G # to fall from "H" to "L", data Q1 corresponding to SRAM address C1 captured after a lapse of time tKHA from the rising edge of clock signal K is output.

In a hit read cycle THR at the time of a cache hit, only access to the SRAM cache is performed, and data is output in the same clock cycle as clock signal K. Here, the reason why the control signal CC1 # is set to “L” only in the first hit / read cycle is to execute an array write cycle of data transfer in the DRAM array. The cycle time of the DRAM array requires a plurality of cycles. Since the array write cycle is executed in the DRAM thereafter, the control signal CC1 # is set to "H" in the subsequent hit / read cycle. When output enable signal G # is at "L", the output of the data input / output circuit shown in FIG. 80 (see FIG. 16) is transmitted to the data output pin. When the address C2 is fetched, the address C
2 is output. When the output enable signal G # is “H”, the output data pin D /
Q is in a high impedance state. In the following description, the CDRAM is in the masked write mode, and a case where a pin M # for receiving mask data and a DQ pin for commonly inputting / outputting D data are shown.

FIG. 98 is a signal waveform diagram representing a cache hit write operation. Cache hit mode THW
Sets the chip select signal E #, the cache hit signal CH #, and the write enable signal W # to "L" at the rising edge of the clock signal K, and sets the control signal CC1
#, CC2 # and refresh instruction signal REF # are set to "H". At this time, the output enable signal G # is set to "H". In this state, at the rising edge of clock signal K, SRAM address signal C1 is taken in, and data D1 applied to data input / output pin DQ at that time is taken in. At this time, in the masked write mode, the data written at this time can be masked by setting the signal potential applied to the data pin M # to "H" or "L". Since the cache hit write mode THW at the time of this cache hit write operation only accesses the SRAM array, the cycle time of the hit write mode THW is the same as the cycle time tK of the clock signal K.

FIG. 99 is a signal waveform diagram representing a cache miss read operation in the low power consumption mode. The cache miss read operation is first started by a miss initiate cycle TMMI. In this initialize cycle TMMI, the chip select signal E # is set to “L” at the rising edge of the clock signal K, and the remaining control signals CH #, C #
It is started by setting C1 #, REF #, CC2 # and W #, and G # to "H". In the initialize cycle TMMI, first, the SRAM address Ac1 is taken in to specify the address of the SRAM array, and at the same time, the same address is given as the DRAM array address signal Aa. At this time, the data transfer is performed collectively, for example, for 16 bits (16 bits × 4) for one memory array. Since the output data is 4 bits, the DRAM address signal Aa is
Of the address (CPUAdd) given from the address table, only the required address bits except the lower address bits are applied.

For low power consumption operation, DRAM address signal Aa is taken in as a row address (ROW) at the rising edge of clock signal K, and column address signal COL is taken at the falling edge of clock signal K. In this state, a memory cell selecting operation in the SRAM array and the DRAM array is performed, and corresponding memory cell data is transferred from the DRAM to the SRAM array. The data selection operation of the DRAM array is performed by setting array active cycle TMMA. This array active cycle TMMA is designated by clock signal K.
By setting all signals to "H" at the rising edge of.

In the array active cycle TMMA, the output enable signal G # falls to "L", whereby data Q1 selected according to the address signal C1 in this SRAM array is output after a predetermined time has elapsed. The transition to the precharge cycle after the completion of the array active cycle in the DRAM
This must be performed in order to write data read from the RAM array and latched by the bidirectional transfer gate circuit into the DRAM array. The setting of the precharge cycle TMMP at the time of the miss read uses the same signal combination at the rising edge of the clock signal K as when the standby is designated or the cache hit operation TH is designated. At this time, if the chip select signal E # is set to "L" and the cache hit signal CH # is set to "L", during the DRAM array precharge cycle, the SRA
Data can be read from the M array.

FIG. 100 is a signal waveform diagram showing a cache miss write operation in the low power consumption mode. This cache miss write operation is realized by setting the chip select signal E # and the write enable signal W # to "L" at the rising edge of the clock signal K. At this time, first, an initialization cycle TMMI of the cache miss write operation is executed. The cache miss write operation differs from the cache miss read operation shown in FIG. 99 only in the direction of data flow.
After or at the same time as the corresponding data is transferred from the array, data D1 is written into the corresponding memory cell according to address signal C1 for the SRAM array. The only difference is whether the write enable signal W # is "L" or not.

FIG. 101 is a signal waveform diagram representing an array write operation. In this array write operation, SRA
The data is transferred from the M array to the bidirectional transfer gate circuit, and the latched data is written to the corresponding memory cell of the DRAM array. Array write operation cycle LTMA
Includes an initialization cycle TMAI and an array active cycle TMAA. The initialization (initialize) cycle TMAI is set by setting the chip select signal E # and the control signal CC2 # to "L" and setting the control signal CH # and the control signal CC1 # to "H" at the rising edge of the clock signal K. It is done by doing. By the initialization cycle TMAI of the array write operation cycle LTMA in the low power consumption mode, the address signal (MissAdd) provided from an external device such as a tag memory is taken in according to the rising edge and the falling edge of the clock signal K. Thus, an internal row address signal and an internal column address signal are generated. Following the initialize (initialization) cycle TMAI, the chip select signal E # and the cache hit signal CH # are set to "L" and the control signal CC1 # at the rising edge of the clock signal K. Thereby, a cache hit operation is set together with the array active cycle TMMAA. At this time, if the write enable signal W # is set to "L", the SRAM address signal Ac is fetched, and data is written to the SRAM array corresponding to the fetched address C2. At this time, mask data M # may be given. In the array active cycle TMAA in the array write operation, a DRAM memory cell is selected in accordance with the fetched address, and the data latched at the bidirectional transfer gate is written to the selected DRAM memory cell.

FIG. 102 is a signal waveform diagram showing an array write operation accompanied by a cache hit read operation. The array write operation accompanied by the cache hit read shows the case of the low power consumption mode. In this cycle LTMAR, data is read from the SRAM cache in parallel with the data transfer from the bidirectional transfer gate to the DRAM array. .

The setting of the operation cycle LTMAR includes:
At the rising edge of clock signal K, chip select signal E #, control signal CC1 #, and cache hit signal CH # are set to "L", and control signal CC2 # and write enable signal W # are set to "H". Since refresh is not performed, refresh instructing signal REF #
Is "H". By setting this signal, an initial cycle TMAI of the array write operation is performed, and a cache read / read cycle THR is performed. That is, in this operation mode, first, the SRA
M address signal Ac is taken in at the rising edge of clock signal K, and corresponding data Q1 is output.

On the other hand, DRAM address signal Aa is taken in as a row address signal and a column address signal at the rising edge and falling edge of clock signal K, respectively. At this time, as a DRAM address signal Aa, an address signal (MissAdd) from an externally provided tag memory, for example, is applied to select a memory cell to which data latched in the bidirectional transfer gate is to be written. Thereby, the data transfer operation to the DRAM array is performed in parallel with the read operation to the cache of the SRAM array.

The execution of an array write cycle is performed by setting an array active and precharge cycle TMAA. The setting of the array active / precharge operation in the array write operation accompanied by the cache hit read is performed by setting the chip select signal E # to "L", setting the cache hit signal CH # to "L", and controlling the control signals CC1 # and CC2 #. Are set to “H”.

FIG. 103 is a signal waveform diagram showing an array write operation cycle LTMAW with a cache hit write in the low power consumption mode. Array write operation cycle LTMAW with cache hit write
Is set at the rising edge of the clock signal K, the chip select signal E #, the cache hit signal CH #, and the control signal CC1 # are set to "L", and the control signal CC
This is performed by setting 2 # and refresh instruction signal REF # to "H". By setting this signal state, an array write initialization cycle TMAI and a hit write cycle THW are set. In response,
At the rising edge of clock signal K, SRAM address signal Ac for selecting an SRAM array is fetched and DRA
M address signal Aa is taken in at the rising edge of clock signal K.

The DRAM address signal Aa is taken in at the falling edge of the clock signal K to generate an internal column address signal. Since this DRAM address signal Aa is an array write operation, it is not the address where the data causing the cache miss should be written, that is, the address given by the CPU, but the address MissAdd given by an external device such as a tag memory. Array write operation cycle LTMA with cache hit write
W is the same except that the state of the array write operation cycle LTMAR with cache hit read shown in FIG. 102 and the write enable signal W # is different. That is, data is written to the SRAM array in accordance with the CPU address in parallel with the transfer of the data latched by the bidirectional transfer gate to the DRAM array.

FIG. 104 is a signal waveform diagram showing a direct array read operation cycle LTDR in the low power consumption mode. In this direct array read operation cycle LTDR, the DRAM array can be directly accessed to read the corresponding memory cell data of DRAMA. In the direct array read operation cycle LDDR, first, at the rising edge of clock signal K, chip select signal E # and control signal CC1
# To “L”, the control signal CC2 # to “H”, the cache hit signal C1 #, the write enable signal W #,
And the refresh instruction signal REF # is set to “H”. By setting this state, first, the initialize cycle TDI in the direct read array cycle LDDR is set.

In the begin cycle TDI, the DRAM address signal Aa is taken in as a row address signal (ROW) at the rising edge of the clock signal K, and then the DRAM address signal Aa and the SRAM address terminal at the falling edge of the clock signal K. Are fetched. Here, during the direct array read operation, the SRA
The reason why the M address signal is also used together is as follows.

In normal array access, batch transmission of 16-bit data per memory block is performed. In the case of a 4M bit DRAM, data of 16 bits × 4 is transferred, so that only a total of 16 bits are generally provided as a row address signal and a column address signal. Therefore, at the time of the direct array read operation, in order to select 4 bits from the memory cell of 16 × 4 bits, SR is used as the lower address signal.
The AM address signals Aac0 to Aac3 are taken in. The fetched 4-bit SRAM address signals Aac0 to Aa
According to c3, a configuration for selecting 4-bit data from the SRAM column decoder may be used. in this case,
Data selected by the DRAM is transmitted and selected via the SRAM bit line. At this time, another configuration may be used.

Next, an array active / precharge cycle TDA in which a memory selecting operation and a data reading operation in the DRAM array are performed is executed. In order to set the array active / precharge cycle TDA during the direct array read operation, all control signals are set to "H". The output timing of the output data Q1 is determined by the output enable signal G #. Thus, the direct array read operation cycle LTDR for directly accessing the DRAM array and reading the memory cell data is completed.

[0523] Direct array read operation cycle LT
After completion of DR, if both chip select signal E # and cache hit signal CH # are set to "L" at the rising edge of clock signal K, SRAM address signal Ac
Read operation of the memory cell according to the above.

FIG. 105 is a signal waveform diagram showing a direct array write operation cycle LTDW in the low power consumption mode. In the direct array write operation cycle LTDW shown in FIG. 105, direct data writing to the DRAM array is performed according to the external address signal. The direct array write operation cycle LTDW is designated by setting the chip select signal E #, the control signal CC1 #, and the write enable signal W # to "L" at the rising edge of the clock signal K, and setting the cache hit signal CH #, refresh Instruction signal REF #, control signal CC2 #, and output enable signal G
# Is set to "H". This direct array write operation cycle LTDW corresponds to FIG.
And the write enable signal W # is set to "L" at the rising edge of the clock signal K.
At this time, data D1 given at the rising edge of clock signal K is applied to DRAM address signals Aa and 4a.
Writing to the selected DRAM memory cell is performed according to bit SRAM address signals Aac0 to Aac3.

[0525] Direct array write operation cycle LT
DW is the initial cycle TDI and the actual DRAM
An array active / precharge cycle TDA for activating the array is included. This array active / precharge cycle TDA is the same as array active cycle TDA shown in FIG. When the DRAM access cycle time ta passes, the SRAM cache can be accessed from outside.

FIG. 106 shows a refresh array operation. This refresh array operation mode LTR
, The DRAM array is refreshed by a refresh control circuit 292 and a counter 291 shown in FIG.
Is performed under the control of. In this case, the refresh row address indicating the row to be refreshed is generated from counter 291 shown in FIG. This refresh cycle is designated by setting refresh instructing signal REF # to "L" at the rising edge of clock signal K.

As a result, a refresh initialize cycle TRI is set, and an array active cycle TRA in which the DRAM array is actually refreshed is executed from the next rise of clock signal K. In the array active cycle TRA in the refresh array operation mode LTR, all control signals are set to "H". FIG. 106 shows a case where a cache hit read operation is performed after refresh is completed.

FIG. 107 is a signal waveform diagram showing a refresh array operation mode involving a cache hit read during low power consumption operation. The refresh array operation is performed only for the DRAM array, and the SRAM array does not need to refresh. Therefore, data can be read by accessing the SRAM array in parallel with the refresh array operation. In the refresh array operation mode LTRR for performing a cache hit read, the rising edge of the clock signal K
Chip select signal E #, cache hit signal CH #
The refresh instruction signal REF # is set to "L", and the control signals CC1 # and CC2 # and the write enable signal W # are set to "H".

[0531] DR is instructed by refresh instructing signal REF #.
A refresh operation of the AM array is instructed, and the cache hit operation is designated by the chip select signal E # and the cache hit signal C1 #. At this time, in the DRAM array, an auto-refresh operation is performed by an output of a built-in address counter. Following the refresh initialization cycle TRI, the DRAM array is refreshed in the array active cycle TRA according to the refresh row address. SR
In the AM array, data is read according to an externally applied address signal Ac.

FIG. 108 is a signal waveform diagram showing a refresh operation mode for performing a cache hit read in the low power consumption mode. Refresh operation mode LTRW involving cache hit write shown in FIG. 108
Is the same as the refresh array operation with cache hit read shown in FIG. 107 except that the write enable signal W # falls to "L". in this case,
In the SRAM array, data is written according to an address signal Ac, and in the DRAM array, the DRAM array is refreshed according to a refresh address.

FIG. 109 is a signal waveform diagram showing a counter check read operation in the low power consumption mode.
The counter check read operation mode LTCR is D
This is an operation mode for testing whether or not an address counter for generating a refresh row address for refreshing the RAM array functions normally. The counter check read operation mode LTCR is set by setting the chip enable signal E #, the control signal CC1 #, and the refresh instruction signal REF # to "L" at the rising edge of the clock signal K, and setting the control signals CC1 #,
The write enable signal W # is set to “H”. In this counter check read operation mode LTCR,
In the initialize cycle TCI, the lower 4 bits Aac0 to Aac3 of the SRAM address signal Ac are taken in as the lower 4 bits of the column address signal of the DRAM array at the rising edge of the clock signal K.

Then, at the falling edge of clock signal K, DRAM address signal Aa is taken in as a column address signal (upper column address signal). 4Mbit DR
In the case of an AM array, a 10-bit column address signal is required to select a 4-bit memory cell.
At that time, as described above, only 6 bits are given as a column address in the DRAM. Therefore, the remaining four bits are taken from the SRAM address signal pin. Next, by setting each control signal to “H” at the rising edge of the clock signal K, the DR according to the taken column address is set.
A memory cell selection operation in the AM array is performed,
The selected memory cell data is read. By comparing the read data with predetermined data or written data, it can be determined whether or not the refresh row address counter functions normally.

FIG. 110 is a signal waveform diagram showing a counter check write operation in the low power consumption mode. In the counter check write operation mode LTCW, the chip select signal E is output at the rising edge of the clock signal K.
#, Control signal CC1 #, refresh instruction signal REF
# And the write enable W # are set to "L", and the cache hit signal CH # and the control signal CC2 # are set to "H". At this time, the state of the control signal is the same except that the counter check read operation mode LTCR shown in FIG. 109 and the write enable signal W # are set to "L". Following the setting of the counter check write operation by the initialization (initialize) cycle TCI, an array active cycle TCA for actually accessing the DRAM array is executed. At this time, in the array active cycle, the address from the refresh row address counter is used as the row address, and externally applied column address signals Aac4 to Aac9 and Aac9.
A matrix selection operation is performed as ac0 to Aac3, and externally applied data is written to the selected DRAM memory cell.

FIG. 111 is a signal waveform diagram showing a command register setting operation in the low power consumption mode. FIG.
The command register setting operation mode LTG shown in FIG. 1 is a mode in which desired data is written to the command register 270 shown in FIG. By utilizing the command register setting operation mode LTG, the CDRAM can be set to a low power consumption operation mode, a first high speed operation mode, a second high speed operation mode, a masked write mode, a DQ separation mode, and the like. it can. To specify the command register setting cycle TG, the chip select signal E # and the control signal CC are set at the rising edge of the clock signal K.
1 # and CC2 #, the write enable signal W # is set to "L" (or "H"), and the refresh instruction signal REF # is set to "H". With this operation mode setting, the command address signal Ar is fetched, and the corresponding command register is selected. At this time, if the write enable signal W # is "L", for example, the operation mode /
Data is written to register WR0 for designating the output mode. When the write enable signal W # is set to “H”, the registers RR0 to RR included in the command register
One of R3 is selected according to command address bits Ar0 and Ar1. FIG. 111 exemplarily shows a case where data is written to any of command registers WR0 to WR3. In the command register setting operation mode LTG, the setting cycle T1 is completed in one cycle of the clock signal K.

FIG. 112 shows an example of an operation sequence of the CDRAM in the low power consumption mode. In the operation sequence shown in FIG. 112, an operation when a cache miss occurs is shown as an example. When a cache miss read occurs, only the chip select signal E # is set to "L" at the rising edge of the clock signal K. Thereby, an initialize cycle TMMI at the time of a cache miss read is performed, and the SRAM address signal C1 and the address signal A for the DRAM array are read.
a (CPU address) is fetched, followed by an array active cycle TMMA at the time of a miss read. In the array active cycle at the time of this misread, D
The memory cell data selected in the RAM array is an SRAM
The memory cell data transmitted to the memory cells of the array and corresponding to SRAM address signal C1 applied at the time of the cache miss is read out as output data Q1 in the last cycle at the time of the miss read.

In the DRAM array, the remaining precharge cycle TMMP of miss read operation cycle TMMR is performed. In this precharge cycle, the CPU can access the SRAM array. In FIG. 112, the hit read operation is set simultaneously with the setting of the precharge cycle, and the address signal C is set.
2 is read out.

[0537] Following this precharge cycle, S
An array write cycle is performed in which data is transferred from the RAM array to the bidirectional transfer gate and latched there. If there is a hit write cycle performed in parallel at this time, the array write cycle is set at the rising edge of the clock signal K at the chip select signal E #, the cache hit signal CH #, and the control signal CC.
1 # and the write enable signal W # are set to "L". As a result, the DRAM enters the array access cycle TMAA, and the address MissAdd given from, for example, the tag memory given next is input.
, A data transfer from the bidirectional transfer gate to the selected memory cell is performed.

In the SRAM array, data D is applied to a memory cell selected in accordance with SRAM address signal C3.
3 is written. In the array write cycle in the DRAM array, a hit read cycle and a hit read cycle are successively performed, and output data Q4, Q5 and Q6 are output corresponding to SRAM address signals C4, C5 and C6, respectively. After the hit read is performed, generation of the clock signal K is stopped to reduce current consumption. This state is shown as a standby state in FIG.

FIG. 113 is a diagram showing another example of the operation sequence in the low power consumption mode. This FIG. 113
Shows a cache miss write operation and a cache hit operation performed subsequently. First, when a cache miss write occurs, an initialization cycle TMMI of a cache miss write cycle is performed. At this time,
Chip select signal E # and write enable signal W
# Is set to “L”. As a result, an address signal for selecting a memory cell in the SRAM array and the DRAM array is taken. Subsequently, an array active cycle is performed, and the SR
Data transfer to the AM array is performed.

After completion of the data transfer or in parallel with the transfer, the data D1 in which the cache miss write has occurred is stored in the SR
Written to the corresponding location in the AM array. After the completion of the array active cycle, a precharge cycle of the DRAM array is performed. At this time, a hit read operation THR is performed on the SRAM. After the completion of the precharge operation, an array write cycle for writing data previously transferred from the SRAM array to the bidirectional transfer gate to the DRAM array is performed.

In the initialization cycle TMAI in the array write cycle, the cache hit cycle TH is performed at the same time, so that the control signal CC1 # is set to "L". After completion of the initialization cycle TMI in the array write, an array active and precharge cycle is performed next. A hit write operation, a hit read operation, and a hit write operation are performed in parallel with the array write cycle operation. After a predetermined time,
When access to the CDRAM does not occur, clock signal K has a longer cycle or is generated intermittently.

As shown in FIGS. 112 and 113, D
In the cycle of the RAM array write, 2 of the clock signal K is used.
Cycles, while accessing the SRAM array requires only one clock. Therefore, the CDRAM operates at a relatively low speed, and low power consumption is regarded as more important than high speed operation.

FIG. 114 is a signal waveform diagram showing a cache hit read operation in the high speed operation mode. FIG. 114 shows a case where data is output in the transparent output mode as the cache hit read operation mode THR in the high speed operation mode. The cache hit read operation mode THR in the high speed operation mode has the same signal waveform as that of cache hit read operation mode LTHR in the low power consumption mode shown in FIG. 97, and detailed description thereof will not be repeated. FIG. 114 shows data input / output terminals in the case of DQ separation mode. That is, in this case, the input data D and the output data Q are input and output via separate pin terminals, respectively.

FIG. 115 is a signal waveform diagram representing a cache hit read operation for outputting data in the latch output mode. The cache hit read operation mode THRL shown in FIG. 115 is performed according to the high speed operation mode. The combination of control signals for setting this operation mode is the same as that shown in FIG. The cache hit read operation mode THR shown in FIG.
The difference from the cache hit read operation mode THRL in the latch output mode shown in FIG. 5 is the timing of output data. That is, in this latch output mode, data read in the previous cycle is output to the invalid data area in the waveform of output data Q shown in FIG. That is, the data read in the previous cycle is continuously output until valid data is output in the next cycle. In this latch output mode, so-called invalid data is not output, and a stable data processing operation can be performed.

FIG. 116 is a signal waveform diagram showing the cache hit read operation mode in the register output mode in the high speed operation mode. The cache hit read operation mode THRR in this register output mode is shown in FIG.
4 and operation modes THR and THR shown in FIG.
This is realized by a combination of signal states similar to L. The register output mode differs from the transparent output mode (see FIG. 114) and the latch output mode (see FIG. 115) in that the memory cell data selected in the previous cycle is output in synchronization with the clock signal K. I have. In this register output mode, data read in the previous cycle is output in synchronization with a clock signal, and thus is suitable for applications such as pipeline use.

FIG. 117 is a signal waveform diagram showing a cache hit write operation in the high-speed operation mode. The cache hit write operation mode THW shown in FIG. 117
Since the combination of cache hit write operation LTHW and its signal state in the low power consumption mode shown in FIG. 98 is the same, description thereof will not be repeated.

FIG. 118 is a signal waveform diagram showing a cache miss read operation in the high speed operation mode. In the cache miss read operation mode TMMR in the high speed operation mode, the initialize cycle TMMI
Is completed in one clock cycle. However, in this high-speed operation mode, the column address signal is taken in at the third rising edge of clock signal K. This point is shown in FIG.
And the cache miss read operation mode LTMMR in the low power consumption mode shown in FIG.

FIG. 119 is a signal waveform diagram showing a cache miss read operation in the latch output mode in the high speed operation mode. The cache miss read operation mode TMMRL shown in FIG. 119 is the same as cache miss read operation mode TMRRL shown in FIG. 118. The difference is that data Q0 read in the previous cycle is output during a period during which invalid data in output data Q is output. The other points are the same as those shown in FIG.

FIG. 120 is a signal waveform diagram showing a cache miss read operation in the register output mode in the high speed operation mode. The cache miss read operation mode TMMRR shown in FIG. 120 is the same as the operation modes TMMR and TMMRL shown in FIGS. 118 and 119.
The only difference is the timing at which the output data Q is output. That is, in the latch output mode, the data read in the previous cycle is output for a fixed period during the period in which invalid data is output, and the signal read in the current cycle after a lapse of a fixed time from the falling point of the clock signal K is output. Is output.

In the register output mode, data is output in synchronization with clock signal K. At this time, if the time from the fall of output enable signal G # to the rise of clock signal K is short, the data read in the previous cycle is output in response to the rise of clock signal K. . Other points are shown in FIG. 118 and FIG.
This is the same as the operation cycle shown in FIG.

FIG. 121 is a signal waveform diagram showing a cache miss write operation in the high-speed operation mode. Cache miss write operation mode TMMW shown in FIG.
Indicates the cache miss write operation mode L shown in FIG.
This is the same as TMMW except that the timing for taking in the DRAM address signal Aa as a column address signal is different. At this time, an array active cycle TMMA cycle is also performed after completion of the initialize cycle TMI, and this array active cycle TMM is performed.
After completion of A, a precharge cycle TMMP is performed.

FIG. 122 is a signal waveform diagram representing an array write operation in the high-speed operation mode. The array write operation mode TMA shown in FIG. 122 is the array write operation mode LT in the low power consumption mode shown in FIG.
Only the timing for taking in the column address signal (COL) in the MA and DRAM address signals is different, and the remaining points are the same. In array write operation mode TMA in this high-speed operation mode, DRAM
The cache hit write operation is executed before the column selection in. The fact that the array write operation is performed indicates that the data transfer to the SRAM has already been completed. Therefore, it is possible to access the SRAM cache at this time.

FIG. 123 is a signal waveform diagram showing an array write operation accompanied by a cache hit read in the high-speed operation mode.

The address write operation mode TMAR with cache hit read shown in FIG. 123 corresponds to FIG.
The combination of the array write operation mode LTMAR and the state of the control signal in the low power consumption mode shown in FIG. 1 is the same, and the only difference is the timing at which the column address signal for accessing the DRAM array is taken.

FIG. 124 is a signal waveform diagram showing an array write operation accompanied by a cache hit read in the latch output mode in the high speed operation mode. In array write operation mode TMARL with cache hit read in this latch output mode, array write operation mode TMA with cache hit read shown in FIG.
R and its signal state are similar, only the timing at which the output data Q appears is different. That is, in this latch output mode, unlike the output data Q shown in FIG. 123, during the invalid data output period, the data read in the previous cycle is continuously output. Other points are the same.

FIG. 125 is a signal waveform diagram showing an arrayed write operation accompanied by a cache hit read at the register output in the high-speed mode operation. The array write operation mode TMARR with cache hit read shown in FIG. 125 is the same as the array write operation modes TMAR and TMARRL shown in FIGS. 123 and 124, except that the data output timing is different. In the register output mode, data read in the previous cycle is output in response to the rising of clock signal K.

FIG. 126 is a signal waveform diagram showing an array write operation accompanied by a cache hit write in the high-speed operation mode. The array write operation mode TMAW with cache hit write shown in FIG.
The combination of the array write operation mode LTNAW shown in FIG. 3 and the state of the control signal is the same. The only difference is the timing of taking in a column address signal as an address for accessing a DRAM array.

FIG. 127 is a signal waveform diagram representing a direct array read operation in the high-speed operation mode. The direct array read operation mode TD shown in FIG.
R is the same as the combination of the direct array read operation mode LTDR shown in FIG. 104 and the state of the control signal. The only difference is the timing at which the column address signal is taken in the DRAM address signal. Therefore, description thereof will not be repeated.

FIG. 128 is a signal waveform diagram representing a direct array write operation in the high-speed operation mode. The direct array write operation mode TD shown in FIG.
W is the same as the combination of the direct array write operation mode LTDW in the low power consumption mode shown in FIG. 105 and the state of the control signal. The only difference is the timing of taking in the column address signal for accessing the DRAM array. Therefore, description will not be repeated.

FIG. 129 is a signal waveform diagram representing a refresh array operation in the high-speed operation mode. This figure 1
The refresh array operation mode TR shown in FIG.
06 is exactly the same as refresh array operation mode LTR in the low power consumption mode, and description thereof will not be repeated.

FIG. 130 is a signal waveform diagram showing a refresh operation involving a cache hit read in the high-speed mode. Refresh operation mode TRR with cache hit read shown in FIG. 130 is exactly the same as refresh array operation mode LTRR with cache hit read shown in FIG. 107, and therefore, detailed description thereof will not be repeated.

FIG. 131 is a signal waveform diagram showing a refresh operation involving a cache write in the high-speed operation mode. The refresh operation mode with cache write TRW shown in FIG. 131 is exactly the same as the combination of the refresh operation mode with cache hit write and the state of the control signal shown in FIG. 108, and detailed description thereof will not be repeated.

FIG. 132 is a signal waveform diagram showing a counter check operation in the high-speed operation mode. This FIG.
The counter check operation mode TCR shown in FIG.
This is the same as the counter check read operation mode LTCR in the low power consumption mode shown in FIG. The only difference is the timing at which the column address signal bits Aac4 to Aac9 are fetched. Therefore, description will not be repeated.

FIG. 133 is a signal waveform diagram showing a counter check write operation in the high-speed operation mode. The counter check write operation mode TC shown in FIG.
W indicates the counter check write operation mode LTCW shown in FIG. 110 and the column address signal bits Aac4 to Aac9.
Only the acquisition timing is different, and the combination of the states of the remaining control signals is the same.

FIG. 134 is a signal waveform diagram representing a command register setting operation in the high-speed operation mode. The command register setting operation mode TG shown in FIG.
Command register setting operation mode LTG shown in FIG.
And the combination of the control signal states is the same.

As described above, in the high-speed operation mode, when it is necessary to access this DRAM array, only the timing of taking in the column address signal for accessing the DRAM array is different. Various operations can be easily realized by combining the same control signal states in each operation mode in the power mode.

FIG. 135 shows an example of the operation sequence of the CDRAM in the high-speed operation mode. In the operation sequence shown in FIG. 135, a case where a cache (SRAM) is accessed in parallel with the miss read operation when a miss read occurs is shown as an example. At the time of misread, first, FIG.
Similarly to the case shown in FIG.
Access to both AM arrays is performed. At this time,
Unlike the low power consumption mode shown in FIG. 112, column address signal COL1 for DRAM array access is taken in at the third rising edge of the clock signal. This misread operation mode TMM causes S
When the data transfer to the RAM array is completed, a precharge cycle starts in the DRAM array. Before the start of the precharge, the reading of the data Q1 by the address signal C1 is completed. A hit read operation is performed in parallel with this precharge cycle.

The hit read operation is performed three times during the precharge cycle. In the high-speed operation mode, a clock signal is applied three times in this precharge cycle, and C2, C3 and C4 are applied as SRAM array address signals Ac in each clock cycle, and output data Q2, Q3, respectively.
And Q4 are output. After the precharge operation is completed, an array write operation is performed. A hit write operation, a hit read operation, and a hit read operation are performed in the SRAM array in parallel with the array write operation.

Therefore, in the high-speed operation mode shown in FIG. 135, the cycle of clock signal K is short and DR
During access to the AM array, data can be read at high speed by accessing the SRAM array.

FIG. 136 shows another example of the operation sequence in the high-speed operation mode. In this case, an operation at the time of occurrence of a miswrite is shown as an example. In the operation sequence shown in FIG. 136, only the miswrite operation is performed instead of the misread operation shown in FIG. 135, and the operation sequence is the same. A hit read cycle, a hit read cycle, and a hit write cycle are performed during a precharge period after the completion of the array access. In the array access cycle after the completion of the precharge, the hit read cycle, the hit write cycle, and the hit read cycle are repeated. Is being done.

In each cycle, a command register cycle and an array active cycle / precharge cycle are included, and each cycle is determined by executing an initialize cycle.

[Another Example of Refresh Configuration] (Built-in Auto Refresh / Self Refresh) FIG.
FIG. 37 is a diagram showing another configuration example of the refresh method of the CDRAM of the present invention. 137, parts corresponding to the circuit configuration shown in FIG. 1 are denoted by the same reference numerals. In the configuration of the CDRAM shown in FIGS. 1 and 80, refresh instruction signal REF # externally applied is provided.
Is performed according to the following. That is, the CDRAM shown in FIGS. 1 and 80 can execute only the auto refresh. Hereinafter, a configuration capable of executing the self refresh even in the normal mode will be described.

Referring to FIG. 137, the CDRAM applies external control signals CR #, CH #, EH # and W # to internal clock int-K from clock buffer 254.
And a command register 270a for setting the refresh mode of the CDRAM to either auto refresh or self refresh.
And the command signal CM from the command register 270a.
, An input / output switching circuit 3102 for setting the pin terminal 3110 to either an input terminal or an output terminal.
The pin terminal 3110 corresponds to the pin terminal of the pin number 44 shown in FIG. When the pin terminal 3110 is set as an input terminal, an external refresh instruction signal R
Receive EF #. Pin terminal 3110, when set as an output terminal, outputs signal BUSY # indicating that self-refresh is performed in the CDRAM.

This CDRAM further includes a timer 3101 activated in response to the command register from command register 270a and outputting a refresh request at predetermined time intervals. The clock generator 3100
This corresponds to the configuration of control clock buffer 250 and DRAM array drive circuit 260 shown in FIG. 1 or FIG.

FIG. 138 is a diagram showing a specific configuration example of clock generator 3100 shown in FIG. FIG.
8, clock generator 3100 receives an externally applied command register set signal CR # and receives an internal control signal int. * CR buffer 3200 for generating CR and control signals CH # and E externally supplied
# And clock signal K, and receives internal control signal int.
RAS signal generating circuit 3201 for generating RAS, and R
AS control signal int.
* In response to RAS and external clock signal K, internal control signal int. * CAS signal generation circuit 3 that generates CAS
202.

[0576] The internal control signal int. * RAS is a signal that defines the operation of a circuit related to the operation of selecting a row of the DRAM array.
This internal control signal int. * DRAM in response to RAS
A row selecting operation and a sensing operation in the array are performed.
Internal control signal in from CAS signal generation circuit 3202
t. * CAS determines the operation of circuits related to column selection in the DRAM. A circuit related to the column selecting operation in the DRAM array includes a DRAM column decoder and the like.

The RAS signal generation circuit 3201 also receives the command signal CM from the command register and the timer 3101
In response to the refresh request signal * BUSY (internal signal) from the internal control signal int. * Includes a circuit that generates RAS. In this case, the external control signals E # and CH # are ignored. In response to the refresh request (signal * BUSY) from the timer 3101, the external control signal is ignored, and the internal control signal int. * The circuit configuration for generating RAS is, for example, “64 Kbit MOS dynamic RAM with built-in auto / self-refresh function”, IEICE Transactions 1
January 983, J66-C, No. 1.

Note that internal control signal int. Generated from RAS signal generation circuit 3201. * RAS and CA
Internal control signal i generated from S signal generation circuit 3202
nt. * CAS corresponds to FIG. 84 shown in the second embodiment.
May be generated from a row address strobe signal 2601 and a column address strobe signal generation circuit 2602 shown in FIG.

The clock generator 3100 further comprises
A refresh detection circuit 3203 for detecting that refresh has been instructed in response to an externally applied refresh instruction signal * REF (which indicates an internal signal);
The refresh control circuit 3204 controls the count value of the refresh address counter 293 in response to a refresh request from the refresh detection circuit 3203 and generates a switching signal MUX for switching the connection of the multiplexer 258.

[0580] The refresh control circuit 3204 further comprises:
In response to the command signal CM from the command register 270a, in response to the refresh request signal (* BUSY) given from the timer 3101, the same operation as when a refresh instruction is given from the refresh detection circuit 3203 is performed. And the operation of the multiplexer 258. Timer 3101 is started in response to command signal CM, and generates a refresh request signal at predetermined time intervals.

In the structure shown in FIG. 138, RAS
Instead of supplying command signal CM and refresh request signal * BUSY to signal generation circuit 3201, a control signal from refresh control circuit 3204 may be supplied to RAS signal generation circuit 3201. In this case, RA
S signal generation circuit 3201 ignores the external control signal in response to the refresh instruction signal from the refresh control circuit, and generates internal control signal int. * Generate RAS. The refresh control circuit 3204 increments the count value of the refresh address counter 293 by one when one refresh cycle ends.

FIG. 139 shows an example of a specific configuration of input / output switching circuit 3202 and command register 270a shown in FIG. 137. Referring to FIG. 139, command register 270a includes a command register RR2 formed of a 2-bit data register. The command register RR2 captures and stores the data applied to the data input pin terminals DQ0 and DQ1 when it is selected. As shown in FIG. 52, the command register RR2 sets the control signals Ar0 and Ar1 to "1" and "0" in the command register setting mode (see FIGS. 76, 111 and 134), respectively, and outputs the external control signal. It is selected by setting W # to "H". Here, the configuration of the data input / output pins when the masked write mode is selected and data is input / output via the same pin terminal is shown.

This command register 270a further includes
Transfer gate transistor T for connecting its command register RR2 to data input pins DQ0 and DQ1.
r201 and Tr202.

A register selection circuit 3120 for setting command register RR2 to a selected state and setting a desired command includes a gate circuit G110 receiving register selection signals Ar0 and Ar1, and internal control signals W, E, and CH.
And int. * Includes gate circuit G111 that receives CR. This register selection circuit 3120 corresponds to the command register mode selector 279 shown in FIG.

The gate circuit G110 outputs an "H" signal when the command selection signal Ar0 is "L" and the control signal Ar1 is "H". When the output of gate circuit G110 attains "H", command register RR2 is activated and latches applied data.

The gate circuit G111 has the internal control signal in
t. * CR and internal chip selector signal E are both at "L", and internal control signals W and CH are at "H".
And outputs an "H" signal. Therefore, in the command register mode, when gate circuit G111 is in a selected state and this output signal is at "H", command register RR2 is connected to data input / output terminals DQ0 and DQ1, and latches given data. .

[0587] Without using this command register RR2,
Using a command register (eg, RR1 and RR2) formed of a 1-bit flip-flop, in a command register setting mode, one flip-flop is set in accordance with a combination of signals Ar0 and Ar1, thereby performing auto-refresh / self-refresh. May be used.

[0588] The input / output switching circuit 3102 includes a NOR circuit G100 and an AND circuit G101 for receiving a 2-bit command signal CM from the command register RR2,
A switching transistor Tr200 that receives the output of R circuit G100 at its gate and passes a signal given to data input / output pin 3110, and a refresh request signal from timer 3101 (see FIG. 137) in response to the output of AND circuit G101. * Includes switching transistor Tr201 that transmits BUSY to terminal 3110.

This switching transistor Tr200
Is transmitted to a refresh signal input buffer circuit which latches the signal in response to the internal clock signal K. The output of the timer 3101 is transmitted to the transistor Tr201 after being buffered. The switching transistors Tr200 and Tr201 may be an input buffer and an output buffer, respectively.
When the switching transistor Tr200 is formed of an input buffer, this input buffer is connected to the gate circuit G10.
The configuration is such that not only the output of 0 but also a given signal is taken in response to the rise of the clock signal.

[0590] Input / output switching circuit 310 shown in FIG.
In the configuration of 2, NOR circuit G100 outputs a signal of "H" when both 2-bit data from command register RR2 are at "L". AND circuit G101
When both of the 2-bit command signals CM are “1”, a “H” signal is output. Therefore, when both 2-bit data DQ0 and DQ1 are "0", the refresh mode of the semiconductor memory device is set to the auto-refresh mode, and the 2-bit data DQ0 and DQ1 are set.
Are both "1", the semiconductor memory device is set to the self-refresh mode.

Other logics of gate circuits G100 and G101 shown in input / output switching circuit 3102 may be used, and bit D of command signal CM for designating auto-refresh and self-refresh.
Other combinations of the values of Q0 and DQ1 may be used.

A 1-bit command signal may be used as a signal bit for designating auto-refresh / self-refresh.

FIG. 140 shows FIGS. 137 to 139.
FIG. 5 is a signal waveform diagram showing an operation of the circuit shown in FIG. Hereinafter, FIG.
The operation will be described with reference to FIGS.

First, consider the case where data "0" (00) indicating auto refresh is set in command register RR2 of command register 270a in accordance with the command register setting mode. In this case, the output of the gate circuit G100 shown in FIG. 139 becomes “H”, and the AND circuit G10
1 becomes "L". Thereby, the input / output switching circuit 3
Reference numeral 102 denotes a pin terminal 3110 as a signal input terminal. This pin terminal 3110 allows an externally applied refresh instruction signal REF # to pass therethrough. In this auto refresh mode, the output of the timer 3101 is ignored or the timer 3101 is reset. In this state, generation of a refresh address and internal control signal int. Under the control of refresh detection circuit 3203 and refresh control circuit 3204 in accordance with externally applied refresh instruction signal REF #. * RAS is generated, and the DRAM array is refreshed according to the generated refresh address.

At time Tx, the command register setting mode is performed, and when "1" (11) is set in register RR2 of command register 270a, gate circuit G
The output of 101 becomes "H" and the output of gate circuit G100 becomes "L". Thus, the input terminal 3110 becomes a data output terminal by the function of the input / output switching circuit 3102. Refresh request signal * BUSY from timer 3101 is transmitted to pin terminal 3110, and is used as a signal indicating that self refresh is being performed inside the semiconductor memory device.

The timer 3101 is started in response to the setting of the self-refresh mode in the command register 270a, and supplies a refresh request to the refresh control circuit 3204. Refresh control circuit 3204
Responds to the refresh request from the timer 3101 to set the multiplexer 258 to the output selection state of the refresh address counter 293 and to set the internal control signal int. * Control the occurrence of RAS. When a refresh request is given from refresh control circuit 3204, RAS signal generation circuit 3201 generates internal control signal int. * Generate RAS.

[0591] This internal control signal int. * Row selection and sense operation in DRAM are performed according to RAS,
A refresh operation is performed on the row specified by the refresh address from refresh address counter 293. When a predetermined period elapses, the timer 3101
Rises to "H". As a result, the refresh period is completed, the refresh control circuit 3204 increments the address count value of the refresh address counter 293 by one, and the internal control signal int. * Stop RAS generation.

The “L” period of the output of timer 3101 is set in advance. The output of this timer 3101 is "L"
Is set to a period substantially equal to a memory cycle in a normal DRAM. After the elapse of this period, the timer 3101 performs the time counting operation again, and after the elapse of a predetermined time, generates a refresh request again and gives it to the refresh control circuit 3204. In accordance with the refresh request, the DRAM array is refreshed again under the control of the refresh control circuit 3204 and the RAS signal generation circuit 3201.

[0599] The timer 3101 count operation is continued during the period when the command signal CM specifies self-refresh. The refresh interval of the timer 3101 may be fixedly set in advance, or may be programmed according to the data retention guarantee time of the semiconductor chip.

As described above, according to the command signal CM set in the command register, the semiconductor memory device can be set to auto refresh or self refresh. When the refresh instruction signal REF # is at "H", the DRAM can be accessed. When the refresh instruction signal REF # is “L”, the timer 3101 is not operating. The refresh operation is externally controlled. During this refresh period, the DRAM array cannot be accessed from outside.

On the other hand, at the time of self-refresh,
During the refresh operation in the DRAM array, refresh execution instruction signal BUSY # is output from pin terminal 3110. Therefore, when the external device monitors the refresh execution instruction signal BUSY #, the DRA
The external device can know whether or not access to M can be performed, and the self-refresh can be performed even in the normal mode.

The transition from the self-refresh to the auto-refresh is performed at the rising edge of the clock signal K by executing the command register setting mode.
The register RR2 at 70a may be set to be in the auto refresh mode (see time Ty in FIG. 140). As a result, the timer is prohibited from timing, and the CDR
The auto refresh mode setting for the AM is executed.

With the above structure, a CDRAM capable of executing auto-refresh and self-refresh on the same chip can be obtained. Further, the execution timing of the self-refresh can be known even in the normal operation mode, and the self-refresh can be used also in the normal operation cycle.

"Modification of Self-Refresh / Auto-Refresh" FIG. 141 shows a modification of the refresh circuit shown in FIG. In the configuration shown in FIG. 141, BBU generating circuit 3210 is provided, and BBU
Command signal CM from command register 270a is transmitted to generating circuit 3210.

A BBU generating circuit 3210 has a circuit configuration for executing a battery backup mode.
For the BU mode, for example, “Battery backup (BBU) mode for reducing data retention current in standard DRAM”, Dosaka et al.
No. 103, ED90-78, pp. 35-40, and "38 ns 4 Mbit DR with BBU Mode"
AM ", IEEE, International Solid State Circuits Conference, 1990, Digest of Technical Papers, pages 230 and 23.
It is disclosed by Konishi et al. On page 1 and page 303. The BBU mode has a configuration in which the number of arrays operating in the normal mode in the battery backup mode in the standard DRAM is further reduced to 1/4, thereby performing refresh with a low current and retaining data.

In the BBU mode, a self refresh is performed. Hereinafter, the BBU mode will be briefly described.

FIG. 142 is a view for explaining the BBU mode. The DRAM array DRMA includes 32 small blocks MBA1 to MBA32. DRAM array D
RAMA is further divided into memory block groups MAB1 to MAB4 for every eight small blocks. One small block is driven in one group. This configuration corresponds to the configuration shown in FIG. Array drivers MAD1 to MAD4 for driving a DRAM array are provided for each of the memory array block groups MAB1 to MAB4. A BBU control circuit BUC is provided to drive the array drivers MAD1 to MAD4.

The BBU control circuit BUC transmits a refresh request signal to one of the array drivers MAD1 to MAD4 when receiving the control signal REFS. This refresh request signal REFR is sequentially transmitted from the BBU control circuit BUC to the array drivers MAD1 to MAD4. The array drivers MAD1 to MAD4 drive one block in the corresponding memory array groups MAB1 to MAB4, respectively. Which block to select is selected according to a row address signal (for example, RA8) provided from a path (not shown). In the normal mode, each of the memory array groups MAB1 to MAB
One block from four is selected. That is, four blocks (memory blocks MBA8, MBA
A16, MBA24 and MBA32) are driven.

In the BBU mode, only one memory array group is driven, and only one memory block is driven (in the example shown, memory array block MBA32). Therefore, in this case, the number of driven blocks is reduced to 1/4 of that in the normal mode, so that the current consumption at the time of refresh is significantly reduced. This BBU generation circuit (BBU control BU)
C) is used in the configuration shown in FIG.

FIG. 143 shows a BBU control circuit BUC.
FIG. 3 is a diagram showing an example of a specific configuration of FIG. In FIG. 143, a timer 3101 includes a ring oscillator 3121 oscillating at a predetermined interval, and a binary counter 3122 that counts a pulse signal from the ring oscillator 3121 and generates a signal every predetermined period. This binary counter 3122
Is the maximum count-up value (for example, 16 ns; specification value of refresh cycle) and refresh timing in self-refresh (for example, every 64 μs)
Generate a decision signal.

[0611] The BBU control circuit BUC further comprises:
Activated in response to command signal CM, binary counter 3
Activated in response to count-up signal CUP1 from battery 122, battery backup mode instructing signal BBU
, A BBU signal generation circuit 3210 for generating a signal, a signal BBU from the BBU signal generation circuit 3210 and a binary counter 31
22 that generates a refresh request signal REFS in response to the refresh cycle definition signal CUP2 from
FS generation circuit 3123 is included.

The BBU signal generation circuit 3210 is activated in response to the self-refresh instruction of the command signal CM, and is activated by the count-up signal C from the binary counter 3122.
Wait for UP1 to be given. BBU signal generation circuit 32
Reference numeral 10 denotes an inactive state when the command signal CM specifies the normal mode or the auto-refresh mode, and resets the refresh timer 3101.

[0613] Upon receiving count-up signal CUP1, BBU signal generation circuit 3210 generates signal BBU.
This signal BBU indicates that the CDRAM has been switched to the battery backup mode. REFS generation circuit 31
23 is activated in response to the signal BBU, and is a refresh cycle defining signal CUP from the binary counter 3122.
2 every time the refresh request signal REFS is supplied.
Occurs.

FIG. 144 shows the internal control signal int. * RA
FIG. 3 is a diagram illustrating a circuit configuration for generating S. This figure 1
In the configuration shown in FIG. 44, RAS signal generation circuit 3201 and refresh control circuit 3204 shown in FIG.
Among the internal control signals int. * Only the circuit configuration that generates RAS is shown. The RAS signal generation circuit 3201
Gate circuit receiving signal * RAS and signal BBU (NO
R circuit) G301, an inverter circuit G302 receiving the gate circuit G301, and a gate circuit G303 receiving the output of the inverter circuit G302 and the refresh request signal RASS from the refresh control circuit 3204.
In the gate circuit G301, both input signals are “L”.
In this case, the signal of the "H" signal is generated. Gate circuit G
303 generates a signal of "H" when one of its inputs is at "L".

The signal * RAS is a CD to which the present invention is applied.
In the RAM, an array access instruction signal determined by signals E and CH taken into the device at the rising edge of clock signal K is shown. This may be a configuration generated from the row address strobe signal generation circuit shown in FIG.

The refresh control circuit 3204 generates the internal control signal int. * Delay circuit 3231 for delaying RAS for a predetermined time, refresh request signal REFS from REFS generation circuit 3123 and output signal of delay circuit 3231 *
A RASS generation circuit 3232 for generating refresh instruction signal RASS in response to SC is included. Delay circuit 3231
Is a signal indicating the completion of sensing generated when the sensing operation in the DRAM is completed and the data of the memory cell to be refreshed is securely latched by the sense amplifier. That is, this RA
The SS generation circuit 3232 supplies the refresh request signal REFS
In response to the internal control signal int. * RAS is activated, and in response to generation of sense completion signal * SC, internal control signal int. * Bring RAS to inactive state.

The operation of the circuits shown in FIGS. 143 and 144 will now be described with reference to the operation waveform diagram of FIG. 145.

The signal * RASS replaces the signal * RAS in the BBU mode. When refresh request signal REFS is generated from REFS generation circuit 3123, signal * RASS from RASS generation circuit 3232 rises to "L" to be activated. In response, the internal control signal output from gate circuit G303 becomes "H".
Internal control signal int. * RAS goes active low.

[0628] This internal control signal int. The row selection operation and the sense operation in the DRAM are performed according to * RAS. When the sensing operation is completed, sense completion signal * SC from delay circuit 3231 falls to active state "L".

RASS generating circuit 3232 responds to the fall of sense completion signal * SC to output signal * RA
SS is raised to “H”. In response, internal control signal int. * RAS becomes "H" active state and DRAM
Is completed.

That is, in this BBU mode,
Refreshing is performed in a self-time manner, all triggered by the rise of the refresh request signal REFS from the REFS generating circuit 3123 (transition to an active state). By applying signal BBU to gate circuit G301, even if an array access is requested in the BBU mode and * RAS is activated to "L", the output of gate circuit G301 remains at "L" and BBU This prevents entry into the array active cycle in the mode.

Here, the activation level of the BBU signal is not shown, but signal BBU attains "H" when the BBU mode is designated.

FIG. 146 shows an example of a specific configuration of RASS generating circuit 3232 shown in FIG. 144. The RASS generating circuit 3232 is constituted by a set / reset type flip-flop. This flip-flop receives a refresh request signal REFS at its set input and a sense completion signal * SC at its reset input / R. A signal * RASS is generated from the / Q output. This flip-flop FFR is set in response to the rise of the signal applied to set input S, the / Q output becomes "0", and enters the reset state in response to the fall of the signal applied to reset input / R. / Q output becomes “H”.

"Application Example to Another Configuration" The above configuration shows an application to a CDRAM. However, this configuration can be applied to a dynamic semiconductor memory device including only a normal DRAM array. An ordinary dynamic semiconductor memory device receives a row address strobe signal * RAS, a column address strobe signal * CAS and a write enable signal WE as external control signals. Thus, the external control signals * RAS, * CAS,
* Switching between auto-refresh and self-refresh can also be performed in a dynamic semiconductor memory device receiving WE.

FIG. 147 is a diagram showing circuit portions related to a refresh mode setting circuit in a normal dynamic semiconductor memory device. In FIG. 147, a refresh-related circuit receives and latches an externally applied refresh mode instruction signal * CR, a command register 3502, and a command signal (refresh mode setting signal) C set in command register 3502.
An input / output switching circuit 3501 for setting the terminal 3510 to either an input terminal or an output terminal in response to M, an external control signal * RAS, * CAS, * WE and a terminal 3510
Receives a refresh instruction signal * REF and a command signal C
M includes a clock generator 3503 that receives M, generates internal control signals of the semiconductor memory device, and controls a refresh operation.

Further, the dynamic semiconductor memory device is
A refresh address counter 3504 for generating a refresh address in response to a control signal from a clock generator 3503;
0 through A9 and the output of the refresh address counter 3504 to pass the internal row address signal RA0.
To row address buffer 3506 that generates.
A column address buffer 3507 receives externally applied address signals A0 to A9 and generates internal column address signals CA0 to CA9. Row address buffer 35
The timing for taking in the respective address signals of 06 and column address buffer 3507 is determined by an internal control signal from clock generator 3503. External row address signal A0 of row address buffer 3506
The timing for taking in .about.A9 is determined by external control signal * RAS, and the timing for taking in external address signals A0 to A9 in column address buffer 3507 is given by external control signal * CAS.

The row address buffer 3506 includes not only a simple buffer circuit but also a multiplex circuit inside. The multiplex circuit includes an external row address A0 to A9 and a refresh address counter 3
A configuration may be adopted in which the output of the 504 is received and one of the outputs is selectively transmitted to the buffer circuit. The multiplex circuit may be configured to receive external row addresses A0 to A9 after being converted to internal row addresses.

FIG. 148 shows an example of a specific configuration of clock generator 3503 shown in FIG.
In FIG. 148, the clock generator 3503
A refresh detection circuit 3510 for receiving a refresh instruction signal * REF to determine whether or not a refresh instruction has been given, and an external control signal * RAS for receiving an internal control signal int. RAS buffer 3511 that generates RAS
And the external control signal * CAS, and the internal control signal in
t. A CAS buffer 3512 for generating a CAS is included.
RAS buffer 3511 and CAS buffer 3512
Are inactive when the refresh detection circuit 3510 gives a refresh instruction. When the timer 3505 outputs a refresh request, the buffers 3511 and 3512
The signal input is prohibited under the control of 513 (this path is not shown).

The clock generator 3503 further comprises
A pulse generation circuit 3514 for generating an internal pulse signal having a predetermined time width in response to a refresh instruction from refresh detection circuit 3510 and refresh control circuit 3513, and an internal control signal RAS from pulse generation circuit 3514 and RAS buffer 3511. Receiving gate circuit 3515. The internal control signal int. An RAS is generated. The active period of the pulse generated by the pulse generation circuit 3514 is a period required until the refresh in the DRAM is completed. The refresh control circuit 3513 includes a timer 350
5 outputs a switching signal MUX for causing a multiplexer (included in row address buffer 3506) to select a refresh address counter output, and also generates a pulse generation circuit 351.
4 is started to generate a pulse signal at a predetermined timing.

The timer 3505 is started in response to the command signal CM from the command register 3502 as in the previous embodiment, and generates a pulse signal (refresh request signal) at a predetermined interval.

When the command signal CM indicates auto-refresh, the refresh control circuit 3513 ignores the output of the timer 3505 and performs control necessary for refreshing in response to the output of the refresh detection circuit 3510. When the command signal CM indicates self-refresh, the refresh control circuit 3513 performs a control operation required for each refresh in accordance with a refresh request from the timer 3505.

Returning to FIG. 147, the command register 35
02 and the input / output switching circuit 3501 are shown in FIG.
The circuit configuration is the same as that shown with reference to 39. In this case, the command register 3502 does not need to latch the refresh mode instruction signal * CR in synchronization with the clock signal, but latches a control signal given at an arbitrary timing. The externally supplied refresh mode setting signal * CR may be a 1-bit signal or a 2-bit signal.

According to the above configuration, both the auto refresh and the self refresh can be performed in a normal DRAM. Also, an input / output switching circuit 3501
, One pin terminal 3510 is switched to an input terminal or an output terminal. When pin terminal 3510 is set as an output terminal, it indicates that self refresh is being performed in this semiconductor memory device.
In the self-refresh mode, the timer 3
The refresh request signal from 505 is output as a refresh execution instruction signal * BUSY. Therefore, by looking at this signal * BUSY, the external device can know the refresh timing.

According to the configuration shown in FIG. 147, ordinary DRA
Also in M, a dynamic semiconductor memory device capable of executing self-refresh in the normal mode can be obtained.

In the structure of the dynamic semiconductor memory device shown in FIG. 147, a structure may be employed in which a BBU generating circuit is further connected as shown in FIG.

In the structure shown in FIGS. 137, 141 and 147, the self refresh mode and the auto refresh mode can be selectively executed. In this case, if the level of the output of command register 3502 is fixed by, for example, wire bonding, pin terminal 3510 is fixed to the input terminal or the output terminal. A semiconductor memory device (dynamic semiconductor memory device or CDRAM) that executes only self-refresh can be obtained. That is, it is possible to obtain a semiconductor memory device that can support both the auto refresh mode and the self refresh mode by designing one semiconductor chip.

In particular, according to the configuration in which the auto-refresh mode and the self-refresh are realized on the same semiconductor chip, the data of the chip is held by using the auto-refresh mode in the refresh interval program required when setting the self-refresh. The guaranteed time can be measured, and a reliable self-refresh cycle period can be set.

In the case of fixing to auto refresh or self refresh, it is not necessary to particularly provide an input / output switching circuit, and pin terminals (for example, FIG.
A configuration in which the terminal 3510 in 47 is set as an input terminal or an output terminal may be used. This configuration is shown in FIG.
9 and FIG. In the configuration of FIG. 149, refresh mode designating command CM for setting the refresh mode setting circuit 3550 is set to one of the power supply potential Vcc or the ground potential V _SS by Wiring. In this configuration, input / output switching circuit 3102 is fixedly set to either an input circuit or an output circuit.

In the configuration shown in FIG. 150, refresh mode setting circuit 3550 is set to either the auto refresh mode or the self refresh mode by wiring, similarly to the configuration shown in FIG. 149. The input / output switching circuit 3551 is set to one of a signal input circuit and a signal output circuit by wiring as indicated by a chain line.

In the self-refresh mode, signal BUSY # is output to the outside of the device even in the above-described configuration, so that the self-refresh can be performed even in the normal mode.

[Another embodiment of address distribution method] As described above, in the CDRAM, the DRAM address Aa
, A row address and a column address are given in a time-division manner. However, as described above, even when the period of the external clock K is lengthened (including intermittent occurrence), the CDRA
It is desirable that M be operated as fast as possible. Less than,
A configuration for operating the CDRAM at high speed will be described. The configuration described below constitutes another embodiment of the address distribution system shown in FIGS. 46 and 47.

FIG. 151 is a diagram showing still another embodiment of the address distribution system. In the configuration shown in FIG. 151, internal address in from address buffer 4001
t. Ac is also supplied to the DRAM column decoder 103. That is, the DRAM column address and the SRAM address share a part thereof.

The address buffer 4001 may be the address buffer 255 shown in FIG.
The address generation circuit 360 shown in FIG. FIG.
In the configuration shown in FIG. 1, a DRAM address can be provided in a non-multiplexed manner without increasing the number of external pin terminals by externally providing a row address as an address Aa and a column address as an address Ac. Therefore, the fetch timing of the column address of the DRAM can be made faster than in the multiplex system, and the DRAM can be operated at high speed. Hereinafter, the configuration in which the SRAM address is used as the DRAM address will be described in detail.

FIG. 152 shows the SRAM address and the DRAM.
It is a figure which shows the structure which shares an address more concretely. In FIG. 152, the address buffer 401
A buffer circuit 4010 for receiving external column address signals Ac0 to Ac3 for RAM and generating an internal address signal, a buffer circuit 4011 for receiving external address signals Ac4 to Ac11 and generating an internal address signal, and an external address signal Aa0 to Aa9. And a buffer circuit 4012 for generating an internal row address signal for the DRAM. Each of buffer circuits 4010, 4011 and 4012 has an internal clock signal int-K or a strobe signal / RAS, /
The external address is latched in response to CAL to generate an internal address signal.

[0645] The internal address signal from buffer circuit 4010 is applied to SRAM column decoder 203. The internal address signal from buffer circuit 4011 is applied to determination circuit 4020. The internal address signal from buffer circuit 4012 is applied to DRAM row decoder 102.

[0646] Judgment circuit 4020 applies the address signal from buffer circuit 4011 to SRA according to chip select signal E and cache hit instruction signal CH (both signals may be internal signals or external signals).
M row decoder 202 and DRAM column decoder 1
03 is determined.

[0647] Judgment circuit 4020 supplies the internal address signal from buffer circuit 4011 to SRAM row decoder 202 when accessing the SRAM array. DRA
At the time of accessing the M array, determination circuit 4020 applies an address signal from buffer circuit 4011 to DRAM column decoder 103.

In the structure shown in FIG. 152, SR
By the output of the AM column decoder 203, four more bits (in the case of a 4MC DRAM) are selected from the column selected by the DRAM column decoder 103 in the DRAM array.

In the structure shown in FIG. 152, address signals Aa0 to Aa9 are used as array row address signals for specifying a row of the DRAM array. The address signals Ac0 to Ac3 are used as a cache column address signal for designating a column of the SRAM array and an array column address signal at the time of direct access to the DRAM array. Address signals Ac4 to Ac9 are SRA
It is used as a cache row address signal for specifying a row of the M array, and is used as an array column address signal for specifying a column of the DRAM array.

As in the structure shown in FIG. 152, address signals Ac0 to Ac11 and Aa0 to Aa9 can be applied independently, and buffer circuit 401
0, 4011 and 4012 simultaneously take in a given address signal and generate an internal address signal, so that a row address signal and a column address signal for a DRAM array can be simultaneously taken in.
The access time in the AM array can be significantly reduced.

FIG. 153 shows the judgment circuit 402 shown in FIG.
FIG. 3 is a diagram showing an example of a specific configuration of 0. Referring to FIG. 153, determination circuit 4020 determines whether internal chip select signal E
And internal cache hit indication signal CH (this is shown in FIG.
, And switching transistors Tr400 and Tr401 selectively turned on in response to the output of gate circuit G400. The switching transistor Tr400 includes a buffer circuit 4011
(See FIG. 152) is transmitted to the SRAM row decoder 202. Switching transistor T
r401 converts the internal address signals Ac4 to Ac11 to DRA.
The signal is transmitted to the M column decoder 103.

The gate circuit G400 generates an "H" signal when both inputs thereof become "L". Signal E
Both CH and CH become "L" at the time of a cache hit and at the time of accessing the SRAM array. In this case, switching transistor Tr400 is turned on, and internal address signals Ac4 to Ac11 are transmitted to SRAM row decoder 202 as SRAM row address signals.

When accessing the DRAM array, the signal C
H # becomes “H”, and the output of the gate G400 becomes “L”.
Becomes The switching transistor Tr401 is turned on, and the internal address signals Ac4 to Ac11 change to DRA.
The signal is transmitted to the M column decoder 103.

In the structure of the decision circuit shown in FIG. 153, address signals cannot be simultaneously transmitted to DRAM and SRAM in the block transfer mode and the copy back mode. In this case, when the block transfer mode and the copy back mode are designated, switching transistors Tr400 and Tr40
A configuration in which both of them are turned on may be further added.

In the structure shown in FIGS. 152 and 153, the SRAM address signal lines Ac4 to Ac11
It branches into an AM address signal line and an SRAM address signal line. In this case, the load capacitance associated with the SRAM address signal line connected to the SRAM row decoder increases. If the load capacitance associated with the SRAM address signal line increases, a signal delay is caused, and an access time at the time of a cache hit is increased. For this reason, SRA
It is desirable to minimize the load on the M address line. FIG. 154 shows a configuration for preventing an increase in load capacitance associated with the SRAM address signal line.

In FIG. 154, SRAM column decoder 203 includes a predecoder 4051 for predecoding the internal address signal from address buffer 4010,
An SRAM row decoder 4052 for further decoding the predecode signal from the predecoder 4051 and selecting a word line in the SRAM array is included. The above-described method of pre-decoding an address is performed in a general semiconductor memory device from the viewpoint of shortening the length of the address signal wiring, reducing the area occupied by the address signal wiring, and reducing the scale of the decoder circuit.

In the configuration shown in FIG. 154,
The predecoded signal from predecoder 4051 is transmitted to the DRAM column decoder as shown in FIG. 154 (I). In this case (I), the SRA from the address buffer 4010
The length of the M address signal wiring can be shortened and the address signal delay is reduced.

[0658] An SRAM word line selection signal from SRAM row decoder 4052 may be applied to the DRAM column decoder (see case (II) in FIG. 154). When an SRAM word line selection signal from SRAM row decoder 4052 is applied to a DRAM column decoder, D
The RAM column decoder has a normal buffer configuration. In the case (II), since a word line driving circuit is provided for each SRAM word line for driving the SRAM word line, no signal transmission delay occurs in the SRAM word line.

In the case of the structure shown in FIG. 154, the effect of the delay caused by the determination operation in determination circuit 4020 on the access time to the SRAM array is reduced. That is,
The determination circuit 4020 requires a certain time to determine whether to access the DRAM array or the SRAM array. In order to perform the cache hit operation at high speed, it is desirable that the time required for the determination operation in the determination circuit 4020 has as little influence as possible on the access to the SRAM array.

[0660] On the other hand, the DRAM array does not operate as fast as the SRAM. Therefore, the judgment circuit 40
The decision time at 20 has little adverse effect on the column selection operation in the DRAM array. Therefore, as shown in FIG. 154, case (I) or (I
As in the case of I), the configuration is such that the SRAM address signal line and the DRAM column address signal line are branched after the predecoder circuit 4051, so that the SRA
An adverse effect on the access time to the M array can be reliably eliminated.

In the structure shown in FIG. 154, a decision circuit shown in FIG. 153 may be provided at a branch point. Instead of this configuration, the signal lines after the predecoder 4051 may be branched directly into the SRAM signal line and the DRAM signal line. In this case, the address signal (predecode signal or SRAM) is directly sent to the DRAM column decoder.
Word line selection signal) is transmitted. The operations of the DRAM row decoder, DRAM column decoder, and SRAM column decoder are controlled by a determination circuit 4030 shown in FIG. The SRAM column decoder 203 is an SRAM
The operation is performed both when accessing the array and when accessing the DRAM array. Also SRAM
In the row decoder 203, the predecoder 4051
When the address signal line is branched in the output stage, the predecoder operates and the operation of the SRAM row decoder 4052 is controlled by the determination circuit 4030. When a branch of the signal line is provided at the output stage of the SRAM row decoder 4052, the determination circuit 4030
, The SRAM row decoder 4052 operates until the determination is completed.

Even if the SRAM column decoder is used for both column selection of the DRAM array and column selection of the SRAM array, only the bit line pair of one array is connected to the internal data line, No collision occurs (see, for example, FIGS. 12, 30 and 41). FIG. 155 shows a configuration in which the drive of the SRAM array and the DRAM array is controlled by this determination circuit.

In FIG. 155, the judgment circuit 4030
It receives internal control signals W, E, CH, CI and CR, and controls the operations of DRAM array drive circuit 260 and SRAM array drive circuit 264 according to the combination of these control signals. Here, the reason why the command register set signal CR is supplied to the determination circuit 4030 will be described later.
This is because the command register setting signal CR (CC2) is used when the high-speed copy-back operation mode is set.
According to the structure shown in FIG. 155, row and column selection operations in the DRAM array and the SRAM array can be performed in parallel, and addresses are taken in parallel in the block transfer mode, the copy back mode, and the like. And row and column selection operations in a DRAM array.

Next, the operation in this address sharing system will be described. FIG. 156 is a timing chart showing an operation at the time of a cache miss. At the time of a cache miss, external control signal E # is set to "L" at the rising edge of clock K, and cache hit instruction signal CH
# Is set to "H". As a result, a cache miss is set. Address signals Aa and Ac externally applied at the rising edge of clock signal K are taken into the device as a row address signal (R) and a column address signal (C) of the DRAM, respectively. As a result, an initiate cycle TMMI is executed. In this initial cycle TMMI, an array active cycle TMMA is executed, and DR is applied according to the applied row address signal (R) and column address signal (C).
A data selection operation in the AM array is performed. An operation such as block transfer or high-speed copy back may be performed in array active cycle TMMA. By setting chip select signal E # to "L" at the rising edge of clock signal K in the last cycle of array active cycle TMMA, data Q corresponding to applied address signals R and C is output (data In case of read operation setting).

In the case of data writing, chip select signal E # and write enable signal W # (not shown) are both set to "L" in this initiate cycle TMMI.
As a result, the write data is written to the SRAM array and also written to the DRAM array.

When the array active cycle TMMA is completed, a precharge cycle TMMP is executed, and DR
The AM array is set to a precharge state. In this precharge cycle TMMP, the SRAM array can be accessed, internal address signal Ac is taken in at the rise of clock signal K as an SRAM address signal, and access to the memory cells in the corresponding SRAM array is executed.

Next, an array write cycle TMA is executed, and data transfer from the SRAM array to the DRAM array (copy back; transfer of latch data to the DRAM array) is executed. This array write cycle TMA includes an initiator cycle TMI and an array active cycle TMAA. In array active initiator cycle TMAI, chip select signal E # is set to "L" at the rising edge of clock signal K, and externally applied addresses Aa and Ac are applied to row address signal (R) and column address signal (C), respectively. Captured as Subsequently, in the array write cycle TMA, the data is transferred to the corresponding data DRAM array of the SRAM array latched by the latch circuit. The data transfer from the latch to the DRAM array is executed in array active cycle TMAA.

In the array write cycle TMA, data transfer from the latch circuit (see FIGS. 30 and 41) to the DRAM array is performed, so that the SRAM array can be accessed. The access to the SRAM array in this array active cycle TMMA is shown in FIG.
At 56, the address signal Ac is represented by a valid state (V). Subsequent to the cache miss cycle TM, a cache hit cycle TH or a standby cycle TS is executed.

Next, a specific read operation and write operation will be described. FIG. 157 is a timing chart showing an operation at the time of a misread. FIG. 157 shows an example in which the clock cycle is 20 ns. At the time of a misread, only the chip select signal E # is set to "H" at the rising edge of the clock signal K. In this case, C
Address (R) given from a PU (external processing unit)
OW1 and COL1) are taken in as a row address signal and a column address signal of the DRAM array, respectively.
At the time of this misread operation, access to the DRAM array is performed according to row address signals ROW1 and COL1. (Data transfer from the DRAM array to the SRAM array may be performed. In this case, the SRA
The same address is given to the M array and the DRAM array. At the time of a miss operation involving data transfer from the DRAM array to the SRAM array, the configuration of determination circuit 4030 shown in FIG. 155 is used. When the configuration of the determination circuit 4020 shown in FIG.
Address signal Ac may be fetched according to the second rising of clock signal K, and a row selecting operation of the SRAM array may be performed. After a predetermined time has elapsed, the output enable signal G # falls to "L". When output enable signal G # falls to "L", data Q1 corresponding to given addresses ROW1 and COL1 is output.

Subsequently, a precharge cycle of the DRAM array is executed. In this precharge cycle, the SRAM array can be accessed. At the same time as the start of the precharge cycle, a hit read operation is performed. In this hit read operation, the chip select signal E # and the cache hit instruction signal CH # are both set to "L" at the rising edge of the clock signal K. Accordingly, address signal Ac is taken in as a signal for selecting a row and a column of the SRAM array, and corresponding memory cell data Q2 is output during this clock cycle. Subsequently, in FIG. 157, a hit read and a hit read are executed. In each hit read cycle, output data Q3 and Q4 are output according to addresses C3 and C4, respectively.

When the DRAM array precharge cycle is completed, an array write cycle is executed. This array write cycle is performed when the SRA
After latching the corresponding data in the M array, the latched data is transferred to the DRAM array. The array write cycle is set by setting the chip select signal E # to "L", the cache hit instruction signal CH # to "H", and the control signal CC1 # (corresponding to the cache access inhibit signal CI #) at the rising edge of the clock signal K. It is set to “L” and the write enable signal W # is set to “L”.

In the array write cycle, externally applied address signals (miss addresses) Ac and Aa are both taken in as a column address signal and a row address signal for DRAM. In this state, the SRA
You cannot access the M array. In the set cycle of the array write cycle, execution of the hit write cycle is prohibited even if a hit write occurs. Therefore, the cache hit instruction signal CH # is set to "H".

A hit read cycle is executed following the set cycle of the array write cycle. In the hit read cycle, the chip select signal E # and the cache hit instruction signal CH # are set to "L", and the output enable signal G # is set to "L". In this state, access to the SRAM array is executed according to address signal Ac, and corresponding data Q5 is output. In FIG. 157, hit read is performed again in the last cycle of the array write cycle, and cache data Q6 according to address C6 is output.

Here, in the array write setting cycle, the address Aa is changed to the miss address (Miss Ad).
Shown as d) is the DR from the SRAM array.
The address required for transferring data to the AM array is an address from an externally provided tag memory.

FIG. 158 shows an operation timing chart at the time of miswriting. Miswriting is set by setting the chip select signal E # to "L" and the write enable signal W # to "L" at the rising edge of the clock signal K. At this time, external addresses Ac and Aa are taken in respectively as column address COL1 and row address ROW1 of the DRAM array, and externally applied write data D1 is taken in. In this miswrite, access is made to a DRAM and an SRAM array, and data D1 is written to a corresponding memory cell in the SRAM array. This SRAM and DR
For writing data to the AM array, any of the data transfer methods described above may be used.

When the miss write cycle is completed, DRA
The M array enters a precharge cycle. In this precharge cycle, the SRAM can be accessed. For FIG. 158, the operations of hit read, hit read, and hit write are performed.
In accordance with each operation cycle, the address Ac is set to SR
It is taken in as AM array addresses C2, C3 and C4, output data Q2 and Q3 are output, and write data D4 is written.

Subsequently, an array write cycle is executed. This array write cycle is similar to that shown in FIG. In the set cycle of the array write cycle, control signal CC1 # (corresponding to array access instruction signal (cache access inhibition signal) CI #) is set to "L", and access to the SRAM array is inhibited. Therefore, even if a hit read occurs in this array write setting cycle, the hit read is not executed.

Following the setting cycle of the array write cycle, a hit write cycle is executed. To set the hit write cycle, the chip select signal E # is set to "L" at the rising edge of the clock signal K. Since hit / read is instructed, in this state, the write enable signal W # is set to "H" and the output enable signal G # is set to "L". Also in this state, an array write cycle is set, an external address (Miss Add) is simultaneously given as addresses Ac and Aa, and these addresses are respectively set to DR.
AM array column address Col2 and row address R
Captured as ow2.

A hit write cycle is executed following the array write setting cycle, address Ac is taken in as address C5 for SRAM, and data D5 given at that time is written in the corresponding SRAM memory cell. . The hit read cycle is executed in the last cycle of the array write cycle, and the address Ac
The data is taken in as the column address C6 of the array, and the corresponding data Q6 is output.

FIG. 159 and FIG. 1 show the connection between the CDRAM and the memory controller according to the address sharing method.
60.

FIG. 159 shows the connection between the CDRAM and the external control device according to the direct mapping method.
The connection configuration shown in FIG. 159 corresponds to the connection configuration shown in FIG. In the connection form shown in FIG.
The 8-bit address signals A6 to A13 from the PU are SR
AM row decoder 202. Of the 8-bit address signals A6-A13, 6-bit address signals A6-A11 are applied to DRAM column decoder 103. The row decoder 102 of the DRAM 100 receives C
Address signals A12 and A13 from PU and selector 67
Two to eight bit address signals A14 to A21 are provided. In the structure shown in FIG.
Since the row address signal and the column address signal are given in a non-multiplex system, no multiplex circuit is provided outside. Clock select circuit 4400 is supplied with chip select signal E # and cache hit instruction signal CH #, and performs operations according to access to SRAM array and access to DRAM array. The clock control circuit 4400 includes the control clock buffer 250, the SRAM array drive circuit 264, and the DRAM array drive circuit 260 in the configuration shown in FIG.
And a decision circuit 4030 shown in FIG.

In FIG. 159, address signals A6 to A11 are supplied from the output of the SRAM row decoder 202 to the column decoder 103 for the DRAM array. This configuration may be a configuration in which a signal is output from a predecoder portion, as shown in FIG.
Further, the configuration may be such that an SRAM word line selection signal is applied. In FIG. 159, only the SRA
It merely indicates that the row address signal of the M array and a part of the column address signal of the DRAM are shared, and does not accurately reflect the actual connection configuration.

The structure of external control circuit 650 is the same as the structure shown in FIG. Therefore, comparing FIG. 54 with FIG. 159, a multiplex circuit 705 for multiplexing the row address signal and the column address signal of the DRAM can be obtained.
Need not be provided, the system size can be reduced, and DRAM column addresses can be easily taken in.

FIG. 160 is a diagram showing a connection structure of addresses when the CDRAM has a 4-way set associative cache structure. The configuration shown in FIG. 160 corresponds to the address connection configuration shown in FIG. In the configuration shown in FIG. 160, the address signals A6-A11 from the CPU and the way addresses W0 and W1 from the controller 750 correspond to the SRAM column decoder 2
02. Among the address signals applied to the SRAM row decoder 202, the address signals A6-A11
Is applied to DRAM column decoder 103. The other structure is the same as the structure shown in FIG. 55 except that multiplex circuit 700 for multiplexing the row address and the column address of the DRAM array is not provided, and the corresponding portions are the same. Assign a reference number.

Therefore, the configuration of the cache can be easily changed in this configuration and in a configuration in which the address signal is shared between the SRAM and the DRAM.

As described above, by using a part of the SRAM address as the DRAM address, the multiplexing of the DRAM address can be performed without increasing the number of pin terminals. It becomes easy to take in column addresses.

[Other Embodiments of Data Transfer System] CDRA
It is desirable that M can be accessed at high speed even at the time of a cache miss. In the following, a configuration for transferring data at a high speed even at the time of a cache miss will be described.

FIG. 158 shows that data transfer is performed at high speed,
In this configuration, even when a cache miss occurs, data can be read at a high speed, and the data transfer operation such as a high-speed copy-back mode can be further accelerated. FIG. 161 shows a configuration of a portion related to one memory block.

In a DRAM, a data read path and a data write path are provided separately. Therefore, global IO line is a pair of global read lines GOLa and GOL for transmitting data read from the DRAM array.
b and global write line pairs GILa and GILb for transmitting write data to the DRAM array. Global read line pair GOLa and global write line pair GIL
a are arranged in parallel with each other, and the global read line pair GOL
b and the global write line pair GILb are arranged in parallel with each other. This global read line pair GOL (general name of global read line pair) and global write line pair GIL
(Global write line pairs are indicated generically) correspond to global IO line pairs GIL shown in FIG.

[0690] Global read line pair GOLa and GOL
b, local read line pairs LOLa and LOLb are provided. Local write line pairs LILa and LILb are provided corresponding to global write line pairs GILa and GILb.

[0690] A read block select signal φRBA is provided between the global read line pair GOLa and the local read line pair LOLa.
, Read gate ROGa which is turned on in response to is provided. A read gate ROGb which is turned on in response to a read block selection signal φRBA is provided between global read line pair GOLb and local read line pair LOLb.

[0690] A write block selection signal φWBA is provided between global write line pair GILa and local write line pair LILb.
Block select gate WI which is turned on in response to
Ga is provided. A write block selection gate WIGb which is turned on in response to a write block selection signal φWBA is provided between global write line pair GILb and local write line pair LILb.

For each bit line pair DBL, a local transfer gate LTG for transmitting the selected memory cell data to local read line pair LOL and a write gate connecting the selected memory cell to local write line pair LIL. An IG is provided.

[0699] A write column select line WCSL and a read column select line RCSL are provided to set local transfer gate LTG and write gate IG to a selected state (conductive state). Write column select line and read column select line RCSL
Are arranged in parallel in pairs. Write column select line W
A write column select signal generated at the time of data writing is transmitted from CRAM to the CSL.
Read column select signal RCSL generated when reading data from the DRAM array is transmitted to read column select line RCSL. Write column select line WCSL and read column select line RCSL are arranged to select two columns each. This configuration corresponds to column select line CS shown in FIG.
L corresponds to a configuration in which a signal line for selecting a column for writing and a signal line for selecting a column for reading are divided into two.

[0699] Local transfer gate LTG includes transistors LTR3 and LTR4 for differentially amplifying the signal on DRAM bit line pair DBL, and read column select line RCSL.
Switching transistors LTR1 and LTR2 transmitting the signal amplified by transistors LTR3 and LTR4 to local read line pair LOL in response to the signal potential of LTR3. Transistor LTR
One terminal of the 3 and LTR4 is connected to a fixed potential V _SS, for example ground potential. In this configuration, local transfer gate LTG inverts the potential of the DRAM bit line pair and transmits it to local read line pair LOL. The transistors LTR3 and LTR4 are constituted by MOS transistors (insulated gate field effect transistors),
Its gate is connected to DRAM bit line pair DBL.
Therefore, this local transfer gate LTG
The DRAM bit line pair DB is transferred to the local read line pair LOL without adversely affecting the signal potential on the M bit line pair DBL.
The signal potential on L is transmitted at high speed.

[0696] Write gate IG is connected to write column select line WC.
Turns on in response to the signal potential on SL
Switching transistors IGR1 and IGR2 connecting bit line pair DBL to local write line pair LIL are included.

The structure of the other DRAM array is the same as that shown in FIG. Transfer gate BTGA and BT
GB are provided corresponding to two global write line pairs and global read line pairs GIL, respectively. Transfer gate BTG (general term for transfer gates BTGA and BTGB) is connected to global read line pair GOL and global write line pair LIL. The configuration of the transfer gates BTGA and BTGB will be described later in detail. Transfer control signals φTSL, φTLD and φTDS are applied to transfer gates BTGA and BTGB.

Control signal φTDS is supplied from DRAM array to S
This signal is generated when data is transferred to the RAM array. Control signal φTSL is a control signal generated when data is transferred from the SRAM array to the latch. The control signal φTLD outputs the latched data to D
This signal is generated when writing to the RAM array. The configuration of the transfer gates BTGA and BTGB will be described in detail later, but includes latch means for latching data read from the SRAM array. Next, the DRAM array and the SRA using the circuit shown in FIG.
The operation of transferring data to and from the M array will be described.

FIG. 162 is a signal waveform diagram representing a data transfer operation from the DRAM to the SRAM in the array configuration shown in FIG. The signal waveform diagram of the data transfer operation shown in FIG. 162 corresponds to the signal waveform diagram showing the data transfer operation shown in FIG.

First, at time t1, equalize signal φE
Q falls to "L", and the precharge state in the DRAM array is completed. Next, at time t2, DR
The AM word line DWL is selected, and the potential of the selected word line rises.

At time ts1, on the other hand, the row selection operation is performed in the SRAM array, and the selected S
The potential of the RAM word line SWL rises to "H", and the memory cell data connected to the selected word line is
The signal is transmitted onto bit line pair SBL. The signal potential on SRAM bit line pair SBL is transferred to latch means included in the transfer gate in response to transfer instruction signal φTSL, where it is latched.

On the other hand, in the DRAM, at time t2, the signal potential of selected word line DWL rises to "H", and when the signal potential of DRAM bit line pair DBL reaches a sufficient level, sense amplifier is activated at time t3. Signal φSAN rises to “L”, and at time t4, sense amplifier activation signal / φSAP rises to “H”. As a result, the signal potentials of DRAM bit line pair DBL are set to "H" and "L" corresponding to the read data, respectively.

[0706] Local transfer gate LTG directly receives the signal potential of DRAM bit line pair DBL.

[0739] Before the rise of sense amplifier activation signal φSAN at time t3, the signal potential to read column select line RCSL rises to "H". Thereby, DRAM
The small change in the signal potential generated on the bit line pair DBL is amplified at high speed by the local transfer gate LTG and transmitted to the local read line pair LOL.

When the signal potential of DRAM bit line pair DBL is transmitted to local read line pair LOL, read block select signal φRBA rises to "H" at time t7 '. Thereby, local read line pair LOL is connected to global read line pair GOL, and DRAM bit line pair DBL
Is transmitted to transfer gate BTG via global read line pair GOL.

At time t7 ', global read line pair G
Before the change in the signal potential of OL occurs, the transfer control signal φTDS is generated at time t3. The signal potential change generated on global read line pair GOL is transmitted at high speed to the corresponding memory cell of the SRAM array.

Therefore, at the time point t5 when the DRAM sense amplifier DSA completes the operation of amplifying the DRAM bit line pair DBL, the data transfer to the SRAM array has already been completed.

As described above, a local transfer gate is provided, and DRAM bit line pair DBL is directly connected to transfer gate BTG.
The data transfer can be performed without waiting for the completion of the sense amplifier operation of the DRAM sense amplifier DSA.

Signal waveforms and arrows shown by broken lines in FIG. 162 show a comparison with the data transfer operation shown in FIG. As is apparent from the comparison of the signal waveforms, DR
Before the activation of the AM sense amplifier DSA, the transfer gate BTG
Is activated (control signal φTDS is generated), and data can be transferred at high speed.

The SRAM array can be accessed immediately after data transfer from this DRAM array. Therefore, even at the time of a cache miss, it is possible to access the SRAM array at high speed.

Next, the data transfer operation from the SRAM array to the DRAM array will be described with reference to the operation timing chart of FIG.

Data transfer from the SRAM array to the DRAM array is performed via global write line pair GIL. In this case, the global read line pair GOL and the local read line pair LOL are not used.

At time t1, the DRAM array precharge cycle is completed. DRAM at time t2
Word line DWL is selected, and the potential of the selected word line rises to "H". At time t3 and time t4, sense amplifier activation signals φSAN and / φSA
P is activated, and DRAM bit line pair DB
The signal potential on L becomes a value corresponding to the data of the selected memory cell.

At time t5, write column select line WCS
The signal potential of the selected write column select line WCSL selected by L rises to “H”. As a result, the write gate I
G is turned on, and the local write line pair LOL is connected to the selected DRAM bit line pair DBL.

At time t6, write block select signal φ
WBA rises to "H". Thereby, local write line pair LIL and global write line pair GIL are connected,
The signal potential of global write line pair GIL has a value corresponding to the signal potential of local write line pair LIL.

At time t7, transfer control signal φTLD rises to "H", and the data latched at transfer gate BTG is transmitted to DRAM bit line pair DBL via global write line pair GIL and local write line pair LIL. Is done.

FIG. 164 shows D in the transfer gate BTG.
FIG. 2 is a diagram showing a configuration of a portion for performing data transfer from a RAM array to an SRAM array. Referring to FIG. 164, transfer gate BTGR is connected to global read lines GOL and * GO.
Transistors Tr500 and Tr501 for differentially amplifying the signal potential on L, and a transfer control signal φTGS
Switching transistors Tr503 and Tr transmitting signal potentials on global IO lines GOL and * GOL to SRAM bit lines SBL and * SBL in response to
502. Here, reference numerals given to each signal line indicate one signal line, not a signal line pair. Transistor Tr500 has its gate coupled to complementary global read line * GOL. Global read lines GOL and * GOL are coupled to local read lines LOL and * LOL, respectively. In the configuration shown in FIG. 164, the read block select gate is omitted.

[0718] In the local transfer gate LTG, D
When the potential of the RAM bit line DBL is "H", the transistor LTR4 is in a deep ON state, the transistor LTR3 is in a shallower ON state, and a large current flows through the transistor LTR4. The signal potential on DRAM bit line DBL is transmitted to global read line * GOL. DRA
The signal potential of the M bit line * DBL is set to the local read line LOL.
Is transmitted to When the signal potential of global read line * GOL is relatively "L" and the potential of global read line GOL is relatively "H", transistor Tr500 is turned on more deeply than transistor Tr501. A current flows to global read line * GOL via transistor Tr500. The current flowing through transistor Tr500 is discharged through transistors LTR2 and LTR4.

[0719] On the other hand, in the transistor Tr501, the same current as that of the transistor Tr500 flows because a current mirror circuit is formed.
Since TR3 is in a shallow on state or off state, the signal potential of global read line GOL is charged to "H" at high speed. The global read lines GOL and * GOL
Is sufficiently amplified to "H" and "L", transfer control signal .phi.TDS rises to "H", and the signal potentials of global read lines GOL and * GOL change to SRAM bit lines SBL and * SBL. Respectively.

In the structure of the transfer gate BTGR, the transistors Tr500, Tr501, LTR1,
LTR2, LTR3 and LTR4 constitute a current mirror type amplifier circuit, and DRAM bit lines DBL, *
Even if the signal potential transmitted to the DBL is minute, it is amplified at a high speed, and the signal potentials of the global read lines GOL and * GOL become (inverted) values corresponding to the DRAM bit lines * DBL and DBL. With this configuration, the potential of the DRAM bit line is amplified by a current mirror type amplifying circuit that directly receives the DRAM bit lines * DBL and DBL and transmitted to the SRAM bit line pair SBL, * SBL. With this configuration, the SRA can be transferred from the DRAM array at high speed.
Data can be transferred to the M array.

FIG. 165 shows a structure for transferring data from the SRAM array of the transfer gate shown in FIG. 161 to the DRAM. The configuration of data transfer gate BTGW shown in FIG. 165 corresponds to the configuration in which the amplifier circuit portion in the data transfer circuit shown in FIG. 41 is omitted.

Referring to FIG. 165, data transfer gate B
TGW responds to transfer control signal φTSL to invert and transmit data on SRAM bit lines SBL and * SBL, and transmit data on SRAM bit lines SBL and * SBL transmitted from transmission gate 5103 to transmission gate 5103. Latch circuit 5100 for latching, and transmission gates 5102a and 5102b for transmitting data latched by latch circuit 5100 to global write lines GIL and * GIL in response to transfer control signal φTLD, respectively. The latch circuit 5100 is configured by an inverter.

[0733] Transfer gate BTGW further sets internal write data line * DBW to global write line * G in response to array write instruction signal AWDE and DRAM column decoder output (which is also an SRAM column decoder output) SAY.
A gate circuit 5101b connected to IL and a gate circuit 5101a connecting internal write data line DBW to global write line GIL in response to write instruction signal AWDE and column decoder output SAY are included. This gate circuit 51
At the time of direct access to the DRAM array via 01a and 5101b, write data is transmitted to the DRAM array.

[0724] Transfer gate BTGW further responds to write instruction signal SWDE to the SRAM array and the output of the SRAM column decoder (which is also a column select signal of the DRAM array) SAY, and external write data lines DBW, * DB
W includes gate circuits 5104a and 5104b connecting W to SRAM bit lines SBL and * SBL, respectively. The structure of the transfer gate BTGW shown in FIG. 165 is similar to that of the transfer gate shown in FIG.
It has the same configuration as the data transfer portion to the AM array, and detailed description thereof will not be repeated.

FIG. 166 shows a write column select signal line WCS.
FIG. 3 is a diagram showing a circuit configuration for driving L and a read column select signal line RCSL. In FIG. 166, D
Column select line CSL from RAM column decoder 103
Is provided with a signal line driver circuit 5110. Signal line drive circuit 5110 includes a gate circuit 5111 receiving column select signal CSL from DRAM column decoder 103 and internal write enable signal * W, and a column select signal CSL.
And a gate circuit 5112 receiving sense completion signal SC and internal write enable signal W. Gate circuit 5111
Outputs a signal for driving read column select line RCSL. A signal for driving write column select line WCSL is output from gate circuit 5112.

[0726] Internal write enable signals * W and W
Clock K in response to an externally applied control signal W #
May be a signal which is taken in synchronizing with. Sense completion signal SC is a signal indicating completion of the sensing operation of sense amplifier DSA in the DRAM array, and is a signal generated by delaying sense drive signal φSANE or φSAPE by a predetermined time. With this configuration,
At the time of writing data to DRAM, read column select line RCS
When L is selected and data is written from the DRAM array, a configuration for selecting write column selection line WCSL is obtained.

FIG. 167 shows a structure of a circuit for generating block select signals φRBA and φWPA. A circuit for generating read block select signal φRBA includes delay circuit 51 for delaying read column select signal RCSL for a predetermined time.
20, the output of the delay circuit 5120 and the block selection signal φB
A (see FIG. 3). Gate circuit 5121 outputs a read block selection signal φRBA.

A circuit for generating write block select signal φWBA includes a delay circuit 5130 for delaying write column select signal WCSL for a predetermined time, and a gate circuit 5131 receiving the output of delay circuit 5130 and block select signal φBA.
including. Gate block 5131 generates a write block selection signal φWBA. Gate circuits 5121 and 51
31 both generate an "H" signal when both inputs are "H".

In the above-described configuration in which the data write path and the read path in the DRAM array are separated, it is preferable to transfer data from the DRAM array to the SRAM array as soon as possible. Therefore, the block selection signal φ
Since the RBA and the read column select line RCSL can be formed, it is preferable to drive them at an early timing. To achieve this configuration, it is most effective to use the configuration shown in FIGS. 151 and 152 in which the address signals of the DRAM array and the SRAM array are shared. According to this configuration, a row address signal and a column address signal to the DRAM array can be applied in a non-multiplexed manner, and a read column select line RCSL is generated immediately after a word line DWL of the DRAM array is selected. The local transfer gate is rendered conductive, and the DRAM bit line pair is connected to the transfer gate BT via the local read line pair LOL and the global read line pair GOL.
To G.

FIG. 168 shows the configuration of a decoder circuit when the configuration of the address non-multiplex system is applied to the IO separated configuration of this DRAM array. Referring to FIG. 168, SRAM column decoder 5141 receives and decodes externally applied address signals Ac0 to Ac3 to generate a column select signal SAY. The column selection signal SAY is used as a column selection signal for the SRAM array and a column selection signal for the DRAM array.

[0731] The SRAM row decoder 5142 receives an externally applied address signal Ac4 to Ac11,
A signal for driving the AM word line SWL is generated. DRA
The M column selection circuit 5143 is one of address signals Ac6 to Ac1 among address signals Ac4 to Ac11 given from the outside.
1 to generate a signal for driving write column select line WCSL and read column select line RCSL. DRAM row selection circuit 5144 receives address signals Aa0 to Aa9, and generates block selection signal φBA and DRAM word line drive signal DWL. In the configuration shown in FIG. 168, address signals Ac0 to Ac11 and Aa0 to
Aa9 can be applied at the same time, the read column select line RCSL can be driven at a high speed, and data can be more effectively transferred from the DRAM array to the SRAM array at a high speed.

In the structure shown in FIG. 161, a structure in which local read line pair LOL and local write line pair LIL are arranged at both ends of bit line pair DBL is shown. However, local read line pair LOL and local write line pair LIL may be arranged on one side of bit line pair DBL (for example, on the side close to transfer gate BTG), or at the center of bit line pair DBL. It may be a configuration to be arranged.

With the above configuration, if a high-speed copy-back method is used even in the event of a cache miss, the precharge and copy-back operations of the DRAM array can be executed in the background of a cache hit. By reducing the time, the performance of the CDRAM is greatly improved.

[0734] Therefore, the structure of separating the data read path and the data write path of the DRAM array has the most remarkable effect by combining the structure of giving this address in a non-multiplex system and the high-speed copy-back operation. Is done.

[Other Functions: Burst Mode] The connection to an external processing unit (CPU) with a burst mode function will be described.

The burst mode is a mode in which data blocks are collectively transferred from the CPU as described above. The control of the burst mode function is realized by using a circuit portion of the additional function control circuit 299 shown in FIG.

FIG. 169 shows a circuit portion for realizing the burst mode operation. Referring to FIG.
The burst mode control system transmits an externally applied burst enable signal BE # to the internal clock signal int. BE buffer circuit 6001 for generating fetch internal burst enable signal / BE in response to K, and first internal burst enable signal / B from BE buffer circuit 6001
One-shot pulse generating circuit 6 for generating one-shot pulse signal φBE having a predetermined pulse width in response to E
002 and the internal clock int. In response to the one-shot pulse signal φBE. Gate circuit 60 for gating K
03 is included. Gate circuit 6003 generates internal clock in when one-shot pulse signal φBE is generated.
t. Prohibit the passage of K. One-shot pulse generation circuit 6002 does not respond to signal / BE after the second time.
It is reset when the burst transfer is completed. This is realized by a configuration in which a timer is provided and pulse generation is inhibited during the operation of the timer.

The burst enable control system further includes an internal address signal int. Provided from an address buffer (see FIG. 1). Ac as an initial value and the internal clock signal int. An address counter 6004 for counting K and an address counter 60
04 and the internal address signal int. Multiplexer circuit 600 for selectively passing any of Ac
7 inclusive. The output of the multiplexer circuit 6007 is S
It is transmitted to the RAM row decoder and the column decoder. The address counter 6004 and the multiplexer circuit 6007 are different from an address counter for generating a refresh address used for a refresh operation and a multiplexer circuit for switching between a refresh address and a DRAM address.

[0739] Furthermore, this burst enable control system
A burst data number storage circuit 6006 for storing the number of burst data, and the internal clock signal int. A down counter 6005 for counting down K is included. The down counter 6005 is B
The internal burst enable signal /
When BE is generated, it is activated and performs a count operation. Down counter 6005 switches the connection path of multiplexer circuit 6007 according to the count value.

[0739] The down counter 6005 outputs the internal clock signal int. When internal burst enable signal / BE is inactive at the rising edge of K, it is reset. Internal clock signal int. When the internal burst enable signal / BE is in an active state ("L" level) at the rising edge of K, a count operation is performed. The down counter 6005 controls the connection path of the multiplexer circuit 6007 so as to select the output of the address counter 6004 during the counting operation. The down counter 6005 further includes a burst data number storage circuit 60.
When the number of burst data stored in the address buffer 06 is counted, the reset state is set, and the connection path of the multiplexer circuit 6007 is set to the internal address signal i from the address buffer.
nt. Switch to the path to select Ac. Next, FIG.
The operation shown in FIG. 9 will be described with reference to the operation waveform diagram of FIG.

At the time of normal access to the SRAM array, at the rising edge of external clock signal K, chip select signal E # is set to "L" and burst enable signal BE # is set to "H".

In this state, internal burst enable signal / BE is also at "H", and no pulse signal is generated from one-shot pulse generation circuit 6002. Further, the down counter circuit 6005 also maintains the reset state. In this state, the multiplexer circuit 6007
Is the internal address signal i supplied from the address buffer.
nt. Ac (cache address) is selected and transmitted to the SRAM row decoder and column decoder. Some are D
It may be provided to a RAM column decoder.

[0746] Therefore, the address Ac1 for the SRAM given at the rising edge of the external clock signal K is
, Access to the SRAM array is performed, and data Q1 corresponding to address Ac1 is output.

At the rising edge of external clock signal K, chip select signal E # and cache hit instruction signal CH
When # and burst enable signal BE # are set to "L", the burst mode is executed. In this state, one-shot pulse signal φBE is generated from one-shot pulse generation circuit 6002 in response to the rise of internal burst enable signal / BE. The address counter 6004 outputs the one-shot pulse signal φ.
BE in response to internal address signal int. Ac (Ac2) is set as the count initial value, and the initial value is supplied to the multiplexer circuit 6007. Gate circuit 6003 receives internal clock signal in when one-shot pulse signal φBE is applied.
t. Prohibit transmission of K. Therefore, in this clock cycle, address signal Ac applied at the rising edge of clock signal K is applied from address counter 6004 to multiplexer circuit 6007.

The down counter 6005 is activated in response to the activation state ("L") of the internal burst enable signal / BE, and performs a countdown operation from the value stored in the burst data number storage circuit 6006. At the time of this counting operation, down counter circuit 6005 generates a signal indicating that the burst mode is being performed and supplies the signal to multiplexer circuit 6007. Multiplexer circuit 6007 selects the output of address counter 6004 in response to the burst mode instruction signal from down counter 6005, and supplies the selected output to SRAM row decoder and column decoder. Access to the SRAM array according to this address Ac2 is performed, and corresponding data Q2 is output.

[0746] Thereafter, when the chip select signal E #, the cache hit instruction signal CH # and the burst enable signal BE # are set to "L" at the rising edge of the external clock signal K, the externally applied address signal Ac is ignored, and the address Access to the SRAM array from the counter 6004 is executed. That is, the internal clock signal int. K is applied to address counter 6004 via gate circuit 6003. Address counter 6
004 performs a count operation (count-up or count-down operation) according to the internal clock signal, and supplies the count value to the multiplexer circuit 6007.

[0747] Multiplexer circuit 6007 selects the count value of address counter 6004 according to the control signal from down counter 6005, and applies the selected value to SRAM row decoder and column decoder. Therefore, during burst mode, address counter 6004
, And corresponding data Q3,... Are output every clock cycle.
In the burst mode operation, the burst mode enable signal BE # is set to “H” at the rising edge of the external clock signal K.
To end in the state set to or
005 ends when the countdown operation is completed.

The information on the number of burst data stored in the burst data number storage circuit 6006 may be fixedly programmed in advance and set, or may be stored in a command register or the like in each burst transfer mode. Good.

In the structure shown in FIG. 169, gate circuit 6003 operates according to one-shot pulse signal φBE to generate internal clock signal int. K transmission is prohibited.
In this case, the internal clock signal int. K and one-shot pulse signal φBE are applied, address counter 6004 reads internal address int. Ac may be configured to be set as the count initial value.

FIG. 171 is a diagram showing an example of a specific configuration of the address counter circuit. Referring to FIG. 171, address counter 6004 includes n continuously connected binary counter circuits BCC1 to BCCn. The binary counter circuits BCC1 to BCCn are asynchronous counter circuits, and the internal clock signal int. K is given.
Each of the binary counter circuits performs a binary counting operation, and when the count value reaches “1”, the carry signal CK
0 to CKn-1 are output. This carry output CK0-C
Kn-1 is a binary counter circuit BCC of the next stage, respectively.
2 to BCCn.

[0751] Binary counter circuits BCC1 to BCCn
From the complementary count values A0, * A0 to An,
* An-1 is generated. Address counter 6004 further includes an up / down switching circuit 6010 for determining whether to perform a count-up operation or a count-down operation. This up / down switching circuit 60
10 selectively passes any of the outputs A0 to An from the counter circuits BCC1 to BCCn and the complementary outputs * A0 to * An-1 in response to the up / down setting signal φUD. When the count-up operation is set, the up / down switching circuit 6010 outputs the counter outputs A0 to A
Select n. When the countdown operation is set, the up / down switching circuit 6010 outputs the complementary output * A0
Select ~ * An-1.

The up / down setting signal φUD may be a control signal set in a command register, or a control signal for fixedly setting one of the count operations by wiring or the like. Is also good.

The configuration of the counter circuit is not limited to the configuration shown in FIG. 171 and any configuration may be used as long as it has a function of setting an initial value.

FIG. 172 shows an example of a specific configuration of burst data number storage circuit 6006 shown in FIG. In the configuration shown in FIG. 172, a command register is used as burst data number storage circuit 6006. Burst data number storage circuit 6006 is a switching transistor Tr60 transmitting data DQ applied to a data input / output pin terminal in response to control signal φCR.
0 and an inverter circuit V6 for latching data given via the switching transistor Tr600.
00, V601 and V602. Inverter circuits V600 and V601 form a latch circuit.

The control signal φCR is a control signal generated in the command register setting mode. A combination of control signals (command register instruction signals Ar, Ar1 and W #) are different.

In the structure shown in FIG. 172, it is shown that the information on the number of burst data is supplied via data input / output terminal DQ. However, this may be a configuration provided from each of the data input terminal D and the data output terminal Q.

The information on the number of burst data may be stored not in the command register but in a dedicated register.

[Application of Burst Mode Function to Another Storage Device] FIG. 173 is a diagram showing a configuration of another semiconductor memory having a burst mode function. In FIG. 173, a semiconductor memory device 6700 includes a memory array 6701 including memory cells arranged in rows and columns, and a memory array 670
A row decoder 6702 for selecting one row and a column decoder 6703 for selecting a column of the memory array 6701 are included.

The semiconductor memory device 6700 further includes an address buffer circuit 6704 that receives an externally applied address ADD and generates an internal address, and sets the output of the address buffer circuit 6704 as a count initial value, and uses the clock signal from the clock control circuit 6706 as a count initial value. Address count circuit 6705 for counting, and clock control circuit 67
And a multiplexer circuit 6707 that passes either the output of the address count circuit 6705 or the output of the address buffer circuit 6704 in response to the control signal BE from 06. Row and column address signals are applied from a multiplexer circuit 6707 to a row decoder 6702 and a column decoder 6703, respectively. This address count circuit 6705 includes an address counter 600 shown in FIG.
4, a down counter 6005, and a configuration of a burst data number storage circuit 6006.

[0760] Clock control circuit 6706 receives an externally applied chip select signal / CS, write enable signal / W, output enable signal / OE and burst mode request signal BE, and generates each internal control signal.

The semiconductor memory device 6700 is assumed to be a static semiconductor memory device. However, a dynamic semiconductor memory device having a high-speed operation mode such as a static column mode or a page mode may be used. The configurations of the address count circuit 6705 and the multiplexer circuit 6707 are the same as those described above, and the configurations are not shown.

As described above, by providing address count circuit 6705 for generating an address in the burst mode, there is no need to connect the burst mode address generation circuit to the outside of the storage device, and the size of the system is reduced. You. In addition, wiring for connecting to the semiconductor memory device by means of an externally provided burst mode address counter is not required, so that it is possible to reduce signal delay on this connection signal line and current consumption due to charging and discharging on this connection wiring. it can. Further, by providing such a burst mode address count circuit inside the semiconductor memory device, the CP with burst mode function is provided.
Connection to U can be easily performed.

In the configuration shown in FIG. 169, the internal address from the address buffer is preset in address counter 6004 as an initial count value. However, the initial count value of the address counter 6004 may be set in the command register.

The semiconductor memory device shown in FIG. 173 may be another semiconductor memory device with a built-in cache.

[0765] "Other functions: sleep mode" An operation mode for reducing current consumption during standby, that is, a sleep mode, will be described below. The function of the sleep mode is realized by the additional function control circuit 299 shown in FIG.

As described above, the CDRAM of the present invention fetches an address signal, an external control signal, and write data in synchronization with external clock signal K. Therefore, even in the standby mode, current is consumed in the buffer receiving the external signal.

FIG. 174 shows the structure of a portion related to one bit of the address buffer (252; FIG. 1: 360 in FIG. 80). Referring to FIG. 174, address buffer 7001 provides internal clock signal int. Clocked inverter 7011 for inverting and passing given data in response to K, and inverters 7013 and 701 for latching the output of clocked inverter 7011
4 inclusive. Clocked inverter 7011 has an internal clock signal int. K to inverter 7
012 and its complementary control input to the internal clock signal int. Receive K.

[0768] Clocked inverter 7014 applies chip select signal E to its positive control input to inverter 701.
5 and receives the chip select signal E at its complementary control input.

[0769] Inverter 7013 and clocked inverter 7014 are connected in an anti-parallel (or cross-connected) configuration to form a latch circuit.

In the structure shown in FIG. 174, internal clock signal int. In response to the rise of K, clocked inverter 7011 attains an output high impedance state. Clocked inverter 7014 functions as an inverter in response to the fall of chip select signal E.
In this state, a latch circuit including inverter 7013 and clocked inverter 7014 is formed in response to the fall of chip select signal E. Inverter 7013 outputs internal address signal int. A is generated.

[0772] In other words, the external address A given at that time at the rising edge of external clock signal K is applied to inverter 7013 and clocked inverter 7.
014 is latched by an internal address int. A is generated.

As shown in FIG. 174, even when chip select signal E is at "H" and the chip is not selected, internal clock signal int. K is given continuously. Therefore, in the standby state, clocked inverter 7011 operates and consumes current.

FIG. 175 shows the structure of the clock buffer circuit included in the control clock buffer. In FIG. 175, a buffer related to chip select signal E # is shown as an example. In FIG. 175, buffer circuit 7021 receives internal clock signal int. P-channel MOS transistor Tr7 receiving K at its gate
00, a p-channel MOS transistor Tr701 receiving an external chip select signal E # at its gate, an n-channel MOS transistor Tr702 receiving its external chip select signal E # at its gate, and an inverted signal / int. An n-channel MOS transistor Tr703 receiving K at its gate is included. Transistor Tr700~Tr703 are connected in series between power supply potential V _CC and the other supply potential (ground potential) V _SS. In the configuration shown in FIG. 175, internal clock signal in
t. At the rising edge of K, buffer circuit 7021 enters an output high-impedance state, and its output portion is set to a floating state of the signal potential applied so far. In the configuration of the buffer circuit, an inverter circuit or a latch circuit may be provided in the next stage.

As shown in FIG. 175, the internal clock signal int. Information is transmitted to the output section in accordance with K, so that current is consumed even during standby. Therefore, a configuration for reducing the current consumption during standby will be described below.

FIG. 176 is a signal waveform diagram representing a sleep mode operation. The sleep mode is set asynchronously with the external clock signal K. The setting of the sleep mode is performed by a command register setting signal CR #. That is, when control signal CR # falls to "L", internal clock signal int. The generation of K is stopped. This allows
For example, the operation of each buffer circuit during standby is stopped. Next, a circuit configuration for realizing the sleep mode will be described.

FIG. 177 is a block diagram functionally showing a circuit configuration for realizing the sleep mode. FIG.
, The sleep mode control system includes a sleep control circuit 7052 that generates a sleep mode control signal SLEEP in response to the control signal CR #, and a sleep control circuit 705.
2 in response to sleep mode control signal SLEEP from internal clock signal int. An internal clock generation circuit 7051 for controlling generation / stop of K is included. This internal clock generation circuit 7051 corresponds to clock buffer 254 shown in FIGS. The sleep control circuit 7052 may be included in the additional function control circuit 299 shown in FIG. 1, or a command register may be used.

FIG. 178 shows an example of a specific configuration of internal clock generation circuit 7051 shown in FIG. 177. Referring to FIG. 178, the internal clock generation circuit 7051
An inverter circuit 7061 receiving a sleep mode control signal SLEEP, a NAND circuit 7062 receiving an external clock signal K and an output of the inverter circuit 7061,
Inverter circuit 706 receiving the output of ND circuit 7062
3 inclusive. The sleep mode control signal SLEEP is set to “H” when the sleep mode is set. The NAND circuit 7062 functions as an inverter when the output of the inverter circuit 7061 is "H". Inverter circuit 706
1 is at "L" level, the NAND circuit 706
2 is fixed at "H" level.

[0778] Therefore, according to the structure shown in FIG. 178, generation and stop of external clock signal K can be controlled by sleep mode control signal SLEEP.

FIG. 179 is a diagram showing an example of a specific configuration of the sleep control circuit 7052 for generating a sleep mode control signal.

Referring to FIG. 179, sleep control circuit 7
A gate circuit 052 receives the external command register setting signal CR # and the output of the inverter circuit 7507.
R circuit) 7501, an inverter circuit 7502 receiving an output of the gate circuit 7501, and an inverter circuit 7502
Circuit 7503 receiving the output of the inverter circuit 7503, the output of the inverter circuit 7503 and the gate circuit (NAND circuit) 75
Gate circuit (NAND circuit) 750 for receiving output 06
3 inclusive.

[0780] Sleep control circuit 7052 further includes an inverter circuit 7504 for receiving external command register setting signal CR #, a gate circuit (NAND circuit) 7505 for receiving the output of inverter circuit 7504 and external control signals Ar0, Ar1, and W #. , A gate circuit 7506 receiving both outputs of NAND circuits 7503 and 7505,
Inverter circuit 75 receiving the output of gate circuit 7506
07 and an inverter circuit 7508 receiving the output of the inverter circuit 7507. Inverter circuit 7508 generates sleep mode control signal SLEEP.

FIG. 179 further shows a CR # buffer 7600. This CR # buffer 7600 is included in a control clock buffer (see reference numeral 250 and the like in FIG. 1). This CR # buffer 7600 receives the internal clock signal int. In response to K, it takes in an external command register setting signal CR # and generates an internal control signal CR.

The operation of sleep control circuit 7052 shown in FIG. 179 will now be described with reference to the operation waveform diagram of FIG.

[0784] The signals CR #, Ar0, and Ar shown in FIG.
1, and W # are all external control signals. Therefore, sleep control circuit 7052 operates asynchronously with clock signal K.

[0785] When external command register setting signal CR # is at "H", the output of gate circuit 7501 is at "L". Therefore, the output of inverter circuit 7503 is also "L".
On the level.

[0786] On the other hand, the output of inverter circuit 7504 is at "L". Therefore, the output of gate circuit 7505 becomes "H" regardless of the state of control signals Ar0, Ar1, and W #. Gate circuit 7506 receives a signal at "H" at both inputs. Therefore, the gate circuit 7506
Becomes “L” and the sleep mode control signal SLE
EP becomes “L”.

In setting the sleep mode, external command register setting signal CR # is set to "L".
The control signals Ar0, Ar1, and W # are followed by "H".
Is set to In this state, gate circuit 750
5 receives an "H" signal at all its inputs, and its output becomes "L". Gate circuit 7506 receives a signal of "L" at one input, so that its output becomes "H" and sleep mode control signal SLEEP rises to "H".

In the state where sleep mode control signal SLEEP has become "H", inverter circuit 750
7 becomes "L". Therefore, the gate circuit 750
1 has both its inputs at "L" and its output at "H". As a result, both inputs of the gate circuit 7503 become "H" level and its output becomes "L".

In this state, gate circuit 7506
Is supplied from gate circuit 7503 to "L" signal, so that external control signals Ar0, Ar1 and W
Regardless of the state of #, the output of the gate circuit 7506 becomes "H".

In this state, when external command register setting signal CR # rises to "H", sleep mode control signal SLEEP rises to "L". Thereby, the sleep mode is released.

[0791] In the sleep mode, the internal clock signal i
nt. When the generation of K is stopped, the internal clock signal i
nt. External refresh instruction signal REF # cannot be taken in at the rising edge of K. For this reason,
Auto refresh cannot be performed. Therefore, during the sleep mode, it is necessary to execute a self-refresh instead of the auto-refresh. FIG. 181 shows a circuit configuration for executing the self-refresh during the sleep mode.

Referring to FIG. 181, a self-refresh switching circuit 7401 is provided for switching the auto / refresh mode according to the execution of the sleep mode. Self-refresh switching circuit 7401 provides internal clock signal int. K is monitored and the internal clock in
t. When the generation of K is stopped, a self-refresh switching signal Self is generated.

[0793] Refresh timer 7402 is started in response to self-refresh switching signal Self, and
A refresh request signal / REFREQ is generated at a predetermined interval and applied to clock generator 7403. Clock generator 7403 receives external clock signal K, external refresh instruction signal REF # and refresh request signal / REFREQ from refresh timer 7402, determines whether or not to execute refresh, and generates various control signals required for executing refresh. I do. As the configuration of clock generator 7403, the configuration shown in FIG. 138 may be used. Clock generator 740
3 performs the same function as that shown in FIG.
However, the function of input / output switching is not shown here.

[0793] Self-refresh switching circuit 7401 provides internal clock signal int. K in response to the rise of internal clock signal int. When K is not applied during a predetermined period (for example, one clock cycle), self-refresh switching signal Self is generated. Self-refresh switching circuit 7401 provides internal clock signal int. Reset is performed in response to the rise of K, and sets self-refresh switching signal Self to an auto-refresh instructing state. Refresh timer 74
02 is the same as that shown in FIG. 137, and generates a refresh request signal / REFREQ at predetermined intervals in response to the self-refresh switching signal Self.

[0795] Clock generator 7403 takes in external refresh instructing signal REF # at the rising edge of external clock signal K, and supplies this refresh instructing signal REF.
When either # or the refresh request signal / REFREQ is in the active state, the operation necessary for refresh is executed. Internal control signals / RAS and / CAS generated from clock generator 7403 are connected to DRAM
This is a control signal for controlling a decoding operation and the like for the array.

[0796] The refresh address counter 7407 corresponds to the refresh address counter 293 shown in FIG.

[0797] In correspondence with the configuration shown in FIG. 1, clock generator 7403 includes an auto refresh mode detection circuit 291 and a refresh control circuit 292.

FIG. 182 is a diagram showing a structure of a circuit for generating refresh signal REF. The configuration shown in FIG. 182 is included in clock generator 7403 shown in FIG. In FIG. 182, the circuit that generates refresh signal REF is driven by internal clock signal int. RE latching external refresh instruction signal REF # in response to K
An F buffer 7440 and a gate circuit 7450 receiving the output of the REF buffer 7440 and the refresh request signal / REFREQ from the refresh timer 7402 are included. Gate circuit 7450 outputs a signal of "H" when one of its inputs becomes "L". The refresh is executed when the refresh signal REF becomes “H”.

FIG. 183 is a signal waveform diagram representing an operation of the circuit shown in FIG. 181. Hereinafter, FIGS. 181 to 18
The switching operation in the auto refresh / self refresh sleep mode will be described with reference to FIG.

At time t1, the sleep mode is set and internal clock signal int. The generation of K is stopped.
Self-refresh switching circuit 7401 executes a counting operation from time t1, and when a predetermined time has elapsed, time t1
At 2, a self-refresh switching signal Self is generated and applied to the refresh timer 7402. The refresh timer 7402 outputs the self-refresh switching signal S
refresh request signal / REFREQ in response to elf
Is generated and supplied to the clock generator 7403.

Clock generator 7403 generates refresh signal REF in response to refresh request signal / REFREQ, and generates internal control signal / RAS. At this time, generation of internal control signal / CAS is stopped. In response to internal control signal / RAS, a row selecting operation and a sensing operation in the DRAM array are performed, and a self refresh is performed.

A refresh timer 7402 generates a refresh request signal / REFREQ every predetermined period. In response, internal control signal / RAS rises to "L",
Refresh is performed. The refresh address of the refresh address counter 7407 is incremented or decremented in each refresh cycle.

When the sleep mode is released at time t3, self-refresh switching circuit 7401 is reset to stop generating self-refresh switching signal Self. As a result, the count operation of refresh timer 7402 is reset and inhibited.

In the structure shown in FIG. 181, self-refresh switching circuit 7401 provides internal clock signal in
t. K is monitored and the self-refresh switching signal Sel is
f has occurred. Self refresh switching circuit 740
1 may be configured to monitor the sleep mode control signal SLEEP. Also, a refresh timer 7402
May be activated in response to sleep mode control signal SLEEP.

The refresh control system shown in FIG. 181 may be shared with the auto-refresh / self-refresh switching circuit shown in FIG.

FIG. 184 shows the sleep mode control signal SLE.
FIG. 11 is a diagram illustrating another example of a circuit configuration that generates an EP. FIG.
In the configuration shown in FIG. 4, the external chip select signal E #
Sleep mode is set by array access instruction signal CI # (corresponding to CC1 #). FIG.
4, sleep mode control circuit 7052 includes an inverter circuit 7 receiving internal chip select signal CE #.
601, a gate circuit 7602 receiving an output of the inverter circuit 7601 and an output of the gate circuit 7604, an inverter circuit 7603 receiving the external array access support signal CI #, and a gate receiving the output of the gate circuit 7602 and the output of the inverter circuit 7603 A circuit 7604 and an inverter circuit 7605 receiving an output of the gate circuit 7604 are included.

In FIG. 184, E buffer 7650 and CI buffer 7 included in the control clock buffer
651 is also shown. The E buffer 7650 and the CI buffer 7651 receive the internal clock signal int. External signals E # and CI at the rising edge of K
# Respectively to generate internal control signals E and CI.

FIG. 185 is a signal waveform diagram representing an operation of the circuit shown in FIG. 184. Hereinafter, the sleep mode setting operation will be described with reference to FIGS. 184 and 185.

In the circuit configuration shown in FIG. 184, the sleep mode is set by a combination of external control signals E # and CI #. Chip select signal E # is "H"
And the cache access inhibit signal CI # is "L"
The sleep mode is set when. In this state, the output of gate circuit 7602 is at "H", and the output of inverter circuit 7603 is at "H". Since both inputs of the gate circuit 7604 become “H” level,
An "L" signal is output. Thereby, sleep mode control signal SLEEP from inverter circuit 7605 rises to "H".

When cache access inhibit signal CI # rises to "H", the output of gate circuit 7604 rises to "H" and sleep mode control signal SLEEP
Falls to “L”. In the configuration shown in FIG. 184, the length of the sleep mode period is determined by cache access prohibition signal CI #.

The chip select signal E # and the cache access inhibit signal CI # are used as control signals when direct access is made to the DRAM array (that is, the chip select signal E # is set to "1" at the rising edge of the clock signal K in FIG. 185). If it is at "L" and the cache access inhibit signal CI # is at "L", the DRAM array is directly accessed.) Therefore, in order to prevent the sleep mode from being set when setting a direct access cycle to this array, As shown in FIG. 186, chip select signal E # and cache access inhibit signal C
A setup time Tsetup and a hold time Thold are set for I #. That is, FIG.
As shown in FIG. 7, the setup time Tsetup from when the chip select signal E # falls to "L" to when the cache access signal CI # shifts to "L" and the cache access prohibition signal CI # become "H". , A hold time Thold from when the chip select signal E # shifts to “H” is designated. At the time of array access, the cache access inhibit signal CI # shifts to "L" after the chip select signal E # shifts to "L". As a result, the chip select signal E # at the time of direct array access
Is "H", the state in which cache access signal CI # falls to "L" is prohibited, and erroneous setting to the sleep mode is prevented.

FIG. 187 shows a list of combinations of control signal states for setting the operation mode of the CDRAM. The operation mode of the CDRAM shown in FIG.
1 corresponds to that shown in Fig. 1, but has been partially modified according to the added functions. In the configuration shown in FIG. 187, burst mode operation, high-speed copy-back operation and D
Data transfer using latches in RAM arrays and SRAM arrays is added.

The additional functions shown in FIG. 187 will be briefly described below. The burst mode is set by the control signals E # and C
This is performed by setting H # and CC2 # (CR #) to "L" and setting the control signal CC1 # (CI #) to "H". Whether data writing or data reading is performed is determined by the state of write enable signal W #. If the write enable signal W # is at "H", the hit read burst operation is executed. If the write enable signal W # is at "L", the hit write burst operation is performed.

[0839] Control signals E #, CH # and CC1 # (C
I #) is "L" and the control signal CC2 # (CR #) is "H".
, The data transfer operation to the DRAM array is executed together with the cache hit operation. That is, in this state, data writing / reading is performed between the cache (SRAM) and the CPU, and the data latched by the latch means included in the transfer gate is transferred to the DRAM array. Whether the hit read operation or the hit write operation is performed is determined by the state of the write enable signal W #.

In the state of a cache miss,
Data is transferred from the cache to the latch means included in the transfer gate, data is transferred from the DRAM array to the SRAM array (cache), and data is written / read with the CPU via the cache (SRAM). Reading is performed. This state is executed by setting the chip select signal E # to "L".
Whether it is a misread or a miswrite is determined by the write enable signal W #.

In order to set an array write operation for executing data transfer from a latch (included in the data transfer gate) to the DRAM array when performing high-speed copy back, control signals E # and CC2 # (CR # ) To “L”
And control signals CH # and CC1 # (CI #)
Is set to “H”. In this state, data transfer from the latch to the DRAM array in the high-speed copy back mode is performed. Control signals E #, CC2 # and W # are set to "L", and control signals CH # and CC1 # (CI
When #) is set to "H", data transfer from the cache (SRAM array) to the DRAM array is executed.
Thereby, the DRAM array is initialized.

[0827] Control signals E # and CC1 # (CI
#) To “L” and control signals CH # and CC2 #
If (CR #) is set to "H", the array can be directly accessed. Whether data is written or read is determined by a write enable signal W #.

"Configuration for Providing Optimum CDRAM" Combination of functions effective for implementation is such that DRAM and SRAM can be addressed independently, and an internal voltage is generated using a continuously input clock signal. Configuration, a configuration of a data transfer path having two systems, an internal data transfer path and a data write path, a configuration of executing a DRAM array auto-refresh while accessing the SRAM array, A configuration for writing data to the SRAM array simultaneously with writing, a configuration for selecting between a high-speed operation mode and a low power consumption operation mode, a configuration for facilitating connection to a CPU with a burst mode function, and a reduction in standby current Combination of configuration with sleep mode and configuration that performs self-refresh even in normal mode A.

In the configuration for generating the internal voltage by the clock K, the charge pump is operated by the clock K to generate the substrate bias voltage.

(2) The most effective configuration of the CDRAM has the following functions. A configuration in which a DRAM and an SRAM can be independently selected; a configuration in which an internal voltage is generated in accordance with an external clock signal;
Configuration of data transfer path with system, high-speed copy-back mode function, configuration to execute auto-refresh of DRAM array during access to SRAM array, configuration to write write data to SRAM array at cache miss write, SRAM address And a DRAM column address, a configuration for switching an address generation method in accordance with a burst mode operation, a sleep mode function, a configuration for performing self-refresh even in a normal mode,
A configuration for separating a data write path and a data read path of a DRAM array.

[0821]

According to the first aspect of the present invention, switching between the self refresh mode and the auto refresh mode is performed by the refresh mode setting means. One terminal is set as a refresh instruction input terminal at the time of auto-refresh, and is switched to a self-refresh execution instruction output terminal at the time of self-refresh. Thus, the refresh timing can be known outside the semiconductor memory device even in the self refresh mode, and the self refresh mode can be used even in the normal mode.

[0822]

[0823]

[0824]

[0825]

[0826]

[0827]

[0828]

[0829]

[0830]

[0831]

[Brief description of the drawings]

FIG. 1 is a diagram functionally showing an entire configuration of a semiconductor memory device with a built-in cache according to an embodiment of the present invention;

FIG. 2 is a diagram schematically showing a configuration of a memory array unit of the semiconductor memory device shown in FIG. 1;

FIG. 3 is a diagram showing a detailed configuration of a memory array shown in FIG. 1;

FIG. 4 is a diagram showing another configuration example of the array arrangement of the semiconductor memory device shown in FIG. 1;

FIG. 5 is a diagram showing an arrangement of an array of a semiconductor memory device incorporating a 4M bit DRAM and a 16K bit SRAM;

6 is a diagram showing a layout of signal lines of a DRAM array in one memory block in the semiconductor memory device shown in FIG. 5;

FIG. 7 is a diagram schematically showing a structure of a bit line and a word line related to a memory cell in the DRAM shown in FIG. 5;

8 is a diagram schematically showing a configuration of a word line in the semiconductor memory device shown in FIG. 5;

9 is a diagram showing a layout of signal lines in the semiconductor memory device shown in FIG. 5;

10 is an SRA in the semiconductor memory device in FIG.
FIG. 3 is a diagram illustrating a configuration of an M array.

11 is a diagram showing a package for accommodating the semiconductor memory device shown in FIG. 5 and a pin arrangement;

12 is a diagram showing a connection form between internal data lines, bit lines of a DRAM array, and bit lines of an SRAM array in the semiconductor memory device shown in FIG. 1;

13 is a diagram showing an example of a configuration of a data input / output circuit in the semiconductor memory device shown in FIG.

14 is a diagram showing another configuration example of the data input / output circuit in the semiconductor memory device shown in FIG.

FIG. 15 is a diagram showing still another configuration of the data input / output circuit of the semiconductor memory device shown in FIG. 1;

16 is a diagram showing a circuit configuration for setting a data output mode of the semiconductor memory device shown in FIG.

FIG. 17 is a diagram showing a configuration of the output circuit shown in FIG.

18 is a diagram illustrating an example of a specific configuration of the latch circuit illustrated in FIG. 16;

19 is a block diagram showing a configuration of the output control circuit shown in FIG.

FIG. 20 is a timing chart showing an operation in the latch output mode of the circuit shown in FIG. 16;

FIG. 21 is a timing chart showing an operation in the register output mode of the circuit shown in FIG. 16;

FIG. 22 is a timing chart showing an operation of the circuit shown in FIG. 16 in a transparent output mode.

23 is a diagram showing an example of a specific configuration of a data transfer circuit in the semiconductor memory device shown in FIG.

FIG. 24 is a diagram showing D when the transfer gate circuit shown in FIG. 23 is used.
FIG. 4 is a signal waveform diagram showing an operation of transferring data from a RAM array to an SRAM array.

25 is another signal waveform diagram showing an operation of transferring data from the DRAM array to the SRAM array when the bidirectional data transfer circuit shown in FIG. 23 is used.

FIG. 26 is a signal waveform diagram illustrating an operation of transferring data from an SRAM array to a DRAM array.

FIG. 27 is a diagram illustrating a data transfer operation at the time of a cache miss in the semiconductor memory device shown in FIG. 1;

28 is a diagram showing a data transfer operation at the time of a cache miss in the semiconductor memory device shown in FIG.

29 is a diagram illustrating a data transfer operation at the time of a cache miss in the semiconductor memory device shown in FIG. 1;

FIG. 30 is a diagram illustrating another configuration example of the bidirectional transfer gate circuit.

FIG. 31 is a diagram showing a specific configuration of the circuit shown in FIG. 30;

FIG. 32 is a diagram showing a DRA by the circuits shown in FIGS. 30 and 31;
FIG. 4 is a diagram illustrating an operation of transferring data from an M array to an SRAM array.

FIG. 33 is a diagram illustrating the data transfer operation shown in FIG. 32;

FIG. 34 is a diagram illustrating the data transfer operation shown in FIG. 32;

FIG. 35 is a signal waveform diagram showing an operation of transferring data from the SRAM array to the DRAM array when the data transfer circuits shown in FIGS. 30 and 31 are used.

FIG. 36 is a diagram illustrating the data transfer operation shown in FIG. 35;

FIG. 37 is a signal waveform diagram showing a data transfer operation from the DRAM array to the SRAM array at the time of a cache miss read when the transfer gate circuit shown in FIGS. 30 and 31 is used.

FIG. 38 is a diagram illustrating the data transfer operation shown in FIG. 37;

FIG. 39 is a diagram illustrating the data transfer operation shown in FIG. 37;

FIG. 40 is a diagram illustrating the data transfer operation shown in FIG. 37;

FIG. 41 is a diagram showing another configuration example of the bidirectional data transfer gate circuit.

FIG. 42 is a diagram showing a detailed structure of the circuit shown in FIG. 41.

FIG. 43 is a signal waveform diagram showing an operation of transferring data from the DRAM array to the SRAM array when the circuit shown in FIG. 41 is used.

FIG. 44 is a diagram illustrating the data transfer operation shown in FIG. 43;

FIG. 45 is a diagram illustrating the data transfer operation shown in FIG. 43;

FIG. 46 shows a DRAM in the semiconductor memory device shown in FIG.
FIG. 4 is a diagram illustrating an example of a form of distribution of addresses and SRAM addresses.

FIG. 47 shows a DRAM in the semiconductor memory device shown in FIG. 1
FIG. 11 is a diagram showing another configuration for distributing addresses and SRAM addresses.

48 is a diagram showing a connection form between an internal data line and an SRAM bit line pair when the address distribution method shown in FIG. 47 is used.

FIG. 49 is a diagram functionally showing the configuration of the transfer gate control circuit shown in FIG. 1;

FIG. 50 is a diagram showing a functional configuration of the DRAM drive circuit shown in FIG. 1;

FIG. 51 is a diagram showing a list of combinations of control signals for performing various operations realized by the semiconductor memory device shown in FIG. 5;

FIG. 52 is a diagram showing a command register and a combination of control signals for selecting the command register in the semiconductor memory device shown in FIG. 1;

FIG. 53 is a diagram illustrating functions realized by the command register shown in FIG. 52;

54 is a diagram illustrating an example of a connection configuration between the semiconductor memory device illustrated in FIG. 5 and an external CPU;

FIG. 55 is a diagram showing another configuration example of the connection between the semiconductor memory device with a built-in cache and the external CPU shown in FIG. 5;

FIG. 56 is a timing chart showing a cache hit write operation in the semiconductor memory device shown in FIG. 5;

FIG. 57 is a timing chart showing a cache hit read operation in the transparent output mode of the semiconductor memory device shown in FIG. 5;

FIG. 58 is a timing chart showing a cache hit read operation in the latch output mode in the semiconductor memory device shown in FIG. 5;

FIG. 59 is a timing chart showing a cache hit read operation in the register output mode in the semiconductor memory device shown in FIG. 5;

FIG. 60 is a timing chart for setting a copy-back operation in the semiconductor memory device shown in FIG. 5;

FIG. 61 is a timing chart for setting a block transfer operation in the semiconductor memory device shown in FIG. 5;

FIG. 62 is a timing chart for setting an array write operation in the semiconductor memory device shown in FIG. 5;

63 is a diagram showing a timing of a control signal for setting an array read operation in the semiconductor memory device shown in FIG. 5;

FIG. 64 is a timing chart for setting an array active cycle in the semiconductor memory device shown in FIG. 5;

65 is a diagram showing a timing of a control signal for setting an array active operation with a transparent output mode in the semiconductor memory device shown in FIG. 5;

66 is a diagram showing a timing of a control signal for setting an array active operation with a latch output mode in the semiconductor memory device shown in FIG. 5;

FIG. 67 is a diagram showing a timing of a control signal for setting an array active operation with a register output mode in the semiconductor memory device shown in FIG. 5;

FIG. 68 is a timing chart showing an array read cycle in a transparent output mode in the semiconductor memory device shown in FIG. 5;

FIG. 69 is a timing chart showing an array read cycle with a latch output mode in the semiconductor memory device shown in FIG. 5;

FIG. 70 is a timing chart showing an array read cycle operation in the register output mode in the semiconductor memory device shown in FIG. 5;

FIG. 71 shows a timing of a control signal for setting a refresh operation in the semiconductor memory device shown in FIG. 5;

72 is a diagram showing timings of respective control signals for simultaneously performing a cache hit write operation and a refresh in the semiconductor memory device shown in FIG. 5;

73 is a diagram showing a timing of a control signal for setting a refresh operation accompanied by a cache hit read in the transparent output mode of the semiconductor memory device shown in FIG. 5;

74 is a diagram showing a timing of a control signal for setting a refresh operation involving a cache read in the latch output mode of the semiconductor memory device shown in FIG. 5;

75 is a diagram showing a timing of a control signal for setting a refresh accompanied by a cache hit read operation at a register output of the semiconductor memory device shown in FIG. 5;

76 is a diagram showing a timing of a control signal for setting a command register setting cycle of the semiconductor memory device shown in FIG. 5;

FIG. 77 is a state transition diagram showing an operation at the time of a cache miss in the semiconductor memory device shown in FIG. 5;

FIG. 78 is a state transition diagram showing an array access operation in the semiconductor memory device shown in FIG. 5;

FIG. 79 is a view showing a state transition during a refresh operation of the semiconductor memory device shown in FIG. 5;

FIG. 80 is a view functionally showing a configuration of a semiconductor memory device according to a second embodiment of the present invention;

FIG. 81 is a waveform chart showing a DRAM address fetch timing of the semiconductor memory device shown in FIG. 80;

FIG. 82 is a view illustrating an effect given by an address generation circuit included in the semiconductor memory device shown in FIG. 80;

FIG. 83 is a view illustrating another effect provided by the address generation circuit shown in FIG. 80;

FIG. 84 shows a specific structure of the address generation circuit shown in FIG. 80.

FIG. 85 shows a specific structure of the row address strobe signal generation circuit shown in FIG. 84.

86 is a diagram showing a specific configuration of a column address strobe signal generation circuit shown in FIG. 84.

FIG. 87 shows a specific configuration of the row address latch shown in FIG. 84.

FIG. 88 shows a specific structure of the column address latch shown in FIG. 84.

89 is a diagram showing a configuration for setting the timing for taking in the address of the circuit shown in FIG. 84.

FIG. 90 illustrates a high speed operation of the address generation circuit shown in FIG. 84.

FIG. 91 illustrates an operation of the address generation circuit shown in FIG. 84 in a low power consumption mode.

FIG. 92 shows another structure of the column address strobe signal generation circuit shown in FIG. 84.

93 is a signal waveform diagram representing an operation of the circuit shown in FIG. 92.

FIG. 94 is a view showing a list of combinations of operations realized by the semiconductor memory device shown in FIG. 80 and states of control signals for giving the operations;

FIG. 95 is a view illustrating a data transfer mode between the SRAM array and the DRAM array of the semiconductor memory device shown in FIG. 80;

96 is a signal waveform diagram representing an operation of the semiconductor memory device shown in FIG. 80 at the time of a cache miss.

FIG. 97 is a timing chart showing a cache hit read operation of the semiconductor memory device shown in FIG. 80.

98 is a waveform diagram showing a cache hit write operation in the low power consumption mode of the semiconductor memory device shown in FIG. 80.

99 is a signal waveform diagram representing a cache read operation in the low power consumption mode of the semiconductor memory device shown in FIG. 80.

100 is a signal waveform diagram representing a cache miss write operation in the low power consumption mode of the semiconductor memory device shown in FIG. 80.

101 is a signal waveform diagram representing an array write operation in the low power consumption mode in the semiconductor memory device shown in FIG. 80.

102 is a signal waveform diagram showing an array write operation accompanied by a cache hit read in the low power consumption mode in the semiconductor memory device shown in FIG. 80.

103 is a signal waveform diagram showing an array write operation accompanied by a cache hit write in the low power consumption mode of the semiconductor memory device shown in FIG. 80.

FIG. 104 is a signal waveform diagram showing a direct array read operation in the low power consumption mode of the semiconductor memory device shown in FIG. 80.

105 is a signal waveform diagram representing a direct array write operation in the low power consumption mode of the semiconductor memory device shown in FIG. 80.

106 is a signal waveform diagram representing a refresh array operation in the low power consumption mode of the semiconductor memory device shown in FIG. 80.

107 is a signal waveform diagram representing a refresh array operation involving a cache hit read in the low power consumption mode in the semiconductor memory device shown in FIG. 80.

108 is a signal waveform diagram showing a refresh array operation accompanied by a cache hit write operation in the low power consumption mode in the semiconductor memory device shown in FIG. 80.

109 is a signal waveform diagram showing a counter check read operation in the low power consumption mode of the semiconductor memory device shown in FIG. 80.

110 is a signal waveform diagram showing a counter check write operation in the low power consumption mode of the semiconductor memory device shown in FIG. 80.

FIG. 111 is a signal waveform diagram showing a command register setting operation in the low power consumption mode in the semiconductor memory device shown in FIG. 80.

112 is a diagram showing an example of a specific operation sequence in the low power consumption mode of the semiconductor memory device shown in FIG. 80;

113 is a diagram showing another example of a specific operation sequence in the low power consumption mode in the semiconductor memory device shown in FIG. 80;

114 is a signal waveform diagram showing a cache hit read operation in a transparent output mode in a high speed operation mode realized by the semiconductor memory device shown in FIG. 80.

115 is a signal waveform diagram showing a cache hit read operation in a latch output mode in a high speed operation mode realized by the semiconductor memory device shown in FIG. 80.

116 is a signal waveform diagram showing a cache hit read operation in a register output mode in a high speed operation mode realized by the semiconductor memory device shown in FIG. 80.

117 is a signal waveform diagram showing a cache hit write operation in a high-speed operation mode realized by the semiconductor memory device shown in FIG. 80.

FIG. 118 is a signal waveform diagram showing a cache miss read operation in a high-speed operation mode realized by the semiconductor memory device shown in FIG. 80.

119 is a signal waveform diagram showing a cache miss read operation accompanied by a latch output mode in a high speed operation mode realized by the semiconductor memory device shown in FIG. 80.

120 is a signal waveform diagram showing a cache miss read operation in a register output mode in a high-speed operation mode realized by the semiconductor memory device shown in FIG. 80.

121 is a signal waveform diagram showing a cache miss write operation in a high-speed operation mode realized by the semiconductor memory device shown in FIG. 80.

FIG. 122 is a signal waveform diagram showing an array write operation in a high-speed operation mode realized by the semiconductor memory device shown in FIG. 80;

123 is a signal waveform diagram showing an array write operation accompanied by a cache hit read in a high-speed operation mode realized by the semiconductor memory device shown in FIG. 80.

124 is a signal waveform diagram showing an array write operation accompanied by a cache hit read in a latch output mode in a high-speed operation mode realized by the semiconductor memory device shown in FIG. 80.

125 is a signal waveform diagram showing an array write operation accompanied by a cache hit read according to a register output mode in a high-speed operation mode realized by the semiconductor memory device shown in FIG. 80.

126 is a signal waveform diagram showing an array write operation accompanied by a cache hit write in the high speed operation mode in the semiconductor memory device shown in FIG. 80.

FIG. 127 is a signal waveform diagram showing a direct array read operation in a high-speed operation mode realized by the semiconductor memory device shown in FIG. 80;

128 is a signal waveform diagram representing a direct array write operation in a high-speed operation mode realized by the semiconductor memory device shown in FIG. 80;

129 is a signal waveform diagram showing a refresh array operation in a high-speed operation mode realized by the semiconductor memory device shown in FIG. 80;

130 is a signal waveform diagram showing a refresh operation accompanied by a cache hit read in a high-speed operation mode realized by the semiconductor memory device shown in FIG. 80.

131 is a signal waveform diagram showing a refresh array operation accompanied by a cache hit write in a high-speed operation mode realized by the semiconductor memory device shown in FIG. 80.

132 is a signal waveform diagram showing a counter check operation in a high-speed operation mode realized by the semiconductor memory device shown in FIG. 80.

FIG. 133 is a signal waveform diagram showing a counter check write operation in a high-speed operation mode realized by the semiconductor memory device shown in FIG. 80;

134 is a signal waveform diagram showing a command register setting operation in a high-speed operation mode realized by the semiconductor memory device shown in FIG. 80.

FIG. 135 is a signal waveform diagram showing an example of an operation sequence performed by the semiconductor memory device shown in FIG. 80 in the high-speed operation mode.

136 is a diagram showing another example of an operation sequence realized by the semiconductor memory device shown in FIG. 80 in the high-speed operation mode;

FIG. 137 is a diagram showing a configuration capable of selectively executing self-refresh and auto-refresh in the semiconductor memory device shown in FIG. 1 or 80.

FIG. 138 is a block diagram showing a specific configuration of the clock generator shown in FIG. 137.

FIG. 139 is a diagram showing an example of a specific configuration of an input / output switching circuit and a command register shown in FIG. 137;

140 is a signal waveform diagram representing an operation of the circuit shown in FIG. 137.

FIG. 141 is a diagram illustrating another configuration example of the circuit illustrated in FIG. 137;

FIG. 142 is a diagram illustrating a battery backup mode.

FIG. 143 is a block diagram showing a specific configuration of the BBU control shown in FIG. 141.

FIG. 144 is a diagram showing a configuration of the clock generator shown in FIG. 141 when the battery backup mode is implemented.

FIG. 145 is a signal waveform diagram representing an operation of the circuit shown in FIG. 144.

FIG. 146 is a diagram showing an example of a specific configuration of the RASS generating circuit shown in FIG. 144;

FIG. 147 is a diagram showing a configuration when the configuration shown in FIG. 137 is applied to a general DRAM.

FIG. 148 is a diagram showing an example of a specific configuration of the clock generator shown in FIG. 147.

FIG. 149 is a diagram showing another configuration example of the input / output switching circuit and the command register shown in FIG. 137.

FIG. 150 is a diagram showing another example of the configuration of the input / output switching circuit and command register shown in FIG. 137;

FIG. 151 is a diagram showing another configuration example of the address distribution method in the semiconductor memory device shown in FIG. 1 or 80.

FIG. 152 is a diagram showing a connection configuration between an address buffer circuit and an address decoder in the array distribution system shown in FIG. 151;

FIG. 153 is a diagram illustrating an example of a specific configuration of the determination circuit illustrated in FIG. 152;

FIG. 154 is a diagram illustrating a division position of an address signal line in the address distribution system shown in FIG. 151;

FIG. 155 is a diagram showing another configuration example for realizing the address division system shown in FIG. 151.

FIG. 156 is a signal waveform diagram representing an operation of the semiconductor memory device in the address distribution system shown in FIG. 151.

FIG. 157 is a timing chart representing an operation of the semiconductor memory device according to the address distribution system shown in FIG. 151.

FIG. 158 is a diagram illustrating an operation of the semiconductor memory device according to the address distribution system shown in FIG. 151;

159. The semiconductor memory device shown in FIG. 151 and an external CP
It is a figure which illustrates the connection form with U.

160 is a diagram illustrating a connection configuration between a semiconductor memory device and an external CPU according to the address distribution system shown in FIG. 151;

FIG. 161 is a diagram showing another configuration example of the DRAM array.

FIG. 162 is a signal waveform diagram representing an operation of transferring data from the DRAM array to the SRAM array in the memory array and transfer gate configuration shown in FIG. 161;

FIG. 163 is a signal waveform diagram representing an operation of transferring data from the SRAM array to the DRAM array in the configuration shown in FIG. 161.

FIG. 164 is a diagram showing a portion of the transfer gate shown in FIG. 161 for transferring data from the DRAM array to the SRAM array;

FIG. 165 is a diagram showing a circuit configuration for performing data transfer from the SRAM array to the DRAM array of the transfer gate shown in FIG. 161;

FIG. 166 is a diagram showing a circuit configuration for generating a signal for driving a column selection line in FIG. 161;

FIG. 167 is a diagram showing a circuit configuration for generating the block selection signal shown in FIG. 161;

FIG. 168 is a diagram illustrating an array distribution method for effectively driving the array configuration shown in FIG. 161;

FIG. 169 is a diagram showing a circuit configuration for realizing data transfer in a burst mode.

170 is a signal waveform diagram representing an operation of the circuit shown in FIG. 169.

FIG. 171 is a diagram showing an example of a specific configuration of the address counter shown in FIG. 169.

FIG. 172 is a diagram showing an example of a specific configuration of the burst data number storage circuit shown in FIG. 169;

FIG. 173 is a diagram showing a configuration for driving a general semiconductor memory device in a burst mode.

FIG. 174 is a diagram showing a specific configuration of an address buffer of the semiconductor memory device shown in FIG. 1 or 80.

FIG. 175 is a diagram showing a specific configuration example of the control clock buffer shown in FIG. 1 or 80.

FIG. 176 is a waveform chart showing an operation in a sleep mode.

FIG. 177 is a block diagram showing a circuit configuration for realizing a sleep mode.

FIG. 178 is a diagram showing an example of a specific configuration of the internal clock generation circuit shown in FIG. 177;

FIG. 179 is a diagram illustrating a specific configuration example of the sleep control circuit illustrated in FIG. 177;

180 is a signal waveform diagram representing an operation of the circuit shown in FIG. 179.

FIG. 181 is a diagram showing a circuit configuration for realizing self-refresh in a sleep mode.

182 is a diagram showing a configuration of a portion related to a refresh request signal of the clock generator shown in FIG. 181. FIG.

FIG. 183 is a signal waveform diagram representing an operation of the circuit shown in FIG. 181.

FIG. 184 is a diagram illustrating another configuration example of the sleep control circuit illustrated in FIG. 177;

185 is a signal waveform diagram representing an operation of the circuit shown in FIG. 184.

FIG. 186 is a diagram exemplifying conditions required for control signals E # and CI # to reliably set a sleep mode.

187 is a view showing a list of operations realized by the semiconductor memory device shown in FIG. 80 together with states of control signals thereof;

FIG. 188 is a diagram showing a configuration of a memory array in a conventional dynamic semiconductor memory device.

FIG. 189 is a diagram showing a configuration of an array unit of a conventional semiconductor memory device with a built-in cache.

FIG. 190 is a diagram illustrating a layout of a cache and a DRAM array in a conventional semiconductor memory device with a built-in cache;

FIG. 191 is a diagram showing a configuration of a cache when a 4-way set associative method is realized in a conventional semiconductor memory device with a built-in cache;

FIG. 192 is a signal waveform diagram showing an operation at the time of auto refresh in a conventional semiconductor memory device.

FIG. 193 is a signal waveform diagram showing a self-refresh operation in a conventional semiconductor memory device.

[Explanation of symbols]

Reference Signs List 1 DRAM 2 SRAM array 3 Bidirectional transfer gate circuit 14 DRAM row decoder 15 DRAM column decoder 22 SRAM column decoder 21 SRAM row decoder 100 DRAM 101 DRAM array 102 DRAM row decoder 103 DRAM column decoder 200 SRAM 202 SRAM row decoder 203 SRAM column decoder 260 DRAM array drive circuit 262 Transfer gate control circuit 264 SRAM array drive circuit 251 Internal data line 210 Bidirectional transfer gate circuit 272 Data input / output control circuit 274 Input / output buffer / output register 270 Command register 250 Control clock buffer 252 Address buffer 254 Clock Buffer 290 Refresh circuit 291 Auto refresh mode Detection circuit 292 Refresh control circuit 293 Counter circuit 299 Additional function control circuit 274a Output circuit 274b Input circuit 274c Input circuit 272a Output control circuit 272b Input control circuit 1810 Gate circuit 1811 Latch circuit 1813 Gate circuit 1815 Gate circuit 1814 Judgment circuit 1817 Gate circuit 360 Address generation circuit 2601 Row address strobe signal generation circuit 2602 Column address strobe signal generation circuit 2603 Row address latch circuit 2604 Column address latch circuit 2605 Reset signal generation circuit 3800 Clock generator 3102 Input / output switching circuit 252a DRAM row address buffer 252b DRAM column address buffer 3210 BBU generation circuit 3101 Timer 3501 I / O off Conversion circuit 3502 Command register 3505 Timer 3503 Clock generator 3110 Refresh pin terminal 4001 Address buffer 4020 Judgment circuit 4030 Judgment circuit LTG Local transfer gate ROG Read block select gate WIG Write block select gate GOL Global read line pair GIL Global write line pair LIL Local write line pair WCSL Write column select line RCSL Read column select line BTGR Circuit transfer gate section for transferring data from DRAM array to SRAM array BTGW Transfer gate section for transferring data from SRAM to DRAM 5110 Column selection Line drive circuit 5141 SRAM column decoder 5142 SRAM row decoder 5143 DRAM column select circuit 5144 DRAM row select circuit 6001 Buffer 6004 address counter 6007 multiplexer 6006 burst data number storing circuit 6700 Burst Mode operable semiconductor memory device 7051 internal clock generating circuit 7052 sleep control circuit 7401 self refresh switching circuit 7402 refresh timer 7407 refresh address counter for the burst enable signal

──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Koji Hayano 4-1-1 Mizuhara, Itami-shi, Hyogo Mitsubishi Electric Corporation Kita-Itami Works (72) Inventor Akira Yamazaki 4-1-1 Mizuhara, Itami-shi, Hyogo Mitsubishi Electric (72) Inventor Hisashi Iwamoto 4-1-1 Mizuhara, Itami-shi, Hyogo Mitsubishi Electric Corporation (72) Inside L-SI, Inc. (72) Inventor Hideaki Abe Mizuhara, Itami-shi, Hyogo 4-1-1, Mitsubishi Electric Corporation Kita-Itami Works (72) Inventor Katsumitsu 4-61-5 Higashino, Itami-shi, Hyogo Pref. Mitsubishi Electric Engineering Co., Ltd. LSI Design Center (72) Invention Yasuhiro Ishizuka 4-61-5 Higashino, Itami-shi, Hyogo Mitsubishi Electric Engineering Co., Ltd. Lee Design Center in (72) inventor Osamu Saeki Hyogo Prefecture Itami Higashino chome 61 No. No. 5 Mitsubishi Electric Engineering Co., Ltd. El es Eye design center in (58) investigated the field (Int.Cl. ^7, DB name ) G11C 11/406

Claims (1)

(57) [Claims] 1. A semiconductor memory device having an array of dynamic memory cells, comprising: means for generating a refresh address; auto-refresh means for refreshing said memory cell array in response to an external refresh instruction; Timer means for outputting a refresh request at predetermined intervals, self-refresh means for refreshing the memory cell array in response to a refresh request from the timer means, and auto-refresh and self-refresh for a refresh mode of the semiconductor memory device. includes a refresh mode setting means for setting any of said timer means, said refresh mode setting when the self refresh mode to the refresh mode setting means is set Is activated by the step, further comprising input and output switching means for setting to one of said refresh mode setting means refresh command input pins of one pin terminal in accordance with the set refresh mode to the terminal or the self-refresh execution instruction output pin terminals, the semiconductor Storage device.