JPH10228766A - Microcomputer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To increase the operational speed of a DRAM serving both as a DRAM and a cache for a microcomputer. SOLUTION: When plural sense amplifier lines 211 of a DRAM 101 is regionally localized. When a memory signal of any memory cell array 221 is read out, plural local bit lines among it are connected to a global bit line being common to the plural memory cell arrays, plural read out memory signals are detected by one of plural sense amplifier lines 211, and it is stored by the sense amplifier lines. The detected memory signal is divided into plural blocks, one of them is transmitted to a main amplifier section 231 through data lines being fewer than global bit lines. When post-read-access is hit, the hit data block is sent to the main amplifier section 231 from the sense amplifier lines 211 holding it.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a dynamic random access memory (D) which can use a sense amplifier as a cache.
(RAM) on a chip.

[0002]

2. Description of the Related Art A semiconductor memory section of a computer system usually has a hierarchical structure. For example, a high-speed, small-capacity cache unit usually constituted by a static random access memory (SRAM) and a medium-speed, large-capacity main storage unit usually constituted by a DRAM. This hierarchical structure is the result of a good combination of the high speed of SRAM and the low bit cost of DRAM. Further, with the recent progress in miniaturization technology, as shown in the block diagram of FIG. 15, a microcomputer unit 901, a cache unit 902, and a DRAM 903 connected to an internal bus 905.
A computer system in which the external bus interface 904 connected to the internal bus 905 and the external bus 906 are all mounted on one semiconductor chip 900 is also being developed. Such an example is described, for example, in the International Conference on Solid-state Circuits, 1996, Technical Paper Digest, pp. 216 to 2
Page 17 (1996 IEEE International
alSolid-State Circuits Co
nreference, pp. 216-217).

On the other hand, the sense amplifier of the DRAM is also an SRAM.
Since the configuration is the same as that described above, a DRAM utilizing this as a cache unit is disclosed in, for example, Japanese Patent Application Laid-Open No. 07-211062. The DRAM shown here includes a plurality of memory cell arrays 9 arranged discretely as shown in FIG.
21 and a plurality of sense amplifier arrays 911 discretely arranged.
And two sense amplifier rows 911 are located on both sides of each memory cell array 921. Column decoder 907
Are arranged near one end of a set of a plurality of memory cell arrays 921 and a plurality of sense amplifier arrays 911.
As shown, a column selection line 908 for selecting the plurality of sense amplifier rows 911 is provided so as to cross from the column decoder 907 to the plurality of memory cell arrays 911 and the plurality of sense amplifier rows 911. .

In order to use a sense amplifier as a cache, when a memory cell column is accessed in response to an external memory access, the memory cell column is used to detect a group of storage signals held in the memory cell column. One of the two sense amplifier rows located on both sides of the row is used. The sense amplifier array holds a group of storage signals read from the memory cell array. Such an operation is performed for any of the sense amplifier arrays. When any new memory access occurs, it is detected whether a group of storage signals held in the memory cell column requested by the access is held in any of the sense amplifier columns, and if the group of storage signals is stored, When a signal is held in one of the sense amplifier rows, a group of stored signals held in the specific sense amplifier row is output as a read signal, and the memory cell row is not accessed. A group of storage signals read from each memory cell column can be held in one of the sense amplifier columns on both sides of the memory cell column. Therefore, these sense amplifier columns on both sides serve as a two-way set associative cache. Operate.

[0005]

In a one-chip computer system as shown in FIG.
The larger the capacity of 02, the higher the cache hit rate,
Since the frequency of operating the slow DRAM 903 is reduced, the computer system becomes effectively faster. On the other hand, on-chip DRAM (hereinafter referred to as on-chip DRA)
M) If the capacity of 903 is large, DRAM outside the chip
(Not shown) becomes unnecessary, and a compact system can be constructed. That is, it is desirable to increase the capacity of both the cache unit 902 and the on-chip DRAM unit 903 as much as possible. For that purpose, Japanese Patent Application Laid-Open No. 07-21106
Considering the technology described in No. 2, on-chip DRA
It is conceivable to use the sense amplifier array in M903 as a cache and delete the cache 902.

However, the on-chip DRAM 903
Is configured as described in JP-A-07-211062, several problems arise. First, the operation speed of the cache unit in the on-chip DRAM increases. That is, in FIG. 16, since the column selection line 908 is arranged across the plurality of memory cell arrays 921 and the plurality of sense amplifier rows 911, the length of this signal line must be increased. The signal propagation delay on the signal line increases. For this reason, the time required to read out a group of storage signals held in the sense amplifier located far from the column decoder 907 becomes longer.

Further, the DRAM having the structure shown in FIG. 16 has a problem in increasing the cache hit rate. In general, it is known that in a set associative cache, the cache hit rate can be improved as the number of ways increases.
However, in the configuration of FIG. 16, it is impossible to make the size larger than two ways.

Accordingly, it is an object of the present invention to provide a DRAM that can use a sense amplifier array as a cache unit and is suitable for operating the cache unit at higher speed, and a microcomputer using the same.

Still another object of the present invention is to provide a DRAM which can use a sense amplifier array as a cache unit and is suitable for increasing the number of ways in the cache unit, and a microcomputer using the same.

[0010]

In a preferred embodiment of the microcomputer according to the present invention, a DRAM is provided on-chip, and a plurality of sense amplifier arrays of the DRAM are also used as a cache. In other words, a plurality of sense amplifier rows arranged in a direction parallel to the word line are collectively arranged to form a sense amplifier cache unit. The sense amplifier cache unit and the DRAM cell unit are connected by a plurality of global bit lines. A plurality of sense amplifiers belonging to different sense amplifier columns are connected to one global bit line via switches, and a plurality of local bit lines connected to a plurality of DRAM cells are connected to the global bit line. Connected via

In a more specific aspect of the microcomputer according to the present invention, a main amplifier for reading data detected by the cache sense amplifier and transferring the data to the microcomputer is connected to a data line different from the global bit line. Connected to the plurality of sense amplifier rows.

In another more specific aspect of the microcomputer according to the present invention, a data line for connecting the cache sense amplifier and a main amplifier for reading data from the cache is also used as the global bit line.

In another preferred embodiment of the microcomputer according to the present invention, a sense amplifier for performing a refresh operation of the DRAM cell is further connected to one of the global bit lines, and the sense amplifier for the refresh operation is connected to the global bit line. Is arranged between the DRAM cell section and the cache sense amplifier section, and the global bit line is appropriately divided into three sections of a DRAM cell section, a refresh sense amplifier section, and a sense amplifier cache section by two switch circuit rows. At the time of a cache mishit in reading, the cache sense amplifier and the refresh operation sense amplifier integrally perform an amplifying operation. At the time of writing, writing is simultaneously performed on the cache sense amplifier and the refresh operation sense amplifier.

In still another preferred embodiment of the microcomputer according to the present invention, of a plurality of sense amplifier caches connected to the same global bit line, a sense amplifier which is farthest from access from the microcomputer is stored. LRU (Least Re
A cache controller having a centrally used circuit is provided on-chip.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a microcomputer according to the present invention (hereinafter, may be referred to as a microcomputer) will be described in more detail with reference to some embodiments shown in the drawings. In the following, the same reference numerals represent the same or similar ones. In the second and subsequent embodiments, differences from the first embodiment will be mainly described.

<First Embodiment> In FIG. 1, a large-scale integrated circuit realizing a so-called one-chip microcomputer is formed as a semiconductor chip 100. That is, a microcomputer section (sometimes called a microcomputer section) 102 and an on-chip DRAM 10
1. The external bus interface 103 is mounted. The microcomputer unit 102 is connected to a DRAM 101 and an external bus interface 103 via an internal bus 106, and the external bus interface 103 is further connected to an external circuit (not shown) via an external bus 109. The microcomputer unit 102 includes a CPU, a ROM storing a program, and other circuits. DR
The AM 101 is used as a main memory of the microcomputer unit 102, but an external RAM (not shown) used as the main memory may be further connected as an external circuit. In this case, the DRAM 101 holds a part of the data to be held in the main memory, whereby the access from the microcomputer unit 102 to the data in the main memory can be speeded up. The internal bus 106 has an internal address bus 106a, an internal data bus 106b, and an internal control bus not shown for simplicity. In the following detailed description of the structure and operation, description of signals on the internal control bus is omitted. Each circuit on the semiconductor chip 100 is configured by an N-type MOS transistor, but may be configured by another type of transistor or a plurality of transistors having different types.

The sense amplifier row of the DRAM 101 is DRA
DRAM to be used as M101 cache
101 is configured. For this purpose, the semiconductor chip 10
0 does not have another cache for the DRAM 101. The DRAM cell unit 203 includes a plurality of, for example, four memory cell arrays (MC arrays) 221 collected in a region, and the sense amplifier cache unit 201.
Includes a plurality of, for example, six sense amplifier rows (SA rows) 211 collected in a region. These memory cell arrays 221 are arranged adjacent to each other, and the same applies to the plurality of sense amplifier rows 211. The sense amplifier cache unit 201 is arranged adjacent to one side of the DRAM cell unit 203. A main amplifier unit 231 is arranged adjacent to the sense amplifier cache unit 201 on the side opposite to the DRAM cell unit 203, is connected to the sense amplifier cache unit 201, and is connected to the microcomputer unit 102 via the internal bus 106 and to the outside. It is connected to the bus interface 103. Adjacent to the upper and lower sides of the sense amplifier cache unit 201, the sense amplifier / main amplifier (S
A / MA) connection circuit 251 and a sense amplifier / memory cell array (SA / MC) connection circuit 241A are provided.
A memory cell decoder (MC decoder) 241B is provided adjacent to the upper side of the RAM memory cell unit 203.

As will be described in detail later, the plurality of memory cells connected to each of the plurality of word lines constituting each memory cell array 221 are, for example, 256, and the number thereof is determined by the number of the internal data bus 106b. Data width, eg 6
It is set to a multiple of 4 bits. A plurality of signals stored in those memory cells connected to the same word line are read out to the sense amplifier cache unit 201 at a time, and held in one of the sense amplifier rows 211. However, the sense amplifier cache unit 201 selects 64 bits equal to the external data bus width from the plurality of signals read at one time as described above and supplies the selected signal to the main amplifier unit 231. 64 bits are transferred to the external data bus 106b. Data transferred to and from the external data bus at one time is called a data block. Therefore, four data blocks (which may be referred to as a data block group) are stored by a plurality of memory cells connected to each word line, and each sense amplifier row 211 is connected to a plurality of memory cells connected to one word line. The data block group read from the memory cell is held, and one of the data blocks is selected and transferred to the main amplifier unit 231. The column 211 to hold data read from a plurality of memory cells connected to any one of the word lines of the DRAM memory cell unit 203 is determined depending on the column 211 to which the word line belongs. More specifically, in the present embodiment, one sense amplifier row 211 is assigned to each of two memory cell arrays 221, and one sense amplifier row is assigned to a half region of each of the other two memory cell arrays 221. Column 211 has been assigned.

The microcomputer unit 102 performs an internal address bus 106 when executing a memory access.
a, and outputs an on-chip DRAM selection signal DS in synchronization with the clock CLK. If the memory access is a write access, a write enable signal WE is further output on line 12. The microcomputer 102 is connected to the DRAM via the line 13
The clock CLK continues to be supplied to 101. The address buffer 121 receives bit portions A1 to AN necessary for accessing the DRAM 101 among the memory addresses on the address bus 106a. When the microcomputer unit 102 requires an external RAM connected to the external bus 109, the address bits A1 to AN are part of the address data transmitted from the microcomputer unit 102 to the address bus 106a. When the microcomputer unit 102 does not require an external RAM, the address bits A1 to AN are equal to all bits of the address transmitted by the microcomputer unit 102 on the address bus 106a. If the capacity of each memory cell array 221 is 16 kbits and the capacity of the DRAM memory cell section 203 is 64 kbits, the value of N is 8.

The address buffer 121 supplies the received address bits A1 to AN to the cache controller 11, and further selects, from the addresses, lower bits necessary for selecting a word line to be accessed in the DRAM memory cell unit 203. Address part, here A3 to AN,
The signal is supplied to the memory cell decoder 241B via the line 17. The cache controller 111 performs a cache hit check based on the addresses A1 to AN given from the address buffer 121, and supplies a cache miss signal miss to the OR gate 10 via a line 325 if a miss is detected. I do. When the cache mishit signal “miss” supplied from the cache controller 111 becomes high, the OR gate 10 supplies a sense amplifier / memory cell array (SA / MC) connection circuit 241A, a memory cell decoder 241B, and a sense amplifier / Main amplifier (SA / MA)
A start signal START is supplied to the connection circuit 251 to start a memory read operation. Further, any one of the selection signals SY1 to SY6 for designating the sense amplifier row to hold the data block group read from the DRAM unit 203 is supplied to the sense amplifier row / memory cell array connection circuit 241A.
And the sense amplifier row / main amplifier connection circuit 251 via the line 14. Further, in order to specify a data block to be read out of the data block group,
The upper two bits A1 and A2 of the memory address are supplied to the sense amplifier column / main amplifier connection circuit 251 via the line 15. In the case of a cache hit, the cache controller 111 supplies any one of the sense amplifier column select signals SY1 to SY6, and further supplies the hit signal hi
t to the sense amplifier / main amplifier connection circuit 251 by line 3
27. In this case, the sense amplifier cache unit 201 is activated and the DRAM unit 203 is not activated. In the case of a write access, the microcomputer unit 102 outputs a write enable signal WE to a line 1
2, the OR gate 10 drives the DRAM unit 203 and the sense amplifier cache unit 201 in response to a start signal START.

Referring to FIG. 2, a DRAM memory cell section 203 is provided with a precharge circuit 202 in addition to a plurality of memory cell arrays 221. Each memory cell array 221 has a switch circuit row 22 provided at the center thereof.
3 and a pair of memory cell blocks 222L and 222R arranged on both sides thereof. A plurality of local bit line pairs BL1 / BB1 to BL256 / BB2 extending in the horizontal direction in the drawing across these two memory blocks
56 are provided. Further, a plurality of global bit line pairs GBL1 / GBB1 to GBL256 / GBB256 respectively corresponding to one local bit line pair are provided extending in the horizontal direction in the drawing. These global bit line pairs are connected to two memory blocks 222L and 22L.
Connected to 2R. Multiple global bit line pairs GBL
1 / GBB1 to GBL256 / GBB256 are a plurality of memory cell arrays 221 and a plurality of sense amplifier arrays 21.
1 to extend in the horizontal direction so as to be connected. These global bit line pairs GBL1 / GBB1 to GBL2
56 / GBB256 is the memory cell array 2
21, a plurality of local bit line pairs BL1 / BB1-B
It is formed on a wiring layer different from the wiring layer on which L256 / BB256 is formed. In the present embodiment, the number of global bit line pairs and the number of local bit line pairs in each memory cell array 221 are 256.

The left memory cell block 222L in each memory cell array 221 has a memory cell decoder 241
Word lines X1L and X2 extending in the vertical direction from FIG.
L,, and the right memory cell block 22
The 2R is provided with word lines X1R, X2R, extending from the memory cell decoder 241B in the vertical direction in the figure. In each memory block, at one of a pair of intersections between each word line and each local bit line pair, a memory cell is provided connected to the word line and one local bit line of the local bit line pair. ing. Therefore, the arrangement of the plurality of memory cells has a so-called folded bit line configuration. Further, a pair of dummy word lines (not shown) are provided so as to intersect with the plurality of local bit line pairs, and a dummy cell (see FIG. 1) is provided at one of a pair of intersections between each dummy word line and each local bit line pair. (Not shown). When reading a plurality of memory cells connected to any one of the word lines, a dummy cell connected to another local bit line forming a pair with the local bit line connected to the memory cell connected to the word line is read. One of the pair of dummy word lines is selected and driven so as to select it. Each memory cell is
A one-transistor memory cell known per se, comprising one transistor QMC and a signal storage capacitance C.

The switch circuit row 223 includes 256 switch circuits SWA1, SWAn (where n = 25) provided corresponding to one global bit line pair.
6), each switch circuit SWA1, or SWA
n represents one corresponding global bit line pair,
One corresponding local bit line pair BLi
/ BBi (i = 1,, or 256) and a pair of transistors QS1 and QS2. The pair of transistors QS1 and QS2 is determined for each memory cell array 221 to which the switch circuit belongs. Driven by the memory cell decoder 241B via the switch control line, for example, MX1. Each local bit line pair BLi / BBi (i = 1,... Or 256) is connected to one corresponding switch circuit SWAj (j = 1,.
Or 256) via a pair of global bit lines GB
Connected to Li / GBBi.

When reading a signal stored in any of the memory cell arrays 221, the memory block 222
L or 222R, the memory cell decoder 241B controls the address bits A
3 to AN, and the potential of the local bit lines BL1 to BL256 or BB1 to B256 connected to each memory cell is changed by the storage signal of a group of memory cells connected to the word line. . Thereafter, when the switch control line MX1 is driven by the memory cell decoder 241B, the potential of each local bit line pair BLi / BBi is transmitted to the corresponding global bit line pair via the corresponding switch circuit SWAj. ing.

The precharge circuit array 202 is provided in common to all the memory cell arrays 221 and includes a plurality of precharge circuits PC1 to PCn each connected to one global bit line pair GBLi / GBBi. Each precharge circuit has a known structure. That is, each precharge circuit includes a pair of transistors QP1 and QP2 for applying a precharge potential VPC (this is assumed to be equal to half of the power supply potential) to a corresponding global bit line pair, and a pair of global bit line pairs. A third transistor QP3 for equalizing the precharge potential. This pair of transistors Q
The sources of P1 and QP2 are connected to the corresponding global bit line pair, and their gates are connected to a precharge control line PCS connected to the memory cell decoder 241B.
, And each drain has a precharge potential VPC connected to the memory cell decoder 241B.
Are connected together. The gate of the third transistor QP3 is connected to the precharge control line PCS, and each source is connected to the corresponding global bit line pair.

When precharging the DRAM 101, the memory cell decoder 241B operates the precharge control line PCS in each of the plurality of memory cell arrays 221.
And drives the switch control lines MXi (i = 1,..., 4) in each memory cell array 221 so that all global bit line pairs correspond to corresponding ones in all memory cell arrays 221. Connect to local bit line pair. As a result, all the local bit line pairs are also precharged to the potential VCS by the precharge circuit array 202.

Referring to FIG. 3, memory cell decoder 2
In 41B, the precharge control circuit 401 causes the activation signal STAR supplied to the line 11 from the OR gate 10 (FIG. 1).
It is activated by T to drive the precharge control line PCS. The memory cell array selection circuit 402 is activated by the activation signal START, and the address buffer 12
1 to one memory cell array 22 specified by the lower address bits A3 and A4 applied via the line 11.
A signal MXi (i = 1,, or 4) for selecting 1 is generated. The X decoder / driver 403 is activated by the activation signal START, and includes a plurality of word lines X1L and X2 belonging to one memory cell array 221 determined by the generated memory cell array selection signal MXi.
R,..., X1L, X2L, address bit A5
The word line specified by .about.AN and one corresponding dummy word line are driven.

Referring to FIG. 4, the sense amplifier cache unit 201 includes, for example, six sense amplifier rows 211. Each column has four global bit line pairs,
For example, a plurality (64 in the present embodiment) provided corresponding to a set of GBL1 / GBB1 to GBL4 / GBB4
Are divided into sense amplifier blocks 214. 6 corresponding to one of these sense amplifier blocks, respectively.
Four data lines DL1 to DL64 are provided. Each data line DLi (i = 1,, or 64) is commonly connected to six corresponding sense blocks 214 in the six sense amplifier rows 211. The main amplifier unit 231 includes 64 main amplifiers Ma connected to one of these data lines and a circuit 261 for controlling these. Each sense amplifier block 214
A sense amplifier SA provided corresponding to each pair of global bit lines, a pair of transistors QSA1 and QSA2 for connecting the sense amplifier SA to the corresponding global bit line pair, and Third transistor QS for connecting to data line DLi corresponding to sense amplifier block 214
A3. At the time of read access or write access operation, one of the six sense amplifier rows 211 used for the memory access is selectively used as described later. For example, when a read access has a mishit, it is necessary to connect the sense amplifier row 211 to the DRAM memory cell unit 203. In such a case, the transistor pairs QS for all connections in the selected sense amplifier row 211
A1 and QSA2 are connected to a drive line SYiA (i = 1, 2) by a sense amplifier / memory cell array connection circuit 241A.
, Or 6), and the corresponding global bit line pair GBL1 / GBB1
~ GBL256 / GBB256.

Each sense amplifier SA is constituted by a flip-flop and is known per se. When the activation stop signal Si supplied thereto is at a low level, the sense amplifier SA is in an activated state and maintains the state of the flip-flop up to that time. That is, the sense amplifier SA is holding the memory read signal detected earlier. However, when the activation stop signal Si is at a high level, the sense amplifier SA is not activated. In this state, the sense amplifier SA is connected to a pair of switches QSA1 and QS connected thereto.
Responds to the input signal from A2. Therefore, the selected sense amplifier row 211 is stored in the DRAM memory cell section 203.
, The high-level activation stop signal Si is supplied to all the sense amplifiers SA by the sense amplifier / memory cell array connection circuit 241A. For example, when a read access miss occurs, the selected sense amplifier row 211
The four data blocks read simultaneously from the M unit 203 are detected and held. This is the same for memory write. That is, between the sense amplifier cache unit 201 and the DRAM unit 203, four data blocks are simultaneously transferred.

As shown in FIG. 5, the sense amplifier / memory cell array connection circuit 241A includes a plurality of ANs provided corresponding to one of the plurality of sense amplifier rows 211, respectively.
Each of the AND gates 409 has both the above-described start signal START and a sense amplifier row selection signal SYi (i = 1,, or 6) for the sense amplifier row 211 corresponding to the AND gate. Outputs a high level when it reaches the level. Rise detection circuit 410 connected to the output of AND gate 409
Detects the rising edge of the output of the AND gate 409, and activates the pulse generation circuit 411 connected to the rising detection circuit 410. When activated, the pulse generation circuit 41 supplies the connection signal SYiA and the sense amplifier activation stop signal Si to the corresponding sense amplifier row 211.

Four switches QSA3 are provided corresponding to each of the four sense amplifiers SA in each sense amplifier block 214. 64 switches QSA3 provided corresponding to 64 corresponding sense amplifiers SA belonging to different sense amplifier blocks 214
Are the same signal lines Yi (i = 1,, or 24) supplied by the sense amplifier / memory array connection circuit 251.
It is connected to the. Therefore, when the signal on the signal line Yi goes high, the 64 switches QSA3 connected to this signal line are turned on, and these switches QSA3 are turned on.
The 64 sense amplifiers SA connected to 3 are simultaneously connected to the data lines DL1 to DL64. Specifically, the signal Y1
Becomes high level, the first sense amplifier SA in each of the 64 sense amplifier blocks 214 is connected to the data lines DL1 to DL64. Therefore, data transfer between the selected sense amplifier row 211 and the main amplifier unit 231 is performed in units of 64 bits. This 6
The four bits are called a data block. Therefore, each sense amplifier row 211 is divided into four sense amplifier groups each including 64 sense amplifiers SA connected to the same signal line Yi. Hereinafter, each of these groups may be referred to as a sense amplifier group for each data block or a sense amplifier group corresponding to the data block. Each signal line Yi may be called a data block selection signal line or a sense amplifier group selection signal line.

As shown in FIG. 6, six decoders 4 correspond to one of the six sense amplifier rows 211, respectively.
In each decoder 419, a corresponding sense amplifier column selection signal SYi (i = 1, 6, or 6) from the cache controller 111 via a line 14 and upper two bits A1, A2 of a memory address are provided. Given. Each decoder 419 is connected to four rising detection circuits 420 and further a pulse generation circuit 421. When the corresponding sense amplifier column selection signal SYi is at a high level, each decoder 419 outputs the upper two bits A of the memory address among the four output lines of the decoder.
One, which is determined by A2, is set to a high level. The rising detection circuit 420 connected to the output line detects the rising of the potential of the output line and activates the corresponding pulse generation circuit 421. The start signal delayed by the delay circuit 422 is supplied to the pulse generation circuit 421. When both the delayed start signal and the start signal to be supplied from the corresponding rise detection circuit 420 are supplied, the pulse generation circuit 421
The corresponding data block selection signal Yi (i = 1,, or 24) is output to the corresponding sense amplifier row 211. The delay circuit 422 is used to delay the generation of the connection control signal by the pulse generation circuit 421 because the operation timing is generally delayed when the access to the memory cell array occurs as described above. . The start signal START is generated when a read access has a mishit or a write access. If read access hits, line 3
In response to a hit signal hit provided from the cache controller 111 via the OR gate 423 via the data block 27, the data block selection signal Yi is immediately generated.

In FIG. 4, the main amplifier MA is controlled by a control circuit 261. 261 is MA depending on whether it is a hit or mishit, and further depending on whether it is a read or a write.
Activation signal AMA, precharge signal PCM, and W
E is output at the timing in each case. FIG.
FIG. 1 shows a configuration example of the main amplifier MA. Precharge unit 1710 is controlled by signal PCM when WE is at a low level, and sets data line DL1 to the potential of VPM, for example, VPM.
Precharge to cc / 2. The latch unit 1711 is controlled by the signal AMA, and outputs a potential of Vcc or Vss to the line 1701 depending on whether the potential of DL1 is higher or lower than the potential of the line 1705. The potential of Vcc or Vss is output to the line 1702 in a complementary manner to the potential of 1701. At the time of a read operation, that is, when WE is at a low level, the line 1702 corresponding to the state of DL1 is connected to 1704 by the operation of the read / write switching unit 1712, and 1
704 is connected to the bus 106 of FIG. 1 (not shown).
During a write operation, that is, when WE is at a high level, 1
712 connects line 1704 to DL1. Note that a complementary data line DB1 may be provided and connected to the line 1705.

In the configuration shown in FIG.
Holds four data blocks, and the sense amplifier cache unit 201 holds a total of 6 × 4 = 24 data blocks. In the same sense amplifier row 211, 256-bit data read at the time of one memory access is divided and held in four blocks. Therefore, the four memory addresses for these four data blocks differ only in the A1 and A2 bits, and the A3 to AN bits are the same.

For example, when a read access is missed, 64 sense amplifiers SA corresponding to each other in a plurality of sense amplifier blocks 214 in the sense amplifier row 211 selected for this access correspond to each other. Data line, for example, DL1-64, and connected to the corresponding main amplifier MA. In this way, 256 pairs of global bit lines GB
Of the memory cell read signals read to B1 / GBL1 to GBB256 / GBL256, 64 pairs of memory cell read signals are detected differentially by the 256 sense amplifiers SA, and then these sense amplifiers SA
Of the data lines D by the signals detected by 64 of them.
The potentials of L1 to DL64 are changed to the power supply potential or the ground potential. Further, main amplifier MA connected to each data line outputs 64-bit data to internal data bus 106b according to the potential of those data lines.

As shown in FIG. 7, the cache controller 111 includes a cache tag 320, a direct mapping control circuit 330, and a signal output unit 310. The cache tag 320 includes, for example, 24 cache tag blocks 321 arranged in four rows and six columns. Each cache tag block 321 corresponds to one of the 24 data blocks held in the sense amplifier cache unit 201 shown in FIG. 4, and when a memory access to the corresponding data block is executed, The lower (N-) of the memory address of the corresponding data block
2) Address data consisting of bits A3 to AN is held. Writing of address data to each cache tag block 321 will be described later.

For a new memory access, the decoder 341 selects one of the four rows of the cache tag 320 from the upper two bits A1 and A2 of the memory address supplied from the address buffer 121. The address data held in the six cache tag blocks 321 belonging to the row is
Is read out on a read bus 322 provided corresponding to each column of. When the on-chip DRAM selection signal DS is supplied, the comparator 323 provided for each column of the cache tag block 321 receives the address data read from the corresponding column and the address data supplied from the address buffer 121. (N-2) bit A of the assigned memory address
3 to AN, and when a match is detected, the output signal BYi of the comparator 324 (i = 1, 2, 2, or 6)
Becomes high level. Output signals B of the six comparators 324
If any of Y1 to Y6 is at a low level, it means a cache mishit, and if any of the comparator outputs is at a high level, this means a cache hit. The signals BY1 to BY6 are used as signals for selecting a sense amplifier row holding data to be read when a cache hit occurs, as described later.
The NOR gate 324 has these comparator output signals BY
1 to 6 are input, the output signal "miss" of the AND gate 329 becomes a high level at the time of a cache mishit in synchronization with the pulse [Phi] m generated with a delay from the rise of the DS signal, Is supplied with a high level signal hit. The OR gate 10 (FIG. 1) generates the above-described memory access start signal START when the miss signal is at a high level. Thus, on a miss hit,
Access to the DRAM memory cell unit 203 for reading the memory starts.

In the case of a cache mishit, the data read by this memory read operation is detected by the direct mapping control circuit 330, and the sense amplifier row 211 to be held is determined as follows. Decoder 331 has four AND gates and three OR gates shown in the figure for decoding bits A3 and A4 of the memory address given from address buffer 121. As a result of decoding, the decoder 331 enables one of the four output lines. Decoder 3
Reference numeral 32 denotes four AND gates shown in the figure for decoding a set of a signal on two output lines corresponding to A3 = 1 among the four output lines of the decoder 331 and an address bit A5.
Gate and one OR gate, and as a result of decoding, A
When 3 = 1, one of the four output lines is newly enabled. Thus, the mask circuit 333 includes the decoder 33
When A3 = A4 = 0 from 1 and A3 = 0, A4 =
At the time of 1, two output lines respectively enabled and four output lines of the decoder 332 are input. The mask circuit 333 outputs the signals on the six input lines to the circuit as the sense amplifier column selection signals CY1 to CY6 at the time of the mishit when the mishit signal miss is at the high level. As a result, at the time of a cache miss, any one of the sense amplifier column selection signals CY1 to CY6 becomes a high level.

The direct mapping control circuit 330
In the case of having the internal structure shown in FIG. 7, two of the four memory cell arrays 221 correspond one-to-one to the two sense amplifier rows 211, and 1 / 2 (for example, 222 in FIG. 2)
L, 222R) correspond to the four sense amplifier rows in a one-to-one correspondence. Therefore, the memory cell array 211 to which the word line determined by the bits A3 to AN of the memory address designated by the memory access to be executed belongs is selected so that one sense amplifier row determined by the above mapping is selected. One of the sense amplifier column selection signals CY1 to CY6 goes high.

The signal output section 310 responds to a set of a sense amplifier column selection signal BYi (i = 1, 6, or 6) at the time of a cache hit and a sense amplifier column selection signal CYi at the time of a cache miss. An OR gate 313 to which a set of signals is input, a rise detection circuit 311 for detecting the rise of its output, and a pulse generation for generating a sense amplifier row selection signal SYi consisting of a pulse of a fixed width when activated by the output of the circuit 311 A circuit 312; Therefore, signal output section 310 generates one sense amplifier column selection signal SYi in both a cache hit and a cache miss,
It is supplied to the sense amplifier / memory array connection circuit 251.

At the time of a cache mishit, the bits A3 to AN of the address used for the memory access to be executed at present are replaced by the cache tag block 321 corresponding to the sense amplifier row selected by the direct mapping circuit 330 as follows. To hold. That is, corresponding to each column of the cache tag 320, the bit A3 to the AN of the address being accessed are transferred to the data bus 322.
Is provided, and the switch 334 corresponding to the column is provided by the high-level sense amplifier column selection signal CYi output from the mask circuit 333.
Is turned on, and AN is supplied to the bus 322 from the address bits A3. Of the four cache tag blocks 321 belonging to that column, one block belonging to the row selected by the coder 321 holds this data.

The operation of the apparatus shown in FIG. 1 will now be described with reference to FIGS.
This will be described with reference to FIG.

FIG. 8 shows operation waveforms at the time of a read hit. In this case, the read operation for the DRAM unit 203 is not performed, and the data block held in any one of the sense amplifier arrays is read. At the time of a read hit, the signal WE remains at the low level, and the cache controller 111 outputs the hit signal hi.
t becomes a high level, any one of the sense amplifier column selection signals BY1 to BY6 at the time of hit, for example, BY1, becomes a high level, and one of the sense amplifier column selection signals SY1 to SY6, for example, SY1 becomes high. Level. The mishit signal miss and the sense amplifier row select signals CY1 to CY6 at the time of mishit remain at low level. As a result, the start signal START is output from the OR gate 10 (FIG. 1).
Is not output. Therefore, the memory cell decoder 24
1B and sense amplifier / memory cell array connection circuit 241
A is not activated. In this state, all local bit lines and all global bit lines are in a precharged state. Therefore, the sense amplifier selection signals SY1A to SY6A provided from the sense amplifier / memory cell array connection circuit 241A remain at the low level, and all the sense amplifier rows 211 are disconnected from all the global bit line pairs GBB1 / GBL1. Up to.

Sense amplifier row activation stop signals S1 to S6
Are all at the low level, all the sense amplifier rows 211 are in the activated state, and continue to latch the data held until then. In response to the hit signal hit and the sense amplifier column selection signal SY1 going high, the sense amplifier / memory array connection circuit 251
Converts one of the data block selection signals Y1 to Y4 for the first sense amplifier row 211 into address bits A1,
Select according to the value of A2. For example, A1 = 0, A2 =
If it is 0, the line Y1 is selected. In this way, the 6 connected to the line Y1 included in the first sense amplifier row 211
The four transistors QSA3 are turned on, and the 64-bit data held in the 64 sense amplifiers SA connected to these transistors QSA3 is transferred to the data line DL1.
~ 64. The main amplifier unit 231 latches these data in synchronization with the AMA signal and transfers the data to the microcomputer unit 102 via the internal data bus 106b. After this latch by the main amplifier unit 231, the sense amplifier / memory array connection circuit 251 returns the data block selection signal Y1 to the low level. The precharge voltage of the data line (VPM in FIG. 17) is half of the power supply voltage.

FIG. 9 shows operation waveforms at the time of a read error. In this case, a read operation is performed on the DRAM unit 203, and one of the sense amplifier arrays is used for detecting a read signal. At the time of a read miss, the signal WE remains at a low level, but in the cache controller 111, the signal miss goes to a high level, and any one of the sense amplifier column selection signals CY1 to CY6 at the time of a miss hit, for example,
CY1 goes high, and the corresponding sense amplifier column selection signal SY1 goes high. At the time of a hit, the sense amplifier row select signals BY1 to BY6 remain at the low level.
Before the generation of the miss signal, the precharge control signal PC
S and the memory cell array selection signals MX1 to MX4 remain at a high level, and all global bit lines and local bit lines are precharged to the VPC potential. mi
A start signal START is generated by the generation of the ss signal. The memory cell decoder 241B is activated. Depending on the values of the address bits A3 and A4, one of the four memory cell arrays 221 is selected, and a selection signal for the selected memory cell array, for example, MX1, is kept at a high level. Memory cell array selection signal M
X2-4 are set to low level. As a result, all the local bit lines of the three memory cell arrays other than the selected one memory cell array are disconnected from all the global bit lines.

The generation of the start signal START also activates the sense amplifier / memory cell array connection circuit 241A. As a result, in response to the high level sense amplifier column selection signal SY1, the first sense amplifier column 211
Is set to a high level. As a result, all the sense amplifiers SA belonging to the selected first sense amplifier row are deactivated and connected to the corresponding global bit line pair. At the timing when these sense amplifiers SA are precharged, the memory cell decoder 241B
Sets the precharge control signal PCS to a low level and brings all the global bit lines into a floating state.
Thereafter, the memory cell decoder 241B outputs a word line determined by, for example, the address bits A3 to AN, for example, X1R.
To read a group of memory cells connected to the word line. As a result, a read signal is generated on all global bit line pairs.

Thereafter, the sense amplifier / memory cell array connection circuit 241A sets the sense amplifier activation stop signal S1 to the low level again to activate the selected first sense amplifier row. Thus, the memory read signal on each global bit line pair is amplified. In the case of a read miss, the sense amplifier / memory array connection circuit 251 sets the data block selection signal Y1 to a high level at a timing later than in the case of FIG. 8 in response to the start signal START delayed by the delay circuit 422. I do. The delay time of the delay circuit 422 is determined so that the selection signal Y1 is output when the amplification by the selected sense amplifier train is completed. Thus, the memory read signal is output to the data lines DL1 to DL64 and latched by the main amplifier unit 231. After this latch by the main amplifier unit 231, the sense amplifier / memory array connection circuit 251 outputs the data block selection signal Y
Return 1 to low level. After that, the memory cell decoder 2
41B returns the selected word line X1R to the low level. Sense amplifier / memory cell array connection circuit 241A
Returns the signal SY1A to low level, and separates the selected sense amplifier row 211 from all the global bit line pairs. Further, the memory cell decoder 241B returns the precharge control signal PCS to the high level, and precharges all the global bit lines again. Further, the memory cell array selection signal MX1 is returned to the high level. In addition,
The miss signal is returned to a low level in accordance with the pulse width of the pulse signal Φm generated with the rising edge of DS as a trigger.

FIG. 10 shows the waveform of the write operation. The operation at this time is the same regardless of a cache hit or a mishit. During a write operation, the microcomputer unit 102 supplies a memory address to the internal address bus 106a and the internal data bus 10a.
The write data is sent to 6b, and a write enable signal WE is supplied to the DRAM 101 via the line 12. The operation of the cache controller 111 is the same as in FIG. 9, so the signals associated with this circuit are S
Only Y1 to Y6 are shown. The operations of the DRAM unit 203 and the sense amplifier cache unit 201 differ from the case of FIG. 9 only in responding to the signal WE. However, in the case of a write operation, the main amplifier 231 latches the write data, and the write data is stored in the DRAM 2
9 differs from FIG. 9 in that the sense amplifier cache unit 201 and the DRAM unit 203 operate so that the data is written to the address 03. That is, the DRAM unit 203 performs the same read operation as that at the time of the read mishit in FIG.
Execute for 1. At this time, one sense amplifier row 211 used for writing the write data is also selected in the same manner as in FIG.
A sets the global bit line pair GBL1 / GBB1 to G
After being connected to BL64 / GBB64, it is activated by a signal S1.

On the other hand, in parallel with the above operation, the write data is latched in the main amplifier unit 231 and the potential of the data lines DL1 to DL64 is changed to the power supply potential or the ground potential by the data held in the corresponding main amplifier MA. Is done. As in the case of FIG. 9, the memory cell array 221
When the data block selection signal Y1 is activated at the time when the data read operation to the memory cell is almost completed, a group of connection transistors turned on by the data lines DL1 to 64 and the signal Y1, and a group of connection transistors connected thereto are turned on. Sense amplifier SA and group of connection transistors QSA
1, the global bit line pair G according to the write data latched by the main amplifier unit 231 via the QSA2.
The potential is transferred to the potential of BL1 / GBB1 to GBL64 / GBB64. These global bit line pairs GBL1 / G
The signals on BB1 to GBL64 / GBB64 correspond to the group of memory cells in which the read operation has been executed by the 64 sense amplifiers SA activated by the signal S1 in the selected sense amplifier row 211. Is written to. According to this write operation, the data newly latched in the selected sense amplifier unit 214 matches the data stored in the DRAM cell associated with the cache tag.

As described above, in this embodiment, since the sense amplifier section is also used as a cache, the capacity of the cache can be made larger than when these are separately provided on one semiconductor integrated circuit. As a result, the cache hit rate can be improved, and the frequency of accessing slow DRAM cells can be reduced, so that a high-speed microcomputer can be obtained effectively.

Further, since the plurality of sense amplifier rows 211 are locally concentrated, the data lines DL1 to 64 connecting these sense amplifier rows to the main amplifier can be shortened. As a result, the capacitance and resistance of these data lines can be reduced, so that reading or writing of a memory cell via these data lines can be performed at a higher speed than in the other case.

Further, the present embodiment is suitable for configuring an on-chip DRAM having a larger capacity or a higher speed. That is, in a DRAM in which a bit line is connected to one sense amplifier and a large number of memory cells are connected to the bit line, a DRAM connected to the bit line is usually used.
When the number of cells is increased, the capacity of the bit line is increased, and DR
The signal amount stored in the AM cell is reduced below the required amount. However, in the present embodiment, the memory cell array is divided into a plurality of cell arrays, and only the memory cells of the cell array are connected to local bit lines in each cell array.
Each local bit line of each memory cell array was connected to a sense amplifier via a global bit line provided commonly to a plurality of memory cell arrays. When the bit lines are hierarchized in this way, the bit line capacity, which is a load on the sense amplifier when reading data from the DRAM cell, is almost equal to the sum of the capacity of one global bit line and the capacity of one local bit line. Become equal. Since the global bit line has almost no junction capacitance, no word line capacitance, and no plate capacitance, the capacitance per unit length can be much smaller than the local bit line.

FIG. 18 shows a sectional structure of the memory cell MC. Global bit line GBL1 (180
The parasitic capacitance in the vertical direction 1) is the capacitance C of the bit line BL1.
bb is a main component thereof, and can be reduced by increasing the interlayer film thickness. On the other hand, local bit line BL1 (1
As the vertical parasitic capacitance 802), the diffusion layer 1804
, The capacitance Cbw of the paired word line 1806,
There is a capacitance Cbp of the pair plate line 1808 and the like. Here, it is difficult to widen the interval between 1802 and 1808 to reduce Cbp. Because 1802
It is necessary to reduce the distance shown by h in FIG. 18 in order to form a plug that electrically connects
When the thickness of the capacitor C or the word line 1806 formed by the storage section 1807 and the plate 1808 is added,
The distance between 2 and 1808 must be reduced. In FIG. 18, reference numeral 1803 denotes a semiconductor substrate;
Is a diffusion layer similar to 1803.

For the above reasons, for example, the capacity of the global bit line per unit length can be made about 20% of the capacity of the local bit line. Therefore, in the first embodiment, the number of DRAM cells connectable to one sense amplifier is approximately four times the number of memory cells connected to local bit lines used in a conventional memory not using global bit lines. , The length of the global bit line is set to four times the length of the local bit line used in the conventional memory that does not use the global bit line, and the length of the local bit line in the first embodiment is reduced. Is 1 / 20th of the length of the global bit line,
The load capacity of each sense amplifier SA is almost the same as the capacity of one bit line which is the load load of the sense amplifier in a conventional memory not using a global bit line. Therefore, in the first embodiment, even if the number of DRAM cells connected to one sense amplifier is almost four times the number of memory cells connected to each bit line of a conventional memory not using a global bit line,
The amount of signal stored in the cell does not decrease. Conversely, when the number of memory cells in the first embodiment is the same as that in the conventional memory that does not use the global bit line, the memory according to the first embodiment has a capacity as a load of the sense amplifier in the conventional memory. Since the memory can be reduced to one fifth, the memory according to the first embodiment can read or write the memory cells at a higher speed than the conventional memory.

<Modifications of First Embodiment of the Invention> Various modifications can be made to the first embodiment. The following is
It is an illustration of those modifications.

(1) Cache Tag 320 In the configuration of the sense amplifier array 211 shown in FIG. 4, as described above, the four data blocks held in the same sense amplifier array 211 are used when one memory access is performed. At the same time. Therefore, in the configuration of the sense amplifier array of FIG. 4, the address bits A3 to AN held in the four blocks belonging to the same column of the cache tag 320 have the same value. Therefore, for the configuration of FIG. 4, 4 rows × 1 column of the cache tag 320 is sufficient. However, the cache tag 320 illustrated in FIG. 7 is configured to be applicable to a configuration other than the configuration illustrated in FIG. 4, for example, a sense amplifier cache unit 201 having a configuration of a sense amplifier array illustrated in FIG.

(2) Precharge Circuit PC1 In the first embodiment, each precharge circuit PC1,..., Or 64 is provided corresponding to one global bit line pair. Memory cell array 2
21 may be provided for each bit line pair. In this case, the total number of precharge circuits is larger than in the present embodiment,
The time until completion of the precharge can be shortened. Further, the precharge potential VCS of the local bit line and the global bit line is set to a value other than half the power supply potential,
For example, the power supply potential or a value close thereto can be used.

(3) Direct Mapping Circuit 330 The direct mapping circuit 330 shown in FIG. 7 includes a plurality of memory cell arrays 221 and a plurality of sense amplifier arrays 2.
11 has been determined depending on the particular mapping already described. Therefore, when this mapping is changed, or when a plurality of memory cell arrays 221 are changed.
When the number of sense amplifier rows 211 is changed, the direct mapping circuit 330
May be changed.

<Embodiment 2> FIG. 11 shows a semiconductor chip which realizes a DRAM having a larger capacity by using the structure of FIG. A plurality of mats 701 are provided on both sides of the microcomputer unit 102, and each mat has a D
RAM memory cell section 203, memory cell decoder 241
B, sense amplifier cache unit 201, sense amplifier /
Memory cell array connection circuit 241A, main amplifier 2
Two sets of 31 are provided, and a sense amplifier / memory array connection circuit 251, an address buffer 121, and a cache controller 111 are provided in common to these two sets. Each mat is connected to the microcomputer unit 102 by one of two internal buses 106. However, the number of memory cell arrays 221 included in the DRAM memory cell unit 203 is assumed to be 16 unlike the case of FIG. Although the size of the mat 701 located on the left half of the figure is shown in a reduced size, it is the same size as the mat 701 shown on the right side of the figure. For example, when the number of mats 701 is 8, a 4-Mbit DRAM is formed on-chip. Also in the present embodiment, similar to the first embodiment,
The sense amplifier cache unit 201 is the main amplifier unit 23
1 and the main amplifier unit 231 is arranged close to the microcomputer unit 102, so that access to the sense amplifier cache unit 201 is fast.

<Third Embodiment of the Invention> FIG. 12 shows another circuit example of the sense amplifier cache unit 201. FIG.
The circuit configuration of D is connected to the same global bit line pair.
In this configuration, data in the RAM cell can be simultaneously taken out to the main amplifier. 12, sense amplifier column selection lines from sense amplifier / memory array connection circuit 251 are provided in a direction crossing sense amplifier column 211, and data output lines DL1A to DL16 to main amplifier unit 231 are provided.
A, DL1B to DL16B, DL1C to DL16C, D
L1D to DL16D are provided in a direction along the sense amplifier row 211. The sense amplifier main amplifier connection circuit 251 provided in parallel with the sense amplifier row 211 simultaneously selects the four sense amplifiers of the block 212 in the sense amplifier row 211 and connects them to the main amplifier unit 231.
On the other hand, the sense amplifier memory cell connection circuit 241A is similar to the sense amplifier memory cell connection circuit 241A of FIG. In FIG. 12, the SA selection line can be made shorter than in the conventional sense amplifier cache shown in FIG. A microcomputer with an on-chip cache and D
As compared with a system constituted by two chips with a RAM, a system which is compact and suitable for portable equipment can be obtained.

<Fourth Embodiment of the Invention> FIG. 13 shows a configuration of another sense amplifier cache unit and a circuit related thereto. The configuration of FIG. 13 differs from FIG. 4 in the following two points. First, the sense amplifier array 21 used as a cache
1, a sense amplifier block unit 502 is provided for refresh operation of the DRAM memory cell unit, and includes global bit lines GBL1 / GBB1 to GBL2.
A sense amplifier 521 provided corresponding to 56 / GBB256 is included. Accordingly, two switch circuit rows 50 are provided at both ends of the sense amplifier block section 502.
3L and 503R are provided. Switch circuit row 5
03R, each global bit line GBLi or GBLi
Transistor QR for dividing Bi (i = 1,, or 256) is provided, and each global bit line GBLi or GBBi (i
= 1, 256 or 256) is provided with a transistor QL. The sense amplifier memory cell connection circuit 241A is connected to these switch circuit rows 503R, 503R.
Control 3L. Second, the data line connected to the main amplifier unit 231 is not particularly provided, and the global bit lines GBL1 / GBB1 to GBL256 / GBB2
Reference numeral 56 also serves as a data line, and is connected to the main amplifier unit 231. Therefore, the connection control transistor QSA3 used in FIG. 4 is not used in each sense amplifier row 211. The main amplifier unit 231 is provided with a multiplexer MPX for selecting one of the pairs of global bit lines adjacent to each other, and a pair of global bit lines selected by each multiplexer MPX is provided. It is connected to the main amplifier MA corresponding to the multiplexer MPX. Note that in FIG.
The signals S1 to S6 generated at A are generated at 251 in FIG. Then, it is generated not from SY1 to SY6 but from Y1 to Y6. Further, the control circuit 261 of the main amplifier receives A1 and A2 in addition to the signals miss, hit, and WE, and outputs a control signal for the multiplexer MPX.

Hereinafter, the operation of this device will be described with reference to FIG. 14, mainly focusing on the operation of the refresh operation sense amplifier 521 and the switches QR and QL provided on both sides thereof. Below, for a certain memory access,
13, the rightmost column is selected from the six sense amplifier columns 211, and a sense amplifier group corresponding to the data block including the uppermost sense amplifier in each of the sense amplifier blocks 214 is selected. The case will be described with an example of a memory access operation to the global bit line pair GBL1 / GBB1. FIG. 14 (a)
In (c), Xi in the DRAM memory cell unit 203 represents a word line to which a group of memory cells holding block data requested by the memory access being executed is connected, and the switch circuit SWA11 is connected to the word line. Xi
, And a signal MX1 represents a signal for controlling this switch circuit. The switch circuit SWA12 and the signal MX2 represent signals for other word lines.

(A) At the time of a read hit, FIG.
As shown in the figure, the switches QSA1 and QSA2 connected to the selected sense amplifier SA are turned on by the data block selection signal Y1, and this sense amplifier SA is connected to the global bit line pair GBL1 / GBB1, and the selected sense amplifier SA is connected. The data held in the SA is read out to the main amplifier MA. Without memory access,
The left switch control signal SYL is held at a low level, and the right switch control signal SYR is held at a high level. As a result, the region of the global bit line pair GBL1 / GBB1 on the side of the sense amplifier SA and the region on the side of the refresh operation sense amplifier 521 are separated by a pair of switches QL. These signals do not change when a read hit occurs. As a result, the bit line capacitance acting as a load on the main amplifier MA can be reduced, and high-speed operation can be performed. In parallel with the reading of the data block held in the selected sense amplifier row 211, the DRAM
In the memory cell unit 203, a refresh operation is performed on a plurality of memory cells connected to the selected word line Xi. That is, unlike the case of Embodiment 1,
The memory cell decoder 241B (FIG. 2)
i, and further supplies the signal MXi to turn on the switch SWA11 corresponding to the word line Xi. Thus, the refresh operation sense amplifier 521 amplifies the storage signals of the plurality of memory cells connected to the word line Xi. The plurality of memory cells are refreshed by this read operation.

(B) At the time of a read error, as shown in FIG. 14B, the signals SYL and SYR are both set to the high level, and the global bit line pair GBL1 / GBB1 is connected from the main amplifier MA to the DRAM cell unit 203. In this state, the read operation is performed on the selected memory cell in the DRAM cell unit 203, and the refresh operation sense amplifier 521 cooperates with the selected sense amplifier SA to read the signal of the memory cell. Used to amplify As described above, the read operation can be performed at high speed by using the selected sense amplifier SA and the refresh operation sense amplifier 521 simultaneously for signal amplification.

FIG. 19 is a specific circuit example of the sense amplifiers SA and 521, and FIG.
3 is an operation waveform at the time of a read error when applied to No. 3.
The SA and 521 cooperative amplification operation will be described with reference to FIGS. In FIG. 19, SA and 521 are formed by well-known flip-flop circuits. In FIG. 20, at the time of a read miss, both SYL and SYR are at a high level. Then, SA is deactivated by S1, and the latched cache data is released. When a memory cell signal is generated in GBL1 / GBB1 in the same manner as in FIG. 9, SA and 521 are activated almost simultaneously by S1 and SR. As a result, SA and 521 cooperate to amplify the signal. At this time, unlike FIG. 9, the AMA almost follows the start of the sense amplifier amplification.
To start the main amplifier operation. Because Figure 9
This is because the data line is also used as a global data line, and a direct signal transmission path is formed from the memory cell to the main amplifier without passing through the sense amplifier cache.

(C) The operation at the time of writing does not depend on a cache hit or a mishit. As shown in FIG. 14C, first, the signal SYL is held at a high level,
YR is changed to low level, and the selection signal Y1 is also changed to high level. As a result, global bit line pair GBL1
/ GBB1 is connected to the selected sense amplifier SA and refresh operation sense amplifier 521;
The switches QSA1 and QSA1 corresponding to the selected sense amplifier SA are separated into portions connected to the RAM cell unit 203.
QSA2 is turned on. As a result, the write data is transferred to the selected sense amplifier SA by the main amplifier MA.
And the refresh operation sense amplifier 521 are simultaneously written. Thus, the selected sense amplifier SA
And writing of write data to the refresh operation sense amplifier 521 is performed by using the global bit line pair GBL.
This is performed using a part of 1 / GBB1. Therefore, since the load capacity of the main amplifier MA is reduced, this writing can be performed at high speed. During this writing, a plurality of memory cells connected to the selected word line Xi are also read in the DRAM cell unit 203.

Next, the signals SYL and Y1 are set to low level, and the signal SYR is set to high level. As a result, the refresh operation sense amplifier 521 is disconnected from the selected sense amplifier SA and connected to the DRAM cell unit 203. After that, the refresh operation sense amplifier 521
Writes the data held therein to the selected memory cell connected to the selected word line in the DRAM cell 203. Thus, the selected sense amplifier SA
And the corresponding data held in the DRAM cell unit 203 can always be matched.
During the write-back, the next memory access requests reading of the same data block or another data block, and if the memory access hits, the memory access is performed by the sense amplifier array holding the data block. It is executed in parallel with the write-back for 211.

According to the present embodiment, main amplifier MA
And the sense amplifier SA serve as a global data line, which has the effect of speeding up read misses. That is, a direct signal transmission path is formed from the memory cell to the main amplifier without passing through the sense amplifier cache. Therefore, as shown in a comparison between FIGS. 9 and 20, in the configuration of FIG. 13, the main amplifier can be activated by AMA almost simultaneously with the activation of the sense amplifier 502 by SR. At the time of a read hit, the sense amplifier cache unit 201 can operate as a cache at high speed because the global bit line portion belonging to the DRAM cell unit 203 can be separated by the switch circuit row 503L. Further, the sense amplifier cache unit 2
01 is used as a cache and the DRAM cell unit 20 is used for reading data held therein.
Since the three refresh operations can be performed in parallel, the period during which this memory cannot be accessed due to the refresh operation is reduced. Also, during a write operation, if a subsequent read access hits during a write back to the DRAM cell unit 203, the read access can be performed in parallel with the write back, so that the data is transferred to the selected sense amplifier SA. A decrease in the operating speed of the memory due to writing and subsequent write-back to the DRAM cell unit 203 can be effectively reduced.

<Modification of the Fourth Embodiment of the Invention> The sense amplifier cache unit 201 according to the fourth embodiment divides DRAM cells on the same word line into a plurality (four in FIG. 13) of sets and individually divides them. It is configured to be easy to handle. For example, at the time of a cache mishit, by setting only the signal Y1 to the high level, only one of the four data blocks stored by the plurality of memory cells connected to the same word line is latched in the cache, and the remaining data blocks are latched. May not be latched. That is, the block size can be made variable. This has the effect of setting the block size optimally according to the application and increasing the cache hit rate. In this case, FIG.
, It is essential that the cache tag 302 has 4 × 6 = 24 blocks.

FIG. 21 shows a circuit example of an SA / MA connection circuit for making the block size variable. The circuit includes signals A (N + 1) and A (N +
2) is given in addition to FIG. When A (N + 1) is at a high level, SY1 to SY6 are valid, but A1 and A2 are invalid. That is, for example, Y1 to Y4 are activated at the same time, and data of the memory cells on the same word line is exchanged with the sense amplifier cache as a group. When A (N + 1) is low and A (N + 2) is high, SY1-6 and A1 are valid but A2 is invalid. That is, for example, Y1 and Y2 are activated at the same time, and data is exchanged with the sense amplifier cache using the data of メ モ リ memory cells on the same word line as a group. When both A (N + 1) and A (N + 2) are at low level, all of SY1 to SY6, A1, and A2 are valid. That is, for example, only Y1 is activated, and the data of １ ／ memory cells on the same word line are grouped together.
Data is exchanged with the sense amplifier cache. The information of the memory cells not connected to the sense amplifier cache is written back by the refresh sense amplifier 521.

<Fifth Embodiment> In the first embodiment of the present invention, one sense amplifier array can be used as a cache for holding the same memory signal of each memory cell array 221. In the present embodiment, a set associative cache having a number of ways larger than two is provided. For this reason, in the present embodiment, each of the four memory cell arrays 221 has six sense amplifier arrays 2
The data read from each memory cell array 221 can be held by any of the sense amplifier arrays. Specifically, each memory cell array 221 is replaced with the direct mapping control circuit 330 (FIG. 7).
A circuit for determining the sense amplifier row to hold the data of the above-mentioned data on a predetermined basis is used. This circuit records the order in which the six sense amplifier arrays 211 were accessed in the past. Thereafter, if a mishit occurs for any of the memory accesses, one of the six sense amplifier rows is selected based on a predetermined reference. The most typical of such circuits is LRU (LeastRe
cent Used) circuit.

FIG. 22 shows a configuration of a cache controller using an LRU circuit. The set associative control circuit 2230 provided in place of the direct mapping control circuit of FIG. 7 includes four LRU circuits 22 corresponding to four rows of the cache tag 320 selected by A1 and A2.
10 are provided. The LRU circuit 2210 stores the latest use time of the sense amplifier group corresponding to each cache tag block 321, and belongs to the corresponding column of the plurality of cache tag blocks 321. Among the four cache tag blocks 321, one cache tag block 321 (the number of the recently used cache tag block) in which the sense amplifier group corresponding to the cache amplifier block has been used recently, the latest use time of the sense amplifier group, and Is stored. That is, every time a memory access that has a cache hit is executed, the address bits A1 and A2 of the memory access and the sense amplifier column select signals BY1,. ,
Or the cache tag block 32 selected by 6
The use time of the sense amplifier group corresponding to the cache block stored for 1 is updated. Also, the latest use time and the number of the recently used cache block of the sense amplifier array corresponding to the column to which the cache tag block 321 belongs are updated. The above-described operation at the time of a hit is controlled by the LRU information hit-time control circuit 2211 that receives the hit and the BY1 to BY6 signals. Thereafter, when a mishit is detected for any of the memory accesses and the miss signal supplied from the OR gate 324 goes high, the LRU
The circuit selects the sense amplifier row selection signals CY1,... CY,... At the time of mishit so as to select the sense amplifier row farthest away from access based on the latest use time stored corresponding to the six sense amplifier rows. , Or 6. The information of the LRU circuit is also rewritten correspondingly. The above-mentioned operation at the time of a mishit is controlled by the LRU information mishit control circuit 2212. Subsequent operation of the apparatus is the same as described above. Thus, 6
A way set associative cache is realized, and the cache hit rate is improved. By changing the number of sense amplifier rows 211, a cache with a way number other than 6 can be realized.

[0073]

According to the microcomputer of the present invention, the sense amplifier for the DRAM portion is a sense amplifier cache that can be used as a cache, so that there is no waste of space.

In particular, the sense amplifier cache portion is locally collected, and the local bit lines in the accessed memory cell array are connected to one sense amplifier row via global bit lines provided in common for a plurality of memory cell arrays. In this case, the sense amplifier cache portion is suitable for high-speed operation.

According to the embodiment of the present invention in which the bit lines of the on-chip DRAM are hierarchized and the cache controller is provided with the LRU circuit, any DRA
Since the M cell can select and connect one of the plurality of sense amplifiers, a set associative cache can be realized, and the cache hit rate is improved.

[Brief description of the drawings]

FIG. 1 is a schematic circuit block diagram of a semiconductor chip according to the present invention.

FIG. 2 is a schematic circuit block diagram of a DRAM cell unit in the device of FIG.

FIG. 3 is a schematic circuit block diagram of a memory cell decoder in the circuit of FIG. 2;

FIG. 4 is a schematic circuit block diagram of a sense amplifier cache unit in the device of FIG. 1;

FIG. 5 is a schematic circuit block diagram of a sense amplifier / memory cell array connection circuit in the device of FIG. 1;

FIG. 6 is a schematic circuit block diagram of a sense amplifier / main amplifier connection circuit in the device of FIG. 1;

FIG. 7 is a schematic circuit block diagram of a cache controller in the device of FIG. 1;

FIG. 8 is an operation waveform diagram at the time of a read hit of the device of FIG. 1;

FIG. 9 is an operation waveform diagram of the device of FIG. 1 at the time of a read error.

FIG. 10 is an operation waveform diagram at the time of writing of the device of FIG. 1;

FIG. 11 is a schematic circuit block diagram of another semiconductor chip according to the present invention.

FIG. 12 is a schematic circuit block diagram of still another semiconductor chip according to the present invention.

FIG. 13 is a schematic circuit block diagram of still another semiconductor chip according to the present invention.

FIG. 14 is a view for explaining the operation of the apparatus in FIG. 13;

FIG. 15 is a schematic circuit diagram of a microcomputer according to the related art.

FIG. 16 is a schematic circuit diagram of a conventional DRAM.

FIG. 17 is a diagram illustrating an example of a circuit configuration of a main amplifier.

FIG. 18 is a cross-sectional structure diagram of a memory cell.

FIG. 19 illustrates an example of a circuit configuration of a sense amplifier.

20 is an operation waveform diagram of the device of FIG. 13 at the time of a read error.

FIG. 21 is a schematic circuit block diagram of a sense amplifier / main amplifier connection circuit of the device of FIG. 13;

FIG. 22 is a schematic circuit block diagram of a cache controller in the device of FIG. 1;

[Explanation of symbols]

GBL1 / GBB1 global bit line pair, BL
1 / BB1 ... local bit line pair, DL1 ... data line

 ────────────────────────────────────────────────── ─── Continued on the front page (72) Inventor Nobuyoshi Kobayashi 1-280 Higashi Koigakubo, Kokubunji-shi, Tokyo Inside Central Research Laboratory, Hitachi, Ltd.

Claims (10)

[Claims] 1. A microcomputer having a CPU, and a dynamic random access memory (DRAM) accessed by the microcomputer.
The DRAM has at least one bit line, a plurality of memory cells connected to the bit line, and any one memory cell specified by a preceding data read access request from the microcomputer part. A data read circuit for reading the signal stored in the bit line, and a detection transfer circuit for detecting the signal read on the bit line and transferring the detected signal to the microcomputer portion Wherein the detection and transfer circuit is a plurality of sense amplifiers concentrated in the vicinity of the plurality of memory cells and arranged in a direction in which the bit lines extend. When it detects a signal read from one of the plurality of memory cells, it is configured to hold the detected signal. A first switch circuit for selectively connecting one of the plurality of sense amplifiers to the bit line; and a response to the preceding data read access request among the plurality of sense amplifiers. Selecting a first sense amplifier to detect a signal held in any one of the memory cells required by the data read access request,
In response to a subsequent data read access request from the microcomputer portion, a selection for selecting any second sense amplifier holding a signal stored in one of the memory cells specified by the request. A control circuit that controls the first switch circuit so as to connect the first sense amplifier to the bit line when the signal is read by the read circuit; and the preceding data read. In response to the access request, the signal detected by the first sense amplifier is read and transferred to the microcomputer part, and held in the second sense amplifier in response to the subsequent data read access request. A microcomputer having a data transfer circuit for reading the stored signal and transferring the read signal to the microcomputer portion. Computer. 2. The method according to claim 1, wherein the bit line includes a global bit line, a plurality of local bit lines arranged in a direction in which the global bit line extends, and the preceding data read request among the plurality of local bit lines. A second switch circuit for selectively connecting one local bit line to which the designated memory cell is connected to the global bit line, wherein the plurality of memory cells are divided into a plurality of memory cell arrays. A plurality of memory cells belonging to each memory cell array are connected to one of the plurality of local bit lines corresponding to the memory cell array; and the first switch circuit connects one of the plurality of sense amplifiers. 3. The microcomputer according to claim 2, further comprising a circuit selectively connected to said global bit line. 3. A refresh operation is performed on a memory cell read by the read circuit via the global bit line and the one local bit line connected to the global bit line by the first switch circuit. And a refresh sense amplifier connected to the global bit line.
The microcomputer as described. 4. The refresh operation sense amplifier,
The global bit line is disposed between the plurality of local bit lines and the plurality of sense amplifiers. A second portion located; a third portion located near the plurality of sense amplifiers; a third switch circuit for connecting the first and second portions; And a fourth switch circuit for connecting the first and second portions. The refresh operation sense amplifier is connected to the second portion. The first switch circuit connects one of the plurality of sense amplifiers. The second switch circuit is connected to the one local bit to which the memory cell read by the read circuit is connected. The microcomputer according to claim 3 comprising a line from the circuit for selectively connecting to said first portion. 5. The third switch circuit connects the first and second parts while the first sense amplifier detects the read signal and after the detection of the signal is completed. The refresh operation is performed by the refresh operation sense amplifier, and the fourth switch circuit controls the second and third portions while the first sense amplifier detects the read signal. 5. The microcomputer according to claim 4, wherein the second and third portions are separated while the refresh operation is performed by the refresh operation sense amplifier after the detection of the signal is completed. 6. In response to a data write request from the microcomputer, the selection circuit selects a third sense amplifier from which the write data designated by the request is to be written, from the plurality of sense amplifiers. The data transfer circuit has a circuit for writing the write data to the third sense amplifier, and the fourth switch circuit connects the second and third parts during the write, and The data is also written to the refresh operation sense amplifier, and after the completion of the writing to the third sense amplifier, the second and third portions are separated from each other. During the writing to the amplifier, the first and second portions are separated, and after the writing is completed, the first and second portions are connected, and the The microcomputer according to claim 4, wherein the writing of the write data into the memory cell to be executed by the sense amplifier the refresh operation Taraito request specifies. 7. A data transfer circuit comprising: a data line provided near the plurality of sense amplifiers; and a third switch for selectively connecting one of the plurality of sense amplifiers to the data line. The control circuit, when the data transfer circuit reads out the signal detected by the first sense amplifier in response to the preceding data read access request, The third switch circuit is controlled so as to selectively connect an amplifier to the data line, and in response to the subsequent data read access request, the signal held by the second sense amplifier is transmitted to the data line. When the transfer circuit reads, the third switch circuit is controlled so as to selectively connect the third sense amplifier to the data line. A main amplifier connected to the data line, for responding to each of the preceding data read request and the subsequent data read request, detecting a signal on the data line, and transmitting the detected signal to the microcomputer portion. The microcomputer according to claim 2, further comprising: 8. The global bit line comprises: a first portion located near the plurality of local bit lines; a second portion located near the plurality of sense amplifiers; And a third switch circuit for connecting to the second portion, wherein the data transfer circuit is connected to the second portion, detects a signal on the second portion, and outputs the detected signal to the second portion. A main amplifier for sending the signal to a microcomputer portion, wherein the third switch circuit responds to the subsequent data read access request, and the first and second switch circuits read the signal when the read circuit reads the signal. In response to the subsequent data read access request, and when the data transfer circuit reads a signal stored in a memory cell designated by the request from the third sense amplifier. The first microcomputer according to claim 2, wherein separating the second portion. 9. The selection circuit records the history of the selected sense amplifier every time each of the plurality of sense amplifiers is selected, and stores the history when the new sense amplifier is selected. 2. The microcomputer according to claim 1, further comprising a circuit for selecting the new sense amplifier based on the signal. 10. The microcomputer according to claim 9, wherein the circuit for recording and selecting the history comprises a circuit for selecting a sense amplifier that has not been selected recently.