JP3348520B2 - Memory circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory circuit such as a DRAM provided with a circuit for initially setting a bit line potential.

[0002]

2. Description of the Related Art FIG. 5 is a circuit diagram showing a configuration example of a conventional DRAM array. In FIG. 5, BL0 and BL
0B to BL7 and BL7B are bit line pairs, WL is a word line, Φ ₁ is a mat select signal, Φ _WL is a word signal,
Φ _SE is a sense amplifier enable signal, Φ _2a , Φ _2b ,
Φ _2c , Φ _2d are column select signals, 1 is a precharge transistor group, 2 is an equalize transistor group, 3
Denotes a memory cell group, 4 denotes a sense amplifier (S / A) driver, 5 denotes a sense amplifier (S / A) group, and 6 denotes a column select transistor group.

Each bit line pair BL0 and BL0B-BL
One end of 7 and BL7B is connected to the supply line of the precharge voltage V _R, the sense amplifiers 50 to 57 of the sense amplifier group 5 is connected to the other end. The N-channel MOS transistors 10a to 17a and 10b to 17b of the precharge transistor group 1 are inserted and connected to the bit lines BL0 to BL7 and BL0B to BL7B. In addition, each bit line pair BL0 and BL
0B to BL7 and BL7B, N channel MOS transistors 20 to 27 of equalizing transistor group 2
Are connected respectively. Then, each N-channel MOS transistor 10 of the precharge transistor group 1
A～17a, the gates of 10B～17b, and the gates of N-channel MOS transistors 20 to 27 of the equalizing transistor group 2 is connected to the supply line of the mat select signal [Phi _1. Also, each bit line BL0
To BL7 (BL0B to BL7B) and the word line WL are connected to the memory cells 30 to 37 of the memory cell group 3.

The sense amplifier driver 4 outputs clock signals SAH and SAL in response to the input of the signal Φ _SE . Output lines of these clock signals SAH and SAL are connected to sense amplifiers 50 to 57. Further, a pair of N-channel MOS transistors 60a and 60b, 61a is provided for each of sense amplifiers 50 to 57.
And 61b, 62a and 62b, 63a and 63
b, 64a and 64b, 65a and 65b, 66a
And 66b, 67a and 67b are connected in parallel, respectively. And transistors 60a and 60
The gates of b, 64a and 64b are connected to a supply line for a column select signal Φ _2a , and the gates of transistors 61a and 61b, 65a and 65b are connected to a supply line for a column select signal Φ _2b.
The gates of a and 62b, 66a and 66b are connected to the supply line of the column select signal Φ _2c , and the gates of the transistors 63a and 63b, 67a and 67b are connected to the supply line of the column select signal Φ _2d .

[0005] In such a configuration, the access of the memory cell is mat select signal [Phi ₁ is set to the high level, the transistors 10a~17a precharging transistor group 1, 10B～17b, and equalizing transistor group 2 are held in the ON state, and the respective bit lines BL0 to BL7, BL
0B to BL7B are precharged to the precharge voltage V _R , and are simultaneously equalized. In this way, the precharging and equalizing operations of the bit lines are performed uniformly and simultaneously.

Next, the mat select signal Φ ₁ is switched to the low level, and the precharge transistor group 1
Transistors 10a to 17a, 10b to 17b, and each transistor 2 of the equalizing transistor group 2.
0 to 27 are turned off, and each bit line BL
In a state where 0 to BL7 and BL0B to BL7B are held in a floating state, the word signal Φ _WL is set to a high level, and data is read.

As a result of data reading, each bit line pair BL
The minute potential differences appearing between 0 and BL0B to BL7 and BL7B are amplified by the sense amplifiers 50 to 57 that have received the clock signals SAH and SAL by the sense amplifier driver 4. Then, read data from the selected sense amplifiers 50 and 54, 51 and 55, 52 and 56, and 53 and 57 are transferred to an output circuit (not shown) in response to the column select signals Φ _{2a to} Φ _2d set to the high level. You.

[0008]

Incidentally, in the write operation in the above-described circuit, like a so-called "flash write" operation of a dual port memory,
When writing data uniformly to the selected word line, there is also a method of transferring the write data to the bit line before the sense amplifier operation, but when writing data to the bit line specified by the normal column address, It is necessary to transfer the write data to the bit line after the sense amplifier operates sufficiently and the data is sufficiently amplified. This is because, if data is transferred before the sense amplifier operates sufficiently, crosstalk will adversely affect adjacent non-selected bit lines whose distance has been reduced due to integration, and the margin will be lost, or in the worst case This causes a malfunction. Therefore, when writing inverted data, the data latched by the sense amplifier must be inverted.

Therefore, in a serial access memory such as an image memory which needs to transfer a large number of data at a time, it is necessary to invert a large number of latched data at a time during a write operation. For this reason, the charge / discharge current and the accompanying noise are large, causing a problem that the operation of the sense amplifier itself is adversely affected, or the performance goes down to other circuits to deteriorate the performance.

As a countermeasure against the noise, the sense amplifier driver signal wiring and the power supply and ground connected thereto may be strengthened. However, if a pair of sense amplifier drivers are arranged on one mat, it is required to perform one operation. As the number of bit line pairs selected at one time in the access increases, the noise in the mat increases, so the number of data transferred in one mat may be reduced. However, in this case, for example, when the circuit of FIG. 5 is used, one mat has 1024 bit line pairs, and the number of data required for one transfer is 64 × 8.
(512 bits), a desired number of data cannot be obtained unless two mats, that is, 2048 bit line pairs are operated. Since the power consumption of the DRAM is mainly due to the charging and discharging of the bit line pair, the power consumption of the entire chip increases due to the increase in the charging and discharging power of the bit line in addition to the power consumption due to the data inversion. . It is also considered effective to disperse the current flow by increasing the number of mat divisions, but in this case, the chip size increases accordingly.

Further, when the number of data to be transferred at one time is reduced, the number of times of accessing the DRAM is eventually increased, the power consumption is increased, and the cycle of the DRAM needs to be set small. The designer considers these trade-offs when designing, but must sacrifice any of power consumption, chip size, and operation margin. As described above, if the write data can be transferred before the sense amplifier operates, the above-described problem can be avoided, but it has not been solved at present.

The present invention has been made in view of the above circumstances, and an object of the present invention is to prevent the influence of crosstalk between bit lines in write data transfer before a sense amplifier operation, to reduce noise during writing, An object is to provide a memory circuit which can reduce power consumption.

[0013]

To achieve the above object, according to an aspect of the present invention is a memory circuit having a plurality of sense amplifiers the bit line is connected, from the plurality of bit lines of at least one bit line is divided into a plurality of bit line groups consisting, a setting circuit for initializing the bit line potential to each bit line group, the initial setting of the bit line potential by the setting circuit
Operation is stopped at different timings for each bit line group.
And write data to one bit line group
The initial setting operation for one bit line group
Stop before the initial setting operation for the bit line group of
Before the initial setting operation for other bit lines is stopped
Transfer write data to one bit line group
After that, the multiple sense amplifiers are
And a circuit that operates at times .

In the present invention , the plurality of bit lines
Should be in the same group every other in the column direction.
It is divided into two and selected for each group.

[0015]

According to the present invention, the bit potential is initially set for each bit line group by the setting circuit. Then, for example, when writing data to one bit line group,
The initial setting operation for one bit line group is stopped before the initial setting operation for another bit line group. Then, before the initial setting operation for the other bit line groups is stopped,
Write data is transferred to one bit line group.
That is, before the sense amplifier operation, transfer of write data to a desired bit line group is performed.

[0016]

FIG. 1 is a circuit diagram showing an embodiment of a memory circuit according to the present invention. In FIG. 1, the same components as those in FIG. That is, BL0 and B
L0B to BL7 and BL7B are bit line pairs, WL is a word line, Φ _1a and Φ _1b are mat select signals, Φ _WL is a word signal, Φ _SE is a sense amplifier enable signal, Φ _2a and Φ _2
2b is a column select signal, 1a and 1b are precharge transistor groups, 2 is an equalize transistor group, 3
Denotes a memory cell group, 4 denotes a sense amplifier (S / A) driver, 5 denotes a sense amplifier (S / A) group, and 6 denotes a column select transistor group.

The precharge transistor group 1a includes bit line pairs BL0 and BL0B,
BL2 and BL2B, BL4 and BL4B, BL6
And N channel MOS transistors 10a, 10b, 12a, 12b, 14a, 1 inserted and connected to BL6B.
4b and 16a, 16b. Further, these transistors 10a, 10b, 12a, 12
b, 14a, 14b and 16a, the gate of 16b are connected to the supply line of the mat select signal [Phi _1a.

The precharge transistor group 1b includes bit line pairs BL1 and BL1B,
BL3 and BL3B, BL5 and BL5B, BL7
And N channel MOS transistors 11a, 11b, 13a, 13b, 15a, 1 inserted and connected to BL7B.
5b and 17a, 17b. Further, these transistors 11a, 11b, 13a, 13
b, 15a, 15b and 17a, the gate of 17b are connected to the supply line of the mat select signal [Phi _1b.

In each of the transistors 20 to 27 of the equalizing transistor group 2, every other bit line pair BL0 and BL0B, BL2 and BL2
N-channel MOS transistors 20, 22, connected between B, BL4 and BL4B, BL6 and BL6B.
24, 26 of the gate is connected to the supply line of the mat select signal [Phi _1a. On the other hand, every other bit line pair BL1 and BL1B, BL3 and BL3B, BL5 and BL5B, BL7 and BL7
N-channel MOS transistor 21 connected between B
Gate of 23, 25 and 27 are connected to the supply line of the mat select signal Φ _1b.

Further, in this embodiment, two column selection signals Φ _2a and Φ _2b are used. The supply line of the column select signal Φ _2a is connected to the gates of the N-channel MOS transistors 60a and 60b, 62a and 62b, 64a and 64b, 66a and 66b which form a pair of the column select transistor group 6. On the other hand, the supply line for the column select signal Φ _2a is connected to N-channel MOS transistors 61a and 61b, 6
3a and 63b, 65a and 65b, 67a and 67b.

As described above, in the present embodiment, the bit line pairs BL0 and BL0B to BL7 and BL7B are divided into two groups so as to be the same group every other in the column direction, and each group is selected. It is configured as follows.

FIG. 2 shows the mat select signal Φ shown in FIG.
Configuration Example of a generation circuit _1a and [Phi _2b is a circuit diagram showing an.
In FIG. 2, reference numeral 101 denotes a two-input NOR circuit;
5 is an inverter, 106 and 107 are 3-input NAND circuits,
108 and 109 are two-input NAND circuits, IWE is a control signal, Φ ₁ is a mat select signal output from the row decoder upon address determination, and Φ _1D is a delay mat select obtained by delaying the mat select signal Φ ₁ by, for example, about 10 nsec. Signals CAa and CAb indicate column select address signals, respectively.

The control signal IWE is fixed at a high level during a write operation, and is fixed at a low level during a read operation or a refresh operation. The address signals CAa and CAb correspond to the DRs for which the internal addresses are determined.
During the access period of the AM, one of the selected ones becomes a high level.

In the configuration shown in FIG.
If the address signal CAa is selected during operation,
Mat select signal Φ_1aIs the input mat select signal
No.Φ ₁Are output at the same timing as. On the contrary,
Generated mat select signal Φ_1bIs a delay mat select
Signal Φ_1DSignal delayed by the delay time set in
Output. Further, the address signal CAb is selected.
The opposite is the case. In addition, during read operation or refresh
During the operation, the mat select signal Φ_1a, Φ _1bBoth delayed
Mat select signal Φ_1DIt operates at the timing of.

FIG. 3 is a block diagram showing a configuration example of an address control system of the DRAM. In FIG.
1 is an address controller, 202 is a row decoder, 2
03 is a column decoder, 204 is a delay circuit, 205 is a word signal (Φ _WL ) generator, 206 is a column selector, 207 is a sense amplifier (S / A) controller,
08 indicates a reset controller.

In the circuit of FIG. 3, a DRAM request is input to address controller 201, for example, RA
When S becomes inactive, a predetermined signal is output from the address controller 201 to the row decoder 202 and the column decoder 203. Row decoder 202
Then, a mat select signal Φ ₁ is generated based on the input signal, and is output to the mat select signal generation circuit shown in FIG. 2 and to the delay circuit 204 and the column selector 206. Mat select signal [Phi ₁ input to the delay circuit 204 receives the delayed action of the order of 10n seconds, delay mat select signal [Phi _1D matting select signal generating circuit and a word signal generator of FIG. 2 20
5 is output.

In the word signal generator 205, the word signal Φ _WL is generated based on the input of the delay mat select signal Φ _1D , applied to the word line WL in FIG. 1, and the word signal Φ _WL is generated. Is output to the sense amplifier controller 207. here,
The setting of the rising timing of the word signal Φ _WL is set with more margin since all precharge and equalizing operations are stopped at the falling timing of the delay mat select signal Φ _1D. do it.

In the sense amplifier controller 207,
According to the signal input by the load signal generator 205.
Amplifier enable signal Φ_SEIs generated and the sensor of FIG.
It is output to the amplifier driver 4. Also sense amplifier
Sense amplifier enable signal from controller 207
Φ _SEA signal indicating that the data has been generated and output is
206 and the reset controller 208
You.

The column decoder 203 receiving the output signal of the address controller 201 generates column select address signals CAa and CAb.
And output to the column selector 206. In column selector 206, the address signals CAa and CAb, mat select signal [Phi _1, the output signal of the sense amplifier controller 207, and the control signal column select signal [Phi _2a and [Phi _2b based on input IWE is generated, the column of Figure 1 Output to the select transistor group 6.

The column selector 206 outputs a column select signal Φ _2a when the address signal CAa from the column decoder 203 is at a high level, and outputs a column select signal Φ when the address signal CAb is at a high level.
_2b is output. The timing of the column select signals Φ _2a and Φ _2b is set so that, during the write operation, one of the mat select signals Φ _{1a and} Φ _1b is turned off (falls) at the timing of the mat select signal Φ ₁ and then delayed. The one-shot pulse is set to be output until the other is turned off (falls). In the case of a read operation, a setting is made such that a one-shot pulse is output after the sense amplifier sufficiently amplifies data and before the word signal Φ _WL is reset.

Next, the write and read operations of the above configuration will be described with reference to the timing chart shown in FIG. First, the write operation will be described. In addition,
Here, it is assumed that the column select address signal is a write cycle in which CAa is selected, and the control signal IWE is at a high level. In addition, the mat select signals Φ _1a and Φ _1b are set to the high level, and the transistors 10 of the precharge transistor groups 1a and 1b are set.
a to 17a, 10b to 17b, and the transistors 20 to 27 of the equalizing transistor group 2 are held in the ON state, and the bit lines BL0 to BL7, BL0B to B
L7B is assumed to be precharged to the precharge voltage V _R.

[0032] In this state, when the address is determined, the mat select signal [Phi ₁ is switched to the low level, it switches to the low level mat select signal [Phi _1a at the timing of the fall. Thereby, the bit line pair BL0
The precharge and equalize operations for BL0B, BL2 and BL2B, BL4 and BL4B, BL6 and BL6B are stopped.

[0033] Since the column select signal [Phi _2a selected by the column select address signals CAa in this state becomes the rising high level, the column select transistor group 6 N-channel MOS transistors 60a, 6
0b, 62a, 62b, 64a, 64b, 66a, 66
b is turned on, and the write data is transferred to the bit line. At this time, the unselected adjacent bit line pair BL1
And BL1B, BL3 and BL3B, BL5 and BL5B, BL7 and BL7B are equalized, it is yet remain clamped to the precharge voltage V _R.

Then, at the falling timing of the delay mat select signal Φ _1D , the column select signal Φ _2a falls, that is, the column select signal Φ _2a rises after having a width which is a one-shot pulse. Thereafter, by switching to low transition Standing mat select signal [Phi _1b, the bit line pair BL1 and BL1
B, BL3 and BL3B, BL5 and BL5B, B
The precharge and equalize operations for L7 and BL7B are stopped. That is, at this time, the precharge and equalizing operations for all the bit line pairs are stopped, and all the bit lines BL0 to BL7 and BL0B to BL7B enter a floating state.

All the bit lines BL0-BL7,
With BL0B to BL7B floating,
The word signal Φ _WL rises and is applied to the word line WL at a high level, so that data reading from the memory cells 30 to 37 is performed. At this time, bit line pairs BL0 and BL0B, BL2 and BL2B, BL4 and BL4B, BL6 and BL6 belonging to the set of address signals CAa
Since the write data has already been transferred to B, the potential fluctuation due to the data in the memory cells 30, 32, 34, and 36 is much smaller than the potential fluctuation due to the transferred write data. The bit line pair BL1 and BL1B, BL3 and BL3 of the set of the address signal CAb
A small potential difference appears in B, BL5 and BL5B, BL7 and BL7B as in normal reading.

Next, when the sense amplifier enable signal Φ _SE is set to the high level, the signals SAH and SAL are output from the sense amplifier driver 4 and the sense amplifiers 50 to 57 are controlled to operate. As a result, the write data is directly amplified by the sense amplifiers 50 to 57, and the word signal Φ _WL is switched to the low level together with the unselected data, so that the data is stored in the memory cells 30 to 57.
37 is restored.

Next, the read operation will be described. In this case, it is assumed that the control signal IWE is at the low level in the read cycle in which CAa is selected, as in the above-described write operation, for the column select address signal.

[0038] In this state, when the address is determined, is switched mat select signal [Phi ₁ is the low level, cut further into the mat select signal [Phi _1a and [Phi _1b are low level at the falling timing of the delayed mat select signal [Phi _1D Be replaced. As a result, the precharge and equalizing operations for all the bit line pairs are stopped, and all the bit lines BL0 to BL7 and BL0B to BL7B enter a floating state.

As in the write cycle described above, all the bit lines BL0 to BL7, BL0B to BL7 in the mat are
With B floating, the word signal Φ _WL rises and is applied to the word line WL at a high level,
Reading of data from the memory cells 30 to 37 is performed.
Next, when the sense amplifier enable signal Φ _SE is set to a high level, the signals SAH and SAL are output from the sense amplifier driver 4 and the sense amplifiers 50 to 57 are output.
Is controlled to the operating state, and the read data is amplified.

[0040] When the data has been sufficiently amplified, it raised a column select signal [Phi _2a selected by the address signal CAa, read data is read outside, for example, a latch circuit and the amplifier circuit, and the like. When the data transfer is completed, switches are lowered a column select signal [Phi _2a to a low level, where the potential of the bit line is sufficiently stable, and to fall the word signal [Phi _WL, data memory cell 30 37 is restored.

As described above, according to the present embodiment,
Bit line pair BL0 and BL0B to BL7 and BL7
B is divided into two groups so that every other group becomes the same group in the column direction and is selected in each group unit. Therefore, in the write data transfer before the sense amplifier operation,
The effect of crosstalk between bit lines can be prevented. Also,
Since the inversion of the latch is not performed, noise reduction at the time of writing and power consumption can be reduced. Further, since the degree of freedom in the chip configuration increases, the chip size can be reduced. Further, in the write operation, data is transferred to the floating bit line, so that there is a margin in the operation margin. Therefore, the present circuit is suitable for an image memory such as a dynamic memory which needs to be configured to transfer a large number of data at once. In recent years, DRAMs have been incorporated into ASICs,
As the capacity increases, such AS
It can also be used in ICDRAM.

This configuration essentially delays the equalizing and precharging timings of the bit lines. With respect to the design of other sequential circuits, the delay after the rise of the word lines is sequentially delayed. Only good. In addition, although the cycle time becomes longer by adding the delay,
If the speed is not pursued like a general-purpose DRAM, it can sufficiently cope. Further, the circuit area can be realized only by a signal line for a newly added mat select signal, the circuit shown in FIG. 2, and the delay circuit of FIG. 3, so that the circuit area does not become so large.

[0043]

As described above, according to the present invention,
Since the write data can be transferred to the bit lines before the operation of the sense amplifier, the influence of crosstalk between the bit lines can be prevented. In addition, since the inversion of the latch is not performed, noise reduction at the time of writing and power consumption can be reduced. Further, since the degree of freedom in the chip configuration is increased, the chip size can be reduced, and there is a margin in the write operation margin. Therefore, it is suitable for an image memory such as a dynamic memory which needs to be configured to transfer a large number of data at once.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing one embodiment of a memory circuit according to the present invention.

FIG. 2 is a circuit diagram showing a configuration example of a mat select signal generation circuit shown in FIG. 1;

FIG. 3 is a block diagram illustrating a configuration example of an address control system of a DRAM.

FIG. 4 is a timing chart for explaining the operation of the circuit of FIG. 1;

FIG. 5 is a circuit diagram showing a configuration example of a conventional DRAM array.

[Explanation of symbols]

BL0 and BL0B to BL7 and BL7B bit line pair WL word line Φ _1a , Φ _1b mat select signal Φ _WL … word signal Φ _SE … sense amplifier enable signal Φ _2a , Φ _2b Charge transistor group 2 ... Equalize transistor group 3 ... Memory cell group 4 ... Sense amplifier driver 5 ... Sense amplifier group 6 ... Column select transistor group 101 ... 2-input NOR circuit 102-105 ... Inverter 106,107 ... 3-input NAND Circuits 108, 109 2-input NAND circuit IWE Control signal Φ ₁ Mat select signal Φ _1D Delay mat select signal CAa, CAb Column select address signal 201 Address controller 202 Row decoder 203 Column decoder 204 Delay Circuit 2 5 ... word signal generator 206 ... column selector 207 ... sense amplifier controller 208 ... Reset Controller

Claims (2)

(57) [Claims] 1. A memory circuit having a plurality of sense amplifiers to which bit lines are connected, wherein the plurality of bit lines are divided into a plurality of bit line groups each including at least one bit line. A setting circuit for initially setting the bit line potential, a circuit for stopping the initial setting operation of the bit line potential by the setting circuit at a different timing for each bit line group, and writing data to one bit line group. If you do
The initial setting operation for one bit line group is stopped before the initial setting operation for another bit line group, and writing is performed for one bit line group before the initial setting operation for another bit line group is stopped. A circuit for simultaneously operating the plurality of sense amplifiers by addressing after transferring data. 2. The memory circuit according to claim 1, wherein the plurality of bit lines are divided into two so as to be in the same group every other in the column direction, and are selected for each group.