JPH0521724A - Semiconductor integrated circuit device and its manufacture - Google Patents

Abstract

PURPOSE:To provide a structure of a semiconductor integrated circuit device having high speed and large capacity suitable for high integration and a method for fabricating the same. CONSTITUTION:On a P-type semiconductor substrate 1 for example with an integrated circuit including a bipolar transistor formed, an N+ buried layer 2 has been formed in advance. A plurality of trenches 9 reaching the layer are formed to provide a capacitor K of an HSPC cell and a plate electrode extracting terminal D therein, so that the layer is used as a plate wire. A MOS structure process can be implemented in a bipolar process with good balance.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a highly integrated semiconductor integrated circuit device, and more particularly to a high speed and large capacity semiconductor integrated circuit device having a bipolar transistor and a method for manufacturing the same.

[0002]

2. Description of the Related Art MOSFET (metal-oxide-semiconduc)
A device having a tor field effect transistor as a constituent element (hereinafter referred to as a MOS device) is a main technology used for an LSI such as a memory or a microprocessor. In MOS devices, high density and high integration have been advanced due to miniaturization, and as a result, high speed performance has been improved. However, if higher speed is required, it is effective to coexist a bipolar device. From this point, for example, complementary MO
Bi-polar CMOS device (Bi-CMOS) that has high integration and low power consumption of S device (CMOS device) and high driving power and high speed of bipolar device
Device) is a realistic and effective technology developed to give LSI multi-functionality. In order to realize a high-performance device, a high current amplification factor for maintaining a high driving force, a high cutoff frequency for maintaining a high speed, and a high output speed It is necessary to secure a low collector resistance in order to maintain a large current. As the process, a bipolar device and a CMOS device can be formed at the same time by adding a part of a MOS process to a normal bipolar process. For example, high precision analog processing and high power drive. It is a technology that enables a bipolar circuit, which is good at high performance, and a CMOS circuit, which is highly integrated and advantageous for low power consumption, to be mounted on the same chip. However, if the process of the MOS device and the process of the bipolar device are simply applied to one semiconductor substrate, the number of manufacturing steps increases, and in order to efficiently manufacture the Bi-MOS device, both processes coexist. A well-balanced manufacturing technology is required.

On the other hand, a semiconductor memory, which is one of the MOS devices as described above, such as a dynamic RAM, is
In three years, the capacity has been increased by four times the speed, and various tevice structures have been proposed for that purpose. These are 2
One is a trench capacitor cell that forms a capacitor inside a silicon substrate, and the other is a stacked capacitor cell that is formed in the surface region of the substrate. In addition, various measures have been taken for each capacitor in order to further increase the capacity.
One of them is the HSPC cell (Half-V _CC Seath-Plate Cap.
acitorCell) (International Electron Devices
See Meeting 1987 Technical Digest p.332). In this cell, the lower electrode of the capacitor formed in the trench is used as a plate, and the plate of each cell is contacted with a buried n ⁺ layer formed in a silicon substrate in a mesh shape to give a plate potential. . This cell is
The storage node is classified into the above trench capacitor cell, and the storage node is insulated from the silicon semiconductor substrate by the insulating film. Therefore, the leakage current between the trenches is low and it is resistant to high alpha particles. The manufacturing process of this cell is as follows. First, a trench having a depth of about 3 μm is formed at the LOCOS end of the silicon substrate surface, and then a CVDSiO ₂ film is deposited on the substrate surface.
This is etched by RIE or the like to form Si on the sidewall of the trench.
Cover the O ₂ film. Then, SiO on the inner wall surface of the trench
₂ Polysilicon is deposited on the film and phosphorus is doped by the gas diffusion method. By this doping, a wiring made of a buried N ⁺ layer (hereinafter referred to as N ⁺ wiring) is formed at the bottom of the trench. This surface is then oxidized after forming a polysilicon storage node. The inside of the oxidized storage node is filled with polysilicon to form a capacitor.
In this method, the buried N ⁺ wiring is formed by diffusion from each trench, and each N ⁺ layer is joined to complete.

By the way, in semiconductor memories such as dynamic RAM, there is an increasing demand for higher speed in parallel with the increase in capacity. Bi-CMOS is one method for increasing the speed.
Memory (see 1990 Simposium on TechnologyDigest p.79). This example is applied to the static RAM, but if it is applied to the dynamic RAM, the following manufacturing process is performed. A collector of a bipolar transistor is formed on a silicon substrate, a well required for CMOS and an element isolation region are sequentially formed, and then a capacitor required for a memory cell is formed. Further, MOSFETs necessary for the CMOS circuit and the memory cell are formed, and at the same time, the emitter and the base of the bipolar transistor are formed. Next, a bit line is formed and then a wiring layer is formed to complete a Bi-CMOS dynamic RAM. As described above, the respective elements required for the CMOS and the bipolar are sequentially formed, so that the number of steps is increased. That is, conventionally, the bipolar technology and the MOS such as CMOS are used.
The technology was applied to the semiconductor substrate without any connection, and no attempt was made to combine the two technologies when applying them.

[0005]

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention As mentioned above,
In forming conventional HSPC cells, pre - the buried N ⁺ layer becomes DOO wire forms a respective N ⁺ layer by diffusion from the trench in which the capacitor is to be formed,
These N ⁺ layers were formed by bonding them to each other. But,
Each trench formed was small N ⁺ layer region area larger by joining pre - to form the door wiring is must not approach somewhat between the trenches, in practice, by the layout, adjacent N ⁺ layer May be too far apart to join. Conventionally, in such a case, a dummy trench was formed to complete the joining of the respective layers, but this also reduces the degree of freedom in layout and hinders high integration. Furthermore, in order to lead the embedded plate wiring to the surface of the semiconductor substrate, the trench is also used. In order to form the plate wiring, the N ⁺ layer is formed only on the bottom of the trench, but in this case, the N ⁺ layer continued from the bottom is also formed on the side surface of the trench, and this portion is led to the surface of the semiconductor substrate. It is used as a terminal. Since the peripheral portion of the trench is also used as a terminal as described above, there is a problem that the degree of freedom in layout is reduced. Moreover, even if a Bi-CMOS structure is introduced in order to increase the capacity and speed of a semiconductor integrated circuit device including a MOS device, each element necessary for a MOS and a bipolar is formed in order. Therefore, there has been a problem that the number of steps increases and the cost reduction is hindered. Further, in forming the bipolar element, the high-concentration impurity diffusion layer connected to the buried layer was used as a means for connecting the collector electrode formed in the buried layer to the wiring on the surface of the semiconductor substrate.
Since this diffusion layer occupies a relatively large area of the semiconductor substrate, it has been one of the factors that hinder the miniaturization of the device. The present invention has been made under such circumstances, and an object thereof is to provide a structure of a high-speed and large-capacity semiconductor integrated circuit device suitable for high integration and a manufacturing method thereof.

[0006]

In order to achieve the above-mentioned object, a semiconductor integrated circuit device of the present invention comprises a semiconductor substrate, a buried high-concentration impurity diffusion layer formed inside the semiconductor substrate, and the surface of the semiconductor substrate. A plurality of capacitors formed in the trench reaching the buried high-concentration impurity diffusion layer from the surface of the semiconductor substrate to the buried high-concentration impurity diffusion layer from the surface of the semiconductor substrate. And a plate electrode lead-out terminal formed of two conductive layers. The capacitance of the capacitor in the trench uses a capacitor insulating film or a junction capacitance, and the capacitor insulating film is a SiO ₂ film or a Si 3 film.
N4 film may be selected from metal oxide film and a composite film thereof, such as the Ta ₂ O ₅ film. Also, a semiconductor substrate, at least one buried high-concentration impurity diffusion layer formed inside the semiconductor substrate, and a bipolar transistor formed in the semiconductor substrate and having the buried high-concentration impurity diffusion layer as a collector electrode. A plurality of capacitors formed on the semiconductor substrate and having the buried high-concentration impurity diffusion layer as a plate wiring;
It is a feature of. The collector electrode is connected to a collector electrode lead terminal formed in a trench reaching from the surface of the semiconductor substrate to the buried high-concentration impurity diffusion layer, and the capacitor is formed from the surface of the semiconductor substrate to the buried high-concentration impurity diffusion layer. Is formed in the trench reaching to. Further, the method for manufacturing a semiconductor integrated circuit device of the present invention comprises the step of forming at least one buried high-concentration impurity diffusion layer of a conductivity type different from that of the semiconductor substrate in a desired region inside the semiconductor substrate, Forming a plurality of trenches from the surface of the semiconductor substrate to reach the buried high-concentration impurity diffusion layer, forming a capacitor in the trench, and using a plate electrode of the capacitor as a plate wiring. And a step of contacting the high-concentration impurity diffusion layer with the trench.
A step of forming a lead electrode lead terminal and bringing the plate electrode lead terminal into contact with the plate wiring; and a bipolar transistor having the buried high concentration impurity diffusion layer as a collector electrode on the semiconductor substrate. Forming process,
Forming a collector electrode lead terminal in the trench and bringing the collector electrode lead terminal into contact with the collector electrode. In the step of forming the capacitor in the trench, the capacitor insulating film may be formed in all the trenches provided in the semiconductor substrate.

[0007]

By using the buried high-concentration impurity diffusion layer formed beforehand in the semiconductor substrate as the plate wiring of the capacitor, it is not necessary to provide a dummy trench, and the plate electrode connected to this plate wiring is eliminated. By forming the lead terminal with two conductive layers in the trench, the trench of the capacitor and the trench of this terminal can be formed in the same step. Further, the buried high-concentration impurity diffusion layer is used as the plate wiring of the capacitor in the semiconductor substrate and the collector electrode of the bipolar transistor, and the trench formed in the semiconductor substrate is used as the extraction terminal of the collector electrode to improve the high speed operation. Effectively integrates the bipolar transistor having the above structure, and significantly improves high integration. In addition, semiconductors such as a trench used as a collector electrode lead-out terminal of a bipolar transistor, a trench used as a lead-out terminal of a plate electrode of a capacitor connected to a buried high-concentration impurity diffusion layer, a trench in which a capacitor is formed, etc. By providing an insulating film on all the trenches in the substrate, it is possible to prevent the manufacturing process from becoming complicated.

[0008]

Embodiments of the present invention will be described with reference to FIGS. FIG. 1 is a sectional view showing an essential part of an HSPC cell according to an embodiment of the present invention. The wafer is composed of a P-type silicon semiconductor substrate 1 and a P-type silicon epitaxial layer 3 grown on the P-type silicon semiconductor substrate 1, and an N ⁺ buried high-concentration impurity diffusion layer 2 (hereinafter referred to as N ⁺ buried layer) between them. )
Are formed in plural. In the epitaxial layer 3, a MOS transistor and a capacitor K that form a dynamic RAM cell are formed. In this MOS transistor, an LDD spacer 24 is provided on the side of the N-type polysilicon gate electrode 22 formed via the gate insulating film 21. The N ⁻ diffusion layer 23 serving as a source and a drain is formed in the epitaxial layer 3, and the drain is an N ⁻ diffusion layer directly connected to the N type polysilicon film 18 of the capacitor K formed in the trench. Includes 19. In the trench 9 in which the capacitor K is formed, an oxide film 10 is formed on the side walls except the bottom side, and an N-type polysilicon film 11 is formed on the surface and the bottom side.
On this polysilicon film 11, an insulating film 13 which serves as a dielectric of the capacitor is formed. Since the polysilicon film 11 is not formed near the entrance of the trench 9, the insulating film 13 near this is formed on the oxide film 10. The insulating film 13 has a bag shape because it is formed on the side wall and the bottom of the trench 9, and the N-type polysilicon film 14 is filled therein. Further, the above-mentioned N-type polysilicon film 18 is provided thereon. The surface of the polysilicon film 18 is covered with an oxide film 20. The capacitor K in the trench 9 is composed of an insulating film 13 and N-type polysilicon films 11 and 1 which are electrodes facing each other via the insulating film 13.
It consists of four. Since the polysilicon film 11 is in contact with the N ⁺ buried layer 2, this buried layer 2 is used as a plate wiring.

Although only one trench in which a capacitor is formed is shown in the figure, a plurality of capacitor trenches are actually provided, and all of them use the N ⁺ buried layer 2 as a plate wiring. . Therefore, the plate electrodes of each cell are connected together. A constant potential of 1/2 Vcc is applied to the plate wiring, and the trench 9 formed on the wafer is used as a plate electrode lead-out terminal D as a terminal for supplying this from the outside. Terminal D
Is composed of a polysilicon film 11 which is a first conductive film formed on the sidewalls of the trench 9 and on the semiconductor substrate, and polysilicon films 14 and 18 which are a second conductive film on the first conductive film. Is connected to an aluminum wiring or a selectively grown tungsten wiring to be the plate electrode lead-out terminal 54 on the semiconductor substrate. That is, the plate electrode lead terminal is composed of the first and second conductive films used as a pair of electrodes in the capacitor trench. A capacitor insulating film is uniformly formed in all the trenches 9 for facilitating the manufacture. The terminal D is provided between the polysilicon film 11 and the polysilicon films 14 and 18. . Therefore, this insulating film must be at least partially removed in order to electrically connect to the external aluminum wiring. In this case, the capacitor insulating film 13 on the oxide film 5 is partially removed by etching. However, the capacitor insulating film 13 exposed on the surface may be removed by etching over the entire surface of the wafer. In this case, there is no need to apply a mask in the etching removal step, which is advantageous in that respect.

Next, a dynamic RAM having a Bi-CMOS structure incorporating the HSPC cell according to the above-described embodiment will be described with reference to FIGS. Figure 2
Is a cross-sectional view of the main part, and FIG.
FIG. 4 is a circuit diagram of the AM, and FIG. 4 is a sectional view of the manufacturing process of the dynamic RAM. FIG. 2 shows an element formed on a P-type silicon wafer. The wafer comprises a P-type silicon semiconductor substrate 1 and a P-type silicon epitaxial layer 3 grown on the P-type silicon semiconductor substrate 1. Has a plurality of N ⁺ buried layers 2. An N well 4 reaching the N ⁺ buried layer 2 is formed in a desired region of the epitaxial layer 3, and the N ⁺ diffusion layer 2 is formed in this well.
5, P ^- diffusion layer 26 is formed to form an emitter and a base, respectively.
And an N ⁺ buried layer 2 used as a collector to form an NPN transistor. On the other hand, in the region of the epitaxial layer 3 where the N well 4 is not formed,
A MOS transistor and a capacitor K forming a dynamic RAM cell are formed. This MOS transistor has, for example, an LDD structure, and an LDD spacer 24 is provided on the side of the N-type polysilicon gate electrode 22 formed via a gate insulating film (SiO ₂ ) 21. The N ⁻ diffusion layer 23 serving as a source and a drain is formed in the epitaxial layer 3, and the drain is an N ⁻ diffusion layer directly connected to the N type polysilicon film 18 of the capacitor K formed in the trench. Includes 19. In the trench 9 where the capacitor K is formed, an oxide film (SiO ₂ ) 10 is formed on the side walls of the trench 9 except the bottom side,
An N-type polysilicon film 11 is formed on the surface and the bottom.

On the polysilicon film 11, an insulating film 13 serving as a dielectric of the capacitor is formed. Since the polysilicon film 11 is not formed near the entrance of the trench 9, the insulating film 13 near this entrance is formed by the oxide film 10.
Is formed on. As a material, SiO ₂ / Si ₃ N
₄ laminated film is used, but in addition to this material, Ta ₂ O ₅ film,
SiO ₂ film, Ta ₂ O ₅ / Si ₃ N ₄ laminated film, SiO ₂
Many materials such as / Si ₃ N ₄ / SiO ₂ laminated film are used. Any material having a high dielectric constant can be used. The insulating film 13 has a bag shape because it is formed on the side wall and the bottom of the trench 9, and the N-type polysilicon film 14 is filled therein. Further, the above-mentioned N-type polysilicon film 18 is provided thereon. The surface of the polysilicon film 18 is an oxide film 20.
Is covered with. The capacitor K in the trench 9 is composed of an insulating film 13 and N-type polysilicon films 11 and 14 which are electrodes facing each other with the insulating film 13 therebetween. Since the polysilicon film 11 is in contact with the N ⁺ buried layer 2, this buried layer 2 is used as a plate wiring. Therefore, each cell is connected to one. A constant potential of 1/2 Vcc is applied to the plate wiring, and as a terminal for externally supplying this, as shown in FIG.
The trench 9 formed in the c is used as the lead electrode lead terminal D. The terminal D is composed of a polysilicon film 11 which is a first conductive film formed on the side wall of the trench 9 and the element isolation oxide film 5, and polysilicon films 14 and 18 which are a second conductive film thereon. , The polysilicon film 18 is connected to the aluminum wiring to be the plate electrode lead-out terminal 54 on the semiconductor substrate.

The N ⁺ buried layer 2 serving as the collector electrode of the NPN transistor described above is connected to the metal wiring layer 32 serving as the collector electrode lead terminal 51 through the collector electrode lead terminal C formed in the trench. The terminal C has the same structure as the terminal D. The base 52 and the emitter 53 are connected to the P ⁻ diffusion layer 26 and the N ⁺ diffusion layer 25, respectively. The surface of the epitaxial layer 3 above the wafer has a thick element isolation oxide film 5 and a gate insulating film 2.
It is covered with a thin oxide film containing 1. The trenches used for terminals and capacitors are formed through the thick oxide film 5. The surface of the N-type polysilicon film 18 formed on each trench is covered with an oxide film 20. The surface of the wafer is covered with interlayer insulating films 27 and 30 such as SiO ₂ film and BPSG film for multi-layer wiring. Then, a metal wiring to be the bit line 42 is formed between them. The bit line is connected to the N ^- diffusion layer 23 which will be the source region of the MOS transistor through a contact hole 28 formed in the interlayer insulating film. On the inter-layer insulating film, the collector electrode lead terminal 51, the base electrode lead terminal 52, the emitter electrode lead terminal 53, the plane electrode
A metal wiring 32, such as aluminum, which serves as a lead-out electrode lead-out terminal 54 is formed.

FIG. 3 is a circuit diagram of the memory cell of the above-described embodiment. As shown in the figure, this memory cell is
The gate electrode 22 of the S-transistor is connected to the word line 41, the source electrode is connected to the bit line 42, and the drain electrode of the S-transistor is provided with a plate potential (1/2 Vcc). Connected to a capacitor K having a gate 54. In such a memory cell, at the time of reading, the bit line pair 42, 43 selected by the column selecting line 49 is connected to the input / output signal line pair 47, 48, and the read information is inputted to the input / output signal line pair 47, 48. Reportedly. In the one-transistor type memory cell, the amount of signal that can be taken out to the bit line at the time of reading is extremely small, and a sense amplifier for detecting and amplifying this is required. Also in this embodiment, the N channel sense amplifier activation signal line 45 and the P channel A CMOS sense amplifier connected to the sense amplifier activation signal line 46 is connected to the bit line pair 42 and 43 to detect and amplify a signal. The read information transmitted to the input / output signal line pair 47, 48 is amplified by the bipolar main amplifier and output (Dout) through the output driver 50. Writing is performed from the data input buffer through the input / output signal line. In this memory circuit, for example, a Bi-CMOS structure is incorporated in a sense amplifier, a main amplifier, etc., so that a semiconductor integrated circuit device excellent in high speed can be obtained. In forming this semiconductor integrated circuit device, first, as the wafer, for example, a thin P-type epitaxial layer formed on a P-type silicon substrate and an N ⁺ buried layer provided thereon is used. The buried layer is used as the plate wiring of the capacitor. The trench formed on the wafer is used as a capacitor and an electrode lead-out terminal such as a collector and a plate. With the above-described structure, the cell area can be reduced, and at the same time, it can be efficiently formed by a well-balanced manufacturing technique in which the MOS process technique is added to the normal bipolar process technique.

Next, a method of manufacturing the semiconductor integrated circuit device of this embodiment will be described with reference to FIGS. First, for example, in a desired region of the P-type silicon semiconductor substrate 1, S
b is diffused to form the N ⁺ buried layer 2 having an impurity concentration of about 5 × 10 ¹⁸ to 10 ²⁰ cm ⁻³ . Next, a P-type silicon epitaxial layer 3 having an impurity concentration of about 5 × 10 ^{15 to} 5 × 10 ¹⁷ cm ^{−3 is} grown on the entire surface of the wafer to a thickness of about 3 to 10 μm. Then, in the desired region, an N well region 4 having a depth (about 2 to 9 μm) reaching the N ⁺ buried layer 2 with the same concentration as the P type epitaxial layer 3 is formed (FIG. 4). Next, an element isolation oxide film 5 having a thickness of about 300 nm is formed on the surface of the epitaxial layer 3 by a known method such as thermal oxidation. Then, epitaxial layer 3
Pad oxide film 6 having a thickness of about 50 nm and a thickness of 100 n
m ₃ Si ₃ N ₄ film 7, SiO about 600 nm thick
_{The two} films 8 are sequentially formed by, for example, CVD. Then, a plurality of trenches 9 reaching the buried layer 2 are formed using these laminated insulating films as a mask. The depth of the trench is, for example, 3 so that the bottom reaches the buried layer 2.
Approximately 10 μm (FIG. 5). Next, the SiO ₂ film 8
And selectively oxidize using the Si ₃ N ₄ film 7 as a mask,
An oxide film (Si having a thickness of about 50 nm is formed only in the trench 9).
After forming O ₂ ) 10, anisotropic etching (RI
By E), the oxide film 10 is removed only on the bottom surface of the trench, and the remaining SiO ₂ film 8 is simultaneously removed by etching. Then, an N-type polysilicon film 11 having a thickness of about 50 nm is deposited on the entire surface of the wafer. At this time, the polysilicon film 11 is in contact with the buried layer 2. Then, using the patterned photoresist 12 as a mask, the polysilicon film 11 is patterned by isotropic etching or the like. The remaining polysilicon film 11 is formed in the trench 9, and the polysilicon film 11 in the trenches other than the trench used as the capacitor partially extends to the element isolation oxide film 5. (Fig. 6).

After removing the photoresist, the capacitor insulating film 13 is deposited on the entire surface of the wafer. The capacitor insulating film 13 is, for example, a 3-5 nm SiO 2 film converted to an oxide film.
_{A 2} / Si ₃ N ₄ laminated film is used. In this embodiment, the insulating film 13 is also formed in trenches other than those for capacitors, but it is not always necessary to do so. Next, the N-type polysilicon film 14 is deposited on the insulating film 13 so as to fill the trench, and isotropically etched back to leave the polysilicon film 14 only in the trench. Next, a photoresist 15 is formed on the wafer, the capacitor insulating film 13 in a predetermined region is removed by using this as a mask, and if the oxide film 10 is present, it is also removed to form contact holes 16 and 17. . Since the insulating film 13 is removed in the contact hole 16, the polysilicon film 11 extending on the element isolation oxide film 5 is exposed, and the polysilicon film 11 is exposed in the contact hole 17. Since the polysilicon film 14 and the oxide film 10 are partially removed, the epitaxial layer 3 in that part is exposed (FIG. 7). Then, the photoresist 15 is removed and an N-type polysilicon film 18 is further deposited on the polysilicon film 14. Next, contact
Impurities are diffused from the groove 17 to the exposed epitaxial layer 3 by, for example, a phosphorus diffusion method or the like to form an N ⁻ diffusion layer 19 of about 10 ¹⁸ cm ^{−3 on} the side wall portion near the entrance of the trench 9. The deposited polysilicon film 18 is patterned into a predetermined shape. This is selectively oxidized by, for example, thermal oxidation using the Si ₃ N ₄ film 7 as a mask and covered with the oxide film 20. After that, the exposed insulating film 13,
The Si ₃ N ₄ film 7, the pad oxide film 6 and the like are removed by etching (FIG. 8).

Then, a gate insulating film (Si) of about 10 to 20 nm is formed on the area of the wafer where the gate electrode is to be formed.
O ₂ ) 21 is formed, and the N-type polysilicon film deposited thereon is patterned to form a gate electrode 22.
Then, a pair of N ⁻ type diffusion layers 23 of about 10 ¹⁸ cm ⁻³ are formed on the epitaxial layer 3 in a self-aligning manner with the gate electrode by a conventional means so as to sandwich the gate electrode. The LDD spacer 24 is formed on the side of the gate electrode in order to correspond the LDD structure to the MOS transistor formed in 1. Then, 1 is formed on the surface of the other region of the epitaxial layer 3.
An N ⁺ diffusion layer 25 of about 0 ²⁰ cm ⁻³ and a P ⁻ diffusion layer 26 of about 10 ¹⁸ cm ⁻³ are formed so as to include this region.
Here, although not shown, the MOS transistor of the peripheral circuit has a DD structure. Further, the N ⁻ diffusion layer 19 formed previously is in contact with one of the N ⁻ diffusion layers 23 and forms a part of the drain electrode. Diffusion layers 25, 2
Reference numeral 6 constitutes an emitter and a base electrode of a bipolar transistor formed in the N well 4, respectively. This MO
A cell composed of an S transistor and a capacitor is repeatedly formed in one wafer (FIG. 9). Then, on the surface of the wafer, for example, a SiO ² film,
An interlayer insulating film 27 such as a BPSG film is deposited. Then, a predetermined region of the interlayer insulating film 27 is etched to open a contact hole 28. Next, a bit line 42 made of polycide such as MoSi ₂ or WSi ₂ is laid on the interlayer insulating film 27, and then the bit line 42 makes contact with the source electrode 23 through the contact hole 28. . Further, an interlayer insulating film 30 of the same type as or different from this insulating film is deposited on the interlayer insulating film 27 and then planarized. After that, a contact hole is opened in a predetermined region of the interlayer insulating film to form a metal wiring layer 32 of aluminum or the like on the interlayer insulating film, and at the same time, metal wiring is applied to the plate wiring or other wiring through the contact hole. By electrically connecting with an electrode or the like, the collector electrode lead-out terminal 5
1, a base electrode lead-out terminal 52, an emitter electrode lead-out terminal 53 and a plate electrode lead-out terminal 54 are formed (FIG. 2).

As described above, the present invention effectively combines the bipolar transistor, the MOS transistor, and the capacitor connected to the MOS transistor into one wafer.
Since the trench can be incorporated in the c and the trench can be used for the terminal, the degree of freedom in layout is improved, and a highly integrated semiconductor integrated circuit device can be efficiently obtained.

The CMOS structure used in the sense amplifier of the semiconductor integrated circuit device shown in FIG. 3 can be manufactured because the same process as other devices can be used by using a trench structure for element isolation. It will be easier. Further, in the same figure, the transistor in the memory cell 44 adopts the LDD structure, but it is not particularly limited to this structure. Furthermore, since the plate electrode 11 of the capacitor is fixed to 1/2 Vcc potential and the collector electrode 2 of the bipolar transistor is connected to the power supply voltage (Vcc), a plurality of collector electrodes are combined into one. Different buried layers 2 are used for the collector wiring and the collector electrode. However, if they are both connected to the same 1/2 Vcc or Vcc, then a common buried layer can be utilized.

As mentioned above, in the conventional HSPC cell,
The plate electrode of each cell is connected as a plate wiring to a buried layer formed in a net shape in the semiconductor substrate. This buried layer is subjected to diffusion treatment when the capacitor of each cell is formed in each trench. The high-concentration impurity diffusion region is formed by connecting the above regions. In the present invention, since the buried layer is formed in the substrate from the beginning without such a trouble, the manufacturing process can be greatly simplified. In the embodiments, the memory is used as the combination of the bipolar transistor and the capacitor, but the present invention is not limited to this, and it goes without saying that the invention can be applied to a capacitor used in another device. Further, although the P type is used for the semiconductor substrate, an N type semiconductor may be used.

[0020]

As described above, according to the present invention, the bipolar manufacturing process and the MOS structure manufacturing process are combined in a well-balanced manner, so that the plate and the collector can be simultaneously formed in one buried layer forming process. It is possible to reduce the manufacturing process. Further, since the inside of the trench formed in the wafer can be used for the lead-out terminal, the degree of freedom in layout is increased, and the high integration of the semiconductor integrated circuit device is significantly advanced.

[Brief description of drawings]

FIG. 1 is a sectional view of an essential part of an HSPC cell according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view of essential parts of a semiconductor integrated circuit device according to an embodiment of the present invention.

FIG. 3 is a circuit diagram of a semiconductor integrated circuit device according to an embodiment of the present invention.

FIG. 4 is a cross-sectional view showing the manufacturing process of the embodiment of the present invention.

FIG. 5 is a cross-sectional view showing the manufacturing process of the embodiment of the present invention.

FIG. 6 is a cross-sectional view showing the manufacturing process of the embodiment of the present invention.

FIG. 7 is a cross-sectional view showing the manufacturing process of the embodiment of the present invention.

FIG. 8 is a cross-sectional view showing the manufacturing process of the embodiment of the present invention.

FIG. 9 is a cross-sectional view showing the manufacturing process of the embodiment of the present invention.

[Explanation of symbols]

1 P-type silicon semiconductor substrate 2 N ⁺ buried layer 3 P-type epitaxial layer 4 N well 5 Element isolation oxide film 6 Pad oxide film 7 Si ₃ N ₄ film 8 SiO ₂ film 9 Trench 10 Oxide film 11 N-type polysilicon film 12 Photoresist 13 Capacitor insulating film 14 N-type polysilicon film 15 Photoresist 16 Contact hole 17 Contact hole 18 N-type polysilicon film 19 N ^- diffusion layer 20 Oxide film 21 Gate insulating film 22 Gate electrode 23 N ^- Diffusion layer 24 LDD spacer 25 N ⁺ Diffusion layer 26 P ⁻ Diffusion layer 27 Interlayer insulation film 28 Contact hole 30 Interlayer insulation film 32 Metal wiring layer 41 Word line 42 Bit line (BL) 43 Bit line (BL) 44 Memory cell 45 N channel sense amplifier activation signal line 46 P channel sense amplifier activation signal line 47 Input / output Line (I / O) 48 O signal lines (I / O) 49 column select line 50 output driver 51 collector electrode lead-out terminal 52 base - scan electrode lead terminal 53 an emitter electrode lead-out terminal 54 pre - gate electrode lead terminal

Claims (8)

[Claims] 1. A semiconductor substrate, an embedded high-concentration impurity diffusion layer formed inside the semiconductor substrate, and a trench formed from a surface of the semiconductor substrate to the embedded high-concentration impurity diffusion layer, the embedded high-concentration impurity diffusion layer being formed. A plurality of capacitors each having a layer serving as a plate wiring; and a plate electrode lead-out terminal which is formed in a trench reaching the buried high-concentration impurity diffusion layer from the surface of the semiconductor substrate and is composed of two conductive layers. And a semiconductor integrated circuit device. 2. The capacitance of the capacitor in the trench is
2. The semiconductor integrated circuit device according to claim 1, wherein a capacitor insulating film or a junction capacitance is used. 3. The capacitor insulating film is a SiO ₂ film,
The semiconductor integrated circuit device according to claim 2, wherein the semiconductor integrated circuit device is selected from a metal oxide film such as a Si ₃ N ₄ film and a Ta ₂ O ₅ film, and a composite film thereof. 4. A semiconductor substrate, at least one buried high-concentration impurity diffusion layer formed inside the semiconductor substrate, and a bipolar formed on the semiconductor substrate and having the buried high-concentration impurity diffusion layer as a collector electrode. A semiconductor integrated circuit device comprising: a transistor; and a plurality of capacitors formed on the semiconductor substrate and having the buried high-concentration impurity diffusion layer as a plate wiring. 5. The collector electrode is connected to a collector electrode lead-out terminal formed in a trench reaching the buried high-concentration impurity diffusion layer from the surface of the semiconductor substrate. Semiconductor integrated circuit device. 6. The semiconductor integrated circuit device according to claim 4, wherein the capacitor is formed in a trench extending from the surface of the semiconductor substrate to the buried high-concentration impurity diffusion layer. 7. A step of forming at least one buried high-concentration impurity diffusion layer of a conductivity type different from that of the semiconductor substrate in a desired region inside the semiconductor substrate; Forming a plurality of trenches reaching the concentrated impurity diffusion layer; forming a capacitor in the trench, and contacting a plate electrode of the capacitor with the buried high-concentration impurity diffusion layer used as a plate wiring; A step of forming a plate electrode lead terminal in the trench and bringing the plate electrode lead terminal into contact with the plate wiring; and the buried high concentration impurity diffusion layer as a collector electrode in the semiconductor substrate. Forming a bipolar transistor, and forming a collector electrode lead terminal in the trench. The method of manufacturing a semiconductor integrated circuit device characterized in that it comprises a step of contacting the lead terminal to the collector electrode. 8. The method of manufacturing a semiconductor integrated circuit device according to claim 7, wherein in the step of forming a capacitor in the trench, a capacitor insulating film is formed in all the trenches provided in the semiconductor substrate. .