JPH0521689A - Multilayer lead frame - Google Patents
Multilayer lead frameInfo
- Publication number
- JPH0521689A JPH0521689A JP3176599A JP17659991A JPH0521689A JP H0521689 A JPH0521689 A JP H0521689A JP 3176599 A JP3176599 A JP 3176599A JP 17659991 A JP17659991 A JP 17659991A JP H0521689 A JPH0521689 A JP H0521689A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- lead
- conductor layer
- power supply
- lead frame
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/49105—Connecting at different heights
- H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、高速伝送用多層リード
フレーム、特に電子部品搭載部の構造に特長を有する多
層リードフレームに関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-layer lead frame for high speed transmission, and more particularly to a multi-layer lead frame having a feature in the structure of an electronic component mounting portion.
【０００２】[0002]
【従来の技術】従来、半導体装置用のリードフレーム
は、半導体パッケージを小型化するため、平板上の金属
製の一層のリードフレームから構成されている。このよ
うな一層のリードフレームは、形状が簡単であるが、リ
ードフレームおよび半導体素子の電源用の端子と信号用
の端子が同一平面上に互いに近接して配置されているた
め、相互の端子間で電磁的な干渉が発生する。すなわ
ち、高い周波数の信号を伝送する場合にクロストークが
発生し、良好な伝送特性が得られないという欠点があっ
た。また、誘導電流を適当に除去できる接地層等もない
ため、静電容量が大きくなり、これも伝送特性の低下の
原因となっている。2. Description of the Related Art Conventionally, a lead frame for a semiconductor device is composed of a flat metal one-layer lead frame in order to miniaturize a semiconductor package. Such a one-layer lead frame has a simple shape, but since the lead frame and the power supply terminal and the signal terminal of the semiconductor element are arranged close to each other on the same plane, the lead frame and Electromagnetic interference occurs. That is, there is a drawback that crosstalk occurs when a high frequency signal is transmitted and good transmission characteristics cannot be obtained. Further, since there is no ground layer or the like capable of appropriately removing the induced current, the electrostatic capacity becomes large, which also causes the deterioration of the transmission characteristics.
【０００３】この欠点を解消するため、近年では、例え
ばリードフレームに絶縁層を介し接地板および電源供給
板をサンドウィッチ状に設けて、半導体素子の接地端子
および電源端子を接地板および電源供給板にそれぞれボ
ンディング接続した多層構造のリードフレームも発表さ
れている。In order to solve this drawback, in recent years, for example, a ground plate and a power supply plate are provided in a sandwich shape on a lead frame via an insulating layer so that the ground terminal and the power supply terminal of a semiconductor element are used as the ground plate and the power supply plate. A multi-layered lead frame with bonding connections has also been announced.
【０００４】リードフレームは、それ自体の強度等から
ある厚さ以下にすることができず、また打ち抜き加工上
からもインナーリードの先端付近の微細加工が難しく、
そのためリードフレームのインナーリードのピッチを一
定以上小さくすることができなかった。例えば０．１０
ｍｍの板厚のリードフレームで０．１８ｍｍピッチが限
界であった。The lead frame cannot be made thinner than a certain thickness due to its own strength, etc., and it is difficult to perform fine processing near the tips of the inner leads from the viewpoint of punching.
Therefore, the pitch of the inner leads of the lead frame cannot be made smaller than a certain value. For example, 0.10
The lead frame having a plate thickness of mm has a limit of 0.18 mm pitch.
【０００５】また、リード数を増加した例としては、米
国ＮＳＣ社製のTape Pac QFP(QuadFlat Package) 等も
ある。このパッケージの構造はＴＡＢテープキャリア型
であり、ＬＳＩ素子とギャング・ボンディング法にて接
続している。しかし、この構造では前述したように一層
の配線であるので、伝送特性の高速化が図れない。Further, as an example of increasing the number of leads, there is Tape Pac QFP (Quad Flat Package) manufactured by NSC, USA. The structure of this package is a TAB tape carrier type, and is connected to an LSI element by a gang bonding method. However, in this structure, since the wiring is one layer as described above, the transmission characteristics cannot be speeded up.
【０００６】またリードフレームのリードの端子数が多
くなると、リードフレームの伝送特性がさらに重要な問
題となってくる。かかるリードフレームにおいて、リー
ドの微細配線化の他に、高周波信号が印加された場合の
伝送特性を向上するために種々の工夫がされている。When the number of lead terminals of the lead frame increases, the transmission characteristics of the lead frame becomes a more important issue. In such a lead frame, in addition to the fine wiring of the leads, various measures have been taken in order to improve the transmission characteristics when a high frequency signal is applied.
【０００７】一般に、高周波信号印加時の遅延時間は、
容量およびインピーダンスに主に関係する。Generally, the delay time when a high frequency signal is applied is
Mainly related to capacitance and impedance.
【０００８】しかし、従来の金属製の一層リードフレー
ムでは遅延時間に関係する容量およびインダクタンスが
十分に低くできなかった。However, the conventional metal one-layer lead frame cannot sufficiently reduce the capacitance and the inductance related to the delay time.
【０００９】本出願人は、上記問題点を解消し、リード
の微細配線化を図るとともに高周波信号の伝送特性を向
上した多層リードフレームを特願平０２−１５２１５６
号に開示している。The applicant of the present invention has proposed a multi-layered lead frame which solves the above-mentioned problems, enables finer wiring of the leads, and improves the transmission characteristics of high frequency signals, in Japanese Patent Application No. 02-152156.
Issue.
【００１０】図３は前記特願平０２−１５２１５６号に
係る多層リードフレームの一例を示す断面図である。FIG. 3 is a sectional view showing an example of a multilayer lead frame according to Japanese Patent Application No. 02-152156.
【００１１】図３においてリードフレームは、接地およ
び電源供給用導体層７と、前記導体層上に設けられる絶
縁層６と、前記絶縁層上にエッチングまたは蒸着により
微細に形成されるインナーリード５と、金属フレームに
より形成される信号用リード１ｂならびに接地および電
源供給用リード１ａとを備え、前記インナーリード５と
信号用リード１ｂとが接合により電気的に接続され、前
記接地および電源供給用リード１ａが前記導体層７に接
続され、前記絶縁層６には半導体素子２の電極と前記導
体層７とをワイヤボンディングするための複数の開口部
が設けられている。３はボンディングワイヤ、４は接合
層、８はバンプである。In FIG. 3, the lead frame includes a conductor layer 7 for grounding and power supply, an insulating layer 6 provided on the conductor layer, and inner leads 5 finely formed on the insulating layer by etching or vapor deposition. , A signal lead 1b formed of a metal frame and a ground and power supply lead 1a, and the inner lead 5 and the signal lead 1b are electrically connected to each other by bonding, and the ground and power supply lead 1a is provided. Are connected to the conductor layer 7, and the insulating layer 6 is provided with a plurality of openings for wire bonding the electrode of the semiconductor element 2 and the conductor layer 7. 3 is a bonding wire, 4 is a bonding layer, and 8 is a bump.
【００１２】[0012]
【発明が解決しようとする課題】ところで、前記特願平
０２−１５２１５６号に示すような接地および電源供給
用導体層の上に絶縁フィルム層を有し、その上に電子部
品を搭載する構造では、例えば絶縁層としてポリイミド
樹脂を使用した場合、熱伝導率は0.0005cal・cm-1・s-1・
℃-1となり４２合金（Ｆｅ−４２％Ｎｉ合金）を用いた
場合の0.0005/0.032≒１／６、無酸素銅を用いた場合の
0.0005/0.94 ≒１／１８８０と非常に小さいため、熱抵
抗が大きくなるという問題があった。By the way, in a structure having an insulating film layer on a ground and power supply conductor layer and mounting an electronic component thereon, as shown in Japanese Patent Application No. 02-152156. , For example, when polyimide resin is used as the insulating layer, the thermal conductivity is 0.0005 cal ・ cm -1・ s -1・
℃ -1 and 0.0005 / 0.032≈1 / 6 when using 42 alloy (Fe-42% Ni alloy), when using oxygen-free copper
Since it is as small as 0.0005 / 0.94 ≈ 1/1880, there is a problem that the thermal resistance becomes large.
【００１３】そこで、３００ピン以上の多ピン多層フレ
ームに搭載する電子部品としてＣＭＯＳ論理ＬＳＩの場
合の消費電力は、１Ｗを越え２〜３Ｗのものがあるため
放熱性の向上を図る構造が求められてきた。Therefore, the power consumption of a CMOS logic LSI as an electronic component mounted on a multi-pin multi-layer frame of 300 pins or more has a power consumption of more than 1 W and 2 to 3 W, so that a structure for improving heat dissipation is required. Came.
【００１４】本発明の目的は、前記した従来技術の欠点
を解消し、熱放散性を大幅に向上させることができる新
規な多層リードフレームを提供することにある。An object of the present invention is to provide a novel multi-layered lead frame which can solve the above-mentioned drawbacks of the prior art and can greatly improve heat dissipation.
【００１５】[0015]
【課題を解決するための手段】上記目的を達成するため
に本発明によれば、接地および電源供給用導体層と、前
記導体層上に設けられる絶縁層と、前記絶縁層上にエッ
チングまたは蒸着により微細に形成されるインナーリー
ドと、金属フレームにより形成される信号用リードなら
びに接地および電源供給用リードとを備え、前記インナ
ーリードと信号用リードとが接合により電気的に接続さ
れ、前記接地および電源供給用リードが前記導体層に接
続され、電子部品を直接搭載するための前記導体層の一
部に前記絶縁層が除去された露出部が設けられているこ
とを特徴とする多層リードフレームが提供される。To achieve the above object, according to the present invention, a ground and power supply conductor layer, an insulating layer provided on the conductor layer, and etching or vapor deposition on the insulating layer. A finer inner lead, and a signal lead and a ground and power supply lead formed by a metal frame. The inner lead and the signal lead are electrically connected by bonding, and the ground and A multilayer lead frame, wherein a power supply lead is connected to the conductor layer, and an exposed portion from which the insulating layer is removed is provided in a part of the conductor layer for directly mounting an electronic component. Provided.
【００１６】ここで、電子部品を直接搭載する前記導体
層露出部は、突き出し加工されているのが好ましい。Here, it is preferable that the exposed portion of the conductor layer on which the electronic component is directly mounted is extruded.
【００１７】以下に本発明をさらに詳細に説明する。The present invention will be described in more detail below.
【００１８】図１は、本発明の多層リードフレームの一
実施例を示す断面図である。FIG. 1 is a sectional view showing an embodiment of the multilayer lead frame of the present invention.
【００１９】本発明において絶縁層６は、市販のポリイ
ミド系樹脂フィルムのカプトン（２５〜１２５μｍ厚
さ）、ユーピレックスｓ（２５〜１２５μｍ厚さ）と市
販のポリイミド系樹脂のワニスタイプ（低熱膨張性ポリ
イミド：熱膨張係数４×１０-7／℃を含む）を挙げるこ
とができるがこれに限るものではない。In the present invention, the insulating layer 6 is a commercially available polyimide resin film Kapton (25 to 125 μm thick), Upilex s (25 to 125 μm thick) and a commercially available polyimide resin varnish type (low thermal expansion polyimide). (Including a coefficient of thermal expansion of 4 × 10 −7 / ° C.), but not limited thereto.
【００２０】また前記絶縁層６は、市販の銅箔等にポリ
イミド系樹脂をキャスティングした２層ＣＣＬ(Copper
Clad Laminates) も使用できる。ポリイミド系樹脂を用
いたものは量産性に優れているので好ましい。The insulating layer 6 is a two-layer CCL (Copper) prepared by casting a polyimide resin on a commercially available copper foil or the like.
Clad Laminates) can also be used. Those using a polyimide resin are preferable because they are excellent in mass productivity.
【００２１】絶縁層６の下側には、例えば銅よりなる接
地および電源供給用導体層（以下、単に導体層という）
７を有する。実施例においては、上記絶縁層６は片面
（すなわち上面）銅箔付ポリイミドフィルムとしてい
る。Below the insulating layer 6, a conductor layer for grounding and power supply made of, for example, copper (hereinafter, simply referred to as a conductor layer).
Have 7. In the embodiment, the insulating layer 6 is a polyimide film with copper foil on one surface (that is, the upper surface).
【００２２】この銅箔は後にエッチングされてインナー
リード５となる。この絶縁層６（下面）には導体層７が
接着剤等により貼着されている。絶縁層６の上側表面に
貼付された銅箔を、例えばエッチングまたは蒸着して、
インナーリード５が形成されて信号層となる。This copper foil is later etched to form inner leads 5. A conductor layer 7 is attached to the insulating layer 6 (lower surface) with an adhesive or the like. The copper foil attached to the upper surface of the insulating layer 6 is etched or vapor-deposited,
The inner lead 5 is formed to serve as a signal layer.
【００２３】本発明では、前記導体層７の一部に電子部
品２を直接搭載するための露出部が設けられている。In the present invention, an exposed portion for directly mounting the electronic component 2 is provided on a part of the conductor layer 7.
【００２４】前記導体層７の電子部品２搭載部分は、予
め図２に示すように突き出し加工しておき、電子部品２
搭載部を高くしておけば、電子部品２搭載部分の平坦性
を確保でき、しかもワイヤボンディング時においてテレ
ビカメラによる認識を確実にでき、ワイヤボンディング
のミスマッチを防止できる効果がある。The portion of the conductor layer 7 on which the electronic component 2 is mounted is preliminarily extruded as shown in FIG.
If the mounting portion is made high, the flatness of the mounting portion of the electronic component 2 can be ensured, and further, the recognition by the television camera can be surely performed at the time of wire bonding, and the mismatch of the wire bonding can be prevented.
【００２５】前記信号層５と信号用リード１ｂとの間
は、例えばＡｕ−Ｓｎの接合層４により電気的に接続さ
れている。The signal layer 5 and the signal lead 1b are electrically connected by, for example, an Au--Sn bonding layer 4.
【００２６】一方、接地および電源供給用リード１ａ
は、導体層７に直接接地される。この接地のため、例え
ば前記絶縁層６の一部が除去されて露出する導体層７と
接地および電源供給用リード１ａとを、例えばＡｕ−Ｓ
ｎの接合層４にて密着させて導通接続している。かかる
多層リードフレームの前記電子部品搭載用露出部に、電
子部品２を直接搭載し、電子部品２の信号端子と信号層
５との間をボンディングワイヤ３でボンディング接続す
るとともに、さらに電子部品２の接地端子と導体層７の
絶縁層６から露出する部分との間をボンディングワイヤ
３でボンディングして接続し半導体装置を作製すること
ができる。On the other hand, grounding and power supply leads 1a
Are directly grounded to the conductor layer 7. For this grounding, for example, the conductor layer 7 exposed by removing a part of the insulating layer 6 and the grounding and power supply lead 1a are connected to, for example, Au-S.
The n bonding layers 4 are in close contact with each other for conductive connection. The electronic component 2 is directly mounted on the exposed portion for mounting the electronic component of the multilayer lead frame, and the signal terminal of the electronic component 2 and the signal layer 5 are bonded and connected by the bonding wire 3. A semiconductor device can be manufactured by bonding and connecting the ground terminal and a portion of the conductor layer 7 exposed from the insulating layer 6 with the bonding wire 3.
【００２７】[0027]
【実施例】以下に本発明を実施例に基づき具体的に説明
する。EXAMPLES The present invention will be specifically described below based on examples.
【００２８】（実施例１）厚さ２５μｍの電解銅箔に厚
さ２５μｍのポリイミド樹脂をキャスティングした２層
ＣＣＬを用い、導体層として厚さ３５μｍの４２合金を
前記ポリイミド樹脂面に貼り合わせ、パターニングエッ
チングして図１に示すように信号層５を形成し、３９ｍ
ｍ×３９ｍｍのＦＰＣ(Flexible Printed Circuit Boar
d)を作製した。リード本数は３８４ピンとした。これに
Ａｕ−Ｓｎ接合にてそれぞれ厚さ０．１５ｍｍの４２合
金製の接地および電源供給用リード１ａと信号用リード
１ｂを導体層７および信号層５に接合し多層リードフレ
ームを作製した。Example 1 A two-layer CCL in which a 25 μm-thick electrolytic copper foil is cast with a 25 μm-thick polyimide resin is used, and a 42 μm-thick 42 alloy is bonded as a conductor layer to the polyimide resin surface and patterned. Etching to form the signal layer 5 as shown in FIG. 1, 39 m
mx 39 mm FPC (Flexible Printed Circuit Boar
d) was prepared. The number of leads was 384 pins. A ground and power supply lead 1a and a signal lead 1b, each made of 42 alloy and having a thickness of 0.15 mm, were joined to the conductor layer 7 and the signal layer 5 by Au-Sn bonding, to produce a multilayer lead frame.
【００２９】つぎにポリイミド樹脂層６を１１ｍｍ角除
去し、導体層７が露出する部分に１０ｍｍ角のダミーチ
ップをＡｇペーストを用いて直接ダミーのダイオード組
入れヒータチップ付けを行い、チップに１０Ｗの電力を
与えて熱抵抗の測定を行った。Next, the polyimide resin layer 6 is removed by 11 mm square, a dummy chip of 10 mm square is directly mounted on the exposed portion of the conductor layer 7 by using Ag paste, and a dummy diode is incorporated into the heater chip to attach a 10 W electric power to the chip. Was given to measure the thermal resistance.
【００３０】比較のために図３に示すようにポリイミド
樹脂層６上にダミーチップを搭載したほかは実施例と同
様にして熱抵抗の測定を行った結果、実施例のものは比
較例のものに比べ熱抵抗が約２０％減少した。For comparison, the thermal resistance was measured in the same manner as in Example except that a dummy chip was mounted on the polyimide resin layer 6 as shown in FIG. The thermal resistance was reduced by about 20%.
【００３１】（実施例２）厚さ３５μｍの圧延銅箔に厚
さ５０μｍのポリイミド樹脂をキャスティングした２層
ＣＣＬを用い、導体層として厚さ１００μｍの無酸素銅
をポリイミド樹脂面に貼り合わせ、パターニングエッチ
ングして図１に示すように信号層５を形成し、３９ｍｍ
×３９ｍｍのＦＰＣ(FlexiblePrinted Circuit Board)
を作製した。リード本数は３０４ピンとした。これにＡ
ｕ−Ｓｎ接合にてそれぞれ厚さ０．１５ｍｍの無酸素銅
製接地および電源供給用リード１ａおよび信号用リード
１ｂを導体層７および信号層５に接合し多層リードフレ
ームを作製した。Example 2 Using a two-layer CCL in which a rolled copper foil having a thickness of 35 μm and a polyimide resin having a thickness of 50 μm are cast, oxygen-free copper having a thickness of 100 μm is bonded as a conductor layer to the polyimide resin surface and patterned. Etching to form the signal layer 5 as shown in FIG. 1, 39 mm
× 39mm FPC (Flexible Printed Circuit Board)
Was produced. The number of leads was 304 pins. A to this
An oxygen-free copper ground and power supply lead 1a and a signal lead 1b each having a thickness of 0.15 mm were joined to the conductor layer 7 and the signal layer 5 by u-Sn joining to produce a multilayer lead frame.
【００３２】つぎにポリイミド樹脂層６を１１ｍｍ角除
去し、導体層７が露出する部分に１０ｍｍ角のダミーチ
ップをＡｇペーストを用いて直接ダミーのダイオード組
入れヒータチップ付けを行い、チップに１０Ｗの電力を
与えて熱抵抗の測定を行った。Then, the polyimide resin layer 6 is removed by 11 mm square, and a dummy chip of 10 mm square is directly mounted on the exposed portion of the conductor layer 7 by using Ag paste to form a dummy diode heater chip. Was given to measure the thermal resistance.
【００３３】比較のために図３に示すようにポリイミド
樹脂層６上にダミーチップを搭載したほかは実施例と同
様にして熱抵抗の測定を行った結果、実施例のものは比
較例のものに比べ熱抵抗が約３０％減少した。For comparison, thermal resistance was measured in the same manner as in Example except that a dummy chip was mounted on the polyimide resin layer 6 as shown in FIG. The thermal resistance was reduced by about 30%.
【００３４】（実施例３）厚さ３５μｍの圧延銅箔に厚
さ７０μｍ（熱膨張係数２０×１０-6／℃）のポリイミ
ド樹脂をキャスティングした２層ＣＣＬを用い、導体層
として厚さ１００μｍの４２合金をポリイミド樹脂面に
貼り合わせ、図２に示すように導体層７のチップ搭載部
分を突き出し加工し、パターニングエッチングして図２
に示すように信号層５を形成し、３９ｍｍ×３９ｍｍの
ＦＰＣ(Flexible Printed CircuitBoard)を作製した。
リード本数は３０４ピンとした。これにＡｕ−Ｓｎ接合
にてそれぞれ厚さ０．１５ｍｍの４２合金製の接地およ
び電源供給用リード１ａと信号用リード１ｂを導体層７
および信号層５に接合し多層リードフレームを作製し
た。Example 3 A two-layer CCL in which a polyimide resin having a thickness of 70 μm (coefficient of thermal expansion of 20 × 10 −6 / ° C.) was cast on a rolled copper foil having a thickness of 35 μm was used, and a conductor layer having a thickness of 100 μm was used. 42 alloy is attached to the polyimide resin surface, and the chip mounting portion of the conductor layer 7 is extruded as shown in FIG.
The signal layer 5 was formed as shown in (3) to prepare a 39 mm × 39 mm FPC (Flexible Printed Circuit Board).
The number of leads was 304 pins. The ground and power supply leads 1a and the signal leads 1b, each made of 42 alloy and each having a thickness of 0.15 mm, are connected to the conductor layer 7 by Au-Sn bonding.
And, it was joined to the signal layer 5 to produce a multilayer lead frame.
【００３５】つぎに、前記突き出し加工したポリイミド
樹脂層６を１１ｍｍ角除去し、導体層７が露出する部分
に１０ｍｍ角のダミーチップをＡｇペーストを用いて直
接ダミーのダイオード組入れヒータチップ付けを行い、
チップに１０Ｗの電力を与えて熱抵抗の測定を行った。Next, the protruding polyimide resin layer 6 was removed by 11 mm square, and a dummy chip of 10 mm square was directly mounted on the exposed portion of the conductor layer 7 by using Ag paste to mount a dummy diode heater chip.
The thermal resistance was measured by applying 10 W of power to the chip.
【００３６】その結果、熱抵抗は、２．７℃／Ｗであ
り、３０４ピン従来構造（図３）は３．９℃／Ｗであっ
た。As a result, the thermal resistance was 2.7 ° C./W and that of the 304-pin conventional structure (FIG. 3) was 3.9 ° C./W.
【００３７】[0037]
【発明の効果】本発明は以上説明したように構成されて
いるので下記の効果を奏する。
（１）絶縁層の一部を除去し直接接地および電源供給用
導体層に電子部品を搭載する構造としたことにより、確
実に熱放散性を向上できる。
（２）上記理由により、従来構造（図３参照）に比べ熱
抵抗を約２０〜３０％低減できる。
（３）本発明は、工業的な生産性に優れ、効率の良い構
造であるため、量産性に富んだ多層リードフレームを得
ることができる。
（４）絶縁層としてポリイミド系樹脂を用いることによ
り量産性に優れた、しかも熱放散の良好な多層リードフ
レームを得ることができる。Since the present invention is configured as described above, it has the following effects. (1) By adopting a structure in which a part of the insulating layer is removed and an electronic component is mounted directly on the conductor layer for grounding and power supply, heat dissipation can be reliably improved. (2) Due to the above reason, the thermal resistance can be reduced by about 20 to 30% as compared with the conventional structure (see FIG. 3). (3) Since the present invention has a structure with excellent industrial productivity and high efficiency, it is possible to obtain a multi-layer lead frame with high mass productivity. (4) By using a polyimide resin as the insulating layer, it is possible to obtain a multi-layer lead frame which is excellent in mass productivity and has good heat dissipation.
【図１】本発明の多層リードフレームの一実施例を示す
断面図である。FIG. 1 is a cross-sectional view showing an example of a multilayer lead frame of the present invention.
【図２】本発明の多層リードフレームの他の実施例を示
す断面図である。FIG. 2 is a sectional view showing another embodiment of the multilayer lead frame of the present invention.
【図３】従来の多層リードフレームの一例を示す断面図
である。FIG. 3 is a sectional view showing an example of a conventional multilayer lead frame.
１ａ 接地および電源供給用リード １ｂ 信号用リード ２ 半導体素子（電子部品） ３ ボンディングワイヤ ４ 接合層 ５ インナーリード（信号層） ６ 絶縁層 ７ 接地および電源供給用導体層 ８ バンプ 1a Grounding and power supply lead 1b Signal lead 2 Semiconductor elements (electronic parts) 3 Bonding wire 4 Bonding layer 5 Inner leads (signal layer) 6 insulating layers 7 Grounding and power supply conductor layers 8 bumps
───────────────────────────────────────────────────── フロントページの続き (72)発明者 御 田 護 茨城県日立市助川町３丁目１番１号 日立 電線株式会社電線工場内 (72)発明者 高 城 正 治 茨城県日立市助川町３丁目１番１号 日立 電線株式会社電線工場内 (72)発明者 村 上 富 男 茨城県日立市助川町３丁目１番１号 日立 電線株式会社電線工場内 ─────────────────────────────────────────────────── ─── Continued front page (72) Inventor Mamoru Mita Hitachi, 1-1 Sukegawa-cho, Hitachi City, Ibaraki Prefecture Electric Wire Co., Ltd. Inside the electric wire factory (72) Inventor Masaharu Takagi Hitachi, 1-1 Sukegawa-cho, Hitachi City, Ibaraki Prefecture Electric Wire Co., Ltd. Inside the electric wire factory (72) Inventor Tomio Murakami Hitachi, 1-1 Sukegawa-cho, Hitachi City, Ibaraki Prefecture Electric Wire Co., Ltd. Inside the electric wire factory
Claims (2)
体層上に設けられる絶縁層と、前記絶縁層上にエッチン
グまたは蒸着により微細に形成されるインナーリード
と、金属フレームにより形成される信号用リードならび
に接地および電源供給用リードとを備え、前記インナー
リードと信号用リードとが接合により電気的に接続さ
れ、前記接地および電源供給用リードが前記導体層に接
続され、電子部品を直接搭載するための前記導体層の一
部に前記絶縁層が除去された露出部が設けられているこ
とを特徴とする多層リードフレーム。1. A ground and power supply conductor layer, an insulating layer provided on the conductor layer, inner leads finely formed on the insulating layer by etching or vapor deposition, and a signal formed by a metal frame. And a grounding and power supply lead, the inner lead and the signal lead are electrically connected by joining, the grounding and power supply lead is connected to the conductor layer, and an electronic component is directly mounted. A multilayer lead frame, wherein an exposed portion from which the insulating layer is removed is provided on a part of the conductor layer for carrying out.
部は、突き出し加工されている請求項１記載の多層リー
ドフレーム。2. The multilayer lead frame according to claim 1, wherein the conductor layer exposed portion on which an electronic component is directly mounted is extruded.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3176599A JPH0521689A (en) | 1991-07-17 | 1991-07-17 | Multilayer lead frame |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3176599A JPH0521689A (en) | 1991-07-17 | 1991-07-17 | Multilayer lead frame |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0521689A true JPH0521689A (en) | 1993-01-29 |
Family
ID=16016391
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3176599A Pending JPH0521689A (en) | 1991-07-17 | 1991-07-17 | Multilayer lead frame |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0521689A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101834258A (en) * | 2009-03-11 | 2010-09-15 | 索尼公司 | The installation of light-emitting component encapsulation, light-emitting device, backlight and liquid crystal indicator |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6364047B2 (en) * | 1979-12-28 | 1988-12-09 | ||
| JPH03132063A (en) * | 1989-10-18 | 1991-06-05 | Dainippon Printing Co Ltd | Lead frame |
-
1991
- 1991-07-17 JP JP3176599A patent/JPH0521689A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6364047B2 (en) * | 1979-12-28 | 1988-12-09 | ||
| JPH03132063A (en) * | 1989-10-18 | 1991-06-05 | Dainippon Printing Co Ltd | Lead frame |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101834258A (en) * | 2009-03-11 | 2010-09-15 | 索尼公司 | The installation of light-emitting component encapsulation, light-emitting device, backlight and liquid crystal indicator |
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| Date | Code | Title | Description |
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| A02 | Decision of refusal |
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