JPH05216702A - Arithmetic unit - Google Patents

Abstract

PURPOSE:To obtain an arithmetic unit capable of continuing a normal arithmetic operation even when a computing error due to a software error, etc., occurs successively at an arithmetic part. CONSTITUTION:This unit is equipped with first to third arithmetic parts 11-13 which perform the same arithmetic processing based on a control signal from a microprogram control part 14, a first comparator 4 which compares computing result data from the first arithmetic part 11 with that of the second arithmetic part 12, and a second comparator 5 which compares the computing result data from the second arithmetic part 12 with that of the third arithmetic part 13. Furthermore, it is comprised of a decision circuit 2 which decides correct computing result data based on the decision results of the first and second comparators 4, 5, and a selection/distribution circuit 1 which selects one of computing result data out of the data in the first to third arithmetic parts 11-13 based on the decision of the decision circuit 2 and outputs it to the outside, and outputs input data from the outside to the first to third arithmetic parts 11-13.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an arithmetic unit, and more particularly to a fault-tolerant microprogram controlled digital arithmetic unit.

[0002]

2. Description of the Related Art FIG. 2 shows a conventional example. In the conventional example shown in FIG. 2, the microprogram control unit 14 for controlling arithmetic operation
And a first arithmetic unit 11, a second arithmetic unit 12, a third arithmetic unit 13 that perform the same arithmetic operation based on a control signal from the microprogram control unit 14, and each arithmetic unit 11, 12, 1.
One operation result data is selected from the operation result data from 3 by a majority decision and is output to the outside, and the input data from the outside is supplied to the first operation unit 11, the second operation unit 12 and the third operation unit.
And a majority decision / distribution circuit 15 for outputting to the calculation unit 13.

Next, the operation of the above conventional example will be described.

Input data from the outside is distributed by the majority / distribution circuit 15 and the first arithmetic unit 11 and the second arithmetic unit 1 are distributed.
2 and the third calculation unit 13 output. Based on a control signal from the micro program control unit 14, the first calculation unit 11
The second calculation unit 12 and the third calculation unit 13 execute the same calculation. The calculation result data in each of the calculation units 11, 12, and 13 is input to the majority / distribution circuit 15. In the majority / distribution circuit 15, the first arithmetic unit 11, the second arithmetic unit 12, and the third arithmetic unit
The majority of the calculation result data from the calculation unit 13 is taken and the correct calculation data is output to the outside.

According to the conventional fault-tolerant microprogram control digital arithmetic unit having the above-mentioned configuration and operation, even if one of the arithmetic units causes an arithmetic error, the arithmetic operation is performed normally as a device by taking the majority of three arithmetic data. Was able to continue.

[0006]

However, in the above-mentioned conventional example, since a majority of three operation data is taken, if an operation error is accumulated in one of the operation units due to a soft error or the like, If a calculation error occurs in another calculation unit after that, the device cannot continue normal calculation.

[0007]

SUMMARY OF THE INVENTION It is an object of the present invention to improve the inconvenience of the conventional example, and in particular, it is possible to continue a normal arithmetic operation even if arithmetic errors due to soft errors or the like occur differently in arithmetic units. It is to provide an arithmetic unit.

[0008]

Therefore, according to the present invention, a micro program control unit for controlling arithmetic operation and first to third arithmetic units for performing the same arithmetic processing based on a control signal from the micro program control unit. And a first comparison circuit for comparing the operation result data from the first operation unit with the operation result data from the second operation unit, the operation result data from the second operation unit, and the third operation unit And a second comparison circuit for comparing the calculation result data from the. Further, the determination circuit that determines correct operation result data based on the comparison result of the first comparison circuit and the comparison result of the second comparison circuit, and the determination circuit of the first to third operation units based on the determination result of the determination circuit. It comprises a selection / distribution circuit that selects one of the calculation result data and outputs it to the outside, and outputs the input data from the outside to the first calculation unit, the second calculation unit, and the third calculation unit. The composition is adopted. This aims to achieve the above-mentioned object.

[0009]

When data is input from the outside, the selection / distribution circuit outputs the input data to the first arithmetic unit, the second arithmetic unit and the third arithmetic unit. The first arithmetic unit, the second arithmetic unit, and the third arithmetic unit execute the same arithmetic operation based on the control signal from the microprogram control unit. The first comparison circuit is the first
The calculation result data from the second calculation unit is compared with the calculation result data from the second calculation unit. The second comparison circuit compares the calculation result data from the second calculation unit with the calculation result data from the third calculation unit. Further, the determination circuit determines correct operation data based on the comparison result of the first comparison circuit and the comparison result of the second comparison circuit. For example, when the comparison result of the first comparison circuit is the same as the comparison result of the second comparison circuit, the calculation result of each calculation unit is determined to be correct. On the other hand, if the comparison results of the first comparison circuit do not match and the comparison results of the second comparison circuit match, it is determined that the calculation results of the second calculation unit and the third calculation unit are correct.

If the comparison result of the first comparison circuit is the same as the comparison result of the second comparison circuit, the comparison results of the first comparison circuit and the second calculation circuit are judged to be correct. Further, when the comparison result of the first comparison circuit does not match and the comparison result of the second comparison circuit does not match, it is determined that the calculation results of the first calculation unit and the third calculation unit are correct. Then, the selection / distribution circuit takes in the calculation result from the initialized calculation unit based on the judgment result from the judgment circuit and outputs it to the outside when the initialized calculation unit is normal. On the other hand, if the initially set arithmetic unit is abnormal, the setting is switched and the arithmetic result from the normal arithmetic unit is fetched and output to the outside.

[0011]

DETAILED DESCRIPTION OF THE INVENTION An embodiment of the present invention will be described below with reference to FIG.

In the embodiment shown in FIG. 1, the micro program control unit 14 for controlling the arithmetic operation and the error recovery processing operation based on the input signal, and the first arithmetic processing for carrying out the same arithmetic processing based on the control signal from the micro program control unit 14 are provided. Computing unit 11,
A second arithmetic unit 12, a third arithmetic unit 13, a first comparison circuit 4 for comparing the arithmetic result data from the first arithmetic unit 11 with the arithmetic result data from the second arithmetic unit 12, The second comparison circuit 5 for comparing the calculation result data from the second calculation unit 12 and the calculation result data from the third calculation unit 13 is provided. Further, a determination circuit 2 that determines correct operation result data based on the comparison result of the first comparison circuit 4 and the comparison result of the second comparison circuit 5 and notifies the microprogram control unit 14 of an operation error, and a determination circuit Based on the determination result of No. 2, the operation result data of one of the first operation unit 11, the second operation unit 12, and the third operation unit 13 is selected and output to the outside, and the input data from the outside is selected. The selection / distribution circuit 1 that outputs to the first calculation unit 11, the second calculation unit 12, and the third calculation unit 13, and the register data in the calculation unit that has caused a calculation error via the selection / distribution circuit 1 The external register 3 stores normal register data for updating the data.

Next, the operation of this embodiment will be described.

.. Data is externally input to the selection / distribution circuit 1.

.. The selection / distribution circuit 1 outputs the input data to the first arithmetic unit 11, the second arithmetic unit 12, and the third arithmetic unit 13.

.. First arithmetic unit 11 and second arithmetic unit 12
And the third arithmetic unit 13 executes the same arithmetic operation based on the control signal from the microprogram controller 14.

.. The first comparison circuit 4 includes the first arithmetic unit 11
And the operation result data from the second operation unit 12 are compared.

.. The second comparison circuit 5 includes the second arithmetic unit 12
And the operation result data from the third operation unit 13 are compared.

.. The determination circuit 2 determines correct operation data based on the comparison result of the first comparison circuit 4 and the comparison result of the second comparison circuit 5. For example, when the comparison result of the first comparison circuit 4 is the same as the comparison result of the second comparison circuit 5, the calculation results of the calculation units 11, 12, and 13 are determined to be correct. When the comparison result of the first comparison circuit 4 does not match and the comparison result of the second comparison circuit 5 matches, it is determined that the calculation results of the second calculation unit 12 and the third calculation unit 13 are correct. First
When the comparison result of the comparison circuit 4 and the comparison result of the second comparison circuit 5 do not match, it is determined that the calculation results of the first calculation unit 11 and the second calculation unit 12 are correct. When the comparison result of the first comparison circuit 4 does not match and the comparison result of the second comparison circuit 5 does not match, it is determined that the calculation results of the first calculation unit 11 and the third calculation unit 13 are correct.

[0020]. Based on the judgment result from the judgment circuit 2, the selection / distribution circuit 1 takes in the calculation result from the initialized calculation unit and outputs it to the outside when the initialized calculation unit is normal. On the other hand, if the initially set arithmetic unit is abnormal, the setting is switched and the arithmetic result from the normal arithmetic unit is fetched and output to the outside.

[0021]. When the comparison results of the first comparison circuit 4 or the second comparison circuit 5 do not match, the determination circuit 2 sends a mismatch signal to the microprogram control unit 14.

.. When the microprogram control unit 14 receives the non-coincidence signal from the determination circuit 2, it branches the microprogram from the normal operation, writes the contents of the register in the normal operation unit to the external register 3 via the selection / distribution circuit 1, and outputs the operation error. The error data is restored by writing to the register in the arithmetic unit that caused the error. When the writing to all the registers is completed, the micro program returns to the normal operation.

Even if the number of arithmetic units increases, the present invention can be realized by increasing the number of comparison circuits.

[0024]

Since the present invention is constructed and functions as described above, it is possible to eliminate the accumulation of errors even if one of the arithmetic units produces an arithmetic error.
It is possible to provide an unprecedented excellent arithmetic device that can continue normal arithmetic operation even if arithmetic errors due to soft errors or the like occur successively in different arithmetic units.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing an embodiment of the present invention.

FIG. 2 is a configuration diagram showing a conventional example.

[Explanation of symbols]

 1: Selection / Distribution Circuit 2: Judgment Circuit 4: First Comparison Circuit 5: Second Comparison Circuit 11: First Operation Unit 12: Second Operation Unit 13: Third Operation Unit 14: Micro Program Control Department

Claims (2)

[Claims] 1. A microprogram control unit for controlling arithmetic operation, first to third arithmetic units for performing the same arithmetic processing based on a control signal from the microprogram control unit, and the first arithmetic operation. A first comparison circuit for comparing the operation result data from the second operation unit with the operation result data from the second operation unit; the operation result data from the second operation unit and the operation from the third operation unit A second comparison circuit for comparing result data, a determination circuit for determining correct operation result data based on the comparison result of the first comparison circuit and the comparison result of the second comparison circuit, and the determination of this determination circuit Based on the result, one operation result data of the first to third operation units is selected and output to the outside, and input data from the outside is output to each of the first to third operation units. Choice / Minute An arithmetic unit comprising: a distribution circuit. 2. A microprogram control unit for controlling an arithmetic operation and an error recovery processing operation based on an input signal, and three first to third units for performing the same arithmetic processing based on a control signal from the microprogram control unit. An operation unit, a first comparison circuit for comparing operation result data from the first operation unit with operation result data from the second operation unit, and operation result data from the second operation unit. The third
A second comparison circuit for comparing the calculation result data from the calculation unit, and correct calculation result data based on the comparison result of the first comparison circuit and the comparison result of the second comparison circuit and a calculation error A determination circuit for notifying the microprogram control unit of the above, and based on the determination result of the determination circuit, one of the first to third operation units, which is the operation result data, is selected and output to the outside and A selection / distribution circuit for outputting the input data from the above to the first to third calculation units, and for updating the register data in the calculation unit in which a calculation error has occurred via this selection / distribution circuit to normal data. An arithmetic unit comprising an external register for storing normal register data.