JPH0521609A - Semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a stabilized through hole contact stepping shape by forming the corners of at least a single crystal silicon island located in close vicinity of the through hole contact into L-shape. CONSTITUTION:The corner shape of a semiconductor element forming region (a single crystal silicon island) 1a, which is located close to a through hole contact 7, is formed into L-shape so that the region 1a is separated from the through hole contact 7. The length (l) of a side of the L-shape should be set at least separated from the through hole contact 7 when isolation interval is the smallest. The through hole contact 7 should be formed on the flat part through the intermediary of the field insulating film 8 on the supporting member layer 5 of an element isolation region. As a result, no effect of irregularity in polishing accuracy in the structure of a dielectric isolation substrate is inflicted, and a stabilized through hole contact stepping shape can be obtained at all times.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a multi-layer wiring structure used in a semiconductor device having dielectric isolation.

[0002]

2. Description of the Related Art In order to realize high integration of semiconductor devices such as ICs and LSIs, interconnection technology between elements formed at high density becomes extremely important. In order to realize this requirement, a technique of forming the wiring into two or more layers is widely used.

The main constituent components of the above-mentioned multilayer wiring structure include a wiring pattern forming each wiring layer, an interlayer insulating film and a through hole contact. The position of the through hole contact is generally formed on the flat portion. On the other hand, when the multilayer wiring structure is applied to the dielectric isolation substrate, the positions of the through holes are generally formed on the isolation region from the viewpoint of the flexibility of pattern layout and high integration.

A multilayer wiring structure applied to a conventional dielectric isolation substrate will be described below with reference to the drawings by way of an example (reference: JP-A-57-45242). Figure 5
5A is a plan view of a conventional multilayer wiring structure, and FIG. 5B is an enlarged cross-sectional view of a portion indicated by II in FIG. 5A.

In these figures, 1 is a single crystal silicon island which will be a semiconductor element forming region, 2 is an isolation insulating film for electrically insulating the single crystal silicon islands 1 from each other, and 3 and 4 are between semiconductor elements. Upper layer wiring and lower layer wiring for functionally coupling to operate the circuit, 5 is a support layer of the dielectric isolation substrate, 6 is an interlayer insulating film for electrically insulating the upper layer wiring 3 and the lower layer wiring 4, Reference numeral 7 is a through-hole contact formed in the interlayer insulating film 6 for electrically connecting the two wirings 3 and 4, 8 is a field insulating film formed on the main surface side of the dielectric isolation substrate, and 9 Is a cross section of the step portion of the through hole contact, and 10 is a cross section of the exposed surface of the dielectric insulating substrate of the isolation insulating film 2.

[0006]

However, in a conventional multi-layer wiring device having a through-hole structure formed on a dielectric isolation substrate, a local increase in current density occurs and so-called electromigration such as voids and hillocks occurs. There was a problem to do.

The above-mentioned increase in current density will be described in detail with reference to the drawings.

As shown in FIG. 5B, in the case of a dielectric isolation substrate, the surface exposed portion 10 of the isolation insulating film 2 is subjected to wet etching or dry etching treatment in the wafer pretreatment step, especially the etching step. Are etched to form depressions. Further, since the oxide film does not grow on the exposed surface portion 10 of the isolation insulating film 2 even in the subsequent oxidation treatment, the recess becomes deeper,
The depth of the depression is usually about 1 μm, though it depends on the number of etching steps and conditions.

Here, when the upper wiring 3 crosses the surface exposed portion 10 of the isolation insulating film 2 at right angles, the wiring resistance value is given the lowest, that is, the XX portion in FIG. 5A, that is, FIG. The current concentrates on the step portion 9 of the through-hole contact in FIG.

As described above, in the case of the dielectric isolation substrate, the position of the through-hole contact is often formed on the isolation region, but in the case of the dielectric isolation having the V groove, the isolation interval W is highly integrated. Although it should be minimized from the viewpoint, the through-hole contact step portion 9 is online with the exposed surface portion 10 of the isolation insulating film (overlaps vertically) with a certain probability because it varies from several μm to several tens μm in terms of polishing accuracy. Therefore, the total step difference in the through-hole contact step portion 9 becomes large, the step coverage of the upper layer wiring 3 deteriorates, and the current density increases.

Therefore, in the semiconductor device having such a multilayer wiring structure, voids and hillocks are frequently generated in the through-hole contact step portion 9 serving as a current concentration point, and electromigration occurs after a certain period of time. There was a problem of causing wiring failure.

In order to prevent the above-mentioned problems, through-hole contacts were often arranged on the element formation region. For example, the thickness of single crystal silicon island is 35 μm.
m, the size of the single crystal silicon island region is 60 to 70.
Since the size of the micrometer is unnecessarily large, a useless area is generated, which hinders the reduction of the chip size.

It is an object of the present invention to provide a semiconductor device having a multi-layer wiring structure which has a highly reliable through-hole contact with less wiring failure and reduced influence of current concentration in the above-mentioned through hole. .

[0014]

In order to achieve the above-mentioned object, according to the present invention, as a multilayer wiring device having a through hole structure formed on a dielectric isolation substrate, a through hole contact is formed in the first embodiment. A part of at least one single crystal silicon island near the region is arranged at least separated from the through hole contact formation region when the separation distance is the minimum.

In the second embodiment, a part of the two single crystal silicon islands adjacent to the through hole contact formation region is arranged at least separated from the through hole contact formation region when the separation distance is minimum. The feature is that the structure is changed.

In the third embodiment, a part of the four single crystal silicon islands adjacent to the through hole contact formation region is arranged at least separated from the through hole contact formation region when the separation distance is the minimum. It is characterized by having a different structure.

Further, in the fourth embodiment, as a multilayer wiring device having a through hole structure formed on a dielectric isolation substrate, when the through hole contact is located on the isolation insulating film, the shape of the through hole contact is isolated. The structure is such that it intersects the insulating film at a certain angle.

[0018]

As described above, according to the present invention, in the through hole structure formed on the dielectric isolation substrate, at least one corner of the single crystal silicon island adjacent to the through hole contact is formed in an L shape or is isolated. By making the structure intersect with the film at a certain angle, the position of the through-hole contact is such that all or most of the position of the through-hole contact is always arranged on the flat part of the support layer through the field insulating film. Therefore, a stable through-hole contact step shape can always be obtained without being affected by variations in polishing accuracy in the structure of the dielectric isolation substrate.

Therefore, the problem of increasing the current density due to the lowering of the step coverage of the upper layer wiring at the step portion of the through hole contact is solved, and the frequency of wiring failure due to electromigration or the like can be reduced.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the semiconductor device of the present invention will be described below with reference to the drawings. It should be noted that the drawings provided below are only schematically illustrated to the extent that the description can be easily understood, and the present invention is not limited to these illustrated examples.

FIG. 1A is a plan view for explaining a first embodiment of a semiconductor device having a multilayer wiring structure according to the present invention.
FIG. 1B is a sectional view of a portion indicated by II in FIG.

In these figures, 1a, 1b and 1c are single crystal silicon islands which will be semiconductor element forming regions, 2 is an isolation insulating film for electrically insulating the single crystal silicon islands 1 from each other, and 3
Reference numerals 4 and 4 respectively denote upper and lower wirings for functionally coupling the semiconductor elements to operate the circuit, 5 is a support layer of the dielectric isolation substrate, and 6 is an upper wiring 3 and a lower wiring 4 electrically. An interlayer insulating film for insulation, 7 is both wirings 3 and 4
Through holes for electrically connecting the interlayer insulating film 6 with each other, 8 is a field insulating film formed on the main surface side of the dielectric isolation substrate, and 9 is a cross section of the step portion of the through hole contact. , 10 is a cross section of the exposed surface of the dielectric isolation substrate of the isolation insulating film.

Here, in FIG. 1A, the shape of the corner of the single crystal silicon island 1 a adjacent to the through hole contact 7 is formed in an L shape so as to be separated from the through hole contact 7. The length l of one side of the L-shape needs to be set so as to be at least separated from the through-hole contact 7 when the separation distance W is minimum (about 1 to 2 μm). Assuming that the length of one side of the through-hole contact 7 is l _TH and the mask misalignment margin between the through-hole contact and the single crystal silicon islands 1a, 1b, 1c is α, the length l of one side of the L-shape is l. It is necessary to set so as to satisfy the condition of ≧ l _TH + α.

As shown in FIG. 1B, the through-hole contact 7 formed under the above conditions is always formed on a flat portion on the support layer 5 in the element isolation region with the field insulating film 8 interposed therebetween. To be done.

FIG. 2 is a plan view for explaining a second embodiment of a semiconductor device having a multilayer wiring structure according to the present invention. The same parts as those in FIG. 1 are designated by the same reference numerals. In this example, in addition to the single crystal silicon island 1a adjacent to the through hole contact 7, the corner of 1b is also formed in an L shape. Here, the relationship between l _x and l _y in the figure is

[0026]

[Equation 1]

It is clear that the following equation holds.

FIG. 3 is a plan view for explaining a third embodiment of a semiconductor device having a multilayer wiring structure of the present invention, and the same parts as those in FIGS. 1 and 2 are designated by the same reference numerals. In this example, in addition to the structure of the second embodiment, the single crystal silicon island 1
The case where the corners c and 1d are also formed in an L shape is shown. Here, the relationship between l _x and l _y in the figure and the length l of one side of the L-shape in the first embodiment is

[0029]

[Equation 2]

It is clear that the following equation holds.

In applying the through-hole structure, the first, second, or third embodiment is applied according to the design rule of the distance between the built-in element formed in the single crystal silicon island and the isolation insulating film. Is desirable.

FIG. 4A is a plan view for explaining a fourth embodiment of a semiconductor device having a multilayer wiring structure according to the present invention, FIG.
(B) and FIG. (C) show II-II and III- in FIG. 4 (A).
FIG. 3 is a sectional view of a portion indicated by III.

Here, in FIG. 4A, the isolation insulating film 2 is formed.
The shape of the through-hole contact 7 adjacent to is substantially quadrangular as in the conventional case, but each side (outer peripheral line) of the isolation insulating film 2 has at least an angle θ (0 ° <θ <90.
It is formed so that a part (angle) of the outer peripheral line intersects at an angle of °, that is, neither parallel nor right angle.

Therefore, the through hole contact step portion 9 of the through hole contact 7 formed under the above conditions.
Most of them are formed on the support layer 5 and on the flat portion of the single crystal silicon island 1 via the field insulating film 8 as shown in FIGS. 4 (B) and 4 (C).

On the other hand, the region where the through-hole contact step portion 9 is formed on the surface exposed portion 10 of the isolation insulating film is shown in FIG.
Only the location of the O mark shown in (A) is shown, and its cross-sectional shape is the same as that in FIG. 5 (B).

[0036]

As described in detail above, according to the first to third embodiments of the present invention, in the through-hole structure formed on the dielectric isolation substrate, at least one single contact near the through-hole contact is formed. By forming the corners of the crystalline silicon island in an L-shape, the positions of the through-hole contacts are always arranged on the flat portion of the support layer through the field insulating film. Therefore, the dielectric isolation substrate is manufactured. Is not affected by variations in polishing accuracy in
A stable through-hole contact step shape can always be obtained.

Therefore, the problem of increasing the current density due to the lowering of the step coverage of the upper wiring at the step of the through-hole contact is solved, and the frequency of wiring failure due to electromigration or the like can be reduced.

For the above reason, the single crystal silicon island
High reliability can be maintained even if through-hole contacts are formed between islands, so there is no need to arrange through-hole contacts on single crystal silicon islands as in the past, so there is no wasted area and chip miniaturization is aimed at. Is possible.

Further, in this through-hole structure, the step coverage of the through-hole contact is improved, and the through-hole contact photolithography can be processed at the flat portion, so that the conventional exposed surface of the isolation insulating film is not affected. The problem of lowering the photolithography accuracy due to the depression can be eliminated, and the through-hole contact diameter can be reduced, and further, the chip can be reduced.

Further, in forming the corners of the single crystal silicon island in the L-shaped structure, there are not two single crystal silicon islands of the L-shaped structure as shown in the second and third embodiments. By sharing the four monocrystalline silicon islands,
Since the length of one side of the L-shape can be reduced, the present invention can be easily applied without affecting the characteristics of the built-in element formed in the single crystal silicon island.

Further, according to the fourth embodiment, in the through hole structure formed on the dielectric isolation substrate, when the position of the through hole contact is at least on the isolation insulating film, the through hole contact shape is Since it has a structure that intersects the isolation insulating film at a certain angle,
The region where the through-hole contact step portion is online with the surface exposed dent portion of the isolation insulating film can be significantly reduced.
Therefore, most of the step portion of the through-hole contact is formed on the flat portion of the support layer or the single crystal silicon island via the field insulating film, and therefore is not affected by the variation in polishing accuracy in manufacturing the dielectric isolation substrate. Therefore, a stable through-hole contact step shape can always be obtained. That is, almost the same effects as those of the first to third embodiments can be obtained.

[Brief description of drawings]

FIG. 1 is a structural diagram of a first embodiment of the present invention.

FIG. 2 is a structural diagram of a second embodiment of the present invention.

FIG. 3 is a structural diagram of a third embodiment of the present invention.

FIG. 4 is a structural diagram of a fourth embodiment of the present invention.

FIG. 5 is a structural diagram of a conventional example.

[Explanation of symbols]

1 Semiconductor element formation area (single crystal silicon island) 2 Separation insulation film 3 Upper layer wiring 4 Lower layer wiring 5 Support layer 6 Interlayer insulation film 7 Through hole contact 8 field insulation film

Claims (3)

[Claims] 1. A semiconductor device having a structure in which a lower-layer wiring and an upper-layer wiring are in contact with each other on the element isolation region of a semiconductor substrate having an element formation region and an element isolation region and are arranged above and below an insulating film, A semiconductor device, wherein all peripheral portions adjacent to a region located under the contact in the element isolation region with a predetermined width are used as element isolation regions. 2. The semiconductor device according to claim 1, wherein the peripheral portion adjacent to the region below the contact is entirely an element isolation region, and thus the element formation around the element isolation region having a contact on the upper portion. A semiconductor device, wherein the region has a cutout portion, and the cutout region of the element formation region is an element isolation region. 3. A semiconductor device having a structure in which a lower-layer wiring and an upper-layer wiring are in contact with each other by being arranged above and below an insulating film in the vicinity of the element isolation region of a semiconductor substrate having an element formation region and an element isolation region A semiconductor device, wherein an outer peripheral line forming an outer periphery of the contact is arranged at a predetermined angle with respect to a boundary line formed by the element isolation region and the element forming region around the contact.