JPH0521590A - Manufacture of dielectric isolation substrate - Google Patents

Manufacture of dielectric isolation substrate

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Publication number
JPH0521590A
JPH0521590A JP17368191A JP17368191A JPH0521590A JP H0521590 A JPH0521590 A JP H0521590A JP 17368191 A JP17368191 A JP 17368191A JP 17368191 A JP17368191 A JP 17368191A JP H0521590 A JPH0521590 A JP H0521590A
Authority
JP
Japan
Prior art keywords
single crystal
semiconductor single
crystal plate
groove
support
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17368191A
Other languages
Japanese (ja)
Inventor
Shuichiro Yamaguchi
周一郎 山口
Yukio Iitaka
幸男 飯高
Hisakazu Miyajima
久和 宮島
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Electric Works Co Ltd
Original Assignee
Matsushita Electric Works Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Works Ltd filed Critical Matsushita Electric Works Ltd
Priority to JP17368191A priority Critical patent/JPH0521590A/en
Publication of JPH0521590A publication Critical patent/JPH0521590A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To obtain a dielectric isolation substrate wherein warp is small and a region available for element formation is wide, by forming a semiconductor island type region and retainer by using the same property material. CONSTITUTION:A semiconductor single crystal plate 6 for a retainer is stuck on a trentch forming surface of a semiconductor single crystal plate 2 for element formation wherein trenches 3 for isolation are formed on the surface and the trench forming surface is covered with an insulating film 4. The surface of the semiconductor single crystal plate 2 for element formation opposite to the trench forming surface is polished until the bottoms of the trenches for isolation are exposed. Thereby a plurality of semiconductor single crystal regions for element formation subjected mutually electrically to dielectric isolation are made to appear.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】この発明は、誘電体(絶縁層)分
離基板の製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a dielectric (insulating layer) separation substrate.

【0002】[0002]

【従来の技術】半導体装置製造用の誘電体分離基板(以
下、適宜「DI基板」と言う)は、互いに電気的に絶縁
分離された素子形成用半導体単結晶領域(以下、適宜
「半導体島状領域」と言う)が支持体上に複数設けられ
てなる構成になっている。従来、誘電体分離基板には反
りが大きいという問題があった。これは、支持体はポリ
シリコン(多結晶シリコン)であるのに対して半導体島
状領域は単結晶であって、形成材料が一方は多結晶で他
方は単結晶と性状の大きく相違するものであったからで
ある。
2. Description of the Related Art A dielectric isolation substrate for producing a semiconductor device (hereinafter referred to as "DI substrate" as appropriate) is a semiconductor single crystal region for element formation (hereinafter referred to as "semiconductor island-like" as appropriate) electrically isolated from each other. A plurality of "regions" are provided on the support. Conventionally, there has been a problem that the dielectric isolation substrate has a large warp. This is because the support is polysilicon (polycrystalline silicon), whereas the semiconductor island-shaped region is single crystal, and the material used is one of which is polycrystalline and the other of which is significantly different in property from single crystal. Because there was.

【0003】そこで、以下のようにして、反りの少ない
誘電体分離基板を得る方法が提案されている。まず、図
8にみるように、2枚の半導体単結晶板81,82を絶
縁膜用の酸化膜83を介して貼り合わせる。一方の半導
体単結晶板81は素子形成用であり、他方の半導体単結
晶板82は支持体用である。ついで、図9にみるよう
に、素子形成用の半導体単結晶板81の表面を研磨し薄
くした後、図10にみるように、素子形成用の半導体単
結晶板81の残りの部分に酸化膜83に達する分離用V
溝84を異方性エッチングにより形成する。
Therefore, a method for obtaining a dielectric isolation substrate with less warpage has been proposed as follows. First, as shown in FIG. 8, two semiconductor single crystal plates 81 and 82 are bonded together with an oxide film 83 for an insulating film interposed therebetween. One semiconductor single crystal plate 81 is for element formation, and the other semiconductor single crystal plate 82 is for a support. Then, as shown in FIG. 9, the surface of the semiconductor single crystal plate 81 for element formation is polished and thinned, and then an oxide film is formed on the remaining portion of the semiconductor single crystal plate 81 for element formation as shown in FIG. Separation V reaching 83
The groove 84 is formed by anisotropic etching.

【0004】その後、図11にみるように、V溝形成面
を絶縁膜用の酸化膜85で覆ってから、図12にみるよ
うに、ポリシリコンの埋立材85でV溝84を埋め立
て、最後に、図13にみるように、V溝形成面側から研
磨して素子形成用半導体島状領域81aの表面を露出さ
せれば、DI基板80が得られる。このDI基板80
は、素子形成用半導体島状領域81aが同じ性状の半導
体単結晶の支持体で支持される構成であるために反りが
少ない。
After that, as shown in FIG. 11, the V-groove forming surface is covered with an oxide film 85 for an insulating film, and then, as shown in FIG. Then, as shown in FIG. 13, the DI substrate 80 can be obtained by polishing from the V groove forming surface side to expose the surface of the element forming semiconductor island region 81a. This DI board 80
Has a small warp because the element-forming semiconductor island region 81a is supported by a semiconductor single crystal support having the same properties.

【0005】[0005]

【発明が解決しようとする課題】しかしながら、上記誘
電体分離基板80は、反りは小さいのであるが、素子形
成可能域も小さいという欠点がある。素子形成用半導体
島状領域81aの表面積(露出面の面積)が小さいので
ある。各半導体島状領域81aは、底が広くて表面が狭
くなる形状であるため、素子形成可能域を決める表面積
が狭くなってしまい、実用的とは言えないのである。
However, although the dielectric isolation substrate 80 has a small warp, it has a drawback that the element formation area is also small. The surface area (the area of the exposed surface) of the semiconductor island-shaped region 81a for element formation is small. Since each semiconductor island region 81a has a shape with a wide bottom and a narrow surface, the surface area that determines the element formable region becomes small, which is not practical.

【0006】この発明は、上記事情に鑑み、反りが小さ
く、素子形成可能域は広い誘電体分離基板を得ることの
できる方法を提供することを課題とする。
In view of the above circumstances, it is an object of the present invention to provide a method capable of obtaining a dielectric isolation substrate having a small warp and a wide element formation area.

【0007】[0007]

【課題を解決するための手段】前記課題を解決するた
め、この発明の誘電体分離基板の製造方法では、表面に
分離用溝が形成され溝形成面が絶縁膜で覆われた素子形
成用半導体単結晶板の前記溝形成面の上に支持体用半導
体単結晶板を貼り合わせておいて、前記素子形成用半導
体単結晶板の溝形成面とは反対の面を前記分離用溝の底
が露出するまで研磨することにより、前記支持体の上に
互いに電気的に絶縁分離された複数の素子形成用半導体
単結晶領域を現出させるようにしている。
In order to solve the above-mentioned problems, in the method of manufacturing a dielectric isolation substrate of the present invention, an isolation semiconductor is formed on the surface thereof, and the isolation surface is covered with an insulating film. A semiconductor single crystal plate for a support is bonded on the groove forming surface of the single crystal plate, and a surface opposite to the groove forming surface of the element forming semiconductor single crystal plate is a bottom of the separation groove. By polishing until it is exposed, a plurality of element-forming semiconductor single crystal regions electrically isolated from each other are exposed on the support.

【0008】この発明では、普通、請求項2のように、
支持体用半導体単結晶板の溝を埋立材で埋めておいてか
ら、支持体用半導体単結晶板を貼り合わせる。通常、埋
立材の埋め跡を研磨して平らにしてから支持体用半導体
単結晶板を貼り合わせるようにする。また、支持体用半
導体単結晶板を貼り合わせる場合、張り合わせ面に酸化
膜を介在させる場合と介在させない場合とがある。後者
の酸化膜を介在させない場合は工程数が少なくて済むと
いう利点がある。
According to the present invention, as described in claim 2,
After filling the groove of the semiconductor single crystal plate for support with the landfill material, the semiconductor single crystal plate for support is bonded. Usually, the filling marks of the landfill material are polished to be flat, and then the semiconductor single crystal plate for a support is bonded. Further, when a semiconductor single crystal plate for a support is bonded, an oxide film may or may not be interposed on the bonding surface. If the latter oxide film is not interposed, there is an advantage that the number of steps can be reduced.

【0009】この発明における素子形成用や支持体用の
半導体単結晶板としては、例えばシリコン単結晶板が用
いられ、埋立材としては、例えばポリシリコンが用いら
れるが、これらに限らないことは言うまでもない。
The semiconductor single crystal plate for element formation and the support in the present invention is, for example, a silicon single crystal plate, and the landfill material is, for example, polysilicon, but it is not limited to these. Yes.

【0010】[0010]

【作用】この発明で得られるDI基板は、半導体島状領
域と支持体が共に半導体単結晶と同じ性状の材料で出来
ているために反りが小さい。この発明で得られるDI基
板は、各半導体島状領域が、表面側が広く底にいくほど
狭くなるという従来とは逆の形状であるため、素子形成
可能域を決める表面積が広く、これに伴って素子可能域
が拡がったのである。これは、この発明の方法では、溝
形成面(溝の開口のある面)と反対の面(溝の底が位置
する断面)が半導体島状領域の表面となるようDI基板
を作製するからである。
The DI substrate obtained by the present invention has a small warp because both the semiconductor island region and the support are made of the same material as the semiconductor single crystal. The DI substrate obtained by the present invention has a shape in which each semiconductor island region is wider on the surface side and narrower toward the bottom, which is the reverse of the conventional shape. Therefore, the surface area that determines the element formable region is large. The device feasible range has expanded. This is because in the method of the present invention, the DI substrate is manufactured so that the surface opposite to the groove forming surface (the surface having the groove opening) (the cross section where the groove bottom is located) becomes the surface of the semiconductor island region. is there.

【0011】すなわち、分離用溝は表面から底に向かう
に従って狭くなっており、溝形成面(溝の開口のある
面)と反対の面(溝の底が位置する断面)との間で、素
子形成可能域となる半導体単結晶の占める面積を比較す
ると、後者の方が広い。それで、後者の溝形成面と反対
の面が半導体島状領域の表面となるように研磨する場合
は、後者の溝形成面が半導体島状領域の表面となるよう
に研磨していた従来の場合に比べ、素子形成可能域とな
る半導体単結晶域が広く、その結果、素子形成可能域が
拡がることとなったのである。
That is, the separation groove is narrowed from the surface toward the bottom, and the element is formed between the groove forming surface (the surface having the groove opening) and the opposite surface (the cross section where the groove bottom is located). Comparing the area occupied by the semiconductor single crystal as the formable region, the latter is wider. Therefore, in the case of polishing so that the surface opposite to the groove forming surface of the latter becomes the surface of the semiconductor island region, in the conventional case where the latter groove forming surface becomes the surface of the semiconductor island region As compared with the above, the semiconductor single crystal region which is the element formable region is wider, and as a result, the element formable region is expanded.

【0012】[0012]

【実施例】以下、この発明の実施例の一例で誘電体分離
基板を作製する時の様子を図面を参照しながら詳しく説
明する。勿論、この発明は下記の実施例に限らない。 −実施例1− 実施例1では以下のようにしてDI基板を得た。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The manner in which a dielectric isolation substrate is manufactured according to an embodiment of the present invention will be described in detail below with reference to the drawings. Of course, the present invention is not limited to the following embodiments. -Example 1-In Example 1, a DI substrate was obtained as follows.

【0013】まず、図2に示す素子形成用の半導体単結
晶板2、すなわち、表面に分離用V溝3が形成され溝形
成面が絶縁層4で覆われた単結晶板2を、以下のように
して準備する。最初に、半導体単結晶板2の片面に、図
1にみるように、異方性エッチングで分離用V溝3を形
成し、ついで、半導体単結晶板2のV溝形成面を絶縁膜
用の酸化膜(例えば、SiO2 膜)4で覆うのである。
First, the semiconductor single crystal plate 2 for element formation shown in FIG. 2, that is, the single crystal plate 2 in which the V groove 3 for isolation is formed on the surface and the groove forming surface is covered with the insulating layer 4 is described below. To prepare. First, as shown in FIG. 1, the isolation V groove 3 is formed on one surface of the semiconductor single crystal plate 2 by anisotropic etching, and then the V groove formation surface of the semiconductor single crystal plate 2 is used as an insulating film. It is covered with an oxide film (eg, SiO 2 film) 4.

【0014】つぎに、図3にみるように、ポリシリコン
(埋立材5)を堆積しV溝3を埋めてから埋め跡を研磨
して平らにする。そして、その上に支持体用の半導体単
結晶板を張り合わせる。すなわち、図4にみるように、
酸化膜(例えば、SiO2 膜)7を介して支持体用の半
導体単結晶板6を貼り合わせるのである。酸化膜を埋立
材の表面と支持体用の半導体単結晶板の張り合わせ側表
面の両方もしくは片方に予め形成しておいて接合するよ
うにする。
Next, as shown in FIG. 3, polysilicon (filling material 5) is deposited to fill the V-grooves 3 and then the fill marks are polished to be flat. Then, a semiconductor single crystal plate for a support is bonded onto it. That is, as shown in FIG.
The semiconductor single crystal plate 6 for a support is bonded via an oxide film (eg, SiO 2 film) 7. An oxide film is previously formed on both or one of the surface of the landfill material and the surface of the semiconductor single crystal plate for support, which is on the bonding side, and is then bonded.

【0015】最後に、図5にみるように、素子形成用の
半導体単結晶板2の裏面(分離用溝形成面と反対の面)
側から分離用V溝3の底が露出するまで研磨すれば、D
I基板1が得られる。得られたDI基板1では互いに電
気的に絶縁分離された半導体島状領域1a・・・複数が
支持体上に現出している。各半導体島状領域1aは表面
側が底側より大きい形状をしており、素子形成可能域が
広くなっている。勿論、半導体島状領域1aと支持体は
同じ半導体単結晶で出来ており、反りが少ないことは言
うまでもない。
Finally, as shown in FIG. 5, the back surface of the semiconductor single crystal plate 2 for element formation (the surface opposite to the separation groove formation surface).
If polishing is performed from the side until the bottom of the separation V groove 3 is exposed,
I substrate 1 is obtained. In the obtained DI substrate 1, a plurality of semiconductor island-like regions 1a electrically isolated from each other are exposed on the support. Each semiconductor island region 1a has a shape in which the surface side is larger than the bottom side, and the element formable region is wide. Needless to say, the semiconductor island region 1a and the support are made of the same semiconductor single crystal, and warp is small.

【0016】−実施例2− 実施例2では、実施例1と同様、図1〜3にみるように
して、素子形成用の半導体単結晶板2のV溝3を埋立材
5で埋めてから埋め跡を研磨して平らにしておいて、つ
ぎに、実施例1とは異なり、図6にみるように、酸化膜
を介さずに支持体用の半導体単結晶板6を埋立材5に直
に貼り合わせる。
Example 2 In Example 2, as in Example 1, as shown in FIGS. 1 to 3, after filling the V groove 3 of the semiconductor single crystal plate 2 for element formation with the landfill material 5, The filling marks are ground and flattened, and then, unlike in the first embodiment, as shown in FIG. 6, the semiconductor single crystal plate 6 for the support is directly attached to the filling material 5 without an oxide film. Pasted on.

【0017】続いて、図7にみるように、素子形成用の
半導体単結晶板2の裏面(分離用溝形成面と反対の面)
側から分離用V溝3の底が露出するまで研磨すれば、D
I基板1が得られる。得られたDI基板1では、やは
り、互いに電気的に絶縁分離された半導体島状領域1a
・・・複数が支持体上に現出している。各半導体島状領
域1aは表面側が底側より大きい形状をしており、素子
形成可能域が広くなっている。
Subsequently, as shown in FIG. 7, the back surface of the semiconductor single crystal plate 2 for element formation (the surface opposite to the separation groove formation surface).
If polishing is performed from the side until the bottom of the separation V groove 3 is exposed,
I substrate 1 is obtained. In the obtained DI substrate 1, again, the semiconductor island regions 1a electrically isolated from each other are formed.
... A plurality of them appear on the support. Each semiconductor island region 1a has a shape in which the surface side is larger than the bottom side, and the element formable region is wide.

【0018】実施例2の場合を実施例1の場合と比較す
ると、素子形成用の半導体単結晶板2と支持体用の半導
体単結晶板6の間に酸化膜を介在させないため、酸化膜
形成工程が不要となった分だけ工程数が減るという利点
がある。
Comparing the case of Example 2 with the case of Example 1, an oxide film is not formed between the semiconductor single crystal plate 2 for forming the element and the semiconductor single crystal plate 6 for the support, and thus the oxide film is formed. There is an advantage that the number of steps is reduced by the amount of steps not required.

【0019】[0019]

【発明の効果】以上に述べたように、この発明で得られ
るDI基板は、半導体島状領域と支持体が共に同じ性状
の材料で出来ているために反りが小さく、しかも、各半
導体島状領域の表面積が大きいために素子可能域が拡が
っており、非常に実用的である。
As described above, the DI substrate obtained according to the present invention has a small warp because the semiconductor island region and the support are made of the same material, and each semiconductor island region has a small warp. Since the surface area of the region is large, the element feasible region is widened, which is very practical.

【図面の簡単な説明】[Brief description of drawings]

【図1】実施例1での分離用溝形成工程説明用の断面図
である。
FIG. 1 is a cross-sectional view for explaining a separation groove forming process in a first embodiment.

【図2】実施例1での溝形成面を覆う酸化膜形成工程説
明用の断面図である。
FIG. 2 is a cross-sectional view for explaining an oxide film forming step for covering a groove forming surface in the first embodiment.

【図3】実施例1での分離用溝埋立工程説明用の断面図
である。
FIG. 3 is a cross-sectional view for explaining a separation groove burying process in the first embodiment.

【図4】実施例1での支持体用の半導体単結晶板貼合工
程説明用の断面図である。
FIG. 4 is a cross-sectional view for explaining a step of laminating a semiconductor single crystal plate for a support in Example 1.

【図5】実施例1で得られたDI基板をあらわす断面図
である。
5 is a cross-sectional view showing the DI substrate obtained in Example 1. FIG.

【図6】実施例2での支持体用の半導体単結晶板貼合工
程説明用の断面図である。
FIG. 6 is a cross-sectional view for explaining a semiconductor single crystal plate bonding step for a support in Example 2.

【図7】実施例2で得られたDI基板をあらわす断面図
である。
FIG. 7 is a cross-sectional view showing a DI substrate obtained in Example 2.

【図8】従来方法での半導体単結晶板貼合工程説明用の
断面図である。
FIG. 8 is a cross-sectional view for explaining a semiconductor single crystal plate bonding step in a conventional method.

【図9】従来方法での半導体単結晶板の表面研磨工程説
明用の断面図である。
FIG. 9 is a cross-sectional view for explaining a surface polishing process of a semiconductor single crystal plate by a conventional method.

【図10】従来方法での分離用溝形成工程説明用の断面図
である。
FIG. 10 is a cross-sectional view for explaining a separation groove forming step in a conventional method.

【図11】従来方法での分離用溝形成面を覆う酸化膜形成
工程説明用の断面図である。
FIG. 11 is a cross-sectional view for explaining an oxide film forming step for covering a separation groove forming surface by a conventional method.

【図12】従来方法での分離用溝埋立工程説明用の断面図
である。
FIG. 12 is a cross-sectional view for explaining a separation groove burying step in a conventional method.

【図13】従来方法で得られたDI基板をあらわす断面図
である。
FIG. 13 is a cross-sectional view showing a DI substrate obtained by a conventional method.

【符合の説明】[Explanation of sign]

1 誘電体分離基板 1a 素子形成用半導体単結晶領域(半導体島状領域) 2 素子形成用半導体単結晶板 3 分離用V溝 4 絶縁膜用の酸化膜 5 溝埋立材 6 支持体用半導体単結晶板 7 酸化膜 1 Dielectric isolation substrate 1a Semiconductor single crystal region for element formation (semiconductor island region) 2 Semiconductor single crystal plate for element formation 3 V groove for separation 4 Oxide film for insulating film 5 groove landfill 6 Semiconductor single crystal plate for support 7 Oxide film

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 表面に分離用溝が形成され溝形成面が絶
縁膜で覆われた素子形成用半導体単結晶板の前記溝形成
面の上に支持体用半導体単結晶板を貼り合わせておい
て、前記素子形成用半導体単結晶板の溝形成面とは反対
の面を前記分離用溝の底が露出するまで研磨することに
より、前記支持体の上に互いに電気的に絶縁分離された
複数の素子形成用半導体単結晶領域を現出させるように
する誘電体分離基板の製造方法。
1. A semiconductor single crystal plate for a support is bonded onto the groove forming surface of an element forming semiconductor single crystal plate having a separation groove formed on the surface and a groove forming surface covered with an insulating film. A plurality of electrically isolated layers are formed on the support by polishing a surface of the element-forming semiconductor single crystal plate opposite to the groove forming surface until the bottom of the separating groove is exposed. A method for manufacturing a dielectric isolation substrate, wherein a semiconductor single crystal region for element formation is exposed.
【請求項2】 支持体用半導体単結晶板の溝を埋立材で
埋めておいてから、支持体用半導体単結晶板を貼り合わ
せる請求項1記載の誘電体分離基板の製造方法。
2. The method for manufacturing a dielectric isolation substrate according to claim 1, wherein the groove of the semiconductor single crystal plate for a support is filled with a filling material, and then the semiconductor single crystal plate for a support is bonded.
JP17368191A 1991-07-15 1991-07-15 Manufacture of dielectric isolation substrate Pending JPH0521590A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17368191A JPH0521590A (en) 1991-07-15 1991-07-15 Manufacture of dielectric isolation substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17368191A JPH0521590A (en) 1991-07-15 1991-07-15 Manufacture of dielectric isolation substrate

Publications (1)

Publication Number Publication Date
JPH0521590A true JPH0521590A (en) 1993-01-29

Family

ID=15965132

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17368191A Pending JPH0521590A (en) 1991-07-15 1991-07-15 Manufacture of dielectric isolation substrate

Country Status (1)

Country Link
JP (1) JPH0521590A (en)

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