JPH05215821A - Lsi with built-in printed circuit board inspecting circuit - Google Patents

Abstract

PURPOSE:To carry out an inspection easily even on a manufacturing line by conducting signal inspections only on inspection places by at least the number of LSIs in relation to a wiring result of a printed board when plural number of LSIs are mounted. CONSTITUTION:A selecting circuit 33 takes in selectively test signals of input terminals 13 and 14, and gives the test signals, to a counter control circuit 36 through a selector 35. This control circuit 36 detects a specific period of the test signals, and drives a counter 37, and generates test signals similar to the test signals on the inside. A comparing circuit 38 can obtain a result by judging normality or abnormality of wirings 11 and 12 according to the fact that an input test signal and an internally generating test signal are equal to each other or not, and can obtain a judged result to an output terminal 32. The internally generating test signal can be supplied to a wiring being connected to the following stage LSI by means of selectors 22-25, and the normality or abnormality of the wiring connection can be detected in a test circuit similar to the following stage.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a printed circuit board inspection circuit built-in LS in which a printed circuit board inspection circuit is built in an LSI.
Regarding I.

[0002]

2. Description of the Related Art Nowadays, digitalization of signal processing is being promoted in various systems including EDTV type television receivers. Nowadays, the complexity of the system and the limit / consumption of the integration degree of LSI (Large Scale Integrated Circuit) are increased. Due to the increase in power and the like, it is difficult to realize the system itself with a one-chip LSI.

On the other hand, a system using a plurality of LSIs is
As the system becomes more complicated, the number of terminals increases, and the inspection time of a printed board on which a large number of such LSIs are mounted tends to increase accordingly.

FIG. 6A shows a printed circuit board inspection (LSI
This is an example of a conventional technique in which a circuit (selector) for facilitating wiring inspection) is incorporated in an LSI. Below, FIG.
The configuration of (A) will be described.

In the figure, an n-bit digital signal input from the input terminal 3 of the LSI is supplied to the signal processing circuit 8 and the selector 9. Similarly, n input from terminal 4
The bit signal is supplied to the signal processing circuit 8 and the selector 10. The signal processing circuit 8 performs signal processing based on the signals supplied from the terminals 3 and 4, and outputs the result to the selector 9
Supply to 10. The selector 9 selects one of the signal supplied from the terminal 3 and the signal supplied from the signal processing circuit 8 based on the signal supplied from the terminal 7, and outputs the selected signal to the terminal 5. Similarly, the selector 10 selects either the signal supplied from the terminal 3 or the signal supplied from the signal processing circuit 8 based on the signal supplied from the terminal 7, and outputs the selected signal to the terminal 6. Output terminal 5 of LSI 1 and LSI
The input terminal 13 of 2 is connected to the wiring 11 on the printed circuit board, and the output terminal 6 of the LSI 1 and the input terminal 14 of the LSI 2 are connected to the wiring 12 on the printed circuit board, respectively, and the signal output to the terminal 5 is connected to the terminal 13. Then, the signal output to the terminal 6 is supplied to the terminal 14, respectively. The signal supplied to the terminal 13 is supplied to the signal processing circuit 21 and the selector 22 of the LSI 2. Similarly, the signal supplied to the terminal 14 is supplied to the signal processing circuit 21 and the selector 23. Terminal 1
The n-bit signal input from the signal 5 is input to the signal processing circuit 21.
To the selectors 24 and 25. Signal processing circuit 21
Performs signal processing based on the signals supplied from the terminals 13, 14, 15 and outputs the result to the selectors 22, 23, 2
Supply to 4,25. The selector 22 selects one of the signal supplied from the terminal 13 and the signal supplied from the signal processing circuit 21 based on the signal supplied from the terminal 20, and outputs the selected signal to the terminal 16. Similarly, the selector 23
Based on the signal supplied from the terminal 20, either the signal supplied from the terminal 14 or the signal supplied from the signal processing circuit 21 is selected and output to the terminal 17. The selectors 24 and 25 select one of the signal supplied from the terminal 15 and the signal supplied from the signal processing circuit 21 based on the signal supplied from the terminal 20, and output it to the terminals 18 and 19, respectively.

FIG. 6B is a diagram showing an example of a test signal when inspecting a printed circuit board. A method of inspecting a printed circuit board in the embodiment of FIG. 9A will be described with reference to FIG. The same figure (B) shows 26A, 26B, 26.
It is a signal waveform diagram of 4 bits of C and 26D.
When SB and 26A are MSBs, 0 to 15 in period 27
Changes with the value of. In FIG. 6A, n = 4 bits is set, and the signal of FIG. 6B is given to the terminals 3 and 4. According to the signal supplied to the terminal 7, the selector 9 outputs the signal supplied from the terminal 3 to the terminal 5, and the selector 10 outputs the signal to the terminal 4.
The signal supplied from is output to the terminal 6. Similarly terminal 2
According to the signal supplied to 0, the selector 22 outputs the signal supplied from the terminal 13 to the terminal 16, the selector 23 outputs the signal supplied from the terminal 14 to the terminal 17, and the selectors 24 and 25 supply from the terminal 15. Signal to be sent to terminal 1
Output to 8 and 19, respectively. The signal of FIG. 1B given to the terminal 3 of the LSI 1 is sent to the terminal 11 via the selector 9.
And is supplied to the input terminal 13 of the LSI 2 through the wiring 11 on the printed board. Further, the signal is output to the terminal 16 via the selector 22. The signal of FIG. 1B given to the terminal 4 of the LSI 1 is output to the terminal 12 via the selector 10 and is supplied to the input terminal 14 of the LSI 2 through the wiring 12 on the printed board. Further, the signal is output to the terminal 17 via the selector 23. The connection of the wirings 11 and 12 on the printed circuit board is inspected for the terminals 3 and 4.
By applying the signal shown in FIG.
It is possible to inspect whether or not the same signal waveform as in FIG.

[0007]

Using the above-mentioned conventional technique, a plurality of LSs existing from the input to the output of the system are present.
It can be inspected without checking all the terminals of the I wiring. However, in reality, as the system becomes more complicated, not only an LSI having one output for one input, but also a plurality of outputs for one input or one for multiple inputs In many cases, an LSI having one output exists in the system. Therefore, in the conventional technique shown in FIG. 6, it is not possible to perform the inspection with only the final stage LSI, and it is necessary to inspect each output terminal for an n-bit signal. However, there is a problem in that it is not possible to easily find defects such as defective solder. Further, when an abnormality is found in the input of an LSI in the middle of the signal path among a plurality of LSIs mounted on the board, the wiring cannot be inspected for the subsequent LSI, so the inspection must be temporarily interrupted. There was the problem of not becoming.

Therefore, according to the present invention, the output of each LSI can be used to easily inspect the normality or abnormality of the wiring on the input side, and the entire wiring can be inspected using the output of the final stage LSI. It is also an object of the present invention to provide a printed circuit board inspection circuit built-in LSI capable of reducing the number of terminals for taking out inspection results.

[0009]

According to the present invention, a selecting means for selecting any one of a plurality of input signals input to an LSI and a specific period of the signal selected by the selecting means are detected. Detection means for outputting as a detection signal, means for generating a test signal similar to the input signal, which is controlled by the detection signal, and means for outputting the test signal to a terminal for outputting a signal processing result of the LSI. Comparing means for comparing the test signal with the output signal of the selecting means, and means for outputting the comparison result of the comparing means to the outside of the LSI.

[0010]

In the wiring inspection of the printed circuit board of an LSI having a plurality of n-bit input terminals, it has conventionally been necessary to inspect at least one set of n-bit terminals. According to the above means, means for selecting any one of the plurality of inputs;
The wiring inspection is performed by the means for comparing the selected signal with the test signal generated in synchronism with the signal obtained by the means and outputting the result. It is possible to quickly check whether or not the inputs from all the lines are normal by simply giving the above-mentioned result and checking the comparison result output. Further, when a large number of LSIs are connected, it is possible to detect the normality of the entire wiring by monitoring the final result of the comparison result synthesis output.

[0011]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing an embodiment of the present invention.
The n-bit digital signal input to the input terminal 13 of the LSI 2 is supplied to the signal processing circuit 21, the selection circuit 32, and the selectors 22, 23, 24, 25. Selector 2
2, 23, 24, and 25 are either one of the signal supplied from the terminal 13 based on the signal supplied from the terminal 20 and the signal supplied from the signal processing circuit 21 to the selectors 22, 23, 24, and 25, respectively. Select, and terminals 16 and 1
It outputs to 7, 18, and 19, respectively. The n-bit signal input from the terminal 14 is supplied to the signal processing circuit 21 and the selection circuit 33, and similarly, the n-bit signal input from the terminal 15 is supplied to the signal processing circuit 21 and the selection circuit 33. The selection circuit 33 selects one of the signals supplied from the terminals 13, 14 and 15 based on the first selection signal supplied from the terminal 28, and supplies the selected signal to the selector 35 and the comparison circuit 38.

The selector 35 selects either the signal from the selection circuit 33 or the signal from the counter 37 based on the second selection signal supplied from the terminal 29 and supplies it to the counter control circuit 36.

The counter control circuit 36 generates a counter control signal indicating a specific period of the signal from the selector 35,
The counter control signal is supplied to the output terminal 31 and the counter 37. The counter 37 is initialized by a counter control signal, performs a counting operation, and outputs an n-bit comparison test signal.
3, 24, 25 and 35, and a comparison circuit 3
Also supplies 8.

The comparison circuit 38 compares the signal supplied from the selection circuit 33 with the comparison test signal from the counter 37, and supplies the result to the comparison signal synthesis circuit 40. The delay circuit 39 is the first circuit supplied from the terminal 30.
And is supplied to the comparison signal synthesizing circuit 40 as the comparison signal. Now, in contrast to the above LSI2, the input side is LSI1
Are connected. The LSI 1 is assumed to be configured as follows.

The n-bit digital signal input from the input terminal 3 is supplied to the signal processing circuit 8 and the selector 9. Similarly, the n-bit signal input from the terminal 4 is supplied to the signal processing circuit 8 and the selector 10. The signal processing circuit 8 performs signal processing based on the signals supplied from the terminals 3 and 4, and supplies the result to the selectors 9 and 10. The selector 9 selects one of the signal supplied from the terminal 3 and the signal supplied from the signal processing circuit 8 based on the signal supplied from the terminal 7, and outputs the selected signal to the terminal 5. Similarly, the selector 10 selects either the signal supplied from the terminal 3 or the signal supplied from the signal processing circuit 8 based on the signal supplied from the terminal 7, and outputs the selected signal to the terminal 6. The output terminal 5 of the LSI 1 and the input terminal 13 of the LSI 2 are wirings 11 on the printed circuit board, and the output terminal 6 of the LSI 1 and the input terminal 14 of the LSI 2 are wirings 1 on the printed circuit board.
The signals output to the terminal 5 are supplied to the terminal 13, and the signal output to the terminal 6 is supplied to the terminal 14, respectively.

FIG. 2A shows the counter control circuit 3 of FIG.
It is a figure which shows the specific structural example of 6. FIG. 2B is a signal waveform diagram for explaining the circuit of FIG. Further, FIGS. 7C and 7D are specific examples of the comparison signal synthesis circuit 40. The embodiment of FIG. 1 will be described in more detail with reference to FIG. Further, the n-bit signal in FIG. 1 is assumed to be 4 bits in order to simplify the explanation.

Signals of waveform signals 34A, 34B, 34C and 34D are supplied to the terminals 34 ₁ , 34 ₂ , 34 ₃ and 34 ₄ from the selection circuit 33 of FIG. These signals are
The logical product is obtained and output to the output terminal 31. The output terminal 31 (input signal to the counter 37) becomes the waveform signal 31A of FIG. 2 (B).

The counter 37 is initialized by the clock signal input during the high level period of the waveform signal 31A, and performs the counting operation during the low level period. The signal obtained from the counter 37 is 37A, 3 in FIG.
7B, 37C, 37D waveform signals. This signal is
The comparison test signal is supplied to the comparison circuit 38, the selector 35, and the like.

That is, when the test signal is input, if the system is normal, the counter 3 is operated during the specific period of the test signal.
7 is initialized and performs a counting operation to generate a comparison test signal having a waveform and timing similar to those of the test signal.

The comparison signal and the test signal are compared by a comparison circuit 36.
Is supplied to. The comparison circuit 36 compares whether the two signals have the same waveform, and the result is compared with the comparison signal synthesizing circuit 4
Supply to 0. The comparison signal synthesis circuit 40 outputs the comparison result to the output terminal 32. Therefore, in the LSI2 part,
When inspecting the state of the wirings 11 and 12, between the pulses indicating the specific period obtained from the terminal 31, the terminal 3
Depending on what level of output is obtained from 2,
It is possible to determine whether the wiring is abnormal or normal during the test.

2C and 2D are views showing a concrete example of the comparison signal synthesizing circuit 37 of FIG. The comparison signal synthesis circuit 37 is used when a large number of LSIs are connected. FIG. 2C is a circuit showing a match when the output of the comparison circuit is at a low level and a mismatch when the output of the comparison circuit is at a high level. Further, FIG. 2D is a circuit showing a match when the output of the comparison circuit 38 is at a high level and a mismatch when the output of the comparison circuit 38 is at a low level. The output from the comparison circuit 38 is input to the terminal 40A of each circuit.

The selector 35 can select and derive the signal from the selection circuit 33 or the counter 37 by the second selection signal from the terminal 29. This is LS
This is because I can be operated as a test signal generator. When the selector 35 selects only the output of the counter 37, this LSI can be used as a test signal generator. Counter control circuit 36
Detects the specific period of the test signal output from the counter 37 and initializes the counter 37. The counter 37 counts clocks from the initial setting and outputs a test signal. In this case, the non-coincidence output is obtained from the comparison circuit 38.

FIG. 3 shows another embodiment of the present invention. The difference from the embodiment of FIG. 1 is that the specific period detection signal (counter control signal) output from the counter control circuit 36 is
This is input to the control prohibition circuit 41. The output of the control prohibiting circuit 41 is supplied to the counter 37. A control signal for determining whether or not the counter 37 is controlled by the output of the counter control circuit 41 is input to the terminal 42. Control prohibition circuit 41 by control signal
Supplies a counter control signal to the counter 37 in the control mode, and supplies a signal to keep the counter 37 in the count state in the control prohibit mode. That is, when the counter 37 counts up or counts down, it is possible to control whether the initialization is performed or whether the counter 37 is started from all zeros or all ones.

Next, some examples of actual inspection using the above LSI will be described. Figure 4 shows three LSs
The example shows the case where I43, 44, and 45 are connected through the wiring of the printed board. In each LSI, the parts corresponding to the internal constituent elements of the LSI of FIG. 1 are shown with an alphabetical suffix. The delay circuit is omitted.

First, the LSI 43 is used as a test signal generator, and wirings 56, 57 for connecting the respective LSIs,
58 shall be tested. A control signal for the selector 35a to select the signal from the counter 37a is applied to the terminal 29a. A control signal is applied to the terminal 20a so that the selectors 22a, 23a and 24a select the test signal from the counter 37a. As a result, the LSI 43 can output the signal generated by the counter 37a as a test signal regardless of the input signal supplied to the input terminal 13a.

In the LSI 44, the selector 35b is controlled so as to select the signal from the selection circuit 33b. In addition, the selectors 22b, 23b, 24b are provided with a counter 37.
Controlled to select the signal from b. In this state, the comparison circuit 38b compares the signals from the selection circuit 33b and the counter 37b, and outputs a high level signal or a low level signal (match signal) when they match, and outputs a high level or low level signal when they do not match. A high level signal (mismatch signal) will be output. Here, it is assumed that the match signal is high level and the mismatch signal is low level. At this time, the comparison signal synthesizing circuit 40b operates as shown in FIG.
In the circuit (D), a high level signal is supplied to the terminal 30b.

First, according to the control signal from the terminal 28b,
It is assumed that the selection circuit 33b selects the test signal of the input terminal 13b. Here, the signals of the terminals 31b and 32b are monitored, and the counter control signal (obtained for each cycle of the counter 37b) output to the terminal 31b is observed, and the counter control signal is acquired at the terminal 32b during one cycle of this signal. It is confirmed whether the signal is high level. During this period, terminal 3
If a signal indicating a low level is given to 2b, it means that there is an abnormality in the printed wiring 57, and if it remains at a high level, it means that it is normal. Similarly, when the printed wiring 58 is inspected, the selection circuit 33b causes the input terminal 1
Controlled to select the 4b test signal. The subsequent test method is the same as that described above.

If at least one of the wirings 57 and 58 is normal, the LSI 44 synchronizes the output of the counter 37b with the test signal passing through the normal wiring and outputs the counter output to the next stage. Can be supplied as a test signal to the LSI 45. However, if there is an abnormality in both wirings, the selector 35b is controlled to select the signal from the counter 37b, and this LSI 44 is used as a test signal generator. Thereby, the states of the printed wirings 59, 60, 61 can be tested. That is, similarly to the test using the LSI 44, the selection circuit 3
The state of each wiring can be inspected by selecting 3c and monitoring the output of the terminal 31c and the output of the terminal 32c. Moreover, when the test signal of the input terminal 13c is selected, the state of the wiring 56 can be tested. The last LS
In I45, the selector 35c is omitted because
This is because it is assumed that the LSI does not exist thereafter, and when the LSI of the next stage exists, the selector is incorporated.

Next, the functions of the comparison signal synthesizing circuits 40b and 40c will be described with reference to FIG. The circuit of FIG. 5 differs from the circuit of FIG. 4 in that terminals 32b and 30c are connected.

Regarding the inspection of the wirings, the first purpose is to check that all the wirings 56 to 61 are normal, and the second purpose is to find an abnormal place next. Therefore, the number of LSIs connected is not 10 as shown in FIG.
In the case of reaching the number of pieces, the terminals 31b, 31c, ..., And the terminals 32b, 32c ,. Therefore, the last stage of the LSI, that is, the terminals 31c and 32c in FIG. 5 are monitored, and the output of the comparison circuit 38b of the preceding stage LSI and the comparison circuit 38c of the LSI 45 are monitored.
If the output of is combined by the comparison signal combining circuit 40c so that it can be obtained at the terminal 32c, it can be judged that all the wirings under the selection test are normal unless there is an abnormal waveform. If an abnormality is seen, the LS of the previous stage
The output of the I comparison signal synthesizing circuit is inspected, and if it is normal, it is found that there is an abnormality in the wiring of the input signal selected by the selecting circuit of the subsequent LSI.

[0032]

As described above, according to the present invention,
With respect to the wiring result of the printed circuit board on which a plurality of LSIs are mounted, it is sufficient to perform a signal inspection on at least as many inspection points as the number of LSIs, and the inspection can be easily performed even on the manufacturing line. In addition, since the test signal can be generated by the preceding LSI, the first LS on the printed circuit board can be used.
All that is required is to provide I with a test signal. LSI on the way
When an abnormality is found in the input side wiring, the subsequent LSI can be operated as an original test signal generator, and wiring inspection does not have to be temporarily interrupted, improving work efficiency. To do.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

2A and 2B are a counter control circuit diagram of FIG. 1, a signal waveform diagram shown to explain the operation thereof, and a configuration example of a comparison signal synthesis circuit.

FIG. 3 is a circuit diagram showing another embodiment of the present invention.

FIG. 4 is a circuit diagram showing an application example of the present invention.

FIG. 5 is a circuit diagram showing another application example of the present invention.

FIG. 6 is a circuit block diagram and signal waveform diagram shown for explaining a conventional LSI test system.

[Explanation of symbols]

21 ... Signal processing circuit, 22-25 ... Selector, 33 ... Selection circuit, 35 ... Selector, 36 ... Counter control circuit, 3
7 ... Counter, 38 ... Comparison circuit, 39 ... Delay circuit, 40
... Comparison signal synthesis circuit.

Claims (3)

[Claims] 1. A selection means for selecting any one of a plurality of input signals input to an LSI, and a detection means for detecting at least a specific period of the signal selected by the selection means and outputting it as a detection signal. A means capable of generating a test signal similar to the input signal, which is controlled by the detection signal; a signal output means for outputting the test signal to a terminal for outputting a signal processing result of the LSI; A printed circuit board inspection circuit built-in LSI, comprising: comparison means for comparing output signals of the selection means; and result output means for outputting the comparison result of the comparison means to the outside of the LSI. 2. The detection means obtains the detection signal by selectively using either one of the output signal of the selection means and the test signal from the internal test signal generation means. 1. A printed circuit board inspection circuit-embedded LSI according to 1. 3. The result output means is configured to combine and output a comparison result signal from an LSI external input terminal and a result signal obtained internally. LSI with built-in printed circuit board inspection circuit.