JPH0521565A - Semiconductor device and diffusion depth measuring method using the same - Google Patents
Semiconductor device and diffusion depth measuring method using the sameInfo
- Publication number
- JPH0521565A JPH0521565A JP3173892A JP17389291A JPH0521565A JP H0521565 A JPH0521565 A JP H0521565A JP 3173892 A JP3173892 A JP 3173892A JP 17389291 A JP17389291 A JP 17389291A JP H0521565 A JPH0521565 A JP H0521565A
- Authority
- JP
- Japan
- Prior art keywords
- diffusion region
- diffusion
- measured
- region
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は、例えば混成集積回路装
置等の半導体装置及び該装置を使用する拡散深さ測定方
法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device such as a hybrid integrated circuit device and a diffusion depth measuring method using the device.
【0002】[0002]
【従来の技術】図1は、半導体装置のウエハの拡散深さ
を測定するときの実施状態を示す断面構造図であり、図
中1はウエハである。ウエハ1には不純物原子を拡散さ
せた拡散領域2が形成されている。拡散領域2は一部割
られており、上面から斜め下方に角度θで角度研磨され
ている。この拡散領域2の角度研磨された部分の上面と
下面とを結ぶ斜辺8の長さxを測定し、該長さxにsin
θを乗じると拡散深さが求まる。2. Description of the Related Art FIG. 1 is a sectional structural view showing an implementation state when measuring a diffusion depth of a wafer of a semiconductor device, in which 1 is a wafer. A diffusion region 2 in which impurity atoms are diffused is formed on the wafer 1. The diffusion region 2 is partially divided, and is angle-polished obliquely downward from the upper surface at an angle θ. The length x of the hypotenuse 8 connecting the upper surface and the lower surface of the angle-polished portion of the diffusion region 2 is measured, and the length x is calculated as sin.
Multiplying θ gives the diffusion depth.
【0003】[0003]
【発明が解決しようとする課題】上述の方法はウエハを
割り、拡散領域を角度研磨し、この角度研磨した部分の
上面と下面とを結ぶ斜辺8の長さxを測定し、これにsi
n θを乗じるという煩雑な過程を経て拡散深さを求める
ものであり、長時間を要するという問題があった。According to the method described above, the wafer is diced, the diffusion region is angle-polished, and the length x of the hypotenuse 8 connecting the upper surface and the lower surface of this angle-polished portion is measured.
Since the diffusion depth is obtained through a complicated process of multiplying by n θ, there is a problem that it takes a long time.
【0004】本発明は拡散の深さと水平方向の長さとの
間に一定の関係があることに着目したものであり、半導
体装置に形成された被測定拡散領域に対する間隔が異な
る複数個の比較拡散領域を形成し、電極を設け、FET
構造が形成されている被測定拡散領域と比較拡散領域の
組について電極の間隔を測定したその最小値に所定の係
数を乗じることにより、容易に拡散深さを求めることが
でき、ウエハプロセスの管理及びウエハの高品質化を図
ることができる半導体装置及び該装置を使用する拡散深
さ測定方法を提供することを目的とする。The present invention focuses on the fact that there is a fixed relationship between the depth of diffusion and the length in the horizontal direction, and a plurality of comparative diffusions having different intervals with respect to a measured diffusion region formed in a semiconductor device. Forming a region, providing electrodes, and FET
The diffusion depth can be easily obtained by multiplying the minimum value of the electrode distance measured for the set of the measured diffusion area where the structure is formed and the comparison diffusion area by a predetermined coefficient, and the wafer process management Another object of the present invention is to provide a semiconductor device capable of improving the quality of a wafer and a diffusion depth measuring method using the device.
【0005】[0005]
【課題を解決するための手段】第1発明の半導体装置
は、被測定拡散領域の長手方向に沿って該被測定拡散領
域との間隔が異なる複数個の比較拡散領域を形成し、前
記被測定拡散領域と前記比較拡散領域の組について夫々
一方にソース電極を、また他方にドレイン電極を設け、
これらの間にゲート電極を設けたものである。第2発明
の拡散深さ測定方法は、半導体装置に形成された被測定
拡散領域との間隔が異なる複数個の比較拡散領域を形成
し、前記被測定拡散領域及び前記比較拡散領域の組につ
いて夫々一方にソース電極を、他方にドレイン電極を設
け、これらの間にゲート電極を設けて、FET構造が形
成されているか否かを調べ、FET構造が形成されてい
る組の中でソース電極とドレイン電極との間隔を測定し
たその最小値に所定の係数を乗じるものである。In a semiconductor device according to a first aspect of the present invention, a plurality of comparison diffusion regions having different intervals from the diffusion region to be measured are formed along the longitudinal direction of the diffusion region to be measured, and the comparison target diffusion region is formed. A source electrode is provided on one side and a drain electrode is provided on the other side for each set of the diffusion region and the comparative diffusion region,
A gate electrode is provided between them. A diffusion depth measuring method according to a second aspect of the present invention forms a plurality of comparative diffusion regions having different distances from a measured diffusion region formed in a semiconductor device, and sets a pair of the measured diffusion region and the comparative diffusion region, respectively. A source electrode is provided on one side, a drain electrode is provided on the other side, and a gate electrode is provided between them to check whether or not an FET structure is formed. In the group in which the FET structure is formed, the source electrode and the drain are formed. The minimum value obtained by measuring the distance to the electrode is multiplied by a predetermined coefficient.
【0006】[0006]
【作用】図2はFET構造から抵抗構造に変わる直前の
ソース電極−ドレイン電極の間隔と拡散深さとの関係を
示した断面構造図であり、図中1はウエハである。ウエ
ハ1の上部には拡散領域2,2が設けられている。拡散
領域2,2上には夫々ソース電極3及びドレイン電極4
が設けられており、その間にはゲート電極5が設けられ
ている。図2は拡散領域2と拡散領域2とがショートし
てFET構造から抵抗構造に変わる直前の状態を示して
おり、拡散領域2と拡散領域2とが接している。拡散領
域2の両端の曲面部の横方向の長さと拡散深さとの間に
は一定の関係がある(柳井久義、永田譲:集積回路工学
(1) プロセスデバイス技術編コロナ社 p10
2)。従って拡散領域2の拡散深さをxj とすると拡散
領域2の曲面部の横方向の長さはk×xj で表される
(k:ウエハ1の種類及びウエハ1に注入して拡散領域
2を形成する不純物等によって決まる係数)。ここでソ
ース電極3とドレイン電極4との間隔をxとすると間隔
xは、次式(1)で表される。
x=2×k×xj …(1)
式(1)より拡散深さxj は次式(2)で表される。
xj =x/2k …(2)
本発明においてはこのFET構造から抵抗構造に変わ
る直前のソース電極−ドレイン電極の間隔xとして、F
ET構造が形成されている被測定拡散領域と比較拡散領
域の組について測定したソース電極−ドレイン電極の間
隔の最小値を採用している。従って長時間を要すること
なく前記間隔の最小値から容易に拡散深さxj を求める
ことができる。2 is a sectional structural view showing the relationship between the distance between the source electrode and the drain electrode and the diffusion depth immediately before the change from the FET structure to the resistance structure, in which 1 is a wafer. Diffusion regions 2 and 2 are provided above the wafer 1. A source electrode 3 and a drain electrode 4 are formed on the diffusion regions 2 and 2, respectively.
Are provided, and the gate electrode 5 is provided between them. FIG. 2 shows a state immediately before the diffusion region 2 and the diffusion region 2 are short-circuited to change from the FET structure to the resistance structure, and the diffusion region 2 and the diffusion region 2 are in contact with each other. There is a certain relationship between the lateral lengths of the curved surface portions at both ends of the diffusion region 2 and the diffusion depth (Hisayoshi Yanai, Joe Nagata: Integrated Circuit Engineering (1) Process Device Technology, Corona Company p10.
2). Therefore, assuming that the diffusion depth of the diffusion region 2 is x j , the lateral length of the curved surface portion of the diffusion region 2 is represented by k × x j (k: type of wafer 1 and diffusion region after injection into the wafer 1) Coefficient determined by impurities forming 2). Here, when the distance between the source electrode 3 and the drain electrode 4 is x, the distance x is expressed by the following equation (1). x = 2 × k × x j (1) From equation (1), the diffusion depth x j is represented by the following equation (2). x j = x / 2k (2) In the present invention, F is defined as the distance x between the source electrode and the drain electrode immediately before the FET structure is changed to the resistance structure.
The minimum value of the distance between the source electrode and the drain electrode measured for the set of the measured diffusion region in which the ET structure is formed and the comparative diffusion region is adopted. Therefore, the diffusion depth x j can be easily obtained from the minimum value of the interval without requiring a long time.
【0007】[0007]
【実施例】以下、本発明の方法をその実施例を示す図面
に基づき具体的に説明する。図3及び図4は本発明の実
施状態を示す平面図である。まず、ウエハ1に設けられ
た、深さを測定すべき不純物の拡散領域2aの一方向に
沿って、拡散領域2aとの間隔が異なる比較拡散領域と
しての拡散領域2b、拡散領域2c、拡散領域2dを設
ける(図3)。拡散領域2aとの間隔は拡散領域2b、
拡散領域2c、拡散領域2dの順に大きい。次に拡散領
域2a上にドレイン電極4を、拡散領域2b、拡散領域
2c、拡散領域2d上に夫々ソース電極3b、ソース電
極3c、ソース電極3dを、拡散領域2aと拡散領域2
b、拡散領域2c及び拡散領域2dとの間にゲート電極
5を設ける(図4)。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The method of the present invention will be specifically described below with reference to the drawings showing the embodiments. 3 and 4 are plan views showing an embodiment of the present invention. First, a diffusion region 2b, a diffusion region 2c, and a diffusion region, which are provided on the wafer 1 and serve as comparison diffusion regions having different distances from the diffusion region 2a along one direction of the impurity diffusion region 2a whose depth is to be measured. 2d is provided (FIG. 3). The distance from the diffusion region 2a is equal to the diffusion region 2b,
The diffusion area 2c and the diffusion area 2d are larger in this order. Next, the drain electrode 4 is provided on the diffusion region 2a, the source electrode 3b, the source electrode 3c, and the source electrode 3d are provided on the diffusion region 2b, the diffusion region 2c, and the diffusion region 2d, respectively.
The gate electrode 5 is provided between b, the diffusion region 2c, and the diffusion region 2d (FIG. 4).
【0008】ゲート電極5に電圧を印加し、ドレイン電
極4とソース電極3b、ソース電極3c、ソース電極3
d夫々の間に電圧を印加する。拡散領域2aと拡散領域
2b、拡散領域2aと拡散領域2c、拡散領域2aと拡
散領域2d夫々の組についてVsd(ソース−ドレイン
電圧)とIsd(ソース−ドレイン電流)との関係を調
べ、グラフに示す。このVsdとIsdとの関係を示し
たグラフが飽和曲線である場合は被測定拡散領域と比較
拡散領域との間にFET構造が形成され、直線状である
場合は抵抗構造が形成されていることが判る。A voltage is applied to the gate electrode 5, and the drain electrode 4, the source electrode 3b, the source electrode 3c, and the source electrode 3
A voltage is applied between each d. The relationship between Vsd (source-drain voltage) and Isd (source-drain current) is investigated for each set of the diffusion region 2a and the diffusion region 2b, the diffusion region 2a and the diffusion region 2c, and the diffusion region 2a and the diffusion region 2d. Show. If the graph showing the relationship between Vsd and Isd is a saturation curve, the FET structure is formed between the measured diffusion region and the comparison diffusion region, and if it is linear, the resistance structure is formed. I understand.
【0009】ここでは、拡散領域2aと拡散領域2bと
の組、拡散領域2aと拡散領域2cとの組がFET構造
をなし、拡散領域2aと拡散領域2dとの組が抵抗構造
をなしているとする。図5は図4のV−V線断面図であ
る。拡散領域2aと拡散領域2cとは接触しておらず、
FET構造が形成されている。図6は図4のVI −VI
線断面図である。拡散領域2aと拡散領域2dとは交わ
っており、抵抗構造が形成されている。Here, the set of the diffusion region 2a and the diffusion region 2b, the set of the diffusion region 2a and the diffusion region 2c form the FET structure, and the set of the diffusion region 2a and the diffusion region 2d form the resistance structure. And FIG. 5 is a sectional view taken along line VV of FIG. The diffusion region 2a and the diffusion region 2c are not in contact with each other,
The FET structure is formed. FIG. 6 shows VI-VI of FIG.
It is a line sectional view. The diffusion region 2a and the diffusion region 2d intersect each other to form a resistance structure.
【0010】VsdとIsdとの関係を示したグラフよ
りFET構造が形成されているか抵抗構造が形成されて
いるかを判断した後、抵抗構造になる直前のFET構造
のソース−ドレイン電極の間隔xの代替として、FET
構造が形成されている組の中で最小となる電極の間隔の
値を選択する。ここでは拡散領域2aと拡散領域2cと
の組がこれに相当するので、拡散領域2cの上に形成さ
れたソース電極3cとドレイン電極4との間隔xを測定
する。この間隔xに1/2k(k:ウエハ1の種類及び
ウエハ1に注入して拡散領域2を形成する不純物等によ
って決まる係数)を乗じると拡散深さxj が求まる。After determining whether the FET structure or the resistance structure is formed from the graph showing the relationship between Vsd and Isd, the distance x between the source and drain electrodes of the FET structure immediately before the resistance structure is formed is determined. Alternatively, FET
Select a value for the smallest electrode spacing in the set in which the structure is formed. Since the set of the diffusion region 2a and the diffusion region 2c corresponds to this here, the distance x between the source electrode 3c and the drain electrode 4 formed on the diffusion region 2c is measured. The diffusion depth x j is obtained by multiplying this interval x by 1/2 k (k: a coefficient determined by the type of the wafer 1 and impurities forming the diffusion region 2 by implanting the wafer 1).
【0011】[0011]
【発明の効果】以上の如く本発明においては、半導体装
置に形成された被測定拡散領域との間隔が異なる複数個
の比較拡散領域を形成し、電極を設け、FET構造が形
成されている被測定拡散領域と比較拡散領域の組につい
て電極の間隔を測定し、その最小値に所定の係数を乗じ
るので、容易に拡散深さを求めることができる。そして
ウエハプロセスの管理及びウエハの高品質化に寄与でき
る等、本発明は優れた効果を奏するものである。As described above, according to the present invention, a plurality of comparative diffusion regions having different intervals from the measured diffusion region formed in the semiconductor device are formed, electrodes are provided, and an FET structure is formed. The distance between the electrodes is measured for the set of the measurement diffusion region and the comparison diffusion region, and the minimum value is multiplied by a predetermined coefficient, so that the diffusion depth can be easily obtained. Further, the present invention has excellent effects such as contribution to the management of the wafer process and the improvement of the quality of the wafer.
【図1】従来方法の実施状態を示す断面構造図である。FIG. 1 is a cross-sectional structure diagram showing an implementation state of a conventional method.
【図2】FET構造から抵抗構造に変わる直前のソース
電極−ドレイン電極の間隔と拡散深さとの関係を示した
断面構造図である。FIG. 2 is a cross-sectional structural diagram showing the relationship between the distance between the source electrode and the drain electrode and the diffusion depth immediately before the change from the FET structure to the resistance structure.
【図3】本発明方法の実施状態を示す平面図である。FIG. 3 is a plan view showing an implementation state of the method of the present invention.
【図4】本発明方法の実施状態を示す平面図である。FIG. 4 is a plan view showing an implementation state of the method of the present invention.
【図5】図4のV−V線断面図である。5 is a sectional view taken along line VV of FIG.
【図6】図4のVI −VI 線断面図である。6 is a sectional view taken along line VI-VI of FIG.
1 ウエハ 2a 拡散領域 2b 拡散領域 2c 拡散領域 2d 拡散領域 3b ソース電極 3c ソース電極 3d ソース電極 4 ドレイン電極 5 ゲート電極 1 wafer 2a diffusion area 2b diffusion area 2c diffusion area 2d diffusion area 3b source electrode 3c source electrode 3d source electrode 4 drain electrode 5 Gate electrode
Claims (2)
定拡散領域との間隔が異なる複数個の比較拡散領域が形
成されており、前記被測定拡散領域と前記比較拡散領域
の組について夫々一方にソース電極が、また他方にドレ
イン電極が設けられており、これらの間にゲート電極が
設けられていることを特徴とする半導体装置。1. A plurality of comparison diffusion regions having different intervals from the measurement diffusion region are formed along one direction of the measurement diffusion region, and a set of the measurement diffusion region and the comparison diffusion region is formed. A semiconductor device, wherein a source electrode is provided on one side and a drain electrode is provided on the other side, and a gate electrode is provided between them.
の一方向に沿って、該被測定拡散領域との間隔が異なる
複数個の比較拡散領域を形成し、前記被測定拡散領域と
前記比較拡散領域の組について夫々一方にソース電極
を、また他方にドレイン電極を設け、これらの間にゲー
ト電極を設けて、FET構造が形成されているか否かを
調べ、FET構造が形成されている組についてソース電
極とドレイン電極との間隔を測定し、測定した間隔の最
小値に所定の係数を乗じて拡散深さを求めることを特徴
とする拡散深さ測定方法。2. A plurality of comparison diffusion regions having different distances from the measurement diffusion region are formed along one direction of the measurement diffusion region formed in the semiconductor device, and the comparison diffusion region and the comparison diffusion region are formed. For each set of diffusion regions, a source electrode is provided on one side and a drain electrode is provided on the other side, and a gate electrode is provided between them to check whether or not an FET structure is formed, and a set in which an FET structure is formed is formed. The diffusion depth measuring method is characterized in that the distance between the source electrode and the drain electrode is measured, and the minimum value of the measured distance is multiplied by a predetermined coefficient to obtain the diffusion depth.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3173892A JPH0521565A (en) | 1991-07-15 | 1991-07-15 | Semiconductor device and diffusion depth measuring method using the same |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3173892A JPH0521565A (en) | 1991-07-15 | 1991-07-15 | Semiconductor device and diffusion depth measuring method using the same |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0521565A true JPH0521565A (en) | 1993-01-29 |
Family
ID=15969038
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP3173892A Pending JPH0521565A (en) | 1991-07-15 | 1991-07-15 | Semiconductor device and diffusion depth measuring method using the same |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0521565A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4828715A (en) * | 1987-03-31 | 1989-05-09 | Basf Aktiengesellschaft | Cleaning and disposal of carbon black and ash containing wastewaters |
US5455176A (en) * | 1994-03-14 | 1995-10-03 | University De Montreal | Microbial contamination test device |
-
1991
- 1991-07-15 JP JP3173892A patent/JPH0521565A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4828715A (en) * | 1987-03-31 | 1989-05-09 | Basf Aktiengesellschaft | Cleaning and disposal of carbon black and ash containing wastewaters |
US5455176A (en) * | 1994-03-14 | 1995-10-03 | University De Montreal | Microbial contamination test device |
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