JPH0521366B2 - - Google Patents
Info
- Publication number
- JPH0521366B2 JPH0521366B2 JP58149453A JP14945383A JPH0521366B2 JP H0521366 B2 JPH0521366 B2 JP H0521366B2 JP 58149453 A JP58149453 A JP 58149453A JP 14945383 A JP14945383 A JP 14945383A JP H0521366 B2 JPH0521366 B2 JP H0521366B2
- Authority
- JP
- Japan
- Prior art keywords
- switch
- resistor
- circuit
- switch means
- level
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 230000005856 abnormality Effects 0.000 claims description 7
- 238000010586 diagram Methods 0.000 description 5
- 239000004065 semiconductor Substances 0.000 description 2
- 230000002950 deficient Effects 0.000 description 1
- 238000003745 diagnosis Methods 0.000 description 1
- 238000004092 self-diagnosis Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
Landscapes
- Keying Circuit Devices (AREA)
- Electronic Switches (AREA)
Description
この発明は、自己診断機能を有する入力回路に
関する。
第１図は従来の入力回路の一例を示す図であ
る。この図において符号１はスイツチ、２は抵
抗、３はコネクタ端子、４はプルアツプ抵抗、５
はバツフアアンプであり、このバツフアアンプ５
から、スイツチ１のオン／オフに対応する信号S1
が出力される。
ところで、このような従来の入力回路にあつて
は、例えばコネクタ不良によりコネクタ端子３が
接地されてしまつた場合、あるいはバツフアアン
プ５が破損した場合等の回路異常時において、ス
イツチ１がオフであるにもかかわらず、スイツチ
１のオンを示す信号S1が出力されてしまう場合が
あつた。このことは、特に自動車等の入力回路に
おいては極めて重大な問題となる。すなわち、例
えばスイツチ１が自動車の窓を自動的に開くため
のスイツチであつた場合、スイツチ１をオンとし
ないのに窓が自動的に開いてしまい、また、例え
ばスイツチ１がワイパを動作させるスイツチであ
つた場合、雨が降つていないのにワイパが動きだ
してしまう。
そこでこの発明は、回路異常を自動的にチエツ
クする機能を有し、スイツチが実際にオン状態と
なつた場合にのみ、スイツチオンを示す信号を次
段へ出力する入力回路を提供することを目的とし
ている。
そして、この発明は、第１のスイツチ手段の一
端に第１の抵抗の一端を接続し、この第１のスイ
ツチ手段の他端に電源電圧の一方の極性を供給し
てなる第１の回路と、前記第１の抵抗の他端に第
２の抵抗の一端を接続すると共に、直列に接続さ
れた第３の抵抗と第２のスイツチ手段とを該第２
の抵抗に並列接続し、この第２の抵抗の他端に前
記電源電圧の他方の極性が供給される第２の回路
と、前記第１および第２の回路の接続点に発生す
る入力電位に応じて前記第１の回路の異常の有無
を判定する判定回路とを具備し、前記判定回路
は、前記第２のスイツチ手段をオン／オフ動作さ
せ、この際に前記入力電位がこのオン／オフ動作
に応じて変化した場合のみ、前記第１のスイツチ
手段がオン状態に設定されていることを表す信号
を次段へ出力するようにしたものである。
以下、図面を参照しこの発明の一実施例につい
て説明する。第２図はこの発明の一実施例の構成
を示す回路図である。この図において１はスイツ
チ（第１のスイツチ手段）、２は抵抗（第１の抵
抗）、３はコネクタ端子、４はプルアツプ抵抗
（第２の抵抗）、５はバツフアアンプであり、これ
らは第１図に示すものと同一である。６は抵抗
（第３の抵抗）、７は故障診断用スイツチ（第２の
スイツチ手段）であり、この抵抗６、スイツチ７
の直列回路が抵抗４に並列に接続されている。ま
た、上述した抵抗２，４，６の各値R2，R4，R6
の間には、
R6＜R2＜R4
なる関係がある。８は、CPU、RAM、ROMお
よび入出力インタフエース等からなる周知のマイ
クロコンピユータによつて構成されるレベル判定
回路である。このレベル判定回路８は、予め定め
られた一定周期毎にスイツチ７を複数回オン／オ
フ動作させ、これに対応して変化するバツフアア
ンプ５の出力レベルVBを検出する。
また、該回路８は、後述する動作に従つて、こ
の検出した出力レベルVBに基づき回路異常の有
無とスイツチ１のオン／オフ状態とを判定する。
ここで、該回路８は、回路異常が無く、かつ、ス
イツチ１がオン状態に設定されたと判定した場合
にのみスイツチ１のオン状態を示す信号S1を発生
する。
ところで、このレベル判定回路８がスイツチ７
を複数回オン／オフ動作させるのは、１回のオ
ン／オフ動作では判定ミスが起こり得るので、こ
れを複数回行つている訳である。なお、この実施
例においてはスイツチ１を１個としているが、通
常は複数のスイツチ１が設けられ、また、各スイ
ツチ１に対応して構成要素２〜７が設けられ、各
バツフアアンプ５の出力が各々１つのレベル判定
回路８へ入力される。
次に、上述した回路の動作を説明する。第１表
は回路異常がない場合におけるスイツチ１，７の
オン／オフ状態とバツフアアンプ５の出力レベル
VBとの関係を示す表である。
The present invention relates to an input circuit having a self-diagnosis function. FIG. 1 is a diagram showing an example of a conventional input circuit. In this figure, 1 is a switch, 2 is a resistor, 3 is a connector terminal, 4 is a pull-up resistor, and 5 is a
is a buffer amplifier, and this buffer amplifier 5
, the signal S 1 corresponding to the on/off of switch 1
is output. By the way, in such a conventional input circuit, when the connector terminal 3 is grounded due to a defective connector, or when the buffer amplifier 5 is damaged, the switch 1 is turned off. Despite this, there were cases in which the signal S1 indicating that switch 1 was on was output. This becomes an extremely serious problem, especially in input circuits for automobiles and the like. That is, for example, if switch 1 is a switch for automatically opening a car window, the window will open automatically even though switch 1 is not turned on. If it is, the wipers will start moving even though it is not raining. Therefore, an object of the present invention is to provide an input circuit that has a function of automatically checking for circuit abnormalities and outputs a signal indicating that the switch is on to the next stage only when the switch is actually turned on. There is. The present invention also provides a first circuit in which one end of a first resistor is connected to one end of the first switch means, and one polarity of the power supply voltage is supplied to the other end of the first switch means. , one end of a second resistor is connected to the other end of the first resistor, and a third resistor connected in series and a second switch means are connected to the second resistor.
a second circuit connected in parallel to the resistor, the other end of which is supplied with the other polarity of the power supply voltage, and an input potential generated at the connection point between the first and second circuits; a determination circuit that determines whether or not there is an abnormality in the first circuit according to the determination circuit, and the determination circuit operates the second switch means on/off, and at this time, the input potential Only when a change occurs in accordance with the operation, a signal indicating that the first switch means is set to the on state is outputted to the next stage. An embodiment of the present invention will be described below with reference to the drawings. FIG. 2 is a circuit diagram showing the configuration of an embodiment of the present invention. In this figure, 1 is a switch (first switch means), 2 is a resistor (first resistor), 3 is a connector terminal, 4 is a pull-up resistor (second resistor), and 5 is a buffer amplifier. It is the same as shown in the figure. 6 is a resistor (third resistor), 7 is a fault diagnosis switch (second switch means), and this resistor 6, switch 7
A series circuit of is connected in parallel to the resistor 4. In addition, each value of the resistors 2, 4, and 6 mentioned above R 2 , R 4 , R 6
There is a relationship between R 6 < R 2 < R 4 . Reference numeral 8 denotes a level determination circuit constituted by a well-known microcomputer consisting of a CPU, RAM, ROM, input/output interface, and the like. This level determination circuit 8 turns on/off the switch 7 a plurality of times at predetermined regular intervals, and detects the output level VB of the buffer amplifier 5 that changes accordingly. The circuit 8 also determines the presence or absence of a circuit abnormality and the on/off state of the switch 1 based on the detected output level VB in accordance with the operation described later.
Here, the circuit 8 generates a signal S1 indicating the on state of the switch 1 only when it is determined that there is no circuit abnormality and the switch 1 is set to the on state. By the way, this level judgment circuit 8 is the switch 7.
The reason why the on/off operation is performed multiple times is because a single on/off operation may result in a judgment error. Although one switch 1 is used in this embodiment, normally a plurality of switches 1 are provided, and components 2 to 7 are provided corresponding to each switch 1, so that the output of each buffer amplifier 5 is Each signal is input to one level determination circuit 8. Next, the operation of the circuit described above will be explained. Table 1 shows the on/off status of switches 1 and 7 and the output level of buffer amplifier 5 when there is no circuit abnormality.
This is a table showing the relationship with VB .
【表】
この表において、まず、スイツチ１がオフの場
合は、スイツチ７のオン／オフ状態にかかわらず
バツフアアンプ５の入力端へ電源電圧＋Ｖが供給
され、この結果レベルVBが“Ｈ”レベルとなる
（状態，）。次に、スイツチ１，７が共にオン
の場合は、バツフアアンプ５の入力端の電圧が、
電源電圧＋Ｖを抵抗４，６の並列抵抗と抵抗２と
で分圧した値となる。ここで、抵抗６の値R6が
抵抗２の値R2より小さく、かつ、抵抗６に抵抗
４が並列接続されることから、バツフアアンプ５
の入力端の電圧が電源電圧＋Ｖに近い値となり、
この結果、レベルVBが“Ｈ”レベルとなる（状
態）。次に、スイツチ１がオン、スイツチ７が
オフの場合は、バツフアアンプ５の入力端へ電源
電圧＋Ｖを抵抗２，４で分圧した電圧が供給され
る。この場合、抵抗２の値R2が抵抗４の値R4よ
り小さいことから、バツフアアンプ５の入力端の
電圧が接地電位に近い値となり、この結果、レベ
ルVBが“Ｌ”レベルとなる（状態）。
しかして、レベル判定回路８はスイツチ７を複
数回オン／オフさせ、この時、レベルVBがスイ
ツチ７のオン／オフに対応して“Ｈ”レベル
“Ｌ”レベルを交互に繰返した場合（状態，
参照）にのみ、スイツチオンを示す信号S1を出力
し、スイツチ７をオン／オフさせたにもかかわら
ずレベルVBが変化しなかつた場合はスイツチオ
ンを示す信号S1を出力しない。この結果、回路異
常が発生した場合、すなわち、抵抗２の値が大き
く変化した場合、コネクタ不良によりコネクタ端
子３の電位が一定レベルに固定されてしまつた場
合、あるいは、バツフアアンプ５が破損した場合
等において、スイツチオンを示す信号S1がレベル
判定回路８から出力されることがなく、したがつ
て、スイツチ１がオフであるにもかかわらずスイ
ツチオンを示す信号S1が出力される虞れが全くな
い。
なお、第３図は第２図に示す回路の電源の極性
を変えた場合であり、この場合、第１表は次の第
２表のようになる。[Table] In this table, first, when switch 1 is off, the power supply voltage +V is supplied to the input terminal of buffer amplifier 5 regardless of the on/off state of switch 7, and as a result, the level V B is "H" level. becomes (state,). Next, when switches 1 and 7 are both on, the voltage at the input terminal of buffer amplifier 5 is
It is a value obtained by dividing the power supply voltage +V by the parallel resistances of resistors 4 and 6 and resistor 2. Here, since the value R 6 of the resistor 6 is smaller than the value R 2 of the resistor 2, and the resistor 4 is connected in parallel to the resistor 6, the buffer amplifier 5
The voltage at the input terminal of becomes a value close to the power supply voltage +V,
As a result, level V B becomes "H" level (state). Next, when the switch 1 is on and the switch 7 is off, a voltage obtained by dividing the power supply voltage +V by the resistors 2 and 4 is supplied to the input terminal of the buffer amplifier 5. In this case, since the value R 2 of the resistor 2 is smaller than the value R 4 of the resistor 4, the voltage at the input terminal of the buffer amplifier 5 becomes a value close to the ground potential, and as a result, the level V B becomes "L" level ( situation). Therefore, the level determination circuit 8 turns the switch 7 on and off a plurality of times, and at this time, if the level V B alternately repeats "H" and "L" levels in response to the on/off of the switch 7 ( situation,
If the level V B does not change even though the switch 7 is turned on/off, the signal S 1 indicating that the switch is on is not output. As a result, if a circuit abnormality occurs, that is, if the value of the resistor 2 changes significantly, if the potential of the connector terminal 3 is fixed at a constant level due to a connector failure, or if the buffer amplifier 5 is damaged, etc. In this case, the signal S1 indicating that the switch is on is not outputted from the level determination circuit 8, and therefore there is no possibility that the signal S1 indicating that the switch is on will be output even though the switch 1 is off. . Note that FIG. 3 shows a case where the polarity of the power supply of the circuit shown in FIG. 2 is changed, and in this case, Table 1 becomes as shown in Table 2 below.
【表】
また、上述した実施例におけるスイツチ１はト
グルスイツチ、スライドスイツチ等の機械的スイ
ツチに限らず、例えばトランジスタ、FET、フ
オトトランジスタ等の半導体スイツチその他いか
なる種類のものでもよい。また、スイツチ７とし
ては、同様に機械的スイツチ、半導体スイツチ等
が用いられる。
以上説明したように、この発明によれば第２の
スイツチ手段（実施例におけるスイツチ７）をオ
ン／オフさせ、この時の判定部（レベル判定回路
８）の入力信号のレベル変化に基づいて第１のス
イツチ手段（スイツチ１）のオン／オフ状態を判
定するようにしたので、第１のスイツチ手段が実
際にオンとなつた場合にのみスイツチオンを示す
信号が出力され、第１のスイツチ手段がオフであ
るにもかかわらずスイツチオンを示す信号が出力
される虞れがない。Further, the switch 1 in the above-described embodiment is not limited to a mechanical switch such as a toggle switch or a slide switch, but may be any type of semiconductor switch such as a transistor, FET, or phototransistor. Further, as the switch 7, a mechanical switch, a semiconductor switch, etc. are similarly used. As explained above, according to the present invention, the second switch means (switch 7 in the embodiment) is turned on/off, and the second switch means (switch 7 in the embodiment) is turned on/off, and the second switch means (switch 7 in the embodiment) is turned on/off, and the second switch means (switch 7 in the embodiment) is turned on/off, and the second switch means (switch 7 in the embodiment) is turned on/off, and the second switch means (switch 7 in the embodiment) is turned on/off, and the Since the on/off state of the first switch means (switch 1) is determined, a signal indicating the switch on is output only when the first switch means is actually turned on, and the first switch means is turned on. There is no possibility that a signal indicating a switch on will be output even though it is off.
第１図は従来の入力回路の構成を示す回路図、
第２図はこの発明の一実施例の構成を示す回路
図、第３図は同実施例における電源の極性を変え
た場合を示す回路図である。
１…スイツチ（第１のスイツチ手段）、２…抵
抗（第１の抵抗）、４…抵抗（第２の抵抗）、６…
抵抗（第３の抵抗）、７…スイツチ（第２のスイ
ツチ手段）、８…レベル判定回路（判定部）。
Figure 1 is a circuit diagram showing the configuration of a conventional input circuit.
FIG. 2 is a circuit diagram showing the configuration of an embodiment of the present invention, and FIG. 3 is a circuit diagram showing the same embodiment when the polarity of the power supply is changed. 1... Switch (first switch means), 2... Resistor (first resistor), 4... Resistor (second resistor), 6...
Resistor (third resistor), 7... switch (second switch means), 8... level determination circuit (determination section).
Claims (1)
端を接続し、この第１のスイツチ手段の他端に電
源電圧の一方の極性を供給してなる第１の回路
と、 前記第１の抵抗の他端に第２の抵抗の一端を接
続すると共に、直列に接続された第３の抵抗と第
２のスイツチ手段とを該第２の抵抗に並列接続
し、この第２の抵抗の他端に前記電源電圧の他方
の極性が供給される第２の回路と、 前記第１および第２の回路の接続点に発生する
入力電位に応じて前記第１の回路の異常の有無を
判定する判定回路とを具備し、 前記判定回路は、前記第２のスイツチ手段をオ
ン／オフ動作させ、この際に前記入力電位がこの
オン／オフ動作に応じて変化した場合のみ、前記
第１のスイツチ手段がオン状態に設定されている
ことを表す信号を次段へ出力することを特徴とす
る入力回路。[Scope of Claims] 1. A first circuit comprising one end of a first resistor connected to one end of a first switch means, and one polarity of a power supply voltage supplied to the other end of the first switch means. and one end of a second resistor is connected to the other end of the first resistor, and a third resistor connected in series and a second switch means are connected in parallel to the second resistor, a second circuit to which the other polarity of the power supply voltage is supplied to the other end of the second resistor; and a determination circuit that determines the presence or absence of an abnormality, and the determination circuit operates the second switch means on/off, and only when the input potential changes in accordance with the on/off operation. , an input circuit that outputs a signal indicating that the first switch means is set to an on state to a next stage.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14945383A JPS6041321A (en) | 1983-08-16 | 1983-08-16 | Input circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14945383A JPS6041321A (en) | 1983-08-16 | 1983-08-16 | Input circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6041321A JPS6041321A (en) | 1985-03-05 |
| JPH0521366B2 true JPH0521366B2 (en) | 1993-03-24 |
Family
ID=15475450
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14945383A Granted JPS6041321A (en) | 1983-08-16 | 1983-08-16 | Input circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6041321A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4643419B2 (en) * | 2005-11-08 | 2011-03-02 | 矢崎総業株式会社 | Load drive device with self-diagnosis function |
| JP6563065B1 (en) * | 2018-04-03 | 2019-08-21 | 三菱電機株式会社 | Electronic control unit |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57182660A (en) * | 1981-05-08 | 1982-11-10 | Fuji Xerox Co Ltd | Inputting circuit |
-
1983
- 1983-08-16 JP JP14945383A patent/JPS6041321A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57182660A (en) * | 1981-05-08 | 1982-11-10 | Fuji Xerox Co Ltd | Inputting circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6041321A (en) | 1985-03-05 |
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