JPH05211152A - Bipolar type semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE:To prevent deterioration of quality in a large current region without increasing capacitance, by using a polycrystalline semiconductor pattern formed so as to surround a part on an island region as an element forming region, and forming an emitter region in an island region so as to be along the outer periphery of the island region. CONSTITUTION:A polycrystalline semiconductor film of a second conductivity type is formed on a semiconductor substrate of a first conductivity type having an island region 204a. By selective oxidation, a polycrystalline semiconductor pattern 205a is formed on the island region 204a, so as to surround a part of said region. At the same time, by diffusing impurities from the polycrystalline semiconductor film, a region 209 of a second conductivity type as a base is formed in the surface part of the island region 204a. After that, impurities of a first conductivity type are introduced in the polycrystalline semiconductor pattern 205a. By impurity diffusion, a first conductivity type region 217 as an emitter is formed in the second conductivity type region 209, so as to be along the outer periphery of the island region 204a. Thereby quality deterioration in a larger current region is prevented without increasing capacitance, and the drive capability of a transistor is increased.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bipolar semiconductor device and a method for manufacturing the same.

[0002]

2. Description of the Related Art ECL / CML is generally used as a semiconductor integrated circuit device, especially in a field requiring high-speed operation.
(Emitter Coupled Logic / Current Mode Logic) type bipolar semiconductor integrated circuit devices are used. E
In the CL / CML system circuit, when the power consumption and the logic amplitude are constant, the operating speed is determined by the parasitic capacitance of the elements and wirings forming the circuit and the base resistance of the transistor and the current gain bandwidth product. Among them, in order to reduce the parasitic capacitance, it is necessary to reduce the junction capacitance between the base and collector of the transistor that makes a large contribution to the operating speed. To this end, polycrystalline silicon is used to form the base electrode as an element. It is effective to draw it out of the region to reduce the base area. Further, a method of forming a polycrystalline silicon resistor and a metal wiring on a thick isolation oxide film to reduce their parasitic capacitance is generally adopted.

On the other hand, in order to reduce the base resistance, it is necessary to lower the resistance of the inactive base layer so as to be as close to the emitter as possible and to reduce the resistance of the active base layer immediately below the emitter by making the emitter thin. is there. Further, in order to improve the current gain bandwidth product, it is effective to make the emitter and base junctions shallow and thin the collector epitaxial layer.

As a conventional technique proposed for realizing these matters, Japanese Patent Laid-Open No. 63-261746 has been proposed.
The manufacturing method disclosed in the publication will be described.

11 (a) to 11 (c) and FIG. 12 (a).
(C) is a figure for demonstrating the said manufacturing method, and in order to avoid making a drawing complicated in these figures, some films are abbreviate | omitted.

In FIG. 11 (a), after element isolation, about 3000 liters of polycrystalline silicon is formed on a semiconductor substrate, and the surface of the polycrystalline silicon is 200
Å About 1000-2000 after oxidation (not shown)
1 shows a state in which a nitride film of Å is selectively formed on the base electrode and collector electrode formation portions, 101 is a P ⁻ type silicon substrate, 102 is an N ⁺ type buried diffusion layer formed on the silicon substrate 101, and 103 is An N ⁻ type epitaxial layer formed on the buried diffusion layer 102, 104 is a silicon substrate 101
And an element isolation oxide film formed on the buried diffusion layer 102, 1
Reference numeral 05 denotes the epitaxial layer 103 and the element isolation oxide film 10.
4, polycrystalline silicon 106a, 106b,
106c is a nitride film selectively formed on the polycrystalline silicon 105. The N ⁻ type epitaxial layer 103 is divided by a device isolation oxide film 104 into a first island region 103a in a device formation region and a second island region 103b in a collector electrode extraction region.

Next, as shown in FIG. 11B, the polycrystalline silicon 105 is selectively oxidized by using the nitride films 106a, 106b and 106c as a mask, and the polycrystalline silicon 105a,
105b and 105c are obtained. 107 is polycrystalline silicon 1
05 is a polycrystalline silicon oxide film obtained by oxidizing 05.
Next, the nitride film 106c on the polycrystalline silicon 105c as the collector electrode is selectively removed as shown in FIG. 11C, phosphorus atoms are ion-implanted into the collector electrode polycrystalline silicon 105c, and heat treatment is performed. By diffusion from the collector electrode polycrystalline silicon 105c, the second island region 103b is used as an N ⁺ type region 108 for extracting the collector electrode. afterwards,
Polycrystalline silicon 105a, 105b as base electrodes
1-5 × 1 of boron through the nitride films 106a and 106b
Ion implantation of about 0 ¹⁵ atoms / cm ² and annealing at a temperature of about 900 ° C. are performed to form the base electrode polycrystalline silicon 105.
The boron atom concentration in a and 105b is made uniform. Then
An emitter formation region 107a of the polycrystalline silicon oxide film 107 is selectively removed as shown in FIG. 11C, and the inner wall is oxidized to form an inner wall oxide film 109 of about 200Å. At this time, the polycrystalline silicon 105a, 105b
The P ⁺ -type inactive base 110 is formed in the first island region 103a of the epitaxial layer by diffusion from the.

Next, BF ₂ is added at 1 to 5 × 10 ¹³ atoms / cm ²
12 is implanted into the first island region 103a after the ion implantation is performed.
After forming the active base 111 as shown in (a), an oxide film (not shown) of about 1000 Å and 2000 Å are formed on the entire surface.
Polycrystalline silicon 112 is formed by CVD.

Next, the polycrystal silicon 112 is etched by reactive ion etching, and the CVD oxide film and the inner wall oxide film 109 are further etched.
An opening for forming an emitter is formed as shown in FIG. At this time, the polycrystalline silicon 112 and the CVD oxide film remain as sidewalls only on the side walls of the opening (the opening where the polycrystalline silicon oxide film 107a is removed), and the opening defined by the nitride film 106a and the nitride film 106b. The opening for forming the emitter, which is narrower than the area, is self-aligned. At the same time, the collector electrode polycrystalline silicon 105c is exposed as shown in FIG.

Next, about 3000 Å of polycrystalline silicon 113 is deposited on the entire surface, an oxide film of about 200 Å is formed on the surface, and then arsenic is ion-implanted into the polycrystalline silicon 113 of about 1 × 10 ¹⁶ atoms / cm ^2. ..

Next, the oxide film on the surface of the polycrystalline silicon 113, the polycrystalline silicon 113, and the nitride films 106a and 10a.
6b is etched to form polycrystalline silicon 113 in FIG.
As shown in (c), it is left only in the emitter forming opening and its peripheral portion. After that, the emitter 114 is formed in the active base 111 by diffusion from the polycrystalline silicon 113 by heat treatment.

Next, polycrystalline silicon 105a, 105
After removing the thin oxide film on the surfaces of b and 113, platinum is vapor-deposited and heat-treated to form platinum silicide 115 on the surfaces of the polycrystalline silicon 105a, 105b, 105c and 113 as shown in FIG. 12 (c). At this time, the thin oxide film is left in a portion such as a resistor that is not silicided. The unreacted platinum remaining on the oxide film is removed with aqua regia. After that, as shown in the figure, CV is applied to the entire surface.
A D oxide film 116 is deposited, contact holes are opened, and metal electrode wirings 117 are formed.

According to the above manufacturing method, the emitter is formed in the selective oxidation region of the polycrystalline silicon, and the high-concentration inert base is formed by diffusion from the remaining polycrystalline silicon adjacent to the oxidation region. The distance between the high-concentration inert base and the emitter can be significantly reduced, and an emitter narrower than the minimum design size can be easily formed. Further, the width of the entire base region may be three times the minimum design size, so that the base-collector junction capacitance can be reduced. Further, almost all of the emitter junction is a junction with a low concentration active base, and the emitter-base junction capacitance is also reduced in combination with the reduction of the emitter width.

Since the maximum junction depth can be set to 0.3 μm or less, the epitaxial layer can be thinned to 1 μm or less, and the carrier depletion layer transit time of carriers can be shortened. Further, the collector time constant and the emitter time constant are shortened due to the decrease in the above-mentioned junction capacitance, and thus the current gain bandwidth product can be improved.
Since the base resistance and parasitic capacitance of the transistor can be reduced and the current gain bandwidth product can be improved as described above, it has a feature that a remarkable increase in speed can be achieved.

[0015]

However, the conventional manufacturing method described above has the following problems. The delay time t _pd of the bipolar transistor circuit is expressed by _Equation 1 (where τ _{TRS is} the propagation delay time of the transistor, C _{L is the} load capacitance, ΔV is the logical amplitude, and I is the current).
It is represented by.

[Equation 1] Here, the load capacitance C _L is significantly changed due to the circuit formation or the like by the total of the junction capacitance, the wiring capacitance, and the like. Further, the logic amplitude ΔV is generally about 0.5 V in consideration of the noise margin. Therefore, in order to reduce the second term on the right side of the equation 1, it is necessary to increase the current I. However, when a large amount of current is passed through a transistor whose emitter area is reduced by the self-alignment technique, such as the transistor manufactured by the conventional manufacturing method, the current density of the emitter is increased, which greatly affects the characteristics. That is, there arises a problem that the grounded-emitter current amplification factor decreases as the emitter current density increases. Therefore, when a current that allows high-speed operation as a circuit is set, the characteristics of the transistor deteriorate, and conversely, if the current is matched to the characteristics of the transistor, the capacitance or the like impedes high-speed performance.

The present invention has been made in view of the above points, and is capable of preventing deterioration of transistor performance in a high current region without increasing capacitance, and a bipolar semiconductor capable of obtaining a higher performance transistor. An object of the present invention is to provide a device and a manufacturing method thereof.

Further, the present invention eliminates the problem that the conventional manufacturing method cannot manufacture an I ² L (Integrated Injection Logic) circuit because it is extremely difficult to manufacture a multi-emitter transistor. hand,
It is an object of the present invention to provide a method for manufacturing a bipolar semiconductor device that can easily manufacture a multi-emitter transistor.

Further, the present invention eliminates the problem that it is necessary to take out the base electrode from the region separated from the device forming region via the buried layer when obtaining the lateral transistor by the prior art, and It is an object of the present invention to provide a bipolar semiconductor device which can reduce the element area and can be highly integrated, and a manufacturing method thereof.

[0019]

According to the present invention, a polycrystalline semiconductor pattern which is formed so as to partially surround an island region which is an element forming region and has been used as a conventional base electrode and a diffusion source of an inactive base. Is used to form an emitter region in the island region along the outer periphery of the island region.

Further, when the polycrystalline semiconductor pattern is formed by selective oxidation, it is formed on the island region so as to be divided into a plurality of pieces when viewed from above, and impurity diffusion from each of the divided polycrystalline semiconductor patterns is performed. A plurality of emitter regions are formed by.

Further, when the polycrystalline semiconductor pattern is formed by selective oxidation, a pair of left and right polycrystalline semiconductor patterns are formed by sandwiching the selective oxide film, and the emitter region and the collector region are formed by impurity diffusion from the pair of polycrystalline semiconductor patterns. On the other hand, the selective oxide film is removed while the base electrode is drawn out from this part by a polycrystalline semiconductor.

[0022]

If the emitter region is formed in the island region along the outer periphery of the island region by using the polycrystalline semiconductor pattern used as the base electrode in the past, the same island region area (the same element area as the conventional device area) can be obtained. , The same base area), the emitter area ratio can be increased from about 8% of the conventional value to about 80%. Therefore, without increasing the capacitance, it is possible to prevent the transistor performance from deteriorating in the high current region, further increase the grounded-emitter current amplification factor, and increase the driving capability of the transistor.

If the polycrystalline semiconductor pattern is divided into a plurality of portions and the emitter region is formed by impurity diffusion from each of the divided polycrystalline semiconductor patterns, the emitter can be divided easily and the multi-emitter can be formed. The transistor is easily formed.

Further, the polycrystalline semiconductor patterns are formed as a left and right pair with a selective oxide film sandwiched therebetween, and an emitter region and a collector region are formed by impurity diffusion from the pair of polycrystalline semiconductor patterns, while the selective oxide film is removed. Then, by pulling out the base electrode from this portion with a polycrystalline semiconductor, the lateral transistor can be formed by pulling out the base electrode from the surface of the element formation region.

[0025]

Embodiments of the present invention will be described below with reference to the drawings. 1 to 3 are process sectional views showing a first embodiment of the present invention. To describe this first embodiment, first, P as shown in FIG. 1 (A) ^- -type silicon substrate 201 N ⁺
After forming the type buried layer 202, an N ⁻ type epitaxial layer is grown, and a part thereof is converted into an element isolation oxide film 203, whereby the first and second island regions 2 of the epitaxial layer are formed.
04a and 204b are formed. The first island region 204a is an element formation region, and the second island region 204b is a collector electrode extraction region. Next, P (phosphorus) is introduced into the second island region 204b to make it an N ⁺ type region, and then the first and second island regions 204a and 204b and the entire surface on the element isolation oxide film 203, That is, a polycrystalline silicon film 205 having a thickness of 2000 to 3000 Å is formed on the entire surface of the conductor substrate, and a silicon oxide film 206 having a thickness of about 200 Å is further formed on the surface thereof.

Next, B (boron) is introduced into the polycrystalline silicon film 205 by using the ion implantation method. At this time, the ion implantation conditions are, for example, an acceleration energy of 40 keV and a dose amount of 1.5 × 10 ¹⁴ cm ^-2 . After that, a silicon nitride film is formed on the silicon oxide film 206 by a CVD method (chemical vapor deposition method), and the silicon nitride film is patterned by a known photolithographic etching technique. Silicon nitride film patterns 207a and 207b are formed as shown in FIG. And
By using the oxidation resistance of the silicon nitride film patterns 207a and 207b to selectively oxidize the polycrystalline silicon film 205, polycrystalline silicon patterns 205a and 205b are formed as shown in FIG. 1C. Here, the polycrystalline silicon pattern 205b is formed on the second island region 204b.
The collector electrode is formed as polycrystalline silicon on top. Further, the polycrystalline silicon pattern 205a is formed on the first island region 204a so as to surround the selective oxide film 208a at the center thereof and extend over the surrounding element isolation oxide film 203. Also, during this selective oxidation, the polycrystalline silicon film 2
The first island region 204a due to the diffusion of B (boron) from 05
A P-type region 209 is formed as a base region in the entire surface of the. Second island region 20 serving as a collector electrode lead-out
The portion 4b remains the N-type conductivity type due to the impurity concentration.

Next, the silicon nitride film pattern 207a,
As (arsenic) is introduced into the polycrystalline silicon patterns 205a and 205b through the ion implantation method via the 207b and the silicon oxide film 206. At this time, the ion implantation conditions are: acceleration energy 200 keV, dose amount 2.0 × 10
¹⁶ cm ^-2 . With this acceleration energy, As (arsenic) does not reach the first and second island regions 204a and 204b. After that, as shown in FIG. 2A, only the selective oxide film 208a, which will be a lead-out portion of the base electrode in the future, is selectively removed to form an opening 210.

Next, as shown in FIG. 2B, a silicon oxide film 211 is formed on the entire surface by a CVD method to a thickness of about 1000 .ANG.
It is formed on the entire surface of about 00Å. After that, the polycrystalline silicon film 212 is etched back by RIE (reactive ion etching), so that the sidewalls 212a of the polycrystalline silicon are formed into the opening 2 as shown in FIG. 2C.
Then, the silicon oxide film 211 is etched using the sidewalls 212a of polycrystalline silicon as an etching mask to form the P-type region 209.
Expose. As a result, the opening 213 is obtained by reducing the opening 210 in a self-aligned manner at the center of the P-type region 209.

Next, polycrystalline silicon is formed on the entire surface, B (boron) is further introduced into the polycrystalline silicon, and then the polycrystalline silicon is patterned by using a known photolithography technique and etching technique. As shown in FIG. 3A, the crystalline silicon is left as the base electrode polycrystalline silicon 214 only in the opening 213 and its peripheral portion. Then, a silicon oxide film 215 is formed on the surface of the base electrode polycrystalline silicon 214 by using a thermal oxidation method. Then, the silicon oxide film 215 and the selective oxide film 2
The exposed portions of the silicon nitride film pattern 207a and the entire exposed silicon nitride film pattern 207b are removed by hot phosphoric acid using 08b and 208c as masks. At this time, B (boron) is diffused from the base electrode polycrystalline silicon 214 into the P-type region 209 to form a P ⁺ -type region 216 as a base electrode lead-out region in the P-type region 209.
At this time, mainly, As (arsenic) diffuses from the polycrystalline silicon pattern 205a to the P-type region 209, and the P-type region 209 has an outer peripheral portion (island region) as shown in FIG. An N ⁺ type region 217 is formed as an emitter region along the outer peripheral portion of 204a). After that, as shown in FIG. 3B, a silicon oxide film 218 is formed on the entire surface by a CVD method, contact holes are opened, and metal wirings 219a, 219b, 219c are formed.

Next, a second embodiment of the present invention will be described with reference to FIGS. The second embodiment is a case where an NPN type multi-emitter transistor and a lateral PNP transistor are simultaneously formed to form an I ² L circuit. In this second embodiment, the collector electrode lead-out portion of the NPN type multi-emitter transistor is the same as that of the first embodiment, so that illustration and description thereof will be omitted.

The second embodiment will be described with reference to FIG.
As shown in (A), after the N ⁺ type buried layer 302 is formed on the P ⁻ type silicon substrate 301, an N ⁻ type epitaxial layer is grown and a part of the N ⁻ type epitaxial layer is converted into an element isolation oxide film 303. The island region 304 of the epitaxial layer is formed. Next, a resist pattern 305 is formed on the surface of the island region 304 and the element isolation oxide film 303, that is, the surface of the semiconductor substrate by a known photolithography technique, and the resist pattern 305 is used as a mask to form the island region 304.
The island region 304 in the partial region 304a of the first region 3
P (phosphorus) is introduced by ion implantation so as to divide into 04b and the second region 304c. At this time, the ion implantation is performed at an acceleration energy of 40 keV and a dose amount of 10 ¹³ to 10 ^14.
Do it in cm ^-2 . It should be noted that the partial region 304a of the island region into which phosphorus is introduced will be a base region of the lateral PNP transistor in the future.

Then, after removing the resist pattern 305, a polycrystalline silicon film 306 is formed on the entire surface of the island region 304 and the element isolation oxide film 303, that is, the entire surface of the semiconductor substrate, as shown in FIG. It has a thickness of 3000Å and a silicon oxide film 3 of about 200Å on its surface.
07 is formed. Then, B (boron) is introduced into the polycrystalline silicon film 306 through the silicon oxide film 307 by an ion implantation method. At this time, the ion implantation conditions are, for example, an acceleration energy of 40 keV and a dose of 1.5 × 10.
¹⁴ cm ^-2 . After that, C is deposited on the silicon oxide film 307.
The silicon nitride film patterns 308a and 308b are formed by the VD method (chemical vapor deposition method) and the photolithographic etching method. Then, the silicon nitride film patterns 308a, 3
By selectively oxidizing the polycrystalline silicon film 306 using 08b as a mask, polycrystalline silicon patterns 306a and 306b are formed as shown in FIG. 5C. here,
The polycrystalline silicon pattern 306a is the first of the island regions.
Is formed on the region 304b so as to surround the selective oxide film 309a and partially extend on the element isolation oxide film 303. The polycrystalline silicon pattern 306b is formed on the second region 304c of the island region so as to surround the selective oxide film 309b and partly extend on the element isolation oxide film 303. Further, the polycrystalline silicon pattern 306
b is formed around the selective oxide film 309b by being divided into, for example, four parts as viewed from above. It goes without saying that the polycrystalline silicon pattern 306b is formed by forming the silicon nitride film pattern 308b as a mask for selective oxidation in the same shape. Also,
During this selective oxidation, B (boron) is diffused from the polycrystalline silicon film 306 to the island region 304, and the first region 304b is formed.
A P-type region 310a serving as an emitter of the lateral PNP transistor is formed on the entire surface of the second region 30.
4c includes a P-type region 310b (lateral PNP) serving as a base of the NPN-type multi-emitter transistor.
(Also serving as the collector of the transistor) is formed. At this time, the partial region 304a of the island region into which P (phosphorus) is ion-implanted remains the N-type conductivity type due to the impurity concentration.

Next, a silicon nitride film pattern 308b is formed on the polycrystalline silicon pattern 306b as the emitter electrode polycrystalline silicon of the NPN type multi-emitter transistor.
Further, As (arsenic) is introduced through the silicon oxide film 307 by using the ion implantation method. At this time, the acceleration energy is 200 keV and the dose is 2.0 × 10 ¹⁶ cm ^-2 . After that, the selective oxide film 309b in the portion to be the extraction portion of the base electrode of the NPN type multi-emitter transistor and the selective oxide film 309a in the portion to be the extraction portion of the emitter electrode of the lateral PNP transistor are removed as shown in FIG. 6 (A). Then, the opening 311 is formed. After that, as in the first embodiment, the side wall 313 of polycrystalline silicon is formed by sandwiching the silicon oxide film 312 on the side wall of the opening 311, as shown in FIG. 6B, and the opening is reduced. Further, B (boron) -doped polycrystalline silicon 314 as an emitter electrode of the lateral PNP transistor and a base electrode of the NPN type multi-emitter transistor is formed in the reduced opening and its peripheral portion. Further, a silicon oxide film 315 is formed on the surface of the polycrystalline silicon 314, and exposed portions of the silicon nitride film patterns 308a and 308b are removed by hot phosphoric acid. At this time, on the side of the lateral PNP transistor, a P ⁺ type region 316a as an emitter electrode extraction region is formed in the P type region 310a by diffusion of boron from the polycrystalline silicon 314. On the other hand, NPN
On the type multi-emitter transistor side, a P ⁺ type region 316b as a base electrode extraction region is formed in the P type region 310b by boron diffusion from the polycrystalline silicon 314. In yet NPN-type multi-emitter transistor side, polycrystalline by diffusion of arsenic from the silicon pattern 306 b, as four emitter region is divided into four as shown in the plan view of FIG. 7 in the P-type region 310b N ⁺ A mold region 317 is formed. After that, a silicon oxide film 318 is formed on the entire surface by the CVD method, contact holes are opened, and metal wirings 319a, 319b, 319c, 3 are formed.
19d is formed.

8 and 9 show a third embodiment of the present invention. The third embodiment is a case where the base electrode is drawn from the surface of the element formation region to manufacture a lateral transistor.

To explain this third embodiment, first, referring to FIG.
As shown in (A), N ^-- on the P ^-- type silicon substrate 401.
Type epitaxial layer is grown, and a part of the epitaxial type epitaxial layer is converted into an element isolation oxide film 402 to form an island region 4 of the epitaxial layer.
Form 03. Next, a polycrystalline silicon film 404 having a thickness of 2000 to 3000 Å is formed on the entire surface of the island region 403 and the element isolation oxide film 402, that is, the entire surface of the semiconductor substrate, and the silicon oxide film 40 having a thickness of about 200 Å is formed on the surface thereof.
5 is formed. Then, B (boron) is introduced into the polycrystalline silicon film 404 by an ion implantation method through the silicon oxide film 405, and then a left and right pair is formed by using a CVD method (chemical vapor deposition method) and a known photolithographic etching technique. Silicon nitride film patterns 406a and 406b are formed.

Next, the silicon nitride film pattern 406.
By selectively oxidizing the polycrystalline silicon film 404 using a and 406b as a mask, the pair of left and right polycrystalline silicon patterns 404a and 404b are sandwiched by the selective oxide film 407 on the island region 403 as shown in FIG. 8B. It is formed so as to extend on the isolation oxide film 402. At this time, the B (boron) introduced into the polycrystalline silicon film 404 is the island region 40.
3 is diffused into the surface region of the island region 403 to form a P-type region 408 as a base.

Next, the silicon nitride film pattern 406a,
As (arsenic) is introduced into the polycrystalline silicon patterns 404a and 404b through the 406b and the silicon oxide film 405 by an ion implantation method. At this time, the acceleration energy is 200 keV, and the dose is 2.0 × 16 ¹⁶ cm ^-2 . With this acceleration energy, As (arsenic) does not reach the island region 403. After that, the selective oxide film 407 in a portion which will be a lead-out portion of the base electrode in the future is removed as shown in FIG. 8C to form an opening 417.

After that, the opening 41 is formed as in the first embodiment.
As shown in FIG. 9, a sidewall 410 of polycrystalline silicon is formed by sandwiching a silicon oxide film 409 on the sidewall of 7.
Shrink the opening. Further, B (boron) -doped polycrystalline silicon 411 as a base electrode is formed in the reduced opening and its peripheral portion. Further, a silicon oxide film 412 is formed on the surface of the polycrystalline silicon 411,
The exposed portions of the silicon nitride film patterns 406a and 406b are removed by hot phosphoric acid. At this time, boron diffuses from the polycrystalline silicon 411 to form a P ⁺ type region 413 as a base electrode extraction region in the P type region 408. Further, due to the diffusion of arsenic from the polycrystalline silicon patterns 404a and 404b, a pair of left and right emitter regions and N ⁺ type regions 414 as collector regions are formed in the P type region 408 as shown in the plan view of FIG. After that CVD
Method is used to form a silicon oxide film 415 on the entire surface, contact holes are opened, and metal wirings 416a, 416b,
416c is formed.

[0039]

As described in detail above, according to the present invention, the device area, particularly the emitter area, has been conventionally reduced in order to reduce the propagation delay time. In order to solve the problem of having to operate the transistor in a situation where it cannot exhibit, in order to increase the emitter area without increasing the element area,
By using the polycrystalline semiconductor pattern used as the base electrode and used as the diffusion source of the inactive base as the diffusion source of the emitter, the ratio of the emitter area can be reduced from about 8% to about 80% in the same base area. Can be made bigger. Therefore, without increasing the capacity
It is possible to prevent deterioration of transistor performance in the high current range and further increase the grounded emitter current amplification factor.
The drive capability of the transistor is increased. Therefore, it becomes possible to operate the transistor under the optimal conditions in terms of the circuit, and it can be expected to reduce the propagation delay time.

Further, according to the present invention, when the polycrystalline semiconductor pattern is formed by selective oxidation, it is formed on the island region so as to be divided into a plurality of pieces as viewed from above, and the divided polycrystalline pieces are formed. By forming the emitter region by impurity diffusion from the semiconductor pattern, the emitter can be divided easily and a multi-emitter transistor can be easily manufactured.
Therefore, it becomes possible to easily form the I ² L circuit by simultaneously forming the opposite type transistors in the same island region. Therefore, it becomes possible to assemble a circuit with low power consumption and a high degree of integration, and it can be expected that the utilization range of the integrated circuit device will be greatly expanded.

Further, according to the present invention, when the polycrystalline semiconductor pattern is formed by selective oxidation, the selective oxide film is sandwiched to form a pair of left and right polycrystalline semiconductor patterns, and the pair of polycrystalline semiconductor patterns are formed. By forming the emitter and collector regions by impurity diffusion and drawing the base electrode from the portion where the selective oxide film is removed by using a polycrystalline semiconductor, a lateral transistor can be formed by drawing the base electrode from the surface of the element forming region. .. Therefore, the capacitance can be significantly reduced, a transistor with excellent high-speed performance can be manufactured as a lateral transistor, and the element area can be significantly reduced, so that the degree of integration of elements can be expected to be increased.

[Brief description of drawings]

FIG. 1 is a process sectional view showing a part of a first embodiment of the present invention.

FIG. 2 is a process sectional view showing a part of the first embodiment of the present invention.

FIG. 3 is a process sectional view showing a part of the first embodiment of the present invention.

FIG. 4 is a plan view of an essential part in the first embodiment of the present invention.

FIG. 5 is a process sectional view showing a part of a second embodiment of the present invention.

FIG. 6 is a process sectional view showing a part of a second embodiment of the present invention.

FIG. 7 is a plan view of an essential part of the second embodiment of the present invention.

FIG. 8 is a process sectional view showing a part of a third embodiment of the present invention.

FIG. 9 is a process sectional view showing a part of a third embodiment of the present invention.

FIG. 10 is a plan view of an essential part in a third embodiment of the present invention.

FIG. 11 is a process cross-sectional view showing a part of a conventional manufacturing method.

FIG. 12 is a process sectional view showing a part of a conventional manufacturing method.

[Explanation of symbols]

201, 301, 401 P ⁻ type silicon substrate 204a, 304, 403 Island region 205, 306, 404 Polycrystalline silicon film 205a, 306b, 404a, 404b Polycrystalline silicon pattern 209, 310b, 408 P type region 217, 317, 414 N ⁺ type region 407 Selective oxide film 411 Polycrystalline silicon 413 P ⁺ type region

Claims (5)

[Claims] 1. A semiconductor substrate having a first conductivity type island region, and a second base as a base formed in a surface portion of the island region.
A conductive type region, a polycrystalline semiconductor pattern formed on the second conductive type region so as to surround a part of the second conductive type region, and a second conductive type region immediately below the polycrystalline semiconductor pattern. ,
A bipolar semiconductor device comprising: a first conductivity type region as an emitter formed along an outer peripheral portion of an island region. 2. A second-conductivity-type polycrystalline semiconductor film is formed on a semiconductor substrate having a first-conductivity-type island region, and the polycrystalline semiconductor film is selectively oxidized to form an island region on the island region. Form a polycrystalline semiconductor pattern to surround a part,
At the same time, a second conductivity type region as a base is formed in the surface portion of the island region by impurity diffusion from the polycrystalline semiconductor film, and then the first conductivity type impurity is introduced into the polycrystalline semiconductor pattern to form the polycrystalline semiconductor pattern. A method for manufacturing a bipolar semiconductor device, wherein a first conductivity type region as an emitter is formed in the second conductivity type region by impurity diffusion from a semiconductor pattern. 3. When the polycrystalline semiconductor pattern is formed on the island region by selective oxidation so as to surround a part of the island region, the polycrystalline semiconductor pattern is formed so as to be further divided into a plurality of portions when viewed from above. 3. A method of manufacturing a bipolar semiconductor device according to claim 2, wherein a plurality of first conductivity type regions as a plurality of emitters are formed in the second conductivity type region by impurity diffusion from each polycrystalline semiconductor pattern. .. 4. A semiconductor substrate having an island region of the first conductivity type, and a second base as a base formed in a surface portion of the island region.
A conductive type region, a pair of left and right polycrystalline semiconductor patterns provided on the second conductive type region, and a left and right pair formed as an emitter and a collector in the second conductive type region immediately below the pair of polycrystalline semiconductor patterns. A first conductive type region, a polycrystalline semiconductor as a base electrode formed between the pair of polycrystalline semiconductor patterns and insulated from these patterns, and in the second conductive type region immediately below the polycrystalline semiconductor. A high-concentration second-conductivity type region as a base electrode lead-out region formed on the substrate. 5. A polycrystalline semiconductor film of the second conductivity type is formed on a semiconductor substrate having an island region of the first conductivity type, and the polycrystalline semiconductor film is selectively oxidized to select the island region on the island region. A pair of left and right polycrystalline semiconductor patterns are formed by sandwiching the oxide film, and at the same time, a second conductivity type region as a base is formed in the surface portion of the island region by impurity diffusion from the polycrystalline semiconductor film,
Thereafter, a first conductivity type impurity is introduced into the pair of polycrystalline semiconductor patterns, and impurities are diffused from the polycrystalline semiconductor pattern to form a pair of left and right first conductivity type regions as an emitter and a collector in the second conductivity type region. On the other hand, the selective oxide film between the pair of polycrystalline semiconductor patterns is removed, and the second conductive type polycrystalline semiconductor as a gate electrode is formed by insulating the selective oxide film between the pair of polycrystalline semiconductor patterns. A method for manufacturing a bipolar semiconductor device, comprising forming a high-concentration second conductivity type region as a base electrode lead-out region in the second conductivity type region.