JPH05208012A - Ultrasonic diagnosing system - Google Patents

Abstract

PURPOSE:To realize a variety of composite modes at a high speed with the simple constitution. CONSTITUTION:This ultrasonic diagnosing system can continuously carry out the execution in a plurality of modes and is equipped with a FIFO memory 26, control data setting means, RAM 28, RAM read-out control circuit 31, and a receiving/transmission means, and reads out the control data in the RAM 28 according to the execution order memorized in the FIFO memory 26, and receiving/transmission-processes the ultrasonic pulse according to the control data corresponding to the result of read-out.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an ultrasonic diagnostic apparatus, and more particularly to an ultrasonic diagnostic apparatus capable of continuously executing a plurality of diagnostic modes such as color Doppler mode and M mode.

[0002]

2. Description of the Related Art In an ultrasonic diagnostic apparatus, it is possible to observe the in-vivo condition by setting diagnostic modes such as B mode, M mode and Doppler mode. In these diagnostic modes, an ultrasonic pulse is normally transmitted into the living body, and information is obtained from its reflected echo. For example, in the B mode, a plurality of ultrasonic pulses are sequentially transmitted to scan the inside of the living body to obtain a tomographic image of the living body. Further, in the M mode, ultrasonic pulses are transmitted in one direction at predetermined time intervals to obtain the temporal movement of the living body at that portion. Further, in the Doppler mode, ultrasonic pulses are transmitted a plurality of times in one direction, and the flow velocity distribution of blood flow in the living body is obtained by the Doppler effect.

These diagnostic modes may be performed individually, but recently, a composite mode such as BM and BD is performed. In the combined mode that executes two or more diagnostic modes, the time interval (repetition frequency: PR
Two or more types of F) are prepared, and they are sequentially switched and transmitted. Also, at the time of transmission and reception at each PRF,
A mode signal and various status signals indicating which diagnostic mode the currently executed transmission is in are generated.

Conventionally, such PRF switching and generation of mode signals and various status signals use a microprocessor or a dedicated switching circuit.

[0005]

In recent years, in addition to the B, M and Doppler modes described above, a diagnostic mode called a color Doppler mode has been used as a diagnostic mode. In the color Doppler mode, the blood flow velocity data in the Doppler mode is combined with the tomographic data of the B mode image to express the blood flow velocity in two dimensions and in real time in color. That is, the tomographic information and the blood flow information are digitized and combined, converted into R, G, and B television signals, and the average velocity profile of the detected blood flow is superimposed on the normal tomographic image. Are displayed in color.

[0006] When continuously switching the combined mode of the color Doppler mode and the above-mentioned mode, the type of PRF and the switching order become complicated.
In addition, there are many types of combinations of switching orders. When the PRF is switched and various status signals are generated by the microprocessor in such a case, PRF data for the next transmission pulse, a mode signal and other status signals must be prepared during one PRF cycle. I won't.

However, in the case of a high frequency Doppler mode, one cycle becomes short, so that all the data cannot be prepared by the microprocessor in time. In addition, when the number of types of data to be prepared increases, it may happen that one cycle is too late. Further, if these complicated switchings are realized by a dedicated switching circuit, the circuit configuration becomes complicated, and the circuit configuration becomes large in order to realize all the various switchings such as various composite modes. I will end up.

An object of the present invention is to realize various combinations of composite modes with a high speed and a simple structure.

[0009]

An ultrasonic diagnostic apparatus according to the present invention is capable of continuously executing a plurality of diagnostic modes and comprises a first storage means, a control data setting means and a second storage means.
The storage means, the reading means, and the wave transmitting / receiving means are provided. The first storage means stores the execution order of the diagnostic modes.
The control data setting means sets a plurality of control data according to each diagnostic mode. The second storage means stores the control data for each diagnostic mode set by the control data setting means. The reading means stores the contents stored in the second storage means into the first content.
Reading is performed according to the execution order stored in the storage means. The transmission / reception unit performs transmission / reception processing of the ultrasonic pulse with the control data according to the reading result of the reading unit.

[0010]

In the ultrasonic diagnostic apparatus according to the present invention, the execution order of the diagnostic modes is stored in the first storage means during diagnosis. Also,
A plurality of control data according to the diagnostic mode is set by the control data setting means. The set control data is the second
It is stored in the storage means. When these storages are completed and the diagnosis is started, the storage contents of the second storage means are sequentially read out in the order of execution stored in the first storage means. At the time of this reading, the control data according to each diagnostic mode is read, and the ultrasonic pulse is transmitted / received by the control data.

Therefore, various diagnostic modes can be supported without providing a dedicated switching circuit and the like, and high-speed processing using a microprocessor becomes possible.

[0012]

FIG. 1 shows an ultrasonic diagnostic apparatus according to an embodiment of the present invention. Here, an example will be described in which the color Doppler B mode and the M mode can be combined. In the figure, the probe 1 is composed of a plurality of transducers, is applied to the surface of the subject 2, transmits an ultrasonic beam into the subject 2, and receives reflected echoes from the subject 2. Probe 1
A pulsar group 3 is connected to. Pulsar group 3
A high frequency pulse is applied to each transducer of the probe 1. An amplification group 4 is connected to the probe 1.

The amplification group 4 is composed of a plurality of amplifiers, is provided corresponding to each transducer of the probe 1, and amplifies the reflected echo received. The amplification group 4 is connected to the waveform processing circuit 5. The waveform processing circuit 5 is for performing waveform processing on the signal from the amplification group 4 to obtain a signal that can be stored in a digital scan converter (hereinafter referred to as DSC) 6. This output signal is a B mode signal or an M mode signal. The amplification group 4 is connected to the mixer waveform processing circuit 7.

The mixer waveform processing circuit 7 mixes the received reflected echo with the reference signal from the transmission system. The output of the mixer waveform processing circuit 7 is the A / D conversion circuit 8
And the speaker 11. The A / D conversion circuit 8 performs A / D conversion on the output of the mixer waveform processing circuit 7. The A / D conversion circuit 8 is connected to the color Doppler calculation circuit 9a and the Doppler mode calculation circuit 9b. The color Doppler calculation circuit 9a is for calculating a mean blood flow value or the like for color Doppler by performing correlation calculation processing or the like on the A / D-converted Doppler signal. The Doppler mode calculation circuit 9b is for calculating the blood flow velocity distribution by performing a fast Fourier transform on the A / D converted Doppler signal.

The color Doppler calculation circuit 9a and the Doppler mode calculation circuit 9b are connected to the DSC 6.
For example, in the DSC6, in the color Doppler B mode, B
The mode image and the color Doppler image are combined. In the M mode, nothing is output from each of the calculation circuits 9a and 9b, and an M mode image is obtained by the output from the waveform processing circuit 5. The DSC 6 is connected to the CRT 10.
The CRT 10 displays a color Doppler image, an M mode image and the like. Further, in the Doppler mode, the spectrum image is displayed and the Doppler sound can be observed by the speaker 11 connected to the mixer waveform processing circuit 7.

These pulser group 3, mixer waveform processing circuit 7, waveform processing circuit 5, DSC 6, color Doppler calculation circuit 9a, Doppler mode calculation circuit 9b, and CR.
The control circuit 14 is connected to T10. Control circuit 1
4 controls each of these parts and also controls the pulsar group 3
Control the transmission timing of. FIG. 2 is a block diagram showing the configuration of the control circuit 14. The control circuit 14 includes a RAM,
A CPU 20 having a memory such as a ROM is provided. C
A queue buffer 24 is provided in the RAM of the PU 20. This function will be described later. The CPU 20 has
The timer 25 and the gate selection circuit 21 are connected. The timer 25 is for controlling the write timing of the FIFO memory 26 described later. The gate selection circuit 21 outputs a gate selection signal for selecting a transmission interval (PRF) and also outputs various control signals. The gate selection circuit 21 includes a trigger generation circuit 22.
It is connected to the. The trigger generation circuit 22 outputs an original trigger signal for setting the transmission interval.
The trigger generation circuit 22 includes a transmission timing generation circuit 23.
It is connected to the. The transmission timing generation circuit 23 is connected to the pulsar group 3 and outputs a signal that determines the transmission timing in the pulsar group 3.

The gate selection circuit 21, as shown in FIG. 3, is a FIFO memory 26, a selection circuit 27, a RAM 28,
A latch circuit 29, a counter 30, and a RAM read control circuit 31 are provided. The FIFO memory 26 is the CPU 20
For storing the pulse transmission order data given from the above and outputting them sequentially as the upper address when reading the RAM 28. The selection circuit 27 receives the write address of the RAM 28 given from the CPU 20 and the FIF.
This is for switching the read address of the RAM 28 given from the O memory 26 and the counter 30 described later. As shown in FIG. 9, the RAM 28 stores control data regarding the ultrasonic beam for each transmission. These are divided into blocks and stored for each beam. The head addresses of these blocks are designated by the FIFO memory 26, and the lower addresses are designated by the counter 30.

The latch circuit 29 outputs the output RM of the RAM 28.
Each control data that is OUT is latched by using the count signal of the counter 30 as a latch trigger. Latch circuit 2
Of the 9 outputs, the data of the transmission interval is the gate selection signal G
It is given to the trigger generation circuit 22 as SS. Also,
Other data is given to other circuits such as the delay amount setting circuit. The trigger generation circuit 22 outputs the original trigger signal OTG to the RAM read control circuit 31 in response to the gate selection signal GSS. The RAM read control circuit 31 outputs a count request signal / CRQ (hereinafter / indicates negative logic) to the counter 30 and a write inhibit request signal / WIRQ to the CPU 20. Also, the FIFO
Read request signal / RRQ to the memory 26 and RAM 28
Is output. The block data written in the RAM 28 is given from the CPU 20 before the diagnosis.

As shown in FIG. 4, the trigger generation circuit 22 is composed of n counters 32, an OR circuit 33, a decoder 34, and a clock generation circuit 35.
The gate selection signal GSS from the gate selection circuit 21 is applied to the decoder 34. The decoder 34 decodes the gate selection signal GSS and, in accordance with the result of the decoding, the gate signal G for selectively selecting each counter.
Outputs T1 to GTn. The clock from the clock generation circuit 35 is applied to the n counters 32,
Only one counter selected by the gate signals GT1 to GTn counts the input clock. The count end values CN1 to CNn of each counter are given from the CPU 20. The count end values CN1 to CNn are determined according to the transmission cycle. The output of each counter is the OR circuit 33.
Is given to and the logical sum is taken. The output of the OR circuit 33 is the original trigger signal OTG, which is RA of FIG.
It is given to the M read control circuit 31 and the transmission timing generation circuit 23 of FIG.

As shown in FIG. 5, the latch circuit 29 (FIG. 3) is composed of, for example, eight latches 41. A count signal from the counter 32 (FIG. 3) is given to each latch as latch triggers / LTG0 to LTG7. Next, the control operation of the CPU 20 will be described based on the flowcharts shown in FIGS.

First, in step S1, R in the CPU 20
Initialize the contents of AM. In step S2, it is determined whether or not an operator has set a diagnostic mode or input a pulse repetition frequency (PRF). If it is determined that there is no input, the process proceeds to step S3. Step S
At 3, it is determined whether or not another command is issued. If it is determined that no other command has been issued, the process proceeds to step S4. In step S4, data for scanning required during scanning is prepared. When the process in step S4 ends, the process returns to step S2.

When it is determined in step S2 that the operator has input a key, the process proceeds to step S5. Input processing is performed in step S5. If it is determined in step S3 that another command has been issued, the process proceeds to step S6. In step S6, other processing according to the command is performed. In the input processing of step S5, as shown in FIG.
First, in step S11, scanning is prohibited. This allows
Ultrasonic beam emission stops. In step S12,
Find the mode signal required for the composite diagnostic mode set by the operator. Further, in step S13, a transmission focus selection signal is obtained according to the set focus distance, and in step S14, transmission / reception time data (transmission cycle) is obtained. It should be noted that although only three data are obtained here for simplification of description, other data are actually obtained. In step S15, step S1
The data group for one group obtained in 2 to step S14 is written in the RAM 28. Here, the data group for one group is a data group read from the RAM 28 during one preparation period for transmission and reception. Therefore, step S15
As a result of the above process, as shown in FIG. 9, a group of data consisting of a mode signal, transmission / reception time data, a transmission focus selection signal, etc. is written in one block of the RAM 28. In step S16, the written upper address of the RAM 28 (block address of one group) is set to the CPU.
It is stored in the address table provided in the RAM in 20. In step S17, it is determined whether or not all the data regarding the diagnostic mode, the transmission / reception time, and the focus set by the operator have been obtained. Steps S12 to S17 are repeatedly executed until all data are obtained.

If all the data have been obtained, step S
The procedure moves from 17 to step S18. In step S18, the contents of the FIFO memory 26 are cleared. In step S19, the upper address of the RAM 28 at the beginning of the scanning procedure is obtained and written in the queue buffer 24 (FIG. 2). The queue buffer 24 is a queue memory area provided on the RAM of the CPU 20, and the capacity of this area is the same as or larger than that of the FIFO memory 26. In step S20, the upper address of the RAM 28 next to the scanning procedure is obtained from the address table and written in the queue buffer 24. Here, the scanning procedure is determined by referring to the address table according to the diagnostic mode set by the operator. In step S28, it is determined whether the area of the queue buffer 24 is completely filled. If not completely filled, step S24
Then, the upper addresses of the scanning procedure are written in the queue buffer 24 from the address table one after another. Step S2
If it is determined that the queue buffer 24 is full in step 1, the process proceeds to step S22.

In step S22, the queue buffer 24
The address data of the upper address is extracted from the
Output to the O memory 26. In step S23, the FIF
It is determined whether or not all areas of the O memory 26 have been filled with address data. The operation of step S22 is continued until the address data is completely filled. When all the areas of the FIFO memory 26 are filled with the address data, the process proceeds to step S24. In step S24, the timer 25 is set. Here, the timer 25 is FI
After filling the FO memory 26 with address data, the next FI
This is for giving the time until the writing to the FO memory 26 is started, and is set shorter than the time until the FIFO memory 26 becomes empty. This time may be variable depending on the factors of the scanning mode and the transmission / reception mode. The timer 25 is provided with setting data of the timer time from the CPU 20. Then, the time-up signal of the timer 25 is given to the CPU 20. In step S25, scanning is permitted upon receipt of this time-up signal. When the scanning is permitted, the transmission of the ultrasonic beam is restarted and the scanning is executed.

In the in-scan preparation process of step S4, preparation for the next ultrasonic beam transmission is performed during scanning. That is, as shown in FIG. 8, first, in step S31, the upper address of the RAM 28 to be written next in the queue buffer 24 is obtained from the address table and written in the queue buffer. In step S32, it is determined whether the area of the queue buffer 24 is completely filled. If all are filled, the process proceeds to step S33. In step S33,
It waits for the time-out of the timer set in step S24 of FIG. 7 or step S36 described later. Timer 2
When 5 is timed up, the process proceeds to step S34. In step S34, the address data is extracted from the queue buffer 24 and output to the FIFO memory 26. In step S35, it is determined whether the FIFO memory 26 is full. The process of step S34 is continued until the FIFO memory 26 is full, and when it is determined that the FIFO memory 26 is full, the process proceeds to step S36. In step S36, the timer 25 is set and the process returns to the main routine.

Next, a concrete operation will be described with reference to an example shown in FIG.
It will be described based on. Here, first of all, Colored Plamo
Mode and then M mode,
Take the case of the Doppler mode as an example. Where
Eight ultrasonic beams in one direction in Doppler mode
The transmission period is t₁Is. Also with the next line
The transmission period between is to eliminate the effects of residual echo
, T₁Longer period t₂I am trying. Further colored
The transmission cycle between puller mode and M mode is similar.
Long period t due to reasons₃I am trying. Also, M mode
Transmission cycle is t_FourAnd M-mode and Colored Plamo
The transmission cycle between the _FiveIs. These transmission cycles
Transmission focus selection signal and transmission / reception of each group A to E for each
As shown in FIG. 9, the transmission time data, the mode signal, etc.
The data is divided into blocks and stored in M28. And queue
The buffer 24 and the FIFO memory 26 have this group.
The top addresses of blocks (blocks) are shown in the order of transmission in FIG.
To be remembered. Therefore, on the FIFO memory 26
By reading the RAM 28 according to the place address,
The contents of the RAM 28 are read in the block transmission order.

FIG. 11 shows the processing contents from transmission to the next transmission, and when transmission is carried out for a predetermined time, reception is carried out immediately. When the reception is completed, preparation for the next transmission is performed. During this preparation period, the during-scan preparation process shown in FIG. 8 is executed, and various control data are set. FIG. 12 is a timing chart showing the contents of the data set during the preparation period.

Here, first, the trigger generation circuit 22
Original trigger signal / OT output from (Fig. 3)
When G is enabled, the write inhibit request signal / WIRQ, read request signal / RRQ and count request signal / CRQ output from the RAM read control circuit 31 are sequentially enabled. Read request signal / RRQ
Is enabled, the upper address FIOUT is output from the FIFO memory 26 to the RAM 28 via the selection circuit 27. Then, when the preparation period ends, the transmission start request signal / TS is transmitted from the transmission timing generation circuit 23 (FIG. 2).
R is output to the pulsar group 3.

More specifically, as shown in FIG. 13, the first upper address FIOUT = “A” is output from the FIFO memory 26, and the count request signal /
When the CRQ is enabled, the counter 30 outputs the count signal CNT and specifies the lower address of the RAM 28. Then, from the RAM 28, the data RM of the A group
OUT (D _{A, 0 to} D _{A, 7} ) are sequentially output. Further, the latch trigger signals / LTG0 to / LTG7 are sequentially output, and the data RMOUT output from the RAM 28 is sequentially latched by the latch circuit 29.

In this way, the group data RMOUT is sequentially read from the RAM 28. According to this data, in the example shown in FIG. 10, the ultrasonic beam for the color Doppler mode is repeatedly transmitted 7 times at the period t ₁ and then one ultrasonic beam is transmitted at the period t ₂ , Further, the ultrasonic beam is repeatedly transmitted 7 times at the cycle t ₁ . After that, after the data of group C is read, D
Group of data is read, after a single ultrasonic beam is transmitting in the period t _3, the ultrasonic beam is repeatedly transmitting in one direction with a period t _4. Further, at the end of the M mode, one ultrasonic beam is transmitted at the cycle t ₅ , and then A
The data of group B and B are read out, and the color Doppler mode is executed.

On the other hand, in the trigger generation circuit 22, when a key input for setting the transmission cycle is made, the CPU 20
From this, counting end values CN1 to CNn corresponding to the transmission cycle are given, and the count value of each counter 32 is set. Then, when the gate selection signal GSS is given from the gate selection circuit 21 during scanning, the decoder 34 analyzes the content thereof and the gate signals GT1 to GT for selecting each counter.
Enable any of Tn. For example, in the example shown in FIG. 14, the gate signal GT1 is _first enabled for a period of t ₁ × 7, and the original trigger signal O is transmitted at the transmission cycle t _1.
Output TG. Then, during the period of t ₂ , the gate signal GT
2 is enabled, the original trigger signal OTG of the transmission cycle t ₂ is output, and subsequently, the original trigger signal OTG of the transmission cycle t ₁ is output. The transmission cycles of the C group, the D group, and the E group are set in the counters 3, 4, and 5 (not shown), respectively. Can be operated alternatively to obtain the original trigger signal OTG of each cycle.

Counters are prepared for different types of transmission cycles, and the count end values CN1 to CNn are given to each counter from the CPU 20 for each key input, so that different transmission cycles can be easily set by selecting the counter during transmission. Obtainable. Therefore, the count values CN1 to C are transmitted during transmission.
Since it is not necessary to change Nn, high speed operation becomes possible.

[Modification] Although the ultrasonic beam selection information (beam number) is not described in the above embodiment,
The beam number is necessary for setting the delay amount and selecting the transducer of the probe 7. Beam number is RAM2
When output from 8, the number of blocks shown in FIG. 9 increases. In this case, as shown in FIG. 15, a FIFO memory 52 is provided, the beam number is written from the queue buffer 51 in the CPU 20 to the FIFO memory 52, and the beam number BNO is read from the FIFO memory 52 in synchronization with the FIFO memory 26. Good.

[0034]

In the ultrasonic diagnostic apparatus according to the present invention, the first
The scanning order is stored in the storage means, the control data is stored in the second storage means, and the control data is read out in the execution order and transmitted / received. Therefore, various diagnostic modes can be performed by simple control without using complicated circuits. Can be continuously executed.

[Brief description of drawings]

FIG. 1 is a schematic block diagram of an ultrasonic diagnostic apparatus according to an embodiment of the present invention.

FIG. 2 is a block diagram of a control circuit.

FIG. 3 is a block diagram of a gate selection circuit.

FIG. 4 is a block diagram of a trigger generation circuit.

FIG. 5 is a block diagram of a latch circuit.

FIG. 6 is a control flowchart of the CPU.

FIG. 7 is a flowchart showing the contents of input processing.

FIG. 8 is a flowchart showing the contents of a preparatory process during scanning.

FIG. 9 is a diagram showing the contents stored in a RAM.

FIG. 10 is a diagram showing an example of a composite diagnosis mode.

FIG. 11 is a diagram showing a state between transmission cycles.

FIG. 12 is a timing chart of a gate selection circuit.

FIG. 13 is a timing chart of a gate selection circuit.

FIG. 14 is a timing chart of a trigger generation circuit.

FIG. 15 is a block diagram corresponding to a part of FIG. 2 of a modified example.

[Explanation of symbols]

 1 probe 3 pulser group 4 amplification group 5 waveform processing circuit 6 DSC 7 mixer waveform processing circuit 8 A / D conversion circuit 9 blood flow calculation circuit 10 CRT 14 control circuit 20 CPU 21 gate selection circuit 22 trigger generation circuit 23 transmission timing generation circuit 26 FIFO Memory 27 Selection Circuit 28 RAM 29 Latch Circuit 30 Counter 31 RAM Read Control Circuit 32 Counter

Claims (1)

[Claims] 1. An ultrasonic diagnostic apparatus capable of continuously executing a plurality of diagnostic modes, comprising: first storage means for storing an execution order of the diagnostic modes; and a plurality of control data according to each diagnostic mode. Control data setting means for setting, second storage means for storing control data for each diagnostic mode set by the control data setting means, and storage contents of the second storage means are stored in the first storage means. An ultrasonic diagnostic apparatus comprising: a reading unit that reads according to the order of execution; and a wave transmitting / receiving unit that transmits / receives an ultrasonic pulse with control data according to the read result of the reading unit.