JPH0520800A - Magnetic recording and reproducing device - Google Patents

Abstract

PURPOSE:To reduce the size of a PLL circuit configuration for the reproduction of multi-tracks with plural heads by processing the reproduction clock, which is obtained through the PLL, with a phase shifter. CONSTITUTION:Two or plural number of magnetic heads 601 and 602 reproduce two or plural number of channel tracks and the reproduced clock is processed by a PLL, which consists of a phase comparator 13, a loop filter 14 and a VCO 15, through a switch 11. And the output of the PLL is phase shifted by phase shifters D type FF 161 and 162 which correspond to the heads 601 and 602, respectively. Having this configuration, no need to provide a PLL corresponding to a head and a single PLL generates a clock whose phase is matched with the simultaneously reproduced data of multi-tracks. As a result, the size of the PLL circuit configuration, which simultaneously reproduces a clock, is reduced during the simultaneously reproduction of multi-tracks.

Description

Detailed Description of the Invention

[0001]

The present invention relates to a PLL (Phase Locked L
More specifically, the present invention relates to a magnetic recording / reproducing apparatus having a PLL circuit suitable for demodulating a digitally modulated signal or reproducing a clock.

[0002]

BACKGROUND ART record de _Lee digital signal, or a magnetic recording and reproducing apparatus for reproducing the reproduction de during reproduction - in order to enable generation of a clock from the data, Deijitarude -
The method of recording by modulating the data is adopted, and during playback,
A system in which a clock is reproduced and data is discriminated by a PLL circuit and data is demodulated is generally used. Among such magnetic recording / reproducing apparatuses, there is a multi-track PCM recorder which distributes and records an input digital signal to a plurality of tracks.

[0003]

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention
In the case of multi-track recording as described in Japanese Patent No. 66520, each track is provided with a PLL circuit for clock reproduction and data identification. Therefore, there is a problem that the circuit scale becomes large and there are many adjustment points.

It is an object of the present invention to reduce the circuit scale of a PLL circuit for data identification and to adjust an adjustment part in a multi-track magnetic recording / reproducing apparatus which distributes a digital signal to a plurality of tracks and simultaneously records and reproduces. There is a reduction.

[0005]

According to the present invention, in a system for simultaneously recording and reproducing by a plurality of heads, the phases of the data recording currents flowing to the respective heads are matched at the time of recording, and at the time of reproduction, the reproduced magnetic tracks of the reproduced magnetic tracks are recorded. It is realized by reproducing the clock using any one of them and identifying the data of all tracks by the reproduced clock. Further, a clock phase shifter corresponding to each track is provided to generate a clock suitable for the phase of the reproduction data of each track to identify the data, which corresponds to device compatibility at the time of reproduction.

[0006]

The recording system digital signal processing circuit outputs a plurality of recording data at the same time after matching the phases of the respective data, and records them on the tape by a plurality of magnetic heads. At the time of reproduction, a transmission clock is reproduced from any one track by a PLL circuit including a phase comparator, a loop filter and a VCO, and the reproduction clock is provided on each track.
Input to the latch circuit for data identification.

In consideration of device compatibility, the reproduction clock is input to the clock phase shifter to generate a clock that matches the reproduction data phase of each magnetic track.
Data identification was performed with this phase-shifted clock to eliminate the effect of head step. Furthermore, in consideration of special reproduction, a tracking error control circuit for obtaining a tracking error signal from signals reproduced from a plurality of heads is provided, and the piezoelectric element is driven by this output error signal, and the head is positioned on the piezoelectric element. Is controlled so that it is on-track to the recording track.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIG. FIG. 1 is a block diagram of a magnetic recording / reproducing apparatus according to the present invention. In Figure 1, 1 is an input signal terminal, 2 is a recording system de _Lee digital signal processing circuit, a recording amplifier 301, 302, 401 and 402 switch, recording and reproduction control terminal 5, 601 and 602 the magnetic head, the 7 Magnetic tape, 8
Is a rotary drum, 901 and 902 are reproduction amplifiers, 101,
102 is a waveform equalizer circuit, 11 is a switch, 12 is a channel select terminal, 13 is a phase comparator, 14 is a loop filter, 15 is a voltage controlled oscillator (hereinafter, referred to as VCO), 161, 162 are D-FF. , 17 is a reproduction system digital signal processing circuit, and 18 is an output signal terminal.

The audio signal or video signal input from the input signal terminal 1 is converted into a digital signal, subjected to a predetermined process by the recording system digital signal processing circuit 2, and then divided into two systems for recording. Amplifier 30
1,302. The recording mode is selected for the recording / reproducing control terminal 5, and the recording current amplified by the recording amplifiers 301 and 302 is mounted on the rotary drum 8 via the switches 401 and 402.
1, 602, and the digital signal is recorded on the magnetic tape 7.

At the time of reproduction, the reproduction mode is selected for the recording / reproduction control terminal 5, and the signals simultaneously reproduced from the magnetic tape 7 by the magnetic heads 601 and 602 are reproduced via the switches 401 and 402. Amplifiers 901 and 902
The waveform is equalized, and the waveform equalization circuits 101 and 102 remove the intersymbol interference of the waveform, and then input to the PLL circuit including the phase comparator 13, the loop filter 14, and the VCO 15.
In the PLL circuit, a clock synchronized with the reproduced signal is reproduced from the reproduced signal, and then the D-FFs 161 and 162 identify the data. The identification data and the reproduction clock are sent to the reproduction system digital signal processing circuit 17 and subjected to a predetermined process to obtain the original audio signal or video signal at the output signal terminal 18.

At this time, the PLL circuit controls the switch 11 by the control signal from the channel select terminal 12 and uses the signal of one of the tracks reproduced from the magnetic head 601 or 602. ing. As the data identifying clock, the output clock of the PLL circuit is used as it is for both tracks. With this configuration, even in a system in which two tracks are reproduced at the same time, the D-FF 161 for data identification,
If two 162 are provided, the PLL circuit for clock recovery need only be one system, so the VCO 15 can be adjusted in only one place and the circuit scale can be reduced.

FIG. 2 is a diagram showing the formation of track patterns on a magnetic tape when multi-track recording is performed.
In FIG. 2, 191 and 192 are magnetic tracks.
The magnetic heads 601 and 602 are general double azimuth heads, have different azimuth angles from each other, and are provided with head steps corresponding to the track pitch. With this configuration, when the rotary drum 8 makes one rotation, the magnetic tape 7 has two
The magnetic tracks 191 and 192 of the book are simultaneously formed. Since the track pitch is determined by the mounting accuracy of the magnetic heads 601 and 602, narrow track recording of about 5 μm can be supported.

FIG. 3 shows the timing of the recording current. In FIG. 3, (a) is the recording current timing of the magnetic head 601, (b) is the recording current timing of the magnetic head 602, and (c) is the reproduction clock timing. As shown in FIG. 3, according to the present invention, the phase of the rising or falling of the recording data is determined by the magnetic head 60.
It is adapted to 1, 602. Therefore, the magnetization patterns of the magnetic tracks 191 and 192 shown in FIG. 2 maintain the phase relationship shown in FIG. That is, during reproduction, the same magnetic heads 601 and 60
When reproduced at 2, even if there is jitter on the rotary drum 8, the amount is the same between both tracks, so both reproduction data can be obtained at the same timing as the recording signal of FIG.

In FIG. 1, at the time of reproduction, for example, the phase comparator 13 and the ruler are controlled by the reproduction signal of the magnetic head 601.
The channel select terminal 12 is controlled so that the PLL circuit composed of the filter 14 and the VCO 15 is operated, and the switch 11 is set to the waveform equalization circuit 101 side.
At this time, the PLL circuit reproduces the clock of (c) in synchronization with the reproduction signal of the same timing as the recording signal shown in FIG. 3 (a), and uses the rising edge of this reproduction clock to generate D-
If the output signal of the waveform equalization circuit 101 is latched by the FF 161, the data can be identified. Further, since the phase of the output signal of the waveform equalization circuit 102 is as shown in FIG. 3B, the same reproduction clock of FIG.
If it is latched by F162, the data can be identified.

As described above, the present invention is achieved by matching the recording current phase relationship between the channels shown in FIG. The channel select terminal 12
For control of, it suffices to select the channel on the side where the envelope can be stably obtained using the envelope detection signal, etc.If the head on one side is clogged, the playback signal can be obtained by dropout for a long time. If you are no longer able to
The PLL circuit may be operated by controlling the channel select terminal 12 and switching the switch 11 to another channel.

FIG. 4 shows a circuit block diagram when a phase correction circuit is added to each channel. 4, the same parts as those in FIG. 1 are designated by the same reference numerals, and 20 is a clock phase shifter. The difference from the circuit operation of FIG. 1 is that the D- for data identification is used.
Points at which the clocks of the FFs 161 and 162 are independently given by the output signals of the clock phase shifter 20 (C1 and C2 in the figure)
It is in.

When performing self-recording / reproduction with one device, the circuit block shown in FIG. 1 may be used, but compatible reproduction is important in an actual device. For example, the magnetic heads 601 and 6 are used.
When reproduction is performed by another device in which the mounting step of 02 is slightly different, the phase relationship of the reproduction data does not become as shown in FIG. This is equivalent to the case where the bit period is constant but the phase is not managed at the recording current timing shown in FIG.

FIG. 5 shows the timing when there is a head step during reproduction. The reproduction signal timing when there is no head step is (a) and (c), which is the same as in FIG.
However, if the head level difference of the reproducing device is different from that at the time of recording, for example, as shown in (d),
The phase relationship between (a) and (d) is shifted. However, since the recording current has the timing shown in FIG. 3, the bit period is constant. At this time, as the reproduction clock for identifying data, the clock C2 shown in (e) is necessary in addition to the reproduction clock C1 shown in (b). The clock phase shifter 20 shown in FIG. 4 performs an operation of generating a clock signal C2 according to the phase difference between the output signals of the waveform equalization circuits 101 and 102 based on the clock C1 reproduced by the PLL circuit.

Although the case where the PLL operation is performed on the waveform equalizing circuit 101 side has been described above, the switch 11 may be selected on the waveform equalizing circuit 102 side. At this time, the clock signal reproduced by the PLL circuit is selected. The clock signal C1 may be generated based on C2.

FIG. 6 shows an embodiment of a clock phase shifter using a multiplexer. In FIG. 6, 211,
212 is a data input terminal, 22 is a clock input terminal, 2
3 is a phase difference detection circuit, 24 is a decoder, 251-259
Is a buffer, 26 is a switch, 27 is a multiplexer,
Reference numerals 281 and 282 are clock output terminals. In FIG.
The phase difference detection circuit 23 detects the phase relationship between the two data input from the data input terminals 211 and 212, sends the output signal to the decoder 24, determines the phase amount, and responds to the phase difference. Switch 26 is selected. On the other hand, the clock signal input from the clock input terminal is sent to the clock output terminal 281 and also input to the buffer 251.
The buffers 251-259 are connected in series, and the respective outputs are connected as taps to the switch 26 to form a multiplexer 27. That is, the output of each buffer 251-259 is delayed in phase by the delay of the buffer alone, and if the switch 26 is selected based on the detection result of the phase difference detection circuit 23, an arbitrary phase-shifted clock is output at the clock output terminal 282. Can be obtained.

FIG. 7 shows the operation timing of the clock phase shifter shown in FIG. When both data are input in the phase states shown in (a) and (c) in the figure, first, the rising edges of both data are detected, and these (b) and (d) are detected.
The phase error signal (e) is obtained from this signal. The decoder 24 selects a clock corresponding to the phase difference in the signal (e) by the switch 26 and outputs it to the clock output terminal 282. Similarly, when the phase difference further increases ((f) in the figure), the phase error signal (h) may be used for control. Since the buffer delay in a normal CMOS process is about 1 ns, if the nine stages of buffers are used as shown in this embodiment, ± 5 ns can be corrected with an accuracy of 1 ns. Can be easily achieved by increasing the number of buffers.

FIG. 8 shows an example of the current control type clock phase shifter, and the same parts as those in FIG. 6 are designated by the same reference numerals. 29 is a current conversion circuit, 311, 312 are constant current sources, 321 and 322 are PMOS transistors, 331,
332 is an NMOS transistor, and 341 and 342 are inverters. In the present embodiment, in contrast to the clock phase shifter of FIG. 6 described above, the phase of the clock is controlled by controlling the current flowing through the inverter in the CMOS integrated circuit. The operation of the phase difference detection circuit 23 is similar to that of FIG. 6, but in the present embodiment, the current conversion circuit 29 is operated by the output signal of the phase difference detection circuit 23, and the constant current sources 311 and 312.
Change the current value of. Since the operating speed of the CMOS circuit changes depending on the current flowing through the device, the current is controlled to increase when the phase of the output clock is advanced, and to decrease when the phase of the output clock is delayed. In FIG. 8, the PMOS transistor 321, the NMOS transistor 331, and the PMOS
The inverter 322 and the NMOS inverter 322 respectively constitute an inverter, and the inverters 341 and 34 are provided.
Reference numeral 2 is for delay correction inserted in the reference clock line. With this configuration, the reproduced clock C2 shown in FIG. 5 can be obtained at the clock output terminal 282.

The clock phase shifter of FIG. 8 described above is shown in FIG.
It is possible to change the phase of the clock linearly compared to. Of course, in this case, if it is desired to have a large variable width of phase shift, the number of inverter stages composed of PMOS and NMOS may be increased. In this embodiment, the power source and PMO
A constant current source is connected between the S transistors 321 and 322, but the GND and the NMOS transistors 331 and 332 are connected.
It goes without saying that you may connect between them.

The operation timing of the phase difference detection circuit shown in FIGS. 6 and 8 may be set in a preamble section composed of a single frequency signal recorded at the head of each magnetic track 191 and 192. Next, when the preamble section ends and becomes the data section, the detected phase error amount may be held until the end of the track.

On the other hand, in the magnetic recording / reproducing apparatus as shown in the present invention, a special reproducing mode (for example, Cu) for reproducing the tape in different tape speeds depending on the normal reproducing state.
e, Rev, etc.). In this mode, for example, 2
Considering the double speed, if no control is given to the head, the head scanning locus will be different from that already recorded, so that it is impossible to reproduce information from all recording tracks. In particular, segment recording is often used in a digital VTR that digitizes and records a video signal, and there is a problem that a good image cannot be obtained when the entire track cannot be reproduced.

FIG. 9 is a block diagram showing an embodiment of the present invention corresponding to such special reproduction. In FIG. 9, FIG.
The same parts as those in FIG. 4 are indicated by the same reference numerals, 35 is a tracking error control circuit, 36 is a drive circuit, and 37 is a piezoelectric element. The tracking error control circuit 35 detects the scanning condition of the head from the two signals reproduced from the magnetic heads 601 and 602, and a drive circuit 36 amplifies the error signal to drive the piezoelectric element 37. Piezoelectric element 37
Is a device whose mechanical position is deviated by the applied voltage. In the present invention, the magnetic heads 601 and 602 are additionally provided.
Is mounted. With these configurations, for example, 2
Magnetic heads 601 and 602 even during double speed special reproduction
Can be traced on the magnetic tracks 191 and 192 shown in FIG. The following clock recovery and data identification operations are exactly the same as those described with reference to FIGS.

The above description is based on the magnetic heads 601 and 602.
However, the amount of recorded information is large and the present invention can be applied to the case where the number of heads is four. At this time,
The latch D-FFs 161 and 162 shown in FIG. 1 may be provided for the number of tracks (four in this case). Similarly, for the embodiments of FIGS. 4 and 9, the clock phase shifters as shown in FIGS. 6 and 8 may be provided independently for each track. In the present embodiment, the recording / reproducing heads have been explained, but independent recording / reproducing heads may be used. Further, although the rotary head type magnetic recording / reproducing apparatus has been described in the present embodiment, the present invention can be applied to a multi-track type magnetic recording / reproducing apparatus using a fixed head as it is.

[0028]

As described above, if the magnetic recording / reproducing apparatus of the present invention is used, clock reproduction and data identification of signals of two or more tracks reproduced simultaneously can be realized by one PLL circuit, and the circuit scale is large. Effective in reducing the number of adjustments and adjustment points.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a diagram showing formation of a magnetic track on a magnetic tape.

FIG. 3 is a diagram showing a timing of a recording current.

FIG. 4 is a block diagram showing another embodiment of the present invention.

FIG. 5 is a diagram showing a timing when there is a head step during reproduction.

FIG. 6 is a diagram showing an embodiment of a clock phase shifter using a multiplexer.

7 is an operation timing chart of the clock phase shifter shown in FIG.

FIG. 8 is a diagram showing an embodiment of a current control type phase shifter.

FIG. 9 is a diagram showing an embodiment of the present invention corresponding to special reproduction.

[Explanation of symbols]

2 Recording system digital signal processing circuit 601, 602 Magnetic head 7 Magnetic tape 8 rotating drums 11 switch 12 Channel select terminal 13 Phase comparator 14 loop filter 15 VCO 161,162 D-FF 17 Reproduction system digital signal processing circuit 191,192 magnetic tracks 20 clock phase shifter 23 Phase difference detection circuit 251-259 Buffer 26 switch 311, 312 constant current source 35 ... Tracking error control circuit 37 ... Piezoelectric element

Claims (8)

[Claims] 1. A time axis compression circuit that divides a digital signal for each predetermined period and compresses the time axis, and a recording / reproducing head that records and reproduces the time axis compressed digital signal on a magnetic recording medium. A PLL circuit including a phase comparator, a loop filter, a voltage or current controlled oscillator for reproducing the transmission clock from the digital signal reproduced by the recording / reproducing head and identifying the data, and extending the time axis of the reproduced signal. In the magnetic recording / reproducing apparatus having a time axis expansion circuit, the recording / reproducing head is composed of a plurality of composite heads each having a different azimuth angle.
Data is recorded on the magnetic recording medium by supplying a recording current in which the phases of the data signals are matched with each other, and at the time of reproduction, one of the signals reproduced simultaneously from the magnetic head is used as a clock by the PLL circuit. The magnetic recording / reproducing apparatus is characterized in that the above clock is used for identifying the data reproduced from each head. 2. A time axis compression circuit that divides a digital signal every predetermined period to compress the time axis, and a recording / reproducing head that records and reproduces a time axis compressed digital signal on a magnetic recording medium. A PLL circuit including a phase comparator, a loop filter, a voltage or current controlled oscillator for reproducing a transmission clock from the digital signal reproduced by the recording / reproducing head and discriminating the data, and expanding the reproduced signal on the time axis. In a magnetic recording / reproducing apparatus having a time axis expansion circuit, the recording / reproducing head is composed of a plurality of composite heads each having a different azimuth angle, and at the time of reproduction, one of signals reproduced simultaneously from the magnetic head. A clock is reproduced from one signal by the PLL circuit, and the reproduced clock is input, so that the reproduced clock and the frequency are A clock phase shifter for generating a plurality of clock signals each having a different phase, and selecting a clock signal having the same phase as each of the plurality of reproduced signals for data identification Magnetic recording / reproducing device. 3. The magnetic recording / reproducing apparatus according to claim 2, wherein the clock phase shifter detects a phase difference detection circuit for detecting a phase difference between a plurality of input data, and an output of the phase difference detection circuit. It is composed of a decoder that determines the phase difference, a clock delayer that connects buffers in multiple stages and outputs each connection point to a plurality of taps, and a switch that is controlled by the output of the decoder and that connects the plurality of taps. While the reproduced clock signal is input to the buffer, the switch is switched by the output signals of the phase difference detection circuit and the decoder to output a clock signal whose phase matches the input data signal. And a magnetic recording / reproducing apparatus. 4. The magnetic recording and reproducing apparatus according to claim 2, wherein the clock phase shifter detects a phase difference between a plurality of input data, and an output signal of the phase difference detecting circuit. A current conversion circuit for converting the phase difference information into a current, a constant current source controlled by the current conversion circuit,
It is composed of an inverter delay device composed of a PMOS transistor and an NMOS transistor, the constant current source is connected between the PMOS transistor and a power supply or between the NMOS transistor and GND, and a reproduction clock signal is input to the inverter. With
By varying the current value of the constant current source according to the output signals of the phase difference detection circuit and the current conversion circuit and changing the delay amount of the inverter, a clock signal whose phase matches that of the input data signal is generated. A magnetic recording / reproducing apparatus characterized in that it is adapted to output. 5. The magnetic recording / reproducing apparatus according to claim 2, wherein the clock phase shifters are provided for the number of the reproducing heads. 6. The magnetic recording / reproducing apparatus according to claim 2, wherein a phase error detection operation by the clock phase shifter is input.
A magnetic recording / reproducing apparatus characterized in that a single frequency signal recorded in a preamble section of the data signal is used. 7. The magnetic recording / reproducing apparatus according to claim 1, wherein the head is installed on a piezoelectric element, and a tracking error control circuit that generates a tracking error signal from reproduced signals from the plurality of heads, A drive circuit for driving the piezoelectric element is provided, and the drive circuit is operated by the output signal of the tracking error control circuit during normal reproduction and special reproduction, and the magnetic head on the piezoelectric element is displaced to record. On-track to the completed track, and the PLL circuit reproduces a clock from any one of the signals reproduced simultaneously from the magnetic head, and the clock reproduces the data of the signals reproduced from the respective heads. A magnetic recording / reproducing apparatus characterized by being used for identification. 8. The magnetic recording / reproducing apparatus according to claim 2, wherein the head is installed on a piezoelectric element, and a tracking error control circuit that generates a tracking error signal from reproduced signals from the plurality of heads, A drive circuit for driving the piezoelectric element is provided, and the drive circuit is operated by the output signal of the tracking error control circuit during normal reproduction and special reproduction, and the magnetic head on the piezoelectric element is displaced to record. On-track to the completed track, the clock is reproduced by the PLL circuit from any one of the signals simultaneously reproduced from the magnetic head, and the reproduced clock is input and the frequency is the same as the reproduced clock. Multiple signals to be regenerated with a clock phase shifter that generates multiple clock signals with different phases A magnetic recording / reproducing apparatus characterized by selecting a clock signal whose phase matches with each other to perform data identification.