JPS63231769A - Bit synchronizing circuit - Google Patents

Bit synchronizing circuit

Info

Publication number
JPS63231769A
JPS63231769A JP62063701A JP6370187A JPS63231769A JP S63231769 A JPS63231769 A JP S63231769A JP 62063701 A JP62063701 A JP 62063701A JP 6370187 A JP6370187 A JP 6370187A JP S63231769 A JPS63231769 A JP S63231769A
Authority
JP
Japan
Prior art keywords
circuit
data
reproduction
fast
clock
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP62063701A
Other languages
Japanese (ja)
Other versions
JPH0770166B2 (en
Inventor
Toshifumi Takeuchi
敏文 竹内
Takao Arai
孝雄 荒井
Nobutaka Amada
信孝 尼田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP62063701A priority Critical patent/JPH0770166B2/en
Publication of JPS63231769A publication Critical patent/JPS63231769A/en
Publication of JPH0770166B2 publication Critical patent/JPH0770166B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Signal Processing For Digital Recording And Reproducing (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

PURPOSE:To enable data reproduction in fast-forward mode by switching the characteristics of a phase-locked loop circuit which extracts reproduced data and performs bit synchronization to characteristics with a wide capture range when a fast-forward reproducing means is put in operation. CONSTITUTION:Signals reproduced by heads 2A and 2B are applied to a playback amplifier 13 through a switch 12 at the time of reproduction and then applied to a bit synchronizing circuit 15 through a waveform shaping circuit 14. The output data and clock of the circuit 15 are supplied to a reproduction processing circuit 16. The circuit 15 inputs data by an FF 100 and a clock is generated by a PLL circuit which compares the data of the circuit 14 with the clock of a voltage-controlled oscillator 10. In normal play mode, a transistor (TR) 108 is turned on with outputs 21F and 21R of a microcomputer 21. In fast search mode, the TR 108 is turned off and the characteristics of the PLL circuit are switched to the characteristics with the wide capture range. Thus, the circuit is put in operation with characteristics with a good error rate in normal play mode and data reproduction can be performed even in fast search mode.

Description

【発明の詳細な説明】 [産業上の利用分野] 本発明は、ディジタル信号再生装置に係り、特に回転ヘ
ッド方式磁気記録再生装置で、早送り巻もどし再生に好
適なビット同期回路に関する。
DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a digital signal reproducing device, and more particularly to a bit synchronization circuit suitable for fast forwarding and rewinding reproduction in a rotary head type magnetic recording and reproducing device.

[従来の技術] 従来ビット同期回路は、通常再生において、誤り率が良
くなるように、フェーズロックドループ(P L L回
路)を設計しており、これに関しては、特開昭59−1
24013号公報で挙げられているような回路が使用さ
れている。
[Prior Art] A conventional bit synchronization circuit is designed as a phase-locked loop (PLL circuit) to improve the error rate during normal reproduction.
A circuit such as that listed in Publication No. 24013 is used.

[発明が解決しようとする問題点] 上記従来技術は、特に回転ヘッド方式磁気記録再生装置
において、高速サーチ時に、データ伝送レートが大幅に
変動することについては考慮されておらず、従来設計で
は、この時、データを再生できないという欠点があった
[Problems to be Solved by the Invention] The above-mentioned conventional technology does not take into account the fact that the data transmission rate changes significantly during high-speed search, especially in a rotating head type magnetic recording/reproducing device. At this time, there was a drawback that the data could not be reproduced.

本発明の目的は、高速サーチ時等、通常再生に比べ大幅
に伝送レートが変動する場合においても、通常再生時の
性能劣化なしに、データを再生することにある。
An object of the present invention is to reproduce data without deteriorating the performance during normal reproduction even when the transmission rate fluctuates significantly compared to normal reproduction, such as during high-speed search.

[問題点を解決するための手段] 上記目的は、PLL回路のループフィルタの定数を高周
波側に切り換える手段を設けることにより達成される。
[Means for Solving the Problems] The above object is achieved by providing means for switching the constant of the loop filter of the PLL circuit to the high frequency side.

[作用] 通常再生時はループフィルタは低周波側に選択すること
から、位相比較器等のパルス状の内乱に対するジッダ発
生を抑圧でき、データの誤りをすくなくでき、高速サー
チ時はループフィルタを高周波側に選択することから、
キャプチャレンジが大となり、伝送レートの大幅な変動
に対し追従しデータを取り込むことができる。
[Function] During normal playback, the loop filter is selected on the low frequency side, so it is possible to suppress the occurrence of jitter due to pulse-like internal disturbances such as in the phase comparator, and data errors can be minimized. During high-speed search, the loop filter is selected on the high frequency side. From choosing to the side,
The capture range is large, and data can be captured while following large fluctuations in the transmission rate.

[実施例] 以下、本発明の一実施例を第1図により説明する。第1
図は、本発明による回転ヘッド方式磁気記録再生装置の
構成図を示したものである。第1図の1はシリンダで、
アジマス角の相異なる2つのヘッド2A、2Bが取付け
られ、シリンダ1が回転することにより、テープ3上に
データを記録再生するもので、送り側リール4、巻取り
側り−ル5及び図示していないキャプスタンによりテー
プ3を送る構成となっている。ヘッド2A、2Bの信号
は、図示していないロータリートランスを介しスイッチ
12と結合されている。記録時の処理は、6L、6Rに
加わったアナログ信号は、オーディオ回路7で、エンフ
ァシスの有無等のアナログ的な処理を行ない、S/H8
L、8Rで一定の標本化周波数でサンプルされ、A/D
変換器9でディジタルデータに変換される。記録信号処
理回路10では、このPCMオーディオデータと、マイ
クロコンピュータ−21からの曲番、時間、曲のスター
ト信号等の制御信号を入力として、誤り訂正符号の付加
や、同期信号の付加といった一定フオーマットに従った
処理を行い記録アンプ11を介してスイッチ12に加わ
る。スイッチ12では、記録時、記録アンプ11側を選
択し、ヘッド2A、2Bに信号を加え、テープ3上に信
号を記録する。
[Example] Hereinafter, an example of the present invention will be described with reference to FIG. 1st
The figure shows a configuration diagram of a rotary head type magnetic recording/reproducing apparatus according to the present invention. 1 in Figure 1 is a cylinder,
Two heads 2A and 2B with different azimuth angles are attached, and by rotating the cylinder 1, data is recorded and reproduced on the tape 3. The tape 3 is fed by a capstan that does not have a capstan. Signals from heads 2A and 2B are coupled to switch 12 via a rotary transformer (not shown). During recording processing, the analog signals added to 6L and 6R are processed in an analog manner such as whether or not emphasis is applied in the audio circuit 7, and then sent to the S/H8.
Sampled at a constant sampling frequency at L, 8R, A/D
The data is converted into digital data by a converter 9. The recording signal processing circuit 10 inputs this PCM audio data and control signals such as the song number, time, and song start signal from the microcomputer 21, and processes it into a certain format such as adding an error correction code and a synchronization signal. The data is processed according to the following and is applied to the switch 12 via the recording amplifier 11. The switch 12 selects the recording amplifier 11 side during recording, applies signals to the heads 2A and 2B, and records the signals on the tape 3.

再生時には、ヘッド2A、2Bで再生された信号をスイ
ッチ12を介して再生アンプ13に加え、増幅し波形等
化処理をおこなう。その後、波形整形回路14で1.0
のパルス波形に整形し、ビット同期回路15に加わる。
During reproduction, the signals reproduced by the heads 2A and 2B are applied to the reproduction amplifier 13 via the switch 12, where they are amplified and subjected to waveform equalization processing. After that, the waveform shaping circuit 14 outputs 1.0
The pulse waveform is shaped into a pulse waveform and applied to the bit synchronization circuit 15.

ビット同期回路の出力データ及びクロックは、再生処理
回路16に加わリ、PCMオーディオデータ及び制御信
号のデータ誤りの検出、訂正処理を行いオーディオデー
タは、D/A変換器17へ、制御信号は、マイクロコン
ピュータ−21に加える。D/A変換器17の出力は、
S/H回路18L、18R及びオーディオ回路19を介
して2OL、2ORにアナログ信号を出力する。
The output data and clock of the bit synchronization circuit are applied to a reproduction processing circuit 16, which performs data error detection and correction processing on PCM audio data and control signals.The audio data is sent to a D/A converter 17, and the control signal is Add to microcomputer-21. The output of the D/A converter 17 is
Analog signals are output to 2OL and 2OR via the S/H circuits 18L and 18R and the audio circuit 19.

このような構成の中で、ビット同期回路15は、フリッ
プフロップ100でデータを取り込む動作を行なうもの
で、そのクロックは、波形整形回路14のデータと、電
圧制御発振器101のクロックを位相比較回路103、
ループフィルタを構成する抵抗104.106.107
、コンデンサ105及びアンプ102からなるPLL回
路で生成するものである。ここでループフィルタは、抵
抗106に直列にトランジスタ108を設け、そのトラ
ンジスタのベースをアンド回路110、抵抗109を介
してON10 F F制御するよう構成する。サーボ回
路22は、テープ送りやシリンダ回転数を制御する回路
で、21FがOで早送り、21RがOで巻戻しとなり、
双方とも1のときプレー状態である。また、21Sは、
プレー状態かストップ状態か制御する信号で、これらの
制御信号はマイクロコンピュータ−21により制御され
る。上記構成で、通常プレー状態では、21. F、2
1Rがともに1であることから、アンド回路110はル
ベルとなりトランジスタ108はONとなり、ループフ
ィルタを構成する。抵抗107に並列に抵抗106が挿
入される。よって抵抗104は変化しないことから高域
における利得が減り、キャプチャレンジは低下するが、
高域のノイズによる位相ずれが生じず、ビット同期回路
としては、誤り率の良い構成となる。また、早送り1巻
戻し時は、21F、21Rどちらか一方がOレベルとな
り、これにより、トランジスタ108は、○FFする。
In such a configuration, the bit synchronization circuit 15 performs the operation of taking in data with the flip-flop 100, and its clock is obtained by combining the data of the waveform shaping circuit 14 and the clock of the voltage controlled oscillator 101 with the phase comparison circuit 103. ,
Resistors 104, 106, 107 that constitute the loop filter
, is generated by a PLL circuit consisting of a capacitor 105 and an amplifier 102. Here, the loop filter is configured such that a transistor 108 is provided in series with the resistor 106, and the base of the transistor is ON10 FF controlled via an AND circuit 110 and a resistor 109. The servo circuit 22 is a circuit that controls tape feeding and cylinder rotation speed, and 21F is fast forward when O is set, 21R is rewind when O is set,
When both are 1, it is in the play state. Also, 21S is
These control signals are controlled by the microcomputer 21, which controls whether the player is in a play state or a stop state. With the above configuration, in the normal play state, 21. F, 2
Since both 1R are 1, the AND circuit 110 becomes a level, and the transistor 108 is turned on, forming a loop filter. A resistor 106 is inserted in parallel with resistor 107. Therefore, since the resistor 104 does not change, the gain in the high frequency range decreases and the capture range decreases.
No phase shift occurs due to high-frequency noise, and the bit synchronization circuit has a configuration with a good error rate. Further, during fast forwarding and rewinding, either 21F or 21R becomes O level, and as a result, the transistor 108 is turned FF.

よって抵抗104.107、容量105によって構成さ
れるラグリードフィルタとなる。これは、通常再生時に
比べ広域のゲインを上げたことになり、キャプチャレン
ジが広がる。高速サーチ時には、音楽信号を忠実再生す
るわけでなく、制御信号を確実に読みだすことが必要で
あり、キャプチャレンジを広くすることによって誤動作
なくデータをとりこめる。
Therefore, it becomes a lag-lead filter composed of resistors 104, 107 and capacitor 105. This means that the gain in a wide range is increased compared to normal playback, and the capture range is expanded. During a high-speed search, it is not necessary to reproduce the music signal faithfully, but to read the control signal reliably, and by widening the capture range, data can be captured without malfunction.

第2図は、本発明による高速サーチ時のヘッド軌跡を示
した図でテープ3上に記録されているトラック30B、
31A、・・・33Aに対してヘッド2Aは、図の様に
横断しながらトレースする。
FIG. 2 is a diagram showing head trajectories during high-speed search according to the present invention. Tracks 30B and 30B recorded on tape 3,
31A, . . . , 33A, the head 2A traces them while crossing them as shown in the figure.

30B、31B、・・・はアジマス角が異なることから
再生されず、30A、31A、32A・・・が、ヘッド
2Aで読みだすことができる。
30B, 31B, . . . are not reproduced because their azimuth angles are different, and 30A, 31A, 32A, . . . can be read by the head 2A.

第3図は、ヘッド2Aで読みだした信号のタイミングを
示す図で、シリンダ回転に対し30A・・・39Aのト
ラック信号を再生することができる。
FIG. 3 is a diagram showing the timing of signals read out by the head 2A, and track signals 30A to 39A can be reproduced with respect to cylinder rotation.

このなかに、記録されている制御信号を読みだし、希望
とする曲の頭だし信号が、検出されるか、再生信号処理
回路16及びマイクロコンピュータ21が、判断する。
The control signals recorded therein are read out, and the playback signal processing circuit 16 and microcomputer 21 determine whether the desired beginning signal of the song is detected.

第4図は、第1図のサーチ動作中のタイミング図で、マ
イクロコンピュータ21は、21S。
FIG. 4 is a timing chart during the search operation of FIG. 1, in which the microcomputer 21 is 21S.

21R,21Fを全てルベルとしプレー状態とする。こ
こで、曲のサーチを行う為、21FをOレベルにし、高
速早送り動作をおこなう。信号処理回路16は、制御信
号を読みだし、希望とする曲の頭だし信号が検出された
タイミング16Sにより、マイクロコンピュータ21は
、21Fを1にし、早送り動作をやめる。テープのオー
バーランを補正する為に21Rを0として、再度向の頭
だし信号が検出されるまで巻戻す。よって、サーチ動作
中は、アンド回路110をOとすることができサーチ動
作中はキャプチャレンジを拡大できる。
21R and 21F are all set as rubels and put into play mode. Here, in order to search for a song, 21F is set to O level and a high-speed fast forward operation is performed. The signal processing circuit 16 reads out the control signal, and at timing 16S when the desired song start signal is detected, the microcomputer 21 sets 21F to 1 and stops the fast forward operation. In order to correct the tape overrun, 21R is set to 0 and the tape is rewound until the beginning signal in the direction is detected again. Therefore, during the search operation, the AND circuit 110 can be set to O, and the capture range can be expanded during the search operation.

第5図は、第1図で、抵抗107の値に対するキャプチ
ャレンジの変化を示す図で、抵抗107を大きくするこ
とによりキャプチャレンジを広くすることができる。
FIG. 5 is a diagram showing changes in the capture range with respect to the value of the resistor 107 in FIG. 1. By increasing the resistor 107, the capture range can be widened.

第6図は、抵抗107の値に対するデータ誤り率の図で
、抵抗値107を小さくすれば、誤り率が下がりよくな
る。
FIG. 6 is a graph of the data error rate with respect to the value of the resistor 107, and the smaller the resistance value 107, the better the error rate will be.

[発明の効果コ 以上、本発明によれば、プレー中と、高速サーチ中で、
ループフィルタを切り換える回路を設けたことにより、
通常再生時は、誤り率の良い状態で再生でき、忠実に音
楽信号を再生でき、高速サーチ中は、キャプチャレンジ
を拡大し、データ伝送速度の変動に追従して、誤り無<
PLL回路がロックできることから制御信号を誤動作な
く検出することができる効果がある。
[Effects of the Invention] As described above, according to the present invention, during play and during high-speed search,
By installing a circuit to switch the loop filter,
During normal playback, the music signal can be reproduced with good error rate and faithfully, and during high-speed search, the capture range is expanded to follow fluctuations in data transmission speed, ensuring no errors.
Since the PLL circuit can be locked, the control signal can be detected without malfunction.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明による回転ヘッド方式磁気記録再生装置
の構成図、第2図は、高速サーチ中のヘッド軌跡を示す
図、第3図は高速サーチ中の再生信号を示す図、第4図
は、第1図のタイミング図、第5図は、第1図のキャプ
チャレンジを示す図、第6図は、第1図の誤り率を示す
図である。 15・・・ビット同期回路、 16・・・再生信号処理回路、 21・・・マイクロコンピュータ、 22・・・サーボ回路、
FIG. 1 is a block diagram of a rotary head type magnetic recording and reproducing apparatus according to the present invention, FIG. 2 is a diagram showing the head trajectory during high-speed search, FIG. 3 is a diagram showing the reproduced signal during high-speed search, and FIG. 4 is a diagram showing the head trajectory during high-speed search. is a timing diagram of FIG. 1, FIG. 5 is a diagram showing the capture range of FIG. 1, and FIG. 6 is a diagram of the error rate of FIG. 15...Bit synchronization circuit, 16...Reproduction signal processing circuit, 21...Microcomputer, 22...Servo circuit,

Claims (1)

【特許請求の範囲】[Claims] (1)ディジタル信号を記録媒体に記録、再生する手段
と、該記録媒体から通常再生時のデータに対し、間欠的
にデータを取り出し早送り再生する手段とを有するディ
ジタル信号再生装置において、再生されたデータを取り
出しビット同期を行なう第1の特性を有するフェーズロ
ックドループ回路と、上記第1の特性に比べ、キャプチ
ャレンジの広い第2の特性に切り換える手段と、上記早
送り再生する手段を動作させる時に、同期して、第2の
特性を有するフェーズロックドループ回路に切り換える
ことを特徴とするビット同期回路。
(1) A digital signal reproducing device that has means for recording and reproducing digital signals on a recording medium, and means for intermittently extracting data from the recording medium and performing fast-forward reproduction of the data during normal reproduction. When operating a phase-locked loop circuit having a first characteristic for extracting data and performing bit synchronization, a means for switching to a second characteristic having a wider capture range than the first characteristic, and a means for fast forward reproduction, A bit synchronization circuit characterized in that it synchronously switches to a phase-locked loop circuit having a second characteristic.
JP62063701A 1987-03-20 1987-03-20 Bit synchronization circuit Expired - Lifetime JPH0770166B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62063701A JPH0770166B2 (en) 1987-03-20 1987-03-20 Bit synchronization circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62063701A JPH0770166B2 (en) 1987-03-20 1987-03-20 Bit synchronization circuit

Publications (2)

Publication Number Publication Date
JPS63231769A true JPS63231769A (en) 1988-09-27
JPH0770166B2 JPH0770166B2 (en) 1995-07-31

Family

ID=13236941

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62063701A Expired - Lifetime JPH0770166B2 (en) 1987-03-20 1987-03-20 Bit synchronization circuit

Country Status (1)

Country Link
JP (1) JPH0770166B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5045818A (en) * 1989-09-19 1991-09-03 Sanyo Electric Co., Ltd. PLL frequency modulator having bias voltage applied to filter capacitor

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59198516A (en) * 1983-04-12 1984-11-10 Sony Corp Digital video tape recorder
JPS6298052U (en) * 1985-12-10 1987-06-22

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59198516A (en) * 1983-04-12 1984-11-10 Sony Corp Digital video tape recorder
JPS6298052U (en) * 1985-12-10 1987-06-22

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5045818A (en) * 1989-09-19 1991-09-03 Sanyo Electric Co., Ltd. PLL frequency modulator having bias voltage applied to filter capacitor

Also Published As

Publication number Publication date
JPH0770166B2 (en) 1995-07-31

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