JPH05207096A - Serial data communication equipment - Google Patents

Abstract

PURPOSE:To provide serial data communication equipment capable of easily performing software processing for the setting of transmission data and the control of a communication start timing, etc. CONSTITUTION:A communication data selection circuit 550 selects one register from communication data registers 561-563 corresponding to count data 5f in a communication counter 540 which counts the number of times of communication, and supplies transmission data 5g stored in a selected register to a shift register 530. When a timer 500 is started up, the shift register 530 fetches supplied transmission data 5f by a communication start signal 5b outputted after the lapse of constant time, and starts transmission. The count data 5f in the communication counter 540 is changed by a communication completion signal 5e, and the next transmission data 5g is supplied to the shift register 530, and continuous serial transmission can be automatically performed by starting up the timer 500 again.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a serial data communication device.

[0002]

2. Description of the Related Art Conventionally, a serial data communication device is capable of communication only with two signal lines for a clock signal and a data signal, and is widely used as a data communication means between one-chip microprocessors. A conventional serial data communication device includes a clock signal generation circuit that generates a clock signal for transferring serial data, a shift register that shifts communication data bit by bit, and a shift counter that counts the number of shifts of communication data. In the case of communication between configured one-chip microprocessors, software controls transmission data setting, reception data storage, communication start timing, and the like.

[0003]

However, in such a conventional configuration, it is necessary to set transmission data at the start of transmission and store the reception data at the end of reception each time data communication is performed. It was Further, in the case where data communication is performed at a constant cycle for reasons such as synchronization between devices that perform data communication, it is necessary to further accurately control the serial data communication device at constant time intervals.

Therefore, when the conventional serial data communication device is used to communicate between one-chip microprocessors, the transmission data is set, the reception data is stored, and the communication start timing is controlled. Software processing becomes complicated, and especially when the communication interval time is short, these processing must be performed frequently, and there is a problem that the execution of software processing that should be originally performed is delayed, which adversely affects normal processing. ..

An object of the present invention is to solve the above-mentioned conventional problems, and it is possible to easily set transmission data, store reception data, control communication start timing, etc., and facilitate software processing. Is to provide.

[0006]

According to a first aspect of the present invention, there is provided a serial data communication device which counts a clock signal and outputs a communication end signal when a predetermined count value is reached, and a clock according to a communication start signal. Communication clock generation means for starting signal output and stopping clock signal output by a communication end signal, a shift register for shifting data bit by bit in synchronization with the clock signal, and at least two for storing data The communication data storage means having the above storage area, the communication counter for counting the number of times of the communication end signal output from the control means, which is the number of times of communication, and the storage area of the communication data storage means according to the count data of the communication counter The storage area selecting means for selecting one of the storage areas and the storage area selecting means at the time of transmission. Has been fed to the shift register the data in the storage area selected Te, during reception, in which a communication data control means for supplying a selected storage area by the data storage area selection means in the shift register.

According to another aspect of the present invention, there is provided a serial data communication device which counts a clock signal and outputs a communication end signal when a predetermined count value is reached, and a communication start signal which starts output of the clock signal. A communication clock generation means for stopping output of a clock signal by a communication end signal, a shift register for shifting data bit by bit in synchronization with the clock signal, and at least two or more storage areas for storing data The communication data storage means, the first and second communication counters that count the number of times the communication means outputs the communication end signal from the control means, and the communication data storage means according to the count data of the first communication counter. One of the storage areas
A first storage area selecting means for selecting one storage area and a second storage area selecting means for selecting one storage area of the storage areas of the communication data storage means according to the count data of the second communication counter. Means for supplying the data in the storage area selected by the first storage area selecting means to the shift register at the time of transmission, and storing the data in the shift register at the time of reception selected by the second storage area selecting means. And communication data control means for supplying the area.

A serial data communication device according to a third aspect is the serial data communication device according to the second aspect.
The second storage area selection means is characterized by selecting one storage area different from the storage area selected by the first storage area selection means. The serial data communication device according to claim 4, wherein a timer that outputs a communication start signal when a set time has elapsed, and a control means that counts a clock signal and outputs a communication end signal when a predetermined count value is reached. And a communication clock generation means for starting the output of the clock signal by the communication start signal and stopping the output of the clock signal by the communication end signal, a shift register for shifting the data bit by bit in synchronization with the clock signal, and the data Communication data storage means having at least two or more storage areas for storing, a communication counter for counting the number of times of communication end signal output from the control means, which is the number of times of communication, and communication according to the count data of the communication counter One of the storage areas of the data storage means is selected, and the selected storage area is selected. Data is obtained and a storage area selecting means for supplying to the shift register of.

[0009]

According to the structure of the first aspect, the storage area selecting means automatically selects a plurality of storage areas of the communication data storing means in accordance with the count data of the communication counter for counting the number of times of communication. Then, at the time of transmission, after the data in the storage area is stored in the shift register by the communication data control means, the data is shifted from the shift register bit by bit in synchronization with the clock signal and output. Further, at the time of reception, after the input data is synchronized with the clock signal, it is shifted bit by bit and stored in the shift register, and then the data in the shift register is stored in the storage area by the communication data control means.

Therefore, it becomes unnecessary to set the data to be transmitted or store the received data for each communication as in the prior art, and it is easy to set the transmission data for a plurality of times and store the received data once. Can be done in
A series of serial data communication can be easily and continuously performed. According to the configuration of claim 2, at the time of transmission, the first storage area selection unit automatically stores a plurality of storages in the communication data storage unit according to the counter data of the first communication counter that counts the number of times of communication. Areas are sequentially selected, and at the time of reception, the second storage area selecting means automatically selects a plurality of storage areas included in the communication data storage area in accordance with the counter data of the second communication counter that counts the number of times of communication. To do. Then, at the time of transmission, after the data in the storage area is stored in the shift register by the communication data control means, the data is shifted from the shift register bit by bit in synchronization with the clock signal and output. Further, at the time of reception, after the input data is synchronized with the clock signal, it is shifted bit by bit and stored in the shift register, and then the data in the shift register is stored in the storage area by the communication data control means.

Therefore, it becomes unnecessary to set the data to be transmitted or store the received data for each communication as in the prior art, and it is easy to set the transmission data for a plurality of times and store the received data once. Can be done in
Serial data communication in which transmission and reception are repeated a plurality of times can be easily performed. According to the configuration described in claim 3, in the configuration described in claim 2, the second storage area selection means is the first storage area.
By selecting one storage area different from the storage area selected by the storage area selecting means, serial data communication in which transmission and reception are repeated a plurality of times can be easily performed, and software processing is facilitated.

According to the fourth aspect of the invention, serial data communication is automatically started by the communication start signal output from the timer, and the storage area selecting means responds to the count data of the communication counter for counting the number of times of communication. A plurality of storage areas included in the communication data storage means are sequentially selected, the data in the selected storage areas are stored in the shift register, and the serial data serving as the transmission data is synchronized with the clock signal from the shift register. Output by shifting bit by bit.

Therefore, unlike the prior art, it is not necessary to set the data to be transmitted for each communication, the transmission data for a plurality of times can be easily set at one time, and the data can be transmitted at regular intervals. It is possible to easily perform continuous serial data communication.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. 1 is a block diagram showing the configuration of a serial data communication device according to a first embodiment of the present invention. As shown in FIG. 1, the serial data communication device is
A control circuit 120 serving as control means and a communication counter 140
A clock signal output circuit 110 serving as a communication clock generating means, a shift register 130, a communication data storage circuit 160 serving as a communication data storing means having communication data registers 161-163 as storage areas, and a storage area selecting means. It comprises a communication data selection circuit 150 and a communication data control circuit 170 which serves as communication data control means.

The clock signal output circuit 110 has a terminal 10
When the communication start signal 1a is supplied from the control circuit 12,
0, the shift register 130 and the terminal 30 are supplied with the clock signal 1b for serial data transfer.
The control circuit 120 counts the clock signal 1b supplied from the clock signal output circuit 110, and when it reaches a predetermined count value, outputs the communication end signal 1d as the clock signal output circuit 110, the communication counter 140, and the communication data control circuit. It is supplied to 170.

The communication counter 140 is a counter for counting the number of times of communication, counts the communication end signal 1d supplied from the control circuit 120, and supplies the count data 1e at this time to the communication data selection circuit 150. .. The communication data storage circuit 160 has three data storage registers, communication data registers 161-163, as storage areas for communication data, and stores communication data.

The communication data selection circuit 150 responds to the count data 1e supplied from the communication counter 140.
Any one of the communication data registers 161 to 163
One to choose one. Communication data control circuit 170
Is a circuit for setting the transmission data and storing the reception data. The transmission / reception operation can be switched according to the transmission / reception switching signal 40a supplied from the terminal 40, and when the communication data is transmitted, the communication start supplied from the terminal 10 is started. Signal 1
The data stored in the communication data registers 161 to 163 selected by the communication data selection circuit 150 is stored in the shift register 130 by a, and when the communication data is received, the communication end signal 1d supplied from the control circuit 120 is used. The communication data register 1 in which the communication data selection circuit 150 selects the data in the shift register 130
It stores in 61-163.

The shift register 130 is a circuit for inputting and outputting the serial data 1c through the terminal 20, and the terminal 4
The transmission / reception operation is switched according to the transmission / reception switching signal 40a supplied from 0, and the set data is output from the terminal 20 while being shifted bit by bit in synchronization with the clock signal 1b at the time of transmission, and from the terminal 20 at the time of reception. The input data is stored while being shifted bit by bit in synchronization with the clock signal 1b.

The operation of the serial data communication apparatus of the first embodiment thus constructed will be described with reference to FIGS. 1 and 2. FIG. 2 is a timing chart of input / output signals of main parts of the serial data communication device shown in FIG. In FIG. 2, 1a indicates a communication start signal supplied from the terminal 10, and 1b indicates a clock signal output circuit 1.
10 shows a clock signal for serial data transfer, 1c shows serial data inputted to and outputted from the terminal 20 by the shift register 130, 1d shows a communication end signal outputted by the control circuit 120, and 1e shows a communication counter 14.
0 indicates the count data output.

First, the operation when transmitting communication data will be described. By the time t0, each of the communication data registers 161 to 163 has three types of 8-bit transmission data, that is, transmission data DATAa (each bit data a0
~ A7. ), Transmission data DATAb (consisting of data b0 to b7 of each bit) and transmission data DA
It is assumed that TAc is set. Also, the communication counter 1
It is assumed that 40 is set to “0” as an initial value.
Further, for the values “0”, “1” and “2” of the count data 1e output from the communication counter 140, the communication data selection circuit 150 causes the communication data register 16 to operate.
1, 162, 163 shall be selected. As a result, since the communication counter 140 is “0” at time t0, the communication data selection circuit 150 selects the communication data register 161. Also, the shift register 1
30 is each transmission data DAT as serial data 1c
It is assumed that Aa, DATAb, and DATAc are output from the terminal 20 in order from the least significant bit.

First, when the leading edge of the communication start signal 1a supplied from the terminal 10 arrives at time t0,
The communication data control circuit 170 includes a communication data selection circuit 15
The transmission data DATAa stored in the communication data register 161 selected by 0 is set in the shift register 130. As a result, the least significant bit data a0 of the transmission data DATAa is output from the terminal 20 as the serial data 1c.
Is output.

When the trailing edge of the communication start signal 1a arrives at time t1, the clock signal output circuit 110 supplies the clock signal 1b to the control circuit 120, the shift register 130 and the terminal 30. This allows
The control circuit 120 starts counting the clock signal 1b. Further, when the trailing edge of the clock signal 1b arrives at the time t2, the shift register 130 shifts the 8-bit transmission data DATAa by 1 bit in the lower bit direction, and from the terminal 20, shifts from the least significant bit of the transmission data DATAa to 2 bits. The bit data a1 is output.

Thereafter, in the same manner, the shift register 130
Each time the trailing edge of the clock signal 1b arrives, the data a2 of each bit of the transmission data DATAa is
.About.a7 are shifted bit by bit in the lower bit direction, and the data a2 to a7 of the third to eighth bits of the transmission data DATAa are sequentially output from the terminal 20. Then, when the shift register 130 outputs all the data a0 to a7 of each bit of the 8-bit transmission data DATAa, that is, at the time t.
When the control circuit 120 counts the eighth leading edge of the clock signal 1b in 3, the control circuit 120
At time t4, the count data (not shown) of the clock signal 1b is initialized, and the communication end signal 1e is supplied to the clock signal output circuit 110, the communication counter 140, and the communication data control circuit 170. Thus, when the leading edge of the communication end signal 1d arrives at the time t4, the clock signal output circuit 110 stops the output of the clock signal 1b thereafter. This clock signal 1
The shift register 130 stops the shift operation by stopping b.

After that, the communication counter 140 displays the time t5.
When the trailing edge of the communication end signal 1d arrives, the count data 1e is counted up from "0" to "1", and accordingly, the communication data selection circuit 150
Selects the communication data register 162 that stores the transmission data DATAb to be transmitted next. Thereafter, similarly, when the leading edge of the communication start signal 1a arrives at the communication data control circuit 170 at time t6, the transmission data DATAb (data of each bit b stored in the communication data register 162 selected by the communication data selection circuit 150 is selected.
It consists of 0 to b7. ) Is set in the shift register 130, and the next serial data transmission is performed. The transmission data output from the terminal 20 is transmitted from the least significant bit,
Since it is changed at the trailing edge of the clock signal 1b, in the shift register (not shown) on the receiving side, the terminal 3
If the received data is fetched from the most significant bit at the leading edge of the clock signal 1b output from 0 and the trailing edge of the clock signal 1b is shifted one bit at a time in the lower bit direction, correct communication can be performed.

Next, the operation at the time of receiving communication data will be described with reference to FIGS. The transmission operation and the reception operation are switched by the transmission / reception switching signal 40a supplied from the terminal 40. The value “0” of the count data 1e output from the communication counter 140,
Communication data selection circuit 150 for “1” and “2”
Are communication data registers 161, 162 and 163.
Shall be selected. Further, as the initial state, the communication counter 140 is “0”, which causes
The communication data selection circuit 150 includes a communication data register 16
It is assumed that 1 is selected. In addition, the shift register 130
It is assumed that the received data DATAa (consisting of data a0 to a7 of each bit), DATAb and DATAc are sequentially transmitted from the terminal 20 as serial data 1c from the least significant bit.

First, when the trailing edge of the communication start signal 1a arrives at time t1, the clock signal output circuit 110 supplies the clock signal 1b to the control circuit 120, the shift register 130 and the terminal 30. This allows
The control circuit 120 starts counting the clock signal 1b. When the leading edge of the clock signal 1b arrives at the time t1, the shift register 130 stores the least significant bit data a0 of the serial data 1c input from the terminal 20 in the most significant bit, and further at the time t2. When the trailing edge of the signal 1b arrives, the data a0 stored in the most significant bit at time t1 is shifted by 1 bit in the lower bit direction and stored.

Thereafter, in the same manner, the shift register 130
Each time the leading edge of the clock signal 1b arrives, the serial data 1c input from the terminal 20 is taken into the most significant bit, and every time the trailing edge arrives, the data taken up to that time is read one bit at a time in the lower bit direction. The data a2 to a7 of the third to eighth bits of the received data composed of the serial data 1c input from the terminal 20 are sequentially stored.

When the shift register 130 receives all the data a0 to a7 of each bit of the 8-bit received data, that is, when the control circuit 120 counts the eighth leading edge of the clock signal 1b at time t3, The control circuit 120 initializes the count data (not shown) of the clock signal 1b at time t4, and
The communication end signal 1d is supplied to the clock signal output circuit 110, the communication counter 140, and the communication data control circuit 170. Thus, when the leading edge of the communication end signal arrives at time t4, the clock signal output circuit 110 stops outputting the clock signal 1b thereafter. The stop of the clock signal 1b causes the shift register 13 to stop the shift operation. In addition, the communication data control circuit 17
When the leading edge of the communication end signal 1d arrives at time t4, the received data DATAa (each bit of data a0 to a7) stored in the shift register 130 is transferred to the communication data register 161 selected by the communication data selection circuit 150. Store.

After that, the communication counter 140 displays the time t5.
When the trailing edge of the communication end signal 1d arrives, the count data 1e is counted up from "0" to "1", and accordingly, the communication data selection circuit 150
Selects the communication data register 162. Thereafter, similarly, when the trailing edge of the communication start signal 1a arrives at time t7, the clock signal 1b is supplied from the clock signal output circuit 110 to the control circuit 120, the shift register 130 and the terminal 30, and the next serial data reception is performed. Done. Received data composed of serial data 1c input from the terminal 20 is taken in from the most significant bit of the shift register 130 in synchronization with the leading edge of the clock signal 1b, and is shifted in the lower bit direction at the trailing edge of the clock signal 1b. Therefore, on the transmitting side, the least significant bit of the transmission data is transmitted, the transmission data is shifted in the lower bit direction at the trailing edge of the clock signal 1b output from the terminal 30, and if the data is transmitted, the communication is correctly performed. be able to.

As described above, in the first embodiment, the communication counter 14 is set by the communication data selection circuit 150 during transmission.
The communication data registers 161 to 163 are sequentially selected according to the count data 1e of 0, and the communication data control circuit 17
Depending on 0, the selected communication data registers 161-1
The 8-bit transmission data stored in 63 is supplied to the shift register 130. Then, the shift register 130
The transmission data is shifted by 1 bit and output. When receiving, the communication data selection circuit 150 sequentially selects the communication data registers 161 to 163 according to the count data 1e of the communication counter 140, and the communication data control circuit 170 causes the selected communication data registers 161 to 163 to be selected. 8 input to the shift register 130
Supplies the received data in bits. That is, at the time of transmission, the transmission data stored in the plurality of communication data registers 161 to 163 are sequentially stored in the shift register 130, and the transmission data stored in the shift register 130 is output bit by bit. Thirteen
Received data stored in 0 is stored in a plurality of communication data registers 1
By sequentially storing in 61 to 163, it is possible to easily set the transmission data for a plurality of times and store the reception data at one time.

As a result, when it is applied to serial data communication between microprocessors, serial data setting, serial data storage, communication start timing, etc. are controlled even in the case of continuous communication with a short communication interval time. The software processing of is simplified. FIG. 3 is a block diagram showing the configuration of the serial data communication device according to the second embodiment of the present invention.

As shown in FIG. 3, the serial data communication device has a control circuit 320 as a control means, a clock signal output circuit 310 as a communication clock generation means, a shift register 330, and a transmission data register 361 as a storage area. -363 and reception data registers 364-36
6, a communication data storage circuit 360 serving as communication data storage means, a transmission counter 340 and a reception counter 341 serving as first and second communication counters that count the number of times of communication, and a transmission serving as first storage area selection means. It comprises a data selection circuit 350, a reception data selection circuit 351 which serves as second storage area selection means, and a communication data control circuit 370 which serves as communication data control means.

The clock signal output circuit 310 has a terminal 10
When the communication start signal 3b is supplied from the control circuit 32,
0, the shift register 330 and the terminal 30 are supplied with the clock signal 3c for serial data transfer.
The control circuit 320 is a circuit that outputs the communication end signal 3e, counts the clock signal 3c supplied from the clock signal output circuit 310, and outputs the communication end signal 3e when the count value reaches a predetermined count value. Circuit 31
0, the transmission counter 340, the reception counter 341, and the communication data control circuit 370.

The transmission counter 340 is a counter that counts the number of transmissions, and counts the communication end signal 3e supplied from the control circuit 320 when the transmission / reception switching signal 40a supplied from the terminal 40 indicates the transmission state. However, the count data 3f at this time is supplied to the transmission data selection circuit 350. Reception counter 341
Is a counter that counts the number of receptions, and the terminal 40
When the transmission / reception switching signal 40a supplied from the device indicates the reception state, the communication end signal 3e supplied from the control circuit 320 is counted, and the count data 3 at this time is counted.
g is supplied to the reception data selection circuit 351.

The communication data storage circuit 360 includes transmission data registers 361 to 363 and reception data register 36.
4 to 366, transmitted data 3h and received data 3
It stores i. Transmission data selection circuit 350
Selects any one of the transmission data registers 361 to 363 according to the count data 3f supplied from the transmission counter 340, and communicates the transmission data 3h stored in the selected transmission data register 361 to 363. It is supplied to the data control circuit 370.

The reception data selection circuit 351 responds to the count data 3g supplied from the reception counter 341.
Received data 3 supplied from the communication data control circuit 370
One receiving data register for storing i is selected from the receiving data registers 364 to 366. The communication data control circuit 370 is a circuit for setting the transmission data 3h and storing the reception data 3i, and the transmission / reception switching signal 40a supplied from the terminal 40.
Accordingly, the transmission start signal 3b supplied from the terminal 10 stores the transmission data 3h supplied from the transmission data selection circuit 350 in the shift register 330 at the time of transmission, and the communication end signal supplied from the control circuit 320 at the time of reception. The reception data 3i received by the shift register 330 by 3e is stored in the reception data registers 364 to 366 selected by the reception data selection circuit 351.

The shift register 330 is a circuit for inputting / outputting the serial data 3d. The transmission / reception operation can be switched according to the transmission / reception switching signal 40a supplied from the terminal 40, and the data set at the time of transmission can be the clock signal 3c. Terminal 2 while shifting bit by bit in synchronization with
The data is output from 0, and at the time of reception, the data input from the terminal 20 is stored while being shifted bit by bit in synchronization with the clock signal 3c.

The operation of the serial data communication apparatus of the second embodiment having such a configuration will be described with reference to FIGS. 3 and 4. FIG. 4 is a timing chart of input / output signals of main parts when the transmission operation and the reception operation are alternately performed in the serial data communication device shown in FIG. In FIG. 4, reference numeral 40a denotes a transmission / reception switching signal supplied from the terminal 40, 3b denotes a communication start signal supplied from the terminal 10, and 3c denotes a clock signal for serial data transfer output from the clock signal output circuit 310. Shows,
3d is serial data that the shift register 330 inputs / outputs from the terminal 20, 3e is a communication end signal output from the control circuit 320, 3f is count data of the transmission counter 340, and 3g is count of the reception counter 341. Data is shown, and 3h is a transmission data selection circuit 350.
3 shows the transmission data supplied to the communication data control circuit 370 from 3i and 3i shows the reception data stored in the reception data register 364.

By the time t0, 8-bit transmission data DATA is stored in each transmission data register 361-363.
a (consisting of data a0 to a7 of each bit), DAT
Ab and DATAc are set respectively. Further, it is assumed that the transmission counter 340 and the reception counter 341 are set to “0” as initial values. Further, the transmission data selection circuit 350 transmits the transmission data registers 361, 362 and 3 for the values “0”, “1” and “2” of the count data 3f of the transmission counter 340.
63 is selected, and the count data 3 of the reception counter 341
For the values of g “0”, “1” and “2”, the reception data selection circuit 351 receives the reception transmission data registers 364, 36.
Suppose 5 and 366 are selected. In addition, the shift register 330 sends the serial data 3 to the terminal 20 during transmission.
It is assumed that the least significant bit of the transmission data is sequentially output as d, and at the time of reception, the least significant bit of the reception data is sequentially transmitted to the terminal 20 as the serial data 3d.
In addition, the transmission / reception switching signal 40 supplied from the terminal 40
The potential of a is either a high potential level or a low potential level. When the potential is a high potential level, transmission is performed, and when it is a low potential level, reception is performed.

First, assume that the transmission / reception switching signal 40a supplied from the terminal 40 has a high potential level at time t0, and the serial data communication apparatus shown in FIG. When the leading edge of the communication start signal 3b arrives at the time t1, the communication data control circuit 370 causes the transmission data selection circuit 350 to select the 8-bit transmission data DATAa (data of each bit) stored in the transmission data register 361. a0 to a7) are set in the shift register 330. As a result, the least significant bit data a0 of the transmission data DATAa is output from the terminal 20.

Next, when the trailing edge of the communication start signal 3b arrives at the time t2, the clock signal output circuit 310 starts outputting the clock signal 3c, and the control circuit 3
The clock signal 3c is supplied to 20, the shift register 330 and the terminal 30. As a result, the control circuit 320 starts counting the clock signal 3c. Further, the shift register 330 receives the 8-bit transmission data DA when the trailing edge of the clock signal 3c arrives at time t3.
TAa is shifted by 1 bit in the lower bit direction, and the terminal 20
Outputs the second bit data a1 from the least significant bit of the transmission data DATAa.

Thereafter, the shift register 330 is similarly processed.
Shifts the transmission data DATAa by 1 bit in the lower bit direction each time the trailing edge of the clock signal 3c arrives, and sequentially outputs the 3rd to 8th bit data a2 to a7 of the transmission data DATAa from the terminal 20. Then, the shift register 330 sets the 8-bit transmission data D
When all the data a0 to a7 of each bit of ATAa are output, that is, at time t4, the control circuit 320 counts the eighth leading edge of the clock signal 3c, and at time t5, count data of the clock signal 3c (not shown). Communication end signal 3e
A clock signal output circuit 310, a transmission counter 340,
It is supplied to the reception counter 341 and the communication data control circuit 370. Thus, when the leading edge of the communication end signal 3e arrives at the time t5, the clock signal output circuit 310 stops the output of the clock signal 3c thereafter. The stop of the clock signal 3c causes the shift register 330 to stop the shift operation. Also, the transmission counter 3
40, when the trailing edge of the communication end signal 3e arrives at time t6, the count data 3f is counted up from “0” to “1”, and accordingly, the transmission data selection circuit 350 sets the transmission data register 362. The transmission data register 362 supplies the transmission data DATAb to the communication data control circuit 370 as the next transmission data.

Next, at time t7, the transmission / reception switching signal 40
When the potential of a changes from the high potential level to the low potential level, the communication mode is switched from the transmission mode to the reception mode, and the terminal 20 inputs the serial data 3d, that is, the reception data DATAa '(each bit data a0' to a.
It consists of 7 '. ) Can be entered. When the trailing edge of the communication start signal 3b arrives at time t8, the clock signal output circuit 310 starts the output of the clock signal 3c, and outputs the clock signal to the control circuit 320, the shift register 330, and the terminal 30, as in the case of transmission. 3c is supplied. As a result, the control circuit 320 causes the clock signal 3
Start counting c. Further, due to the leading edge of the clock signal 3c at the time t8, the shift register 330 stores the least significant bit data a0 ′ of the serial data 3d input from the terminal 20 in the most significant bit, and further at the time t9, the clock signal 3c. When the trailing edge of 3c arrives, the data a0 ′ stored in the most significant bit at time t8 is shifted by 1 bit in the lower bit direction and stored.

Thereafter, in the same manner, the shift register 330
Captures the serial data 3d input from the terminal 20 in the most significant bit each time the leading edge of the clock signal 3c arrives, and captures the serial data 3d previously captured each time the trailing edge of the clock signal 3c arrives. By shifting in the direction of lower bits by 1 bit, 3 of received data input from the terminal 20 can be obtained.
8th bit data a2 'to a7' are sequentially stored.

Then, the shift register 330 outputs 8-bit received data DATAa ', which is the data a of each bit.
When all 0'-a7 'are received, that is, when the control circuit 320 counts the eighth leading edge of the clock signal 3c at time t10, the control circuit 320 at time t11 outputs count data of the clock signal 3c (not shown). (3) is initialized and the communication end signal 3e is supplied to the clock signal output circuit 310, the reception counter 341 and the communication data control circuit 370. Accordingly, when the leading edge of the communication end signal 3e arrives at the time t11, the clock signal output circuit 310 stops the output of the clock signal 3c thereafter. The stop of the clock signal 3c causes the shift register 330 to stop the shift operation. Further, the communication data control circuit 370 determines that the time t1
When the leading edge of the communication end signal 3e arrives at 1, the received data DA stored in the shift register 330
TAa ′ (consisting of data a0 ′ to a7 ′ of each bit) is stored in the reception data register 364 selected by the reception data selection circuit 351.

After that, the reception counter 341 displays the time t1.
When the trailing edge of the communication end signal 3e arrives at 2, the count data 3g is counted up from "0" to "1".
Selects the reception data register 365 as a register for storing the next reception data. Thereafter, in the same manner, by the transmission / reception switching signal 40a supplied from the terminal 40,
When the transmission operation or the reception operation is designated and the communication start signal 3b is supplied from the terminal 10, the data stored in the transmission data registers 362 and 363 at the time of transmission is sequentially set in the shift register 330 at the start of transmission and then 1 bit is set. The shift register 330 receives the received data at the time of reception, and the received data is sequentially stored in the received data registers 365 and 366 at the end of the reception.

In FIG. 4, the reception is performed after the end of the transmission, but the same communication can be performed when the transmission is performed after the end of the reception or when the reception or the transmission is continuously performed. As described above, in the second embodiment, the transmission data register 36 for storing the transmission data and the reception data is stored.
1-363 and the reception data registers 364-366 are independent, the transmission data selection circuit 350 and the reception data selection circuit 351 for selecting them are independent, and the reception counter 34 for giving count data 3f, 3g to them is further provided.
0 and the transmission counter 341 are independent. And
The transmission data registers 361 to 363 and the reception data registers 364 to 3 are automatically generated according to the count data 3f and 3g of the transmission counter 340 and the reception counter 341.
66 in order, and when transmitting, the communication data control circuit 3
After the transmission data 3h in the transmission data registers 361 to 363 is stored in the shift register 330 by 70, the serial data 3d is shifted from the shift register 330 by 1 bit in synchronization with the clock signal 3c and output. Also, the serial data 3 that is input when receiving
After d is shifted bit by bit in synchronization with the clock signal 3c and stored in the shift register 330, the data in the shift register 330 is stored in the reception data registers 364 to 366 by the communication data control circuit 370.

Therefore, it becomes unnecessary to set the data to be transmitted or store the received data for each communication as in the conventional case, and it is easy to set the transmission data for a plurality of times and store the received data once. Can be done in
Serial data communication in which transmission and reception are repeated a plurality of times can be easily performed. As a result, when applied to serial data communication between microprocessors, even in the case of communication in which communication interval time is short and transmission and reception are alternately repeated, serial data setting, serial data storage, communication start timing, etc. are controlled. The software processing for this becomes simple.

FIG. 5 is a block diagram showing the configuration of a serial data communication device according to the third embodiment of the present invention. Figure 5
As shown in FIG.
00, a control circuit 520 serving as control means, a clock signal output circuit 510 serving as communication clock generation means, a shift register 530, and communication data storage serving as communication data storage means having communication data registers 561 to 563 as storage areas. The area 560 includes a communication counter 540 that counts the number of times of communication, and a communication data selection circuit 550 that serves as a storage area selection unit.

The timer 500 is a circuit for generating a timing signal for starting serial communication, and has a terminal 1
The operation is started by the timer start signal 5a supplied from 0 or the communication end signal 5e supplied from the control circuit 520, and when a preset time elapses, the communication start signal 5b is sent to the clock signal output circuit 510 and the shift register 530. To supply.

The clock signal output circuit 510 is a circuit for generating a clock signal 5c for serial data transfer. When the communication start signal 5b is supplied from the timer 500, the clock signal output circuit 510 outputs a clock to the control circuit 520, the shift register 530 and the terminal 30. It supplies the signal 5c. The control circuit 520 is a circuit that outputs the communication end signal 5e,
The clock signal 5c supplied from the clock signal output circuit 510 is counted, and when a predetermined count value is reached, the communication end signal 5e is supplied to the timer 500, the clock signal output circuit 510 and the communication counter 540.

The communication counter 540 is a counter for counting the number of times of communication, and supplies the count data 5f at this time to the communication data selection circuit 550. The communication data storage circuit 560 includes communication data registers 561-5.
63, and stores communication data.
The communication data selection circuit 550 selects any one of the communication data registers 561 to 563 according to the count data 5f supplied from the communication counter 540 and stores the selected one in the selected communication data registers 561 to 563. The transmission data 5g is supplied to the shift register 530.

The shift register 530 is a circuit for outputting the serial data 5e, stores the transmission data 5g supplied from the communication data selection circuit 550 in response to the communication start signal 5b supplied from the timer 500, and stores the stored transmission data 5g. The data 5g is output from the terminal 20 while being shifted bit by bit in synchronization with the clock signal 5c.

The operation of the serial data communication apparatus of the third embodiment having the above configuration will be described with reference to FIGS. 5 and 6. FIG. 6 is a timing chart of input / output signals of main parts of the serial data communication device shown in FIG. In FIG. 6, 5a indicates a timer start signal supplied from the terminal 10, and 5b indicates a timer 500.
5c indicates a communication start signal output from the clock signal output circuit 510, 5c indicates a serial data transfer clock signal output from the clock signal output circuit 510, 5d indicates serial data output from the shift register 530 from the terminal 20, and 5e indicates a control circuit. Reference numeral 5f indicates the communication end signal output from 520, 5f indicates the count data of the communication counter 540, and 5g indicates the transmission data supplied from the communication data selection circuit 550 to the shift register 530.

By the time t0, the timer 570 has preset the preset timing data DATAt corresponding to the communication interval time T, and each of the communication data registers 561 to 563 has 8 pieces.
Bit transmission data DATAa (each bit data a0
~ A7. ), DATAb (data b of each bit
It consists of 0 to a7. ) And DATAc are set in advance, and “0” is set as an initial value in the communication counter 540. Further, for the count data “0”, “1”, “2” of the communication counter 540, the communication data selection circuit 550 causes the communication data register 5 to
It is assumed that 61, 562 and 563 are selected. Further, the shift register 530 outputs serial data 5d which is transmission data from the terminal 20 in order from the least significant bit.

First, at time t0, the leading edge of the timer start signal 5a from the terminal 10 changes to the timer 570.
Is supplied to the timer 570, the timer 570 starts operating. When the communication interval time T has elapsed, the timer 570 supplies the communication start signal 5b to the shift register 530 and the clock signal output circuit 510, sets the timing data DATAt corresponding to the communication interval time T again, and stops the operation.

When the leading edge of the communication start signal 5b arrives at time t1, the shift register 530 sends the transmission data DAT supplied from the communication data selection circuit 550.
Store Aa. By setting the transmission data DATAa in the shift register 530, the terminal 20 outputs the data a0 of the least significant bit of the transmission data as the serial data 5d.

The clock signal output circuit 510 outputs the time t2.
When the trailing edge of the communication start signal 5b arrives at, the output of the clock signal 5c is started, and the control circuit 52
0, the clock signal 5c is supplied to the shift register 530 and the terminal 30. As a result, the control circuit 520 starts counting the clock signal 5c, and the terminal 30 outputs the clock signal 5c. In addition, the shift register 5
When the trailing edge of the clock signal 5c arrives at time t3, 30 shifts the transmission data DATAa by 1 bit in the lower bit direction, and the transmission data DAa is transmitted from the terminal 20.
The second bit data a1 of TAa is output.

Thereafter, similarly, the shift register 530
Shifts the transmission data DATAa by 1 bit in the lower bit direction each time the trailing edge of the clock signal 5c arrives, and outputs from the terminal 20 the serial data 5d as the third to eighth bits of the transmission data DATAa a2.
a7 is sequentially output. The shift register 530 uses the data a0 to a7 of each bit of the transmission data DATAa of 8 bits.
Is output, that is, at time t4, the control circuit 520
When the 8th leading edge of the clock signal 5c is counted by the control circuit 520, the control circuit 520 initializes the count data (not shown) of the clock signal 5c at the time t5 and outputs the communication end signal 5e to the clock signal output circuit 5c.
10, the communication counter 540 and the timer 570. Thus, when the leading edge of the communication end signal 5e arrives at time t5, the clock signal output circuit 510 stops the output of the clock signal 5c thereafter. The stop of the clock signal 5c causes the shift register 530 to stop the shift operation. Also, the communication counter 5
40, when the trailing edge of the communication end signal 5e arrives at time t6, the count data is changed from "0" to "1".
The communication data selection circuit 550 selects the communication data register 562 accordingly and supplies the transmission data DATAb as the next transmission data to the shift register 530. Further, the timer 570 is set to the time t6.
The operation is started by the trailing edge of the communication end signal 5e.

Similarly, when the communication interval time T elapses from time t6, the communication start signal 5b is supplied from the timer 570 to the communication data control circuit 570 and the clock signal output circuit 510 at time t7, and the communication start signal 5b is output. When the leading edge arrives at the communication data control circuit 170, the shift register 530 causes the communication data selection circuit 55 to move.
The transmission data DATAb supplied from 0 is stored, and the second serial data transmission is performed. The transmission data output from the terminal 20 is transmitted from the least significant bit and is changed at the trailing edge of the clock signal 5c. Therefore, in the shift register on the receiving side, at the leading edge of the clock signal 5c output from the terminal 30. If the received data is fetched from the most significant bit and is shifted by one bit in the lower bit direction at the trailing edge of the clock signal 5c, correct communication can be performed.

As described above, in the third embodiment, the timer 5
00 automatically outputs the communication start signal 5b to start serial data communication, and the communication data selection circuit 550 causes the communication data register 561-5 to correspond to the count data 5f of the communication counter 540 which counts the number of times of communication.
63 in order and select the selected communication data register 5
After storing the data in 61 to 563 in the shift register 530, the serial data 5d is shifted from the shift register 530 by 1 bit in synchronization with the clock signal 5c and output.

Therefore, unlike the conventional case, it is not necessary to set the data to be transmitted for each communication, and it is possible to easily set the transmission data for a plurality of times at one time, and to transmit at a constant interval. It is possible to easily perform continuous serial data communication. As a result, when applied to serial data communication between microprocessors, software processing for setting serial data and controlling communication start timing and the like becomes simple even in the case of communication in which transmission is continuous at regular intervals.

In the first, second and third embodiments of the present invention, the bit length of the transmitted / received data is 8 bits.
Although bits are used, serial communication of data of any bit length is similarly performed by increasing or decreasing the number of bits of the shift registers 130, 330 and 530 and the number of bits of the counters inside the control circuits 120, 320 and 520. You can Further, in each embodiment, the communication data storage circuits 160, 360 and 560 each have three communication data registers 161-1 as storage areas.
63, 364-366 and 561-563 using 3
Although the transmission or reception of various types of communication data has been described, the number of communication data registers serving as a storage area and the number of bits of the communication counter 540 are increased / decreased to achieve the same regardless of the number of communication data. be able to. Further, although the communication counters 140 and 540, the transmission counter 340 and the reception counter 341 are up counters, the same effect can be obtained even if they are down counters. Further, the serial data 1c, 3d and 5d input and output from the terminal 20 are changed at the trailing edge of the clock signals 1b, 3c and 5c, but the clock signals 1b, 3c and 5c are changed.
By starting output from the trailing edge,
The serial data 1c, 3d and 5d are clock signals 1
Even if the structure is changed by the leading edges of b, 3c and 5c, exactly the same effect can be obtained.

[0064]

According to the serial data communication device of the present invention, the storage area selection means automatically provides a plurality of storage areas in the communication data storage means according to the count data of the communication counter for counting the number of times of communication. In order. Then, at the time of transmission, after the data in the storage area is stored in the shift register by the communication data control means, the data is shifted from the shift register bit by bit in synchronization with the clock signal and output. Further, at the time of reception, after the input data is synchronized with the clock signal, it is shifted bit by bit and stored in the shift register, and then the data in the shift register is stored in the storage area by the communication data control means.

Therefore, it becomes unnecessary to set the data to be transmitted or store the received data for each communication as in the conventional case, and it is easy to continuously set the transmission data and store the received data for a plurality of times. The serial data communication can be easily performed at one time. As a result, even in the case of continuous communication in which the communication interval time is short, it is possible to easily set and store the serial data, control the communication start timing, etc., and simplify the software processing.

According to the serial data communication device of the second aspect, at the time of transmission, the first storage area selection means causes
According to the counter data of the first communication counter that counts the number of times of communication, a plurality of storage areas of the communication data storage means are automatically selected in order, and the number of times of communication is counted by the second storage area selection means when receiving. A plurality of storage areas included in the communication data storage area are automatically selected in order according to the counter data of the second communication counter. Then, at the time of transmission, after the data in the storage area is stored in the shift register by the communication data control means, the data is shifted from the shift register bit by bit in synchronization with the clock signal and output. Further, at the time of reception, after the input data is synchronized with the clock signal, it is shifted bit by bit and stored in the shift register, and then the data in the shift register is stored in the storage area by the communication data control means.

Therefore, it becomes unnecessary to set the data to be transmitted or store the received data for each communication as in the conventional case, and it is easy to set the transmission data for a plurality of times and store the received data once. Can be done in
Serial data communication in which transmission and reception are repeated a plurality of times can be easily performed. As a result, even in the case of the communication in which the communication interval time is short and the transmission and reception are alternately repeated, it is possible to easily control the setting and storage of the serial data and the communication start timing, and the software processing is simplified.

According to the serial data communication device of the third aspect, in the serial data communication device of the second aspect, the second storage area selecting means is different from the storage area selected by the first storage area selecting means. By selecting one storage area, serial data communication in which transmission and reception are repeated a plurality of times can be performed easily, and software processing becomes easy.

According to the serial data communication device of the fourth aspect, the serial data communication is automatically started by the communication start signal output from the timer, and the count data of the communication counter for counting the number of communication by the storage area selecting means. According to the above, a plurality of storage areas of the communication data storage means are sequentially selected, the data in the selected storage areas are stored in the shift register, and the serial data to be the transmission data is synchronized with the clock signal from the shift register. Then, the data is shifted bit by bit and output.

Therefore, it is not necessary to set the data to be transmitted for each communication as in the conventional case, and it is possible to easily set the transmission data for a plurality of times at one time and to transmit the data at a constant interval. It is possible to easily perform continuous serial data communication. As a result, even in the case of communication in which transmission is continuous at regular intervals, setting of serial data, control of communication start timing, etc. can be facilitated, and software processing becomes simple.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a serial data communication device according to a first embodiment of the present invention.

FIG. 2 is a timing chart of input / output signals of main parts of the serial data communication device shown in FIG.

FIG. 3 is a block diagram showing a configuration of a serial data communication device according to a second embodiment of the present invention.

4 is a timing chart of input / output signals of main parts when a transmission operation and a reception operation are alternately performed in the serial data communication device shown in FIG.

FIG. 5 is a block diagram showing a configuration of a serial data communication device according to a third embodiment of the present invention.

6 is a timing chart of input / output signals of main parts of the serial data communication device shown in FIG.

[Explanation of symbols]

110, 310, 510 Clock signal output circuit (clock signal generating means) 120, 320, 520 Control circuit (control means) 130, 330, 530 Shift register 140, 540 Communication counter 340 Transmission counter (first communication counter) 341 Reception Counter (second communication counter) 150, 550 Communication data selection circuit (storage area selection means) 350 Transmission data selection circuit (first storage area selection means) 351 Received data selection circuit (second storage area selection means) 161 To 163 communication data register (storage area) 361 to 363 transmission data register (storage area) 364 to 366 reception data register (storage area) 160, 360, 560 communication data storage circuit (communication data storage means) 170, 370 communication data control Circuit (communication data control means 500 timer 1b, 3c, 5c clock signal 1a, 3b, 5b communication start signal 1d, 3e, 5e communication end signal 1e, 3f, 3g, 5f count data

Claims (4)

[Claims] 1. A control unit that counts clock signals and outputs a communication end signal when a predetermined count value is reached; output of the clock signal by a communication start signal; and the clock by the communication end signal. Communication clock generation means for stopping signal output, shift register for shifting data bit by bit in synchronization with the clock signal, and communication data storage means having at least two or more storage areas for storing the data And a communication counter for counting the number of times the control means outputs the number of times of communication, which is the number of times of communication, and one of the storage areas of the communication data storage means according to the count data of the communication counter. Storage area selecting means for selecting an area, and the area selected by the storage area selecting means at the time of transmission A serial data communication device comprising: communication data control means for supplying data in a storage area to the shift register, and for receiving data in the shift register to the storage area selected by the storage area selecting means at the time of reception. 2. Control means for counting a clock signal and outputting a communication end signal when the count value reaches a predetermined count value; output of the clock signal by a communication start signal; and output of the clock signal by the communication end signal. Communication clock generation means for stopping signal output, shift register for shifting data bit by bit in synchronization with the clock signal, and communication data storage means having at least two or more storage areas for storing the data And first and second communication counters for counting the number of times of output of the communication end signal from the control means, which is the number of times of communication, and the communication data storage means according to the count data of the first communication counter. A first storage area selecting means for selecting one of the storage areas; and a second storage counter of the second communication counter. Second storage area selecting means for selecting one storage area out of the storage areas of the communication data storage means according to count data; and a storage area selected by the first storage area selecting means at the time of transmission. And a communication data control means for supplying the data in the shift register to the storage area selected by the second storage area selecting means at the time of reception. .. 3. The serial data communication device according to claim 2, wherein the second storage area selection means selects one storage area different from the storage area selected by the first storage area selection means. 4. A timer which outputs a communication start signal when a set time has elapsed, a control means which counts a clock signal and outputs a communication end signal when a predetermined count value is reached, said communication start signal Communication clock generation means for starting the output of the clock signal by the communication end signal and stopping the output of the clock signal for the communication end signal; a shift register for shifting data bit by bit in synchronization with the clock signal; Communication data storage means having at least two or more storage areas for storing, a communication counter for counting the number of times of the communication end signal output from the control means, which is the number of times of communication, and a count data of the communication counter. Select one of the storage areas of the communication data storage means, and select this And a storage area selecting means for supplying the data in the storage area to the shift register.