JPH05206287A - Multilayer interconnection structure - Google Patents

Abstract

PURPOSE:To prevent the generation of a disconnection in a multilayer interconnection structure and to contrive the improvement of the reliability of the structure by a method wherein a part only of the Ti layer which comes into contact with a via metal film in the Ti/Au layers of an upper layer wiring is removed and the Au layer of the Ti/Au layers is directly brought into contact to the via metal film. CONSTITUTION:A semiconductor element and the like are formed on an epitaxially grown layer 21 formed on a substrate 1 and moreover, an interlayer insulating film 3 is provided thereon. A via metal film 4 consisting of Au is buried in a via hole bored in is film 3 and an upper layer wiring 5 formed by laminating a Ti wiring layer 51 and an Au wiring layer 52 is provided on this metal film 4. The layer 51 is removed at a part only of this wiring 5 which comes into contact to the surface of the metal film 4, and the layer 52 directly comes into contact to the surface of the metal film 4 and is covered with a surface protective film 6. Accordingly, even if water content to intrude in a package corrodes the layer 51, the generation of a disconnection between the metal film 4 and a wiring of the layer 52 is prevented.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer wiring structure of a compound semiconductor device including a GaAs IC and the like, and more particularly to a multilayer wiring technology thereof.

[0002]

2. Description of the Related Art Conventionally, as a wiring layer of a compound semiconductor device such as an IC, the document "HEMT LS" by Kosugi and Tanaka et al.
Ti / A as described in "Multilayer Wiring Technology for I"
The u layer has been heavily used. In this laminated structure, the Ti layer enhances the adhesion with the underlying insulating film provided on the element, while the Au layer has excellent oxidation resistance and prevents the occurrence of electromigration and the like. ..

[0003]

When the above-mentioned IC is mounted in a plastic mold package, it is inexpensive but inferior in moisture resistance to conventional ceramic packages. It has been clarified as a result of the investigation so far that the moisture that has permeated through the plastic mold package has a problem that it selectively corrodes Ti of the wiring metal and causes the disconnection of the Ti metal wiring and the via metal. There is.

An object of the present invention is to solve the above problems and obtain a highly reliable compound semiconductor device.

[0005]

In the multilayer wiring structure according to the present invention, the multilayer wiring is provided through the via metal provided in the interlayer insulating film, and the upper wiring of the multilayer wiring is Ti / A.
The Ti layer of the Ti / Au layer is formed by removing only the portion of the Ti / Au layer in contact with the via metal.
The layer is in direct contact with the via metal.

[0006]

According to the present invention, the Ti layer is removed only in the portion in contact with the surface of the via metal in the upper wiring made of the Ti / Au layer, and Au having excellent oxidation resistance directly contacts the via metal. is doing. Therefore, even if the moisture that has penetrated into the package corrodes the Ti layer, it does not affect the wiring between the via metal and the Au layer, and the occurrence of disconnection can be prevented.

[0007]

EXAMPLES Examples of the present invention will be described below.

FIG. 1 is a perspective view showing the structure of a compound semiconductor device according to the present invention. As shown in the figure, a semiconductor element or the like is formed on the epitaxial growth layer 21 (or ion implantation layer) formed on the substrate 1, and an interlayer insulating film 3 is further provided thereon. In the figure, reference numeral 22 indicates the ohmic metal of the FET formed in the epitaxial growth layer 21 (or the ion implantation layer). A via metal 4 made of Au is embedded in a via hole formed in the interlayer insulating film 3, and a Ti wiring layer 51 and Au are formed on the via metal 4.
The upper layer wiring 5 formed by stacking the wiring layers 52 is provided. In the upper wiring 5, the Ti wiring layer 51 is removed only in the portion in contact with the surface of the via metal 4, and the Au wiring layer 52 is in direct contact with the surface of the via metal 4. Further, these surfaces are covered with a surface protective film 6.

According to the structure described above, when this semiconductor device is mounted in a plastic mold package, even if moisture invading from the outside corrodes the Ti wiring layer 51,
The Au wiring layer 52 having excellent oxidation resistance is the via metal 4
Since it is in contact with the upper part, it is possible to prevent disconnection between wirings.

Next, a manufacturing process of the above compound semiconductor device will be described. 2 and 3 are sectional views of the steps.

First, as shown in FIG. 2A, the interlayer insulating film 3 is laminated on the epitaxial growth layer 21 provided with the semiconductor element 22 and the like. A via hole is formed in the interlayer insulating film 3 by using a known method, and a metal is embedded to form a via metal 4. A Ti film 510 is formed on the entire surface by sputtering (shown in FIG. 2B). The formation conditions at this time are RF (high frequency) power of 400 W, Ar gas flow rate of 60 _SCCM , pressure of 1 Torr, and the formed Ti film 51.
The thickness of 0 is 200 angstrom. Next, after forming a resist pattern 71 having an opening on the via metal 4 (shown in FIG. 2C), RIE (reactive ion etching) is performed to remove an unnecessary portion of the Ti film 510 (FIG. 2). (D) Illustration). The formation conditions at this time are RF power of 150 W, CF ₄ gas flow rate of 60 _SCCM , pressure of 0.5 T.
orr. Next, the resist pattern 71 is removed,
A Ti wiring layer 51 is formed ((e) in the figure). After that, the polarities of the substrate side and the target side in normal sputtering are reversed, so-called reverse sputtering is performed for 1 minute, and unnecessary particles such as dust and oxides are removed from the surface including the formed Ti wiring layer 51. Scatter to make a clean surface (not shown).

Further, an Au film 520 is formed by sputtering on the entire surface of the clean substrate on which the Ti wiring layer 51 is formed.
The formation conditions at this time are RF power of 450 W, Ar gas flow rate of 60 _SCCM , pressure of 1 Torr, and the formed Au film 520 has a thickness of 5000 to 10000 angstroms (see FIG. 3A). Next, a resist pattern 72 is provided on the Au film 520 (shown in FIG. 3B), and unnecessary Au film 520 is removed by ion milling to form an Au wiring layer 52 (shown in FIG. 3C). ). The conditions at this time were as follows: discharge voltage 600 eV, Ar ion beam 100 m
A, the milling angle is 15 °. After that, the surface protective film 6 is deposited on the entire surface to obtain a compound semiconductor device. These forming conditions can be changed according to the purpose of the semiconductor device provided with the multilayer wiring structure.

A pressure cooker test was conducted in order to examine the moisture resistance of the multilayer wiring structure obtained by the above steps. The test conditions were a temperature of 130 ° C and a humidity of 8
It was stored in 5% for 1000 hours, and the number of failures after that was examined. As a result, the number of failures due to the disconnection of the compound semiconductor device according to the present invention is 0 out of 100, which is significantly larger than the result that the number of failures of the conventional device under the same condition is 98 out of 100. I was able to make an improvement.

[0014]

As described above, according to the compound semiconductor device of the present invention, even if the moisture that has penetrated into the package corrodes Ti which is the wiring material, the via metal and the Ti are used.
This has no effect on the wiring with Au, which is the above-mentioned metal wiring material, so that the occurrence of disconnection can be prevented. Therefore, it is possible to provide a GaAs IC excellent in moisture resistance with a very small number of corrosion failures.

[Brief description of drawings]

FIG. 1 is a diagram showing a structure of a compound semiconductor device according to the present invention.

FIG. 2 is a process sectional view of a compound semiconductor device according to the present invention.

FIG. 3 is a process sectional view of a compound semiconductor device according to the present invention.

[Explanation of symbols]

1 ... Substrate, 21 ... Epitaxial growth layer, 22 ... FET
Ohmic metal, 3 ... Interlayer insulating film, 4 ... Via metal, 51 ... Ti wiring layer, 52 ... Au wiring layer, 6 ... Surface protection film.

Claims (1)

[Claims] 1. A multilayer wiring is provided through a via metal provided in an interlayer insulating film, an upper wiring of the multilayer wiring is made of a Ti / Au layer, and a Ti layer of the Ti / Au layer is made of the via. A multilayer wiring structure characterized in that only a portion in contact with a metal is removed, and the Au layer of the Ti / Au layer is in direct contact with the via metal.