JPH05206255A - Jig for semiconductor - Google Patents
Jig for semiconductorInfo
- Publication number
- JPH05206255A JPH05206255A JP1173292A JP1173292A JPH05206255A JP H05206255 A JPH05206255 A JP H05206255A JP 1173292 A JP1173292 A JP 1173292A JP 1173292 A JP1173292 A JP 1173292A JP H05206255 A JPH05206255 A JP H05206255A
- Authority
- JP
- Japan
- Prior art keywords
- jig
- semiconductor
- charged
- negatively
- positively
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Packaging Of Annular Or Rod-Shaped Articles, Wearing Apparel, Cassettes, Or The Like (AREA)
- Packaging Frangible Articles (AREA)
- Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は半導体装置の製造用治具
に係り、特に前工程に使用され異物付着を防止を必要と
するものに適用して有効な技術に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a jig for manufacturing a semiconductor device, and more particularly to a technique which is effective when applied to a jig which is used in a pre-process and requires prevention of foreign matter adhesion.
【0002】[0002]
【従来の技術】半導体装置の製造においては、微細加工
上異物付着は極力防止しなくてはならない。特に前工程
と呼ばれる半導体ウエハの処理工程においては重要な課
題である。このような異物は一般的に治具が帯電し異物
を吸着するため、異物吸着防止の方法として治具に帯電
防止剤をコーティングし帯電を防止するのが一般的であ
る。2. Description of the Related Art In the manufacture of semiconductor devices, it is necessary to prevent foreign substances from adhering as much as possible in view of fine processing. In particular, it is an important issue in the semiconductor wafer processing step called the pre-step. Since such a foreign substance is generally charged by the jig and adsorbs the foreign substance, as a method of preventing the foreign substance adsorption, it is general to coat the jig with an antistatic agent to prevent the electrostatic charge.
【0003】このような帯電防止剤の記載はないが半導
体製造用治具の一例を示したものとしては特開昭63−
213358号がある。There is no description of such an antistatic agent, but as an example of a jig for manufacturing a semiconductor, JP-A-63-
There is 213358.
【0004】[0004]
【発明が解決しようとする課題】しかし、上記した手段
では帯電防止剤を薄くコーティングしただけのものであ
るため、半導体ウエハを収納し洗浄工程等を複数回行う
と半導体ウエハと摩耗しコーティング材が剥がれ帯電防
止効果がなくなってしまうという問題があった。本願発
明の目的は上記したような問題を解決し帯電防止効果の
なくならない半導体用治具を提供することにある。However, since the above-mentioned means is only thinly coated with the antistatic agent, if the semiconductor wafer is housed and the cleaning process is performed a plurality of times, the semiconductor wafer is worn and the coating material is not formed. There was a problem that the peeling-off antistatic effect was lost. It is an object of the present invention to provide a semiconductor jig that solves the above problems and does not lose the antistatic effect.
【0005】[0005]
【課題を解決するための手段】本願において開示される
発明のうち代表的なものを記載すれば下記のとおりであ
る。The typical ones of the inventions disclosed in the present application will be described as follows.
【0006】すなわち半導体用治具において、前記治具
は正に帯電する素材と、負に帯電する素材を張りあわせ
等により組合わせ形成されてなることを特徴とする半導
体用治具である。That is, in the semiconductor jig, the jig is formed by combining a material that is positively charged and a material that is negatively charged by bonding or the like.
【0007】[0007]
【作用】上記した手段によれば、正に帯電する素材と負
に帯電する素材とがそれぞれの帯電すべき電荷でお互い
の持つ電荷を打ち消しあうので、どちらの電荷にも帯電
しない半導体用治具が可能となる。According to the above-mentioned means, the positively charged material and the negatively charged material cancel each other's electric charges by the respective electric charges to be charged, so that the semiconductor jig is not charged with either electric charge. Is possible.
【0008】[0008]
【実施例】図1は本願発明の半導体装置用治具の構成を
示した一部断面側面図、図2はその断面図である。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a partial sectional side view showing the structure of a semiconductor device jig of the present invention, and FIG. 2 is a sectional view thereof.
【0009】以下、図1および図2によって本願発明の
実施例を説明する。An embodiment of the present invention will be described below with reference to FIGS. 1 and 2.
【0010】本実施例において対象となる工程は半導体
ウエハの前工程でエッチング後の洗浄を行う工程であ
る。In the present embodiment, the target process is the process of cleaning the semiconductor wafer after etching in the pre-process.
【0011】図1に示したように本実施例の半導体用治
具1は半導体ウエハ2が複数を収納されている。半導体
治具1は半導体ウエハ2収納のために上方が広く下方が
狭く形成されている。また半導体ウエハ2の収納用の溝
3がそれぞれ形成されている。As shown in FIG. 1, the semiconductor jig 1 of this embodiment accommodates a plurality of semiconductor wafers 2. The semiconductor jig 1 is formed so that the upper side is wide and the lower side is narrow to accommodate the semiconductor wafer 2. Further, grooves 3 for accommodating the semiconductor wafer 2 are formed respectively.
【0012】この中で半導体ウエハ2は並立されてそれ
ぞれの平面部が向き合うようになっている。図2に示し
たように前記半導体治具は帯電防止のために正に帯電す
る素材であるポリテトラフルオロエチレンから形成され
た部分1aおよび負の電荷に帯電するレーヨンで形成さ
れた部分1bとで半導体ウエハ2を挾んで半導体治具1
の両側面部を組合され形成されており、底面4の中央部
において導電性の接着剤にて接続されている。このよう
に半導体ウエハ2が収納された状態で半導体ウエハ2は
純水で洗浄等の処理工程が行なわれる。Among them, the semiconductor wafers 2 are arranged side by side so that their plane portions face each other. As shown in FIG. 2, the semiconductor jig has a portion 1a formed of polytetrafluoroethylene, which is a material that is positively charged to prevent electrostatic charge, and a portion 1b formed of rayon, which is negatively charged. A semiconductor jig 1 with a semiconductor wafer 2 in between
Are formed by combining both side surface portions of the above, and are connected by a conductive adhesive at the central portion of the bottom surface 4. With the semiconductor wafer 2 stored in this manner, the semiconductor wafer 2 is subjected to processing steps such as cleaning with pure water.
【0013】本実施例によれば、両側面をそれぞれ正の
電荷を帯電する素材および負の電荷を帯電する素材で治
具の底面で接続し形成することができるので半導体治具
の製造が簡単に行うことが可能となる。According to the present embodiment, both side surfaces can be connected and formed on the bottom surface of the jig with a material that charges a positive electric charge and a material that charges a negative electric charge, so that a semiconductor jig can be easily manufactured. It becomes possible to do it.
【0014】以上本願発明を本願の背景となった技術に
基ずいて説明したが本願実施例は上記実施例に限定され
るものではなく、その技術を逸脱しない範囲で種々変更
可能であることはいうまでもない。すなわち正の電荷を
帯電する素材としてポリテトラフルオロエチレンンを用
い、負の電荷を帯電するものとしてレーヨンを用いたが
それぞれの電荷に帯電するものであればどのような素材
を使用しても構わない。Although the present invention has been described above based on the technology which is the background of the present application, the embodiments of the present application are not limited to the above embodiments, and various modifications can be made without departing from the technology. Needless to say. That is, polytetrafluoroethylene was used as a material for charging a positive charge and rayon was used as a material for charging a negative charge, but any material may be used as long as it is charged to each charge. Absent.
【0015】例えばポリアミドのようなものでもよい。
また素材の組合せに関しては本実施例では底面を導電性
接着剤を用いたが別の方法にて組み合わせても構わな
い。また本実施例においては半導体用治具としウエハを
対象としたものを示したが、帯電防止用治具として完成
した半導体装置を保持する治具や作業台等にも使用する
ことができる。For example, a material such as polyamide may be used.
Further, regarding the combination of the materials, the conductive adhesive is used for the bottom surface in this embodiment, but the combination may be made by another method. Further, in the present embodiment, the semiconductor jig is intended for the wafer, but it can also be used as a jig for holding the completed semiconductor device, a workbench, etc. as an antistatic jig.
【0016】[0016]
【発明の効果】本願において開示される発明のうち代表
的なものによって得られる効果を記載すれば下記のとお
りである。The effects obtained by the representative ones of the inventions disclosed in the present application will be described below.
【0017】すなわち正の電荷を帯電する素材と負の電
荷を帯電する素材とを組み合わせることによりお互いに
帯電する電荷を打ち消すことになるので電荷を帯電しな
いため、異物の付着の防止できる半導体治具を提供する
ことが可能となる。また完成した半導体装置においては
静電破壊の防止できる半導体治具が可能となる。That is, by combining a material that is charged with a positive charge and a material that is charged with a negative charge, the charges that are charged with each other will be canceled out. Can be provided. Further, in the completed semiconductor device, a semiconductor jig capable of preventing electrostatic breakdown can be provided.
【図1】 図1は本願発明の半導体装置用治具の構成を
示した一部断面側面図である。FIG. 1 is a partial cross-sectional side view showing a configuration of a semiconductor device jig of the present invention.
【図2】 図2は図1に示した半導体用治具の断面図で
ある。FIG. 2 is a cross-sectional view of the semiconductor jig shown in FIG.
1..半導体用治具、1a..ポリテトラフルオロエチ
レン部、1b..レーヨン部、2..半導体ウエハ、
3..溝、4..底面1. . Semiconductor jig, 1a. . Polytetrafluoroethylene part, 1b. . Rayon part, 2. . Semiconductor wafer,
3. . Groove, 4. . Bottom
Claims (1)
帯電する素材と、負に帯電する素材が組合されてなるこ
とを特徴とする半導体用治具。1. A jig for semiconductors, wherein the jig is a combination of a material that is positively charged and a material that is negatively charged.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1173292A JPH05206255A (en) | 1992-01-27 | 1992-01-27 | Jig for semiconductor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1173292A JPH05206255A (en) | 1992-01-27 | 1992-01-27 | Jig for semiconductor |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH05206255A true JPH05206255A (en) | 1993-08-13 |
Family
ID=11786208
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1173292A Pending JPH05206255A (en) | 1992-01-27 | 1992-01-27 | Jig for semiconductor |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH05206255A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0696649A1 (en) | 1994-08-12 | 1996-02-14 | Sumitomo Electric Industries, Ltd. | Process for the production of heat- and corrosion-resistant porous metal body |
-
1992
- 1992-01-27 JP JP1173292A patent/JPH05206255A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0696649A1 (en) | 1994-08-12 | 1996-02-14 | Sumitomo Electric Industries, Ltd. | Process for the production of heat- and corrosion-resistant porous metal body |
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