JPH05206174A - Field effect semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To solve problems such as a leak current of a gate electrode, variation of a threshold value and corrosion of a semiconductor substrate due to entering of chemicals by improving coverage of a gate electrode. CONSTITUTION:A layer 10 formed of a compound of tungsten and silicon is formed in a lowermost layer of a gate electrode by sputtering, and a tungsten layer 11 is formed thereon by thermal CVD method; thereby, the layer 10 is formed with good coverage and the tungsten layer 11 formed thereon is formed to blanket shape with good coverage.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field effect semiconductor device and a method of manufacturing the same.

[0002]

2. Description of the Related Art In recent years, semiconductor devices or semiconductor integrated circuit devices have been required to have higher speed and higher density. In order to meet these demands, formation of short electrode elements necessary for manufacturing a semiconductor device having a fine structure is required. Technology is being eagerly developed. At present, in order to miniaturize the element, development of high-resolution resist, advancement of lithography technology such as phase shift technology, improvement of light source such as EB and SOR, and development of peripheral technology such as development of high precision stepper have been made. However, ultrafine pattern forming technology is required to obtain higher characteristics.

Prior to the description of the present invention, an example of a conventionally known method of manufacturing a FET having a short electrode structure will be described.

4A to 4D and 5E to 5H.
FIG. 7 is an explanatory diagram of a manufacturing process of a conventional field effect semiconductor device. In this figure, 31 is a semiconductor substrate, 32 is an insulating film, 33 is a photoresist film, 34 is a tungsten silicide (WSi) layer, 35 is a Ti layer, and 36 is gold (Au).
A layer, 37 is a platinum (Pt) layer, and 38 is a photoresist film.

A conventional HEM according to the manufacturing process explanatory diagram
A method of manufacturing a semiconductor device having a T structure will be described.

First step (see FIG. 4A) [Insulating film deposition] n-GaAs layer, n-AlGaA on the surface
An insulating film 32 such as SiON having a thickness of 3400Å is formed on the semiconductor substrate 31 on which the s layer and the i-GaAs layer are formed.

Second step (see FIG. 4B) [Formation of gate resist pattern] A photoresist film 33 is formed on the insulating film 32 formed in the previous step, and an opening is formed in the gate region.

Third Step (See FIG. 4C) [Etching] The insulating film 32 is selectively etched using the photoresist film 33 having the opening formed in the previous step as a mask.

Fourth step (see FIG. 4D) [Resist removal] The photoresist film 33 used as a mask in the previous step is removed.

Fifth step (see FIG. 5E) [Sputtering of WSi] A tungsten silicide (WSi) layer 34 having a thickness of 1000 Å is sputtered on the surface of the insulating film 32 and the semiconductor substrate 31 exposed in the opening. Form by the method.

Sixth step (see FIG. 5 (F)) [Sputtering of Ti, Au, Pt] WS formed in the previous step
On the i layer 34, a titanium (Ti) layer 3 having a thickness of 100 Å
A gold (Au) layer 36 having a thickness of 5,300 Å and a platinum (Pt) layer 37 having a thickness of 80 Å are formed by a sputtering method.

Seventh step (see FIG. 5G) [Pattern upper part pattern formation] Pt layer 3 formed in the previous step
A photoresist film 38 is formed on the area above the gate electrode 7 where the gate electrode is to be formed.

Eighth step (see FIG. 5H) [Formation of gate electrode] With the photoresist film 38 formed in the previous step as a mask, the Pt layer 37, the Au layer 36, and the Ti layer are formed.
The layer 35 and the WSi layer 34 are sequentially removed by etching to form a gate electrode. After that, the photoresist film 38 is removed, and the source region and the drain region and their electrodes are formed by a conventionally known process to form the HEMT.
A semiconductor device having a structure is configured.

As described above, conventional HEMs, for example,
In the method of manufacturing a T-structure semiconductor device, the lowermost layer of the gate electrode uses a compound of tungsten and silicon, which are refractory metals, and a Ti layer, an Au layer, and
The Pt layer was formed by the sputtering method. The metal coating property by the above-mentioned sputtering method is superior to that when it is formed by the vapor deposition method.

[0015]

However, in the structure having a fine cross-sectional shape as shown in the figure, the excellent coverage by the sputtering method is not sufficient, and the thermal stress near the interface between the insulating film and the substrate causes the problem. There are problems that cracks may occur in the insulating film, gate leaks may occur due to the cracks, threshold values may fluctuate, and chemicals may enter during the manufacturing process to corrode the semiconductor substrate.

According to the present invention, the lowest layer of a compound of tungsten and silicon (WSi) and Ti formed thereon are formed.
The W layer is interposed between the stacked layers of the Au layer, the Au layer, and the Pt layer, and the thermal CVD method having a high covering property is adopted as a method for forming the W layer. The purpose is to solve problems such as fluctuations and substrate corrosion due to chemical infiltration.

[0017]

In a field effect semiconductor device according to the present invention, a gate electrode including a structure in which a layer of a compound of tungsten and silicon is formed in the lowermost layer and a tungsten layer is formed thereon Adopted the configuration that has.

Further, in the method of manufacturing a field effect semiconductor device according to the present invention, a step of forming a compound layer of tungsten and silicon on the lowermost layer of the gate electrode by a sputtering method, and a step of forming a compound layer of tungsten and silicon on the compound layer. A process of forming tungsten by the thermal CVD method was adopted.

[0019]

As in the present invention, the W layer as the gate electrode is heated by the heat C
When deposited by the VD method, the coating property is extremely good,
When the WSi layer is formed as a base of the W layer, it becomes possible to deposit the WSi layer on the surfaces of the W layer semiconductor substrate and the insulating film in a blanket-like manner with good coverage due to the activity of the WSi layer. Further, in this case, the thermal CVD step of the W layer can automatically recover the damage to the semiconductor substrate which has occurred when the WSi layer was previously formed as the base by the sputtering method.

[0020]

EXAMPLES Examples of the present invention will be described below. (First Embodiment) FIG. 1 is a structural explanatory view of a field effect semiconductor device according to the first embodiment of the present invention. In this figure, 1
Is a semi-insulating GaAs substrate, 2 is a buffer layer, 3 is i-G
aAs active layer, 4 is a two-dimensional electron gas channel, 5 is n-
AlGaAs electron supply layer, 6 ohmic region, 7 insulating film, 8 source electrode, 9 drain region, 10 tungsten silicide (WSi) layer, 11 tungsten (W) layer, 12 titanium (Ti) layer, 13 is gold (Au)
The layer, 14 is a platinum (Pt) layer.

This embodiment shows an example of a semiconductor device having a HEMT structure, in which a buffer layer 2, an i-GaAs active layer 3, and an n-AlGaAs are formed on a semi-insulating GaAs substrate 1.
An electron supply layer 5 is grown, and S having a thickness of 3400Å is formed on the electron supply layer 5.
An insulating film 7 such as iON is formed, and a source electrode 8 and a drain region 9 are formed together with the ohmic region 6 through openings formed at both ends of the insulating film 7.

In addition, tungsten silicide (W which becomes a gate electrode is formed through an opening formed in the central portion of the insulating film 7).
Si) layer 10, tungsten (W) layer 11, titanium (T
The i) layer 12, the gold (Au) layer 13, and the platinum (Pt) layer 14 are formed. Then, 2 in the i-GaAs active layer 3
A three-dimensional electron gas channel 4 is formed.

In the semiconductor device having the HEMT structure of this embodiment, WSi having an excellent covering property is used as the base of the W layer 11.
Since the layer 10 is formed, the coverage of the W layer 11 formed on the layer 10 is also improved, and the W layer 11 is deposited in a blanket form, which causes a leak current of the gate electrode and a threshold current. It is possible to eliminate problems such as corrosion of the substrate due to the influx of chemicals from fluctuations in the gate electrode or cracks in the gate electrode.

The Pt layer 14 which is the uppermost layer of the gate electrode
When integrating the semiconductor device having the HEMT structure,
It is formed to function as an etching stop layer when an insulating film is formed on the gate electrode and a contact hole reaching the gate electrode is formed in the insulating film by etching. Pt is the uppermost layer of this gate electrode
When the Au layer 13 is exposed without forming the layer 14, the Au layer 13 is not formed when the contact hole is formed by etching.
Reacts with the CF-based etching gas to increase the contact resistance.

(Second Embodiment) FIGS. 2A to 2D and FIG.
(E)-(H) is a manufacturing process explanatory drawing of the field effect type semiconductor device of the 2nd Example of this invention. In this figure, 2
1 is a semiconductor substrate, 22 is an insulating film, 23 is a photoresist film, 24 is a tungsten silicide (WSi) layer, 25
Is a tungsten (W) layer, 26 is a titanium (Ti) layer, 2
7 is a gold (Au) layer, 28 is a platinum (Pt) layer, and 29 is a photoresist film.

A method of manufacturing a HEMT structure semiconductor device according to an embodiment of the present invention will be described with reference to the manufacturing process explanatory diagrams.

First step (see FIG. 2A) [Insulating film deposition] n-GaAs layer, n-AlGaA on the surface
An insulating film 22 of SiON or the like having a thickness of 3400Å is formed on the semiconductor substrate 21 on which the s layer and the i-GaAs layer are formed.

Second step (see FIG. 2B) [Formation of gate resist pattern] A photoresist film 23 is formed on the insulating film 22 formed in the previous step, and an opening is formed in the gate region.

Third Step (See FIG. 2C) [Etching] The insulating film 22 is selectively etched using the photoresist film 23 having the opening formed in the previous step as a mask, and then the photoresist film 23 is removed. Remove.

Fourth step (see FIG. 2D) [Sputtering of WSi] The insulating film 22 formed in the previous step is formed by one step.
After cleaning with 0% ammonia water, a thickness of 10 is formed on the surface of the insulating film 22 and on the semiconductor substrate 21 exposed in the opening.
A 00Å tungsten silicide (WSi) layer 24 is formed by the sputtering method. The coverage of the WSi layer 24 deposited by sputtering is better than when deposited by evaporation.

Fifth Step (Refer to FIG. 3E) [Thermal CVD of W] The semiconductor substrate 21 subjected to the previous step
Is heated to 450 ° C. in a thermal CVD apparatus, and a tungsten (W) layer 25 having a thickness of 1000 Å is deposited on the entire surface.

Sixth Step (See FIG. 3F) [Sputtering of Ti, Au, Pt] On the W layer 25 formed in the previous step, a titanium (Ti) layer 26, 3 having a thickness of 100 Å is formed.
00Å gold (Au) layer 27, 80Å thick platinum (Pt)
The layer 28 is formed by the sputtering method.

Seventh step (see FIG. 3G) [Formation of gate upper pattern] Pt layer 2 formed in the previous step
A photoresist film 29 is formed on the entire surface of 8 and patterned into the shape of the gate electrode planned region.

Eighth step (see FIG. 3H) [Formation of gate electrode] Using the photoresist film 29 patterned in the previous step as a mask, the Pt layer 28 and the Au layer 2 are formed.
7, the Ti layer 26, the W layer 25, and the WSi layer 24 are sequentially removed by etching to form a gate electrode. Then, the photoresist film 29 is removed.

Although not shown, the HEMT structure semiconductor device is formed by forming the source region and the drain region and their electrodes by a conventionally known process.

As in the prior art, as in the present invention, WSi
If a W layer is attempted to be deposited on the insulating film and the semiconductor substrate by a thermal CVD method without forming a layer as a base,
When the temperature of the semiconductor substrate is about 450 ° C., it is difficult to deposit the W layer on the inactive insulating film. Therefore, it is difficult to deposit the W layer in a blanket form on the entire surface of the semiconductor substrate and the insulating film. ..

However, when the underlying WSi layer 24 is formed as a pre-step of depositing the W layer 25 by the thermal CVD method as in this embodiment (fifth step), this WSi layer 2 is formed.
Since 4 is active, the W layer 25 can be deposited in a blanket form. This step also has the effect of recovering damage to the semiconductor substrate 21 that has occurred when the WSi layer 24 was formed by the sputtering method in the fourth step.

Although the HEMT structure semiconductor devices have been described in the above embodiments, the present invention is not limited to the MESF.
It is also applicable to ET, and MIS using i-semiconductor layer
It can also be applied to FETs, MISFETs and MOSFETs using insulating films such as SiO ₂ films and Si ₃ N ₄ films.

[0039]

As described above, according to the present invention,
By improving the coverage of the gate electrode, it is possible to eliminate problems such as generation of leakage current of the gate electrode, fluctuation of threshold current, and corrosion of the substrate due to chemical intrusion from cracks in the gate electrode. , In the step of depositing a W layer on the semiconductor substrate by the thermal CVD method when the compound of tungsten and silicon is formed on the semiconductor substrate, the damage is automatically recovered without taking it out from the deposition apparatus. be able to.

[Brief description of drawings]

FIG. 1 is a structural explanatory view of a field effect semiconductor device according to a first embodiment of the present invention.

2A to 2D are explanatory views (1) of the manufacturing process of the field effect semiconductor device according to the second embodiment of the present invention.

3 (E) to (H) are explanatory views (2) of the manufacturing process of the field effect semiconductor device according to the second embodiment of the present invention.

4A to 4D are explanatory views (1) of a manufacturing process of a conventional field effect semiconductor device.

5 (E) to (H) are explanatory views (2) of the manufacturing process of the conventional field effect semiconductor device.

[Explanation of symbols]

 1 semi-insulating GaAs substrate 2 buffer layer 3 i-GaAs active layer 4 two-dimensional electron gas channel 5 n-AlGaAs electron supply layer 6 ohmic region 7 insulating film 8 source electrode 9 drain region 10 tungsten silicide (WSi) layer 11 tungsten ( W) layer 12 titanium (Ti) layer 13 gold (Au) layer 14 platinum (Pt) layer

Claims (2)

[Claims] 1. A field-effect semiconductor device having a gate electrode including a structure in which a compound layer of tungsten and silicon is formed as a lowermost layer, and a tungsten layer is formed thereon. 2. The method comprises the steps of forming a compound layer of tungsten and silicon on the lowermost layer of the gate electrode by a sputtering method, and forming tungsten on the compound layer of tungsten and silicon by a thermal CVD method. A method for manufacturing a field effect semiconductor device.