JPH05206163A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH05206163A JPH05206163A JP29687891A JP29687891A JPH05206163A JP H05206163 A JPH05206163 A JP H05206163A JP 29687891 A JP29687891 A JP 29687891A JP 29687891 A JP29687891 A JP 29687891A JP H05206163 A JPH05206163 A JP H05206163A
- Authority
- JP
- Japan
- Prior art keywords
- resist
- source
- drain
- exposure sensitivity
- low
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 239000004065 semiconductor Substances 0.000 title claims description 14
- 238000004519 manufacturing process Methods 0.000 title description 8
- 230000035945 sensitivity Effects 0.000 claims abstract description 12
- 150000002500 ions Chemical class 0.000 claims abstract 3
- 239000000758 substrate Substances 0.000 claims description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 11
- 238000005468 ion implantation Methods 0.000 abstract description 10
- 239000012535 impurity Substances 0.000 abstract description 9
- 238000000206 photolithography Methods 0.000 abstract description 3
- 239000011248 coating agent Substances 0.000 abstract description 2
- 238000000576 coating method Methods 0.000 abstract description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract 2
- 229910052710 silicon Inorganic materials 0.000 abstract 2
- 239000010703 silicon Substances 0.000 abstract 2
- 238000009792 diffusion process Methods 0.000 description 13
- 238000000034 method Methods 0.000 description 7
- 238000000059 patterning Methods 0.000 description 3
- 230000000295 complement effect Effects 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
- H01L29/66598—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET forming drain [D] and lightly doped drain [LDD] simultaneously, e.g. using implantation through the wings a T-shaped layer, or through a specially shaped layer
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体装置の製造方法に
関し、特にＭＯＳ型トランジスタのゲート端のソース及
びドレイン近傍の拡散層の不純物濃度を低く形成する方
法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming a low impurity concentration in a diffusion layer near the source and drain at the gate end of a MOS transistor.
【０００２】[0002]
【従来の技術】図２の（ａ）乃至（ｃ）は従来のＭＯＳ
型トランジスタのゲート端のドレインとソース近傍の不
純物濃度が低い拡散層を形成する製造方法を工程順に示
す断面図である。まず図２（ａ）において、半導体基板
１の表面に、酸化膜２，ゲート酸化膜３をそれぞれ選択
的に成長させ、ゲート酸化膜３の上に多結晶シリコン４
を成長させてパターニングした後、セルフアラインで、
イオン注入を行ない不純物濃度の低い拡散層６を形成す
る。2. Description of the Related Art FIGS. 2A to 2C show a conventional MOS.
6A to 6C are cross-sectional views showing, in the order of steps, a manufacturing method of forming a diffusion layer having a low impurity concentration near the drain and source at the gate end of the type transistor. First, in FIG. 2A, an oxide film 2 and a gate oxide film 3 are selectively grown on the surface of a semiconductor substrate 1, and polycrystalline silicon 4 is formed on the gate oxide film 3.
After growing and patterning, self-aligning
Ion implantation is performed to form a diffusion layer 6 having a low impurity concentration.
【０００３】次に、図２（ｂ）のごとく、熱酸化膜１０
を表面に被覆し、多結晶シリコン４の主面及び不純物濃
度の低い拡散層６が露出するように熱酸化膜１０をエッ
チングする。この時、多結晶シリコン４の側面には、熱
酸化膜１０が厚く付着したまま残る。Next, as shown in FIG. 2B, the thermal oxide film 10 is formed.
And the thermal oxide film 10 is etched so that the main surface of the polycrystalline silicon 4 and the diffusion layer 6 having a low impurity concentration are exposed. At this time, the thermal oxide film 10 remains thickly attached to the side surface of the polycrystalline silicon 4.
【０００４】その後、図２（ｃ）のごとく再びイオン注
入を行ない多結晶シリコン４と熱酸化膜１０に対しセル
フアラインでソース及びドレイン拡散層７を形成する。Then, as shown in FIG. 2C, ion implantation is performed again to form source and drain diffusion layers 7 by self-alignment with the polycrystalline silicon 4 and the thermal oxide film 10.
【０００５】[0005]
【発明が解決しようとする課題】この従来の半導体装置
の製造方法では、ゲート端のソース及びドレイン近傍に
不純物濃度の低い拡散層を形成するため、２回のイオン
注入を行ない、またソース及びドレイン拡散層をセルフ
ァラインで形成するため多結晶シリコンの側面に熱酸化
膜を付着しなければならなかった。In this conventional method of manufacturing a semiconductor device, since a diffusion layer having a low impurity concentration is formed near the source and drain at the gate end, ion implantation is performed twice, and the source and drain are also implanted. In order to form the diffusion layer by self-alignment, a thermal oxide film had to be attached to the side surface of the polycrystalline silicon.
【０００６】さらにまた、相補型ＭＯＳ半導体集積回路
装置を構成する場合ゲート端のソース及びドレイン近傍
に不純物濃度の低い拡散層を、Ｎチャネル型ＭＯＳトラ
ンジスタ、Ｐチャネル型ＭＯＳトランジスタについてそ
れぞれ形成するために、ホトリソグラフィー工程及びイ
オン注入工程をそれぞれ２回行なわなければならないと
いうような問題点があった。Furthermore, in the case of constructing a complementary MOS semiconductor integrated circuit device, diffusion layers having a low impurity concentration are formed near the source and drain at the gate end for the N-channel MOS transistor and the P-channel MOS transistor, respectively. However, there is a problem that the photolithography process and the ion implantation process must be performed twice.
【０００７】[0007]
【課題を解決するための手段】本発明によれば、半導体
基板の表面にゲート電極をパターニングし、ソース及び
ドレインを形成する工程において、露光感度の高い第１
のレジストを塗布した上にこの第１のレジストより露光
感動の低い第２のレジストを塗布し、ソース及びドレイ
ンのパターンを露出するように露光を行なう工程，現像
を行なって第１のレジストをゲート電極のパターンより
も小さく第２のレジストを、ゲート電極のパターンより
も大きく残す工程，イオン注入を行ない第２のレジスト
を介さずに垂直にイオン注入された高濃度のソース及び
ドレイン領域と第２のレジストのみを介してゲート端に
斜めに同時にイオン注入された低濃度のソース及びドレ
イン領域を形成する工程とを含む半導体装置の製造方法
を得る。According to the present invention, in the step of patterning the gate electrode on the surface of the semiconductor substrate to form the source and the drain, the first exposure-sensitivity is high.
After applying the second resist, which has a lower exposure sensitivity than the first resist, and performing exposure so as to expose the source and drain patterns, the development is performed to gate the first resist. A step of leaving the second resist smaller than the pattern of the electrode larger than the pattern of the gate electrode, ion implantation is performed, and the high-concentration source and drain regions and the second high-concentration source and drain regions vertically implanted without the intervention of the second resist. And a step of forming low-concentration source and drain regions that are simultaneously and obliquely ion-implanted at the gate end through the resist only.
【０００８】[0008]
【実施例】次に本発明について図面を参照して説明す
る。The present invention will be described below with reference to the drawings.
【０００９】図１（ａ）乃至（ｂ）は本発明の一実施例
の半導体装置の製造方法を工程順に示す断面図である。1A and 1B are sectional views showing a method of manufacturing a semiconductor device according to an embodiment of the present invention in the order of steps.
【００１０】まず、図１の（ａ）に示すように、半導体
基板１の表面に、酸化膜２と、ゲート酸化膜３をそれぞ
れ選択的に成長させ、ゲート酸化膜３の上に多結晶シリ
コン４を成長させてパターニングした後、露光感度の高
いレジスト７を塗布し、その上に露光感度の低いレジス
ト８を塗布する。First, as shown in FIG. 1A, an oxide film 2 and a gate oxide film 3 are selectively grown on the surface of a semiconductor substrate 1, and polycrystalline silicon is formed on the gate oxide film 3. After growing and patterning 4, resist 7 having high exposure sensitivity is applied, and resist 8 having low exposure sensitivity is applied thereon.
【００１１】次に図１の（ｂ）のごとくソース及びドレ
インのパターンを露出するように露光と現像を１回だけ
行ない露光感度の高いレジスト７を多結晶シリコン４よ
り小さく残し、さらに露光感動の低いレジスト８を多結
晶シリコン４より大きく残す。次に半導体基板１の表面
に垂直な方向からイオン注入を１回だけ行なうと、多結
晶シリコン４の端のソース及びドレイン近傍はレジスト
８が影となってイオン注入量が、ソース及びドレイン拡
散層５よりも少なくなり、不純物濃度が低い拡散層６が
形成される。Next, as shown in FIG. 1B, exposure and development are carried out only once so as to expose the source and drain patterns, and the resist 7 having a high exposure sensitivity is left smaller than the polycrystalline silicon 4, and the exposure sensitivity is further increased. The low resist 8 is left larger than the polycrystalline silicon 4. Next, when ion implantation is performed only once from a direction perpendicular to the surface of the semiconductor substrate 1, the resist 8 is shaded in the vicinity of the source and drain at the end of the polycrystalline silicon 4, and the ion implantation amount is the source and drain diffusion layers. 5, the diffusion layer 6 having a lower impurity concentration is formed.
【００１２】本実施例を用いれば相補型ＭＯＳ半導体集
積回路装置の製造工程において従来例に比べてホトリソ
グラフィー工程及びイオン注入工程がそれぞれ２回削減
できる。By using this embodiment, the photolithography process and the ion implantation process can be reduced twice each in the manufacturing process of the complementary MOS semiconductor integrated circuit device as compared with the conventional example.
【００１３】[0013]
【発明の効果】以上説明したように、本発明は、露光感
度の異なるレジストを２重に塗布することによって異な
る２種類の拡散層が１回の露光と現像及びイオン注入で
同時に形成できる等の効果が得られる。As described above, according to the present invention, two different types of diffusion layers can be simultaneously formed by one-time exposure, development and ion implantation by double coating resists having different exposure sensitivities. The effect is obtained.
【図面の簡単な説明】[Brief description of drawings]
【図１】（ａ）乃至（ｂ）は本発明の一実施例の半導体
装置の製造方法を工程順に示す断面図1A and 1B are cross-sectional views showing, in the order of steps, a method for manufacturing a semiconductor device according to an embodiment of the present invention.
【図２】（ａ）乃至（ｃ）は従来の半導体装置の製造方
法を工程順に示す断面図2A to 2C are cross-sectional views showing a method of manufacturing a conventional semiconductor device in the order of steps.
１ 半導体基板 ２ ロコス酸化膜 ３ ゲート酸化膜 ４ 多結晶シリコン ５ 第１の拡散層 ６ 第２の拡散層 ７ 高感度のレジスト ８ 低感度のレジスト ９ レジスト １０ 側面酸化膜 1 semiconductor substrate 2 locos oxide film 3 gate oxide film 4 polycrystalline silicon 5 first diffusion layer 6 second diffusion layer 7 high-sensitivity resist 8 low-sensitivity resist 9 resist 10 side oxide film
Claims (1)
る工程と、 露光感度の高い第１のレジストを塗布した上に、さらに
前記第１のレジストより露光感度の低い第２のレジスト
を塗布し、前記ゲート電極の両側部のソース及びドレイ
ン領域のパターンが露出するように露光を行なう工程
と、 現像を行なって前記第１のレジストを前記ゲート電極の
パターンよりも小さく残して、前記第２のレジストを前
記ゲート電極のパターンよりも大きく残して、イオン注
入を行ない前記第２のレジストを介さずに垂直にイオン
注入された高濃度のソース及びドレイン領域と前記第２
のレジストのみを介してゲート端に同時に斜めにイオン
注入された低濃度のソース及びドレイン領域を形成する
工程とを含むことを特徴とする半導体装置の製造方法。1. A step of forming a gate electrode on a surface of a semiconductor substrate, and applying a first resist having a high exposure sensitivity, and further applying a second resist having an exposure sensitivity lower than that of the first resist. Exposing the source and drain regions on both sides of the gate electrode so that the pattern is exposed; and developing to leave the first resist smaller than the pattern of the gate electrode, Ions are implanted by leaving the resist larger than the pattern of the gate electrode, and the high-concentration source and drain regions and the second regions which are vertically ion-implanted without going through the second resist.
Forming a low-concentration source and drain regions simultaneously and obliquely ion-implanted into the gate end only through the resist.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP29687891A JPH05206163A (en) | 1991-11-13 | 1991-11-13 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP29687891A JPH05206163A (en) | 1991-11-13 | 1991-11-13 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05206163A true JPH05206163A (en) | 1993-08-13 |
Family
ID=17839335
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP29687891A Withdrawn JPH05206163A (en) | 1991-11-13 | 1991-11-13 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH05206163A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100824619B1 (en) * | 2006-10-27 | 2008-04-24 | 동부일렉트로닉스 주식회사 | Method for manufacturing semiconductor device by using dual photoresist |
-
1991
- 1991-11-13 JP JP29687891A patent/JPH05206163A/en not_active Withdrawn
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100824619B1 (en) * | 2006-10-27 | 2008-04-24 | 동부일렉트로닉스 주식회사 | Method for manufacturing semiconductor device by using dual photoresist |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A300 | Withdrawal of application because of no request for examination |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 19990204 |