JPH05204349A - Image data processor - Google Patents

Abstract

PURPOSE:To improve operability by outputting a chrominance signal directly when image data is outputted in the form of a chrominance signal, and converting the data into a chrominance signal and outputting the signals when the data is outputted in the form of a brightness signal and a color difference signal. CONSTITUTION:When the image data DG outputted from an image memory 50 corresponding to the contents of a mode register 110 are the image data DG of chrominance signals SR, SB and SG which are red, blue and green, the chrominance signals SR, SB and SG of the image data DG are directly outputted, and when the image data outputted from the image memory 50 are the image data DG of the luminance signal Y and color difference signals R-Y and B-Y, the image data DG are converted into the chrominance signals SR, SB and SG which are red, blue and green and the chrominance signals are outputted. Consequently, the chrominance signals SR, SB and SG are always outputted even when processing form is changed, thus the processing form is freely changed by abbreviating connection changing operation or the like.

Description

Detailed Description of the Invention

[0001]

[Table of Contents] The present invention will be described in the following order. Field of Industrial Application Conventional Technology Problems to be Solved by the Invention Means for Solving the Problems (FIG. 27) Action (FIG. 27) Example (1) Overall Configuration (FIGS. 1 and 2) (1-1) CPU board (Fig. 3) (1-2) Graphic board (Fig. 4) (1-3) Video signal processing device (Fig. 5) (2) Image memory control (Figs. 6 to 18) (3) Lucky backup Table Control (FIGS. 19 to 26) (4) Encoder (FIG. 27) (5) Cursor Control (FIGS. 28 to 30) (6) Effect of Embodiment (7) Effect of Other Embodiment

[0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image data processing device, and can be applied to, for example, an image synthesizing device for synthesizing an image generated by a computer with a desired image.

[0003]

2. Description of the Related Art Conventionally, in an image synthesizing apparatus, an image is generated by a computer or the like, and then the image is synthesized with a desired image to be used as, for example, a telopa.
Some have been designed so that a desired title or the like can be superimposed.

That is, in this type of image synthesizing apparatus, after the image data output from the computer is once stored in the image memory and then replaced with the image data of the background image based on the desired key signal, for example, a desired image signal is obtained. It is designed so that the title can be superimposed and characters such as people and animals can be embedded in natural paintings.

[0005]

By the way, in this type of image synthesizing apparatus, it would be convenient if the usability could be improved with a simple structure. The present invention has been made in consideration of the above points, and an object thereof is to propose an image data processing device which can improve usability with a simple configuration.

[0006]

In order to solve such a problem, the present invention provides a color signal SR for red, blue and green.
Processing format of SB, SG, or luminance signal Y and color difference signal R
In the image data processing device 1 which selects the processing format of -Y and BY, and processes the image data DG in the selected processing format, the mode register 110 which stores the mode of the processing format.
And the red, blue, and green color signals S corresponding to the processing format
The image memory 50 stores the image data DG of R, SB, SG, or the image data DG of the luminance signal Y and the color difference signals RY, BY, and the image memory 50 according to the contents of the mode register 110. When the image data DG to be reproduced is the image data DG of the red, blue and green color signals SR, SB and SG, the color signals SR, SB and S of the image data DG.
G is directly output, and when the image data DG output from the image memory 50 is the image data DG of the luminance signal Y and the color difference signals RY and BY, the image data DG is red, blue,
An image data conversion circuit 75 for converting and outputting green color signals SR, SB, SG is provided.

[0007]

According to the contents of the mode register 110, the image data DG output from the image memory 50 is red, blue,
In the case of the image data DG of the green color signals SR, SB, SG, the color signals SR, SB, SG of the image data DG are directly output, and the image data DG output from the image memory 50.
Is the image data DG of the luminance signal Y and the color difference signals RY and BY, if the image data DG is converted into the color signals SR, SB and SG of red, blue and green and outputted, the processing format becomes Even if the switching is performed, the color signals SR, SB, SG can always be output, and the processing format can be freely switched by omitting the connection switching work and the usability can be improved accordingly.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail with reference to the drawings.

(1) Overall Structure In FIG. 1, reference numeral 1 denotes a video graphic system as a whole, and a computer 2 comprising a workstation.
An image for compositing (hereinafter referred to as a compositing image) is created with.

That is, as shown in FIG. 2, in the computer 2, the video signal SV1 is output from the computer main body 6 to the display device 8 via the display board 4.
As a result, the user operates the keyboard 10, the mouse 12 and the tablet 14 while monitoring the display screen of the display device 8 and operates the video graphics system 1
It is designed to be able to operate.

At this time, in the computer 2, the CP
The image data of the image for composition can be stored in the graphic board 18 via the U board 16. Further, in the computer 2, in response to the operation of the keyboard 10 or the like, a command is sent to the CPU board 16, which causes the graphic board 18 via the bus BS1.
The image data stored in the video signal processing device 20 can be sent to the video signal processing device 20, and the image data sent from the video signal processing device 20 can be stored in the graphics board 18 as needed. As a result, the computer 2 can input / output the synthesizing image, the image data for synthesizing the image and the like to / from the video signal processing device 20.

Further, in the computer 2, the video signal SV2 of the composite image can be sent to the display device 21, so that the composite image can be created while monitoring the display screen of the display device 21. Has been done.

In the computer 2, the display board 4, the CPU board 16 and the graphic board 18 are respectively housed in three slots provided on the back surface.

The video signal processing device 20 is adapted to capture a background image or the like for image composition by capturing the video signal SV3 of the video tape recorder (VTR) 22, and the command input via the bus BS1 is used. In response, the background image and the image for composition are combined to generate a combined video signal. Further, the video signal processing device 20 outputs the composite video signal SV4 to the video tape recorder 26 via the switcher 24 and, if necessary, outputs it to the image display device 21 to record the composite image.
It is designed to be monitored.

Further, the video signal processing device 20 outputs the video signal SV3 from the video tape recorder 22 to the computer 2.
Output to the computer 2
In this, the image for synthesis can be generated by using the video signal SV3.

(1-1) CPU Board Here, as shown in FIG. 3, the CPU board 16 has a CPU 30 dedicated to image processing, and a computer main body 6 and a 64-bit CPU are provided via an input / output circuit 32 having a buffer memory configuration. The bus BS2 is used for connection.

That is, the CPU 30 operates by the clock signal output from the oscillation circuit 31, and when the power supply of the video graphics system 1 is turned on, the EPROM 3
The processing program stored in 4 is executed. As a result, when the power is turned on, the CPU 30 downloads the processing program output from the computer main body 6 to the memory circuit 36 according to the processing program.

At this time, in the CPU board 16, the memory circuit 35 is controlled by the memory controller 35 based on the decoding result of the address decoder 33, whereby the sequentially input data is stored in a predetermined area of the memory circuit 36. It is designed to be stored.

Further, the CPU 30 responds to the operation of the keyboard 10 etc. from the computer main body 6 to the input / output circuit 32.
When a command is input to the interrupt control circuit 38, the interrupt signal INT output from the input / output circuit 32 is input via the interrupt control circuit 38. As a result, the CPU 30 interrupts the execution of the processing program based on the interrupt signal INT, then accesses the memory circuit 36, and thereby executes a predetermined processing procedure according to the command.

As a result, the CPU 30 outputs the subsequently input image data to the graphic board 18 via the bus BS3 and, if necessary, the graphic board 1.
The control signal is output to 8. Further, the CPU 30 reads out the image data from the graphic board 18, and also performs arithmetic processing on the image data and outputs the image data, whereby the air brush processing, the mask processing, the image deformation processing and the like can be performed.

At this time, the CPU 30 controls the control signal (RS 232-C) input via the input / output circuits 40 and 41.
It becomes possible to switch the operation based on
As a result, in the videographic system 1, an external device can be separately connected to control the entire operation.

In the CPU board 16, the input / output circuit 4 consisting of an 8-bit device is connected to the 64-bit bus BS3 via the rate conversion circuit 42 and the address decoder 43.
0, 41, etc. are connected, and the timer 44
Is used to refresh the whole at a predetermined timing.

(1-2) Graphic board As shown in FIG. 4, the graphic board 18 is a bus B.
The 32-bit image data input via S3 is accumulated in the image memory 50, and the image data of the image for composition is output to the video signal processing device 20 by sequentially outputting the image data at a predetermined timing. Further, the graphic board 18 stores the image data input from the video signal processing device 20 in the image memory 50 and sends it to the CPU board 16 as necessary.

Here, the image memories 50 are each 2 [M
B], which is composed of four frame memories (hereinafter referred to as banks, respectively represented by symbols BK0 to BK3), and two banks BK0, BK1 and BK2, BK3 are normally connected to two input / output channels. It is designed to be done.

Further, the image memory 50 uses the memory controller 5 based on the decoding result of the address decoder 51.
The write and read operations are controlled by 2 and the two banks BK0, BK1 and BK at this time are controlled.
By using 2 and BK3 in combination, various processes can be executed with a small memory capacity. Further, the image memory 50 includes banks BK0,
The image data of BK1, BK2, and BK3 is selected by the selector 5
Input / output can be performed via 4, 56.

The selector 58 selectively takes in and outputs the image data output from the selectors 54 and 56,
In the case of this embodiment, the output channel of the selector 58 is used as the main channel CH0. On the other hand, the selector 60 is configured to be able to selectively input / output image data to / from the selectors 54 and 56. In the case of this embodiment, the selector 60 side is used as a sub-channel CH1. Image data can be input to and output from the video signal processing device 20.

A look-up table (LUT) 61 having a memory circuit configuration inputs image data output from the selector 58 as address data and sends data accessed by the address data as image data. ing. As a result, the lookup table 61 can convert the output data of the selector 62 into image data in accordance with a predetermined rule and output the image data. At this time, the contents of the table are updated by the CPU board 16 to, for example, the address. The conversion rule of the image data can be set in a desired relationship so that the data and the output data have a 1: 1 correspondence.

Further, a selector 62 is inserted between the look-up table 61 and the selector 58, whereby the graphic board 18 directly outputs desired image data based on the address data generated by the memory controller. It is designed to be able to do.

On the contrary, the graphic board 1
In FIG. 8, the output data of the look-up table 61 is fed back to the memory controller 52, so that the address data can be generated based on the output data of the look-up table 61 as needed. There is.

Thus, in the graphic board 18, the main channel CH0 is dedicated to the output of image data,
The sub-channel CH1 is assigned to input / output of image data.

Further, at this time, the graphic board 18 operates by using the external synchronizing signal GENLOCK input from the video signal processing device 20 as a reference, whereby a predetermined format (that is, CCIR 601) with the video signal processing device 20. It is designed to be able to input and output image data in the format specified in (1). Correspondingly, each bank BK0 of the image memory 50
The BK3 is designed to be able to store a total of 32 bits of image data consisting of 8 bits of color signal and alpha signal respectively for 1024 × 512 pixels in the x and y directions, whereby the NRSC system defined in CCIR601 is established. Digital video signal (ie consisting of 720 x 485 pixels)
Is capable of handling.

The decoder 63 is adapted to decode the digital video signal of the main channel CH0 output by the format to convert the image data of the main channel CH0 into the video signal SV2 which is a color signal and output it. There is.

(1-3) Video Signal Processing Device As shown in FIG. 5, in the video signal processing device 20, the combiner 69 combines and outputs the image data of the main channel CH0 and the sub-channel CH1. At this time, in the video signal processing device 20, the entire operation is controlled by the controller 68, and further, in the controller 68, the control signal RS3 (that is, RS
232C and RS 422 format).

Further, in the video signal processing device 20, the video signal SV3 of the video tape recorder 22 is converted into a color signal by the decoder 70 and then output to the combiner 69 via the analog digital conversion circuit (A / D) 71. As a result, the image data composed of the video signal SV3 can be used in place of the image data of the sub-channel CH1, and the image data output from the analog digital conversion circuit 71 can be further converted as necessary. It can be output to the graphic board 18.

On the contrary, the video signal processing device 2
In the case of 0, the image data of the sub-channel CH1 is converted into an analog signal by the digital analog conversion circuit (D / A) 72, and then converted into the video signal SV5 by the encoder 73 for output, whereby the pre-view image is obtained. Is designed to be able to monitor.

On the other hand, the combiner 69 outputs the alpha signal S which is included in the image data of the main channel CH0.
Main channel CH based on α (that is, the transparency of the main channel CH0 image data)
The image data of 0 and the image data of the sub-channel CH1 or the image data output from the analog digital conversion circuit 71 are multiplied and added, whereby the image data is combined to form a desired image.

That is, the multiplication value is complementarily switched between the value 0 and the value 1, and the image data of the main channel CH0 is sub-selected by multiplying the image data of the main and sub-channels CH0 and CH1 by the multiplication value and performing addition processing. You can superimpose on the image of the channel. At this time, for example, if the image of the main channel CH0 is scrolled, the superimposed title can be scrolled in the combined image. On the other hand, if the multiplication value is sequentially changed in a complementary manner, it is possible to synthesize the image so that the image of the main channel is blurred to the image of the sub-channel.

Digital analog conversion circuit (D / A) 7
Reference numeral 4 converts the image data output from the combiner 69 into a digital signal and outputs the digital signal. The encoder 75 converts the output signal of the digital analog conversion circuit 74 into the video signal S.
Convert to V4 and output. As a result, the video signal processing device 20 can output the video signal SV4 of the composite image via the encoder 75.

At this time, the encoder 75 outputs the video signal SV4 in the form of a video signal, and the color signals R, G, B or the luminance and luminance signal Y, and the color difference signals U, V.
The video signal processing device 20 is capable of outputting the video signal in the form of, and thus the video signal processing device 20 can freely switch the connection according to the type of the external device, thereby improving the usability of the video graphics system 1 as a whole. It is designed to be able to do.

The rate conversion circuit 76 outputs an 8-bit alpha signal Sα which changes in the range from 0 gradation to 255 gradations.
Converted to an α signal that changes in the range of 16 to 235 gradations,
As a result, the gradation of the alpha signal Sα is converted into the gradation of the luminance signal and output.

The digital-analog conversion circuit 77 converts the α signal into an analog signal and outputs it.

The level controller 78 switches the operation based on the control signal output from the computer 2,
As a result, the α signal is directly output via the encoder 80, and converted into the key signal SK according to the type of the external device and output. As a result, the video signal processing device 20
In this case, the key signal SK or the 8-bit α signal can be selectively output according to the external device, and the usability of the entire system can be improved.

In the video signal processing device 20,
The burst signal SREF is given to the clock generation circuit 82,
Here, various reference signals such as an external synchronizing signal GENLOCK and the like are generated with reference to the burst signal SREF, so that the entire system operates in synchronization with the video tape recorder 22.

(2) Control of Image Memory Here, as shown in FIG. 6, in the graph board 18, the address data generated by the memory controller 52 is output to the selector controllers 82 and 84, whereby the selector controller 82 concerned. And 84 control the selectors 54 and 56, and also control the selectors 58 and 60 based on the address data.

That is, in the memory controller 52, when the image data is accumulated, the address data is sequentially generated according to the address data output from the CPU board 16, and the sequential image data DG is sequentially generated in a predetermined area of each of the banks BK0 to BK3. accumulate. On the other hand, when the image data is read, in the memory controller 52, the main channels CH are respectively generated by the address generation circuits 85 and 86.
0 and sub-channel CH1 address data is generated,
The lower bit data of the address data is output to the frame memory 50 via the multiplexer (MPX) 83.

That is, as shown in FIG. 7, the address generation circuits 85 and 86 have the same configuration and have an X address counter 88 and a Y address counter 89, respectively.
Generates address data in x and y directions.

At this time, in the X address register 90 and the Y address register 91, the reference address data ADREF output from the CPU board 16 is accumulated and stored in the X address register.
The address data is output to the address counter 88 and the Y address counter 89. In the X address counter 88 and the Y address counter 89, the address data is sequentially generated in raster scanning order starting from the image data determined by the reference address data ADREF. It is designed to do. As a result, in the videographic system 1, the image can be cut out from the image memory 50 and processed based on the starting point only by designating the position of the starting point with the mouse 12.

Therefore, in the video graphic system 1, the image to be cut out can be designated by a simple operation, and the usability is improved accordingly. Further, at this time, in the CPU board 16, the position of the starting point determined by the reference address data ADREF is sequentially updated according to the setting by the user, whereby the position of the image to be cut out is sequentially moved, and the composite image is scrolled. It is designed to be able to do.

Thus, in the video graphics system 1, the composition image can be scrolled with a simple structure in which the address data is generated from the position of the starting point determined by the reference address data ADREF, so that the periphery of the image memory 50 can be scrolled. The circuit can be simplified, and the entire configuration can be simplified accordingly.

Further, in this embodiment, the X address counter 88 and the Y address counter 89 generate address data in the address space as shown in FIG.

That is, the X address counter 88 is provided from address 0 to 2047 which is an address space for two banks in the X direction.
While the address data in the X direction is generated in the range up to the address, the Y address counter 89 operates in the bank 4 in the Y direction.
Address data in the Y direction is generated in the range from address 0 to address 2047, which is the address space for each piece. Further, in the X address counter 88, the generated lower 10 bits of the address data X0 to X9 are stored in the banks BK0 to BK3.
On the other hand, the Y address counter 89 outputs the generated lower 9-bit address data Y0 to Y8 to the banks BK0 to BK3.

As a result, in each of the banks BK0 to BK3, image data is output simultaneously in parallel based on the address data X0 to X9 and the address data Y0 to Y8.

Further, the X address counter 88 has the upper 1
While the bit address data X10 is output to the look-up table (LUT) 93, the Y address counter 89 uses the upper two bits of the address data Y9 and Y1.
0 is output to the look-up table (LUT) 94.

Here, the backup table 93 and 94
In this case, the contents can be updated by the CPU board 16 so that, for example, the address data held in a 1: 1 correspondence with the address data X10 and the address data Y9, Y10 is output. There is. In this case, the memory controller 52 outputs the bank switching signal via the look-up table 93 so that the logical value rises when the address data in the X direction exceeds the address 1024, while the same is done via the look-up table 94. Address data in the Y direction is 512
A 2-bit bank switching signal is output so that the logical value is sequentially switched when the addresses, 1024 and 1536 are exceeded.

The memory controller 52 controls the selectors 54 to 60 based on the bank switching signal to selectively output the image data output from the banks BK0 to BK3 in parallel at the same time. From this, the image memory 50 is controlled in a virtual address space as if eight frame memory circuits were used. As a result, in the memory controller 52,
The arrangement of the banks BK0 to BK3 can be switched and controlled according to the address data, and four frame memories can be used as if there are eight frame memories, which allows the video graphic system 1 to have a small memory space. Is designed to improve usability.

That is, the OR circuit 95 receives the most significant bits of the address data in the X and Y directions via the look-up tables 93 and 94, respectively, and outputs the resulting output signal CH0BK1 (CH1BK1) to the selector 58 (60). Output to. As a result, the OR circuit 95
For each of the main and sub channels CH0 and CH1, the address data in either the X direction or the Y direction is 1024.
When the address is exceeded, the image data output from the selector 56 is selectively output instead of the image data output from the selector 54 side.

On the other hand, the selector controllers 82 and 84 output the output signal CH0BK1 (CH
1BK1) and the data CH0BK0 (CH1BK0) of the second upper bit of the Y-direction address data, and controls the selectors 54 and 56.

That is, in the selector 54, in the range where the address data in the X direction does not exceed the address 1024,
Bank BK when Y direction address data exceeds 512
Instead of 0, the image data of the bank BK1 is selected. On the other hand, the selector 56 selects the image data of the bank BK3 instead of the bank BK2 when the Y-direction address data exceeds 1536 within the range where the X-direction address data does not exceed 1024. If the address data in the X direction exceeds 1024, the address data in the Y direction will range from 512 to 1023 and from 1536.
In the range of address 2047, the image data of bank BK3 is selected instead of bank BK2.

As a result, the graphic board 18 can use the banks BK0 to BK3 as if image memories were allocated to the virtual address space as shown in FIG. The usability of the system 1 can be improved. Further, in the graphic board 18, the reference address AD
Since the arrangement of the banks BK0 to BK3 can be switched and used by simply generating the address data within the range of the virtual address space with reference to REF, the configuration of the peripheral circuit of the image memory 50 can be simplified accordingly. it can.

That is, as shown in FIGS. 9 and 10, when the address data in the Y direction generated by the address generation circuits 85 and 86 are in the range of 0 to 1023 and 1024 to 2048, respectively, the main and sub channels respectively. Banks BK0, BK1 and BK2, BK3 are assigned to CH0 and CH1, and a combination image can be formed with image data in a hatched area, for example.

In this state, as shown by arrows a to c in FIGS. 11 to 13, the value of the reference address ADREF is set in the Y direction and the X direction.
Direction, X and Y directions, and when the address data generated by the X and Y direction address generation circuits 85 and 86 respectively exceed 1024 addresses, the banks BK are respectively changed.
Image memory 5 such that banks BK2 and BK3 are arranged in the Y direction, the X direction, and the X and Y directions with respect to 0 and BK1.
0 can be used.

In this case, for example, as shown in FIG.
When the address data generated by the X-direction address generation circuit 85 changes beyond address 1024, the address data in the X-direction is address 1023 with respect to the horizontal synchronizing signal HD (FIG. 15A) as shown in FIG. , The output signal CH0BK1 (FIGS. 15B and 15D) of the OR circuit 95 is held at the logic L level, while the output signal CH0BK0 (FIG. 15B) directly output from the lookup table 94.
In (C) and (E)), banks BK0 and BK
The horizontal scanning period starting with I is held at the H level and the L level, respectively, whereby the arrangement of the banks BK0 to BK3 can be switched to improve the usability of the video graphics system 1.

Further, in this embodiment, the contents of the look-up tables 93 and 94 can be updated by using the CPU board 16, for example, by constructing the table so that the logic level is inverted with respect to the input.
Banks BK0-3 can be used in an inverted arrangement.

Further, by setting the contents of the table so as to output the output data held at a constant value with respect to the input data, as shown in FIGS. 16 to 18 corresponding to FIGS. 11 to 13, Image data can be output such that only one bank BK0 to BK3 is selected and the image is folded back.

Thus, the cleanup tables 93 and 9
The configuration of the image memory can be variously changed for each of the main and sub channels CH0 and CH1 with a simple configuration only by updating the contents of 4, and the usability of the videograph system 1 can be improved accordingly. You can

(3) Control of Lookup Table As shown in FIG. 19, the lookup table 61 is composed of four types of lookup tables 61α, 61R, 61G and 61B for alpha, R, G and B. Formed,
The 8-bit alpha signal Sα is output from the alpha-lookup table 61α, while the R-, G-, and B-lookup table 61R, 61G, and 61B are output.
From 8 bits each of image data DR, DG and DB
Is output.

Correspondingly, in the image memory 50, each bank BK0 to BK3 is formed by an 8-bit alpha plane 50α, an R plane 50R, a G plane 50G, and a B plane 50B, and a video signal in a color signal mode. When processing, the red, green, and blue color signals are assigned to the R plane, G plane, and B plane 50R, 50G, and 50B, respectively, whereas when the video signal is processed in the color difference signal mode, the R plane and G plane are respectively processed. I signals, luminance signals, and Q signals are assigned to the planes and B planes 50R, 50G, and 50B, and an alpha signal Sα is commonly assigned to the alpha plane 50α.

Here, each look-up table 61α, 6
Each of 1R, 61G, and 61B is formed of a table of 256 words and 16 pages, and each page can be selected according to a page selection signal SELP output through the selector 100.

That is, when the operation mode of the video graphics system 1 is set to the alpha 8 mode based on the control signal output from the CPU board 16, the selector 100 causes the page selection register 102 to output the page selection register 102. Signal SELP to the backup table 6
Output to 1. In the page selection register 102,
The contents can be updated based on the control data output from the CPU board 16.

As a result, in the alpha 8 mode, each lookup table 61α, 61R, 61G, 61B.
A predetermined page is selected via the CPU board 16, and the image data DG is converted using the selected page.

That is, as shown in FIG. 20, the look-up table 61 receives the image data DG (FIG. 20 (A)) output from each plane, and the page selected by the page selection signal SELP (FIG. 20).
The image data DG is output via (B)). As a result, in the video graphic system 1,
If necessary, gamma correction processing of image data, highlight scene enhancement processing, and the like are executed, and the processing can be switched between a color signal mode and a color difference signal mode.

At this time, in the video graphic system 1, the look-up table 61 is independently accessed with the 8-bit address data and the 8-bit image data DR, DG, and DB are output to output a natural image. Image processing is performed without deteriorating the image quality of.

On the other hand, when the alpha 6 mode is selected, the alpha plane 5 is selected in the selector 100.
The upper 2 bits of the image data output from 0α are selected and input, and the upper 2 bits of the page selection signal output from the page selection register 102 are replaced and output. As a result, when the alpha 6 mode is selected, in the video graphic system 1, the top 2 of the alpha signals are selected.
It is designed to use the bit as a page selection signal,
As a result, the paint process and the like can be easily executed.

That is, as shown in FIG. 21, the alpha 6
When the mode is selected, in the look-up table 61, for the R plane, G plane, and B plane image data (FIG. 21A), the upper 2 bits of the alpha signal and the lower 2 bits of the page selection register 102 are selected. The page determined by is selected, and the image data DR, DG, and DB are output using the page (FIG. 21 (B)). As a result, as shown in FIG. 22, in the graphic board 18, a natural image (FIG. 22 (A)) generated by the image data of the R plane, G plane, and B plane is generated, and at this time, the higher order of the alpha signal Sα is generated. The two bits are switched to a rectangular shape (FIG. 22 (B)). In the lookup table 61, the table is set so that the image data of the same value is output for all pages assigned to the rectangular area, and the input data remains unchanged for the pages assigned to the rest. By forming the table so that the values are output, a rectangular cursor can be displayed on the natural image (FIG. 22).
(C)).

At this time, in the videographic system 1, the image data of the R, G and B planes stored in the image memory 50 can be displayed by the cursor without any operation, so that the image memory 5 is simply displayed.
The cursor can be displayed at a desired position with a simple configuration in which the image data is read from 0 through the lookup table 61.

Further, in the system 1, it is also possible to freely set the area for switching the upper two bits of the alpha signal Sα and freely fill the natural image with a desired color.

At this time, in the system 1,
By switching the upper 2 bits of the alpha signal Sα in the area at a predetermined cycle and storing different image data in each page corresponding to the upper 2 bits, the filled area is changed to a desired color in the cycle. It is possible to switch and obtain a display image in which the area is blinking.

Practically, in a so-called personal use computer or the like, as shown in FIG.
The 8-bit image data DG output from 5 is directly converted to the red, green, and blue look-up tables 106-1.
08, so that the color space is expanded and many colors are reproduced in a small-capacity image memory.

In the case of this method, the image data DG stored in the image memory 105 is not the data of the displayed image itself, but simply the lookup table 106 to 10.
It is just address data that specifies the address of 8. Therefore, in the case of this method, the backup table 106-
The image memory 10 so that a predetermined area 108 is accessed.
By directly rewriting the image data DG stored in 5, the rewritten area can be set to a predetermined color.

This makes it possible to easily fill a desired area and to switch the filled color by sequentially updating the address data of the area, and to easily realize a function called palette animation.

However, this method has a drawback that it can only reproduce a color space determined by 8-bit address data and cannot reproduce a delicate color space such as a natural picture. In the case of the error, it is difficult to reproduce the original data again by operating the image data DG stored in the image memory 105.

On the other hand, as in the alpha 8 mode of this embodiment, when the look-up tables 106 to 108 for red, green and blue are accessed by independent 8-bit image data, a natural image is obtained. Although it is possible to reproduce a fine color space, there is a drawback that the function of the palette animation cannot be realized without rewriting all the image data of 8 bits × 3 systems.

That is, there is a drawback that it is impossible to easily perform palette animation and it is difficult to reproduce the original data again by manipulating the image data itself even when the image is painted in a desired color.

On the other hand, in this embodiment, by operating only the alpha signal Sα, a desired area can be easily filled, and the original image can be easily reproduced even after the painting. Furthermore, by switching the mode, it is possible to reproduce a fine color space such as a natural image.

Further, as shown in FIG. 24, if the original image data is rewritten, the color of the filled area can be easily changed. That is, in the videograph system 1, the upper 2 bits of the alpha signal Sα are set to the value 00 with respect to the original natural image M, and the upper 2 bits of the alpha signal Sα are set in the area of the arrow in the natural image M. Set the value to 01.

On the other hand, in the lookup table 61, the value 00 is set so that the input data is output as it is.
The table of pages determined by is formed, and the table of pages determined by the value 01 is formed so that the hue sequentially changes as the address increases.

In this state, in the image memory 50, the image data is rewritten in the area indicated by the arrow so that the value sequentially changes at a predetermined pitch, and the value is sequentially increased for each predetermined value with the change of time. So that the image data is updated. As a result, in the videographic system 1, the area of the arrow can be filled so that the hue sequentially changes from left to right, and the color can be set so as to change with time.

Thus, the look-up tables assigned to the red, blue, and green color signals or luminance signals and color difference signals are independently accessed by 8-bit image data, so that a fine color space such as a natural image can be obtained. Can be reproduced. Further, at this time, by using the data of the upper 2 bits of the alpha signal Sα, by switching the look-up tables assigned to the color signals or the luminance signals and the color difference signals of red, blue and green, the cursor can be easily displayed. The predetermined area can be filled, and further, the palette animation can be easily performed, and the usability of the video graphics system 1 can be improved with a simple configuration.

In the graphic board 16, if the upper 2 bits of the alpha signal Sα are used as the page selection signal in the alpha 6 mode, the alpha signal Sα
The bit length that can be used as is eventually 6 bits. Therefore, in this embodiment, the alpha-lookup table 61α is used to convert the 6-bit alpha signal Sα into 8 bits in the alpha 6 mode and output it.

That is, in the alpha 6 mode, the look-up table 61α selects a page determined by the upper 2 bits of the alpha signal and the lower 2 bits of the page selection register 102, and the alpha signal S is selected using the page.
Output α (FIG. 21 (C)). At this time, by using the upper 2 bits of the alpha signal for the page selection signal, the lower 6 bits in the image data of the alpha plane are used.
The look-up table 61α is accessed by a bit, thereby generating an alpha signal in the address space of addresses 0-63.

At this time, as shown in FIGS. 25 and 26,
Lucky table 6 selected in Alpha 6 mode
In the page of 1α, the data of the value 0 to the value 255 is output with respect to the address data of the address 0 to the address 63, so that even if the mode is switched, the same video signal processing device 20 is used. It is designed to be able to perform processing.

(4) Encoder In this embodiment, in the video graphic system 1, the processing format of the video signal can be selected, and the format of the color signal or the format of the luminance signal or the color difference signal is selected by the user. It is adapted to process video signals.

That is, in a normal image processing apparatus,
The video signal is processed in the form of a color signal. However, in this type of image processing, for example, when smoothing processing is performed, it is possible to generate a sharp image by smoothing only the luminance signal.

Therefore, in this embodiment, the processing format of the video signal can be selected by the user's selection, and the usability can be improved.

Therefore, as shown in FIG. 27, in the CPU board 16, a control signal is output to the graphic board 18 and the contents of the mode register 110 are updated to set the processing format in the graphic board 18. It is designed to be able to do. The graphic board 18 is configured to selectively output image data composed of red, blue, and green color signals, or image data composed of a luminance signal and a color difference signal.

In the video signal processing device 20, the image data output from the image memory 50 is transferred to the digital analog conversion circuit 74 via the combiner 69 (FIG. 5).
The encoder 7 converts the signal into a digital signal.
Output to 5. Therefore, in the encoder 75, the color signals SR, SG, SB of red, green, and blue or the luminance signal Y and the color difference signals RY and BY are input according to the processing format of the video graphics system 1. It

The conversion circuit 112 is composed of a matrix circuit, which allows the luminance signal Y and the color difference signals RY and B-.
For Y, the following equation

[Equation 1]

[Equation 2]

[Equation 3] The brightness signal Y and the color difference signals RY and B are calculated by performing a calculation process that is the reverse of the calculation process for creating the luminance signal and the color difference signal.
-Y is converted into a color signal.

The selector 114 includes the mode register 110.
When the video graphic system 1 processes image data in the color signal format, the color signal output from the digital-analog conversion circuit 74 is directly output in response to the switching signal output from the digital analog conversion circuit 74. On the other hand, when the video graphic system 1 processes image data in the format of the luminance signal and the color difference signal, the color signal output from the conversion circuit 112 is selectively output.

As a result, in the videographic system 1, the color signal can always be output to the display device 26 even when the image data processing format is the luminance signal or the color difference signal. Switching of the connection of 26 and the like can be omitted. Therefore, in the video graphic system 1, the processing format can be easily switched without switching the connection of the external device, and the usability can be improved accordingly.

Further, in this embodiment, the encoder 75 has the output signal S of the digital-analog conversion circuit 74.
V6 can be separately output, so that a color signal, a luminance signal, or a color difference signal can be output according to the processing format of the video graphics system 1. Therefore, in the video graphic system 1, the output signal SV6 can be connected to a display device as needed to drive the display device in the form of a color signal, a luminance signal, or a color difference signal, and the usability is improved accordingly. can do.

(5) Cursor control The computer main body 6 is adapted to be able to input a processing procedure through the display screen of the display device 8, and displays an image or the like to be processed through the display device 21.

That is, as shown in FIG. 28, the computer main body 6 displays a plurality of windows W1 to W4 on the display screen M1 of the display device 8 by superimposing them, and the user uses the mouse 12 to select predetermined windows W1 to W4. When the cursor is clicked together with Kassosol K, the window is displayed on the upper side. For this reason, the computer 6 takes in coordinate data via the mouse 12, divides the display screen M1 vertically and horizontally into 1080 × 1024 display areas, and moves the cursor to the corresponding display area based on the fetched coordinate data. It is designed to display K.

Further, in the computer 6, when the mouse 12 moves laterally to move the cursor K in the direction indicated by the arrow a to extend the display screen M1, the display of the cursor on the display screen M1 is stopped. To do. When the mouse 12 further moves to a predetermined area in this state, the computer body 6 outputs the coordinate data of the mouse 12 and the control signal to the CPU board 16.

In response to this, in the CPU board 16, the upper 2 bits of the alpha signal are switched in the display area determined by the coordinate data, whereby the cursor is displayed on the display screen M2 of the display device 21 using the above-mentioned display method. Display K1. Thus, in the videographic system 1, by setting the cursor K1 at a predetermined position, for example, the image processing subsequently designated is executed for the area designated by the cursor K1.

Therefore, in the CPU board 16, like the display screen M1, the display screen M2 is vertically and horizontally divided into 720 × 485 display areas, and the cursor is moved to the corresponding display area based on the coordinate data taken in. It is designed to display K1. Therefore, in the videographic system 1, the coordinate input area as shown in FIG. 28 is set for the coordinate data input by the mouse 12, whereby one coordinate input means is displayed on the display screen M1. , And M2 for easy operation.

By the way, when the mouse 12 is moved in this way to switch and use the coordinate input means, there are drawbacks that the moving operation is complicated and the operation requires time. Furthermore, after the display of the cursor K on the display screen M1 is stopped, until the cursor K1 is displayed on the display screen M2, the position designated by the mouse 12 cannot be visually confirmed, which causes a malfunction. ..

Therefore, in this embodiment, in addition to this, the processing procedure shown in FIG.
Switch the display of 1. That is, in the computer main body 6, when the power is turned on and the computer starts up from the initial state, the process moves from step SP1 to step SP2, and after performing various processes in response to the operation of the mouse 12 and the keyboard 10, the process proceeds to step SP3.

Here, the computer main body 6 displays the display screen M
It is determined whether or not the cursor jump button B1 in 1 is clicked, and if a negative result is obtained here, step S
Return to P2. That is, as shown in FIG. 30, in this embodiment, the computer main body 6 displays the function button window W4 on the display screen M1. For example, when the first function button F1 is operated, line drawing is performed. It is designed to switch to the mode of.

The computer body 6 has a window W
The cursor jump button B1 is displayed in the lower column of 4, and the mouse 12 is clicked by placing the cursor K on the cursor jump button B1 and clicking.
It is possible to determine whether or not the cursor jump button B1 has been clicked.

When the cursor jump button B1 is clicked here, an affirmative result is obtained in step SP3, so that the computer main body 6 moves to step SP4, where the display of the cursor K is stopped and the CPU board A predetermined control signal is output to 16. In response to this, on the CPU board 16, the cursor K1 is displayed in the central portion of the display screen M2.

As a result, in the video graphics system 1, the display can be switched from the cursor K to the cursor K1 by simply clicking the cursor jump button B1 without moving the mouse 12, so that an erroneous operation can be performed. This is done so that the cursor can be switched easily and surely by preventing it.

Subsequently, in the computer main body 6, the process proceeds to step SP5, where the coordinate data is fetched via the mouse 12, and the fetched coordinate data is transferred to the CPU board 16. As a result, in the CPU board 16, with the display position of the cursor K1 at the center of the screen as a reference,
The cursor K1 is moved in accordance with the coordinate data, so that various processes can be executed in the video graphics system 1 according to the position of the cursor K1.

Then, in the computer main body 6, the process proceeds to step SP6 and the right button 12B of the mouse 12 is pressed.
It is determined whether or not (FIG. 1) has been pressed. If a negative result is obtained here, the process returns to step SP5, whereas if a positive result is obtained, the process proceeds to step SP7. Here, the computer main body 6 outputs a control signal to the CPU board 16,
The display of the cursor K1 is canceled and the window W4 is displayed.
A cursor K is displayed at a predetermined position inside.

As a result, in the videographic system 1, the display can be switched from the cursor K1 to the cursor K simply by pressing the button 12B without moving the mouse 12 to the original position. There is. Therefore, the display of the cursors K and K1 can be switched easily and surely, and the usability of the video graphic system 1 can be improved by that much.

(6) Effects of the Embodiments According to the above configuration, the conversion circuit converts the luminance signal and the color difference signal into the color signal, and the output signal of the conversion circuit or the digital analog conversion circuit according to the contents of the mode register. By selectively outputting the output signal of, the color signal can always be output even when the image data processing format is a luminance signal or a color difference signal, which allows the processing format to be freely selected without switching the connection of the display device. The video graphic system 1 can be selected, and the usability of the video graphic system 1 can be improved accordingly.

(7) Other Embodiments In the above embodiments, the case where the four banks are divided into two systems and switched to form the image memory has been described, but the present invention is not limited to this, and various embodiments are possible. It can be widely applied when an image memory having a configuration is used.

Further, in the above-mentioned embodiment, the case where the color signal is converted into the analog signal and outputted is described. However, the present invention is not limited to this, and the digital signal may be outputted.

Further, in the above-mentioned embodiment, the case where the present invention is applied to the videographic system has been described, but the present invention is not limited to this and is widely applied to various image data processing devices such as animation devices. be able to.

[0119]

As described above, according to the present invention, based on the contents of the mode register, when the image data is output in the color signal format, the color signal is directly output and the image data is output as the luminance signal. When the color difference signal format is output, the color signal can be output by converting the color signal and outputting the color signal even when the image data processing format is the luminance signal or the color difference signal. The processing format can be freely switched by omitting the connection switching work such as the above, whereby an image data processing apparatus with improved usability can be obtained.

[Brief description of drawings]

FIG. 1 is a block diagram showing a video graphics system according to an embodiment of the present invention.

FIG. 2 is a block diagram showing the overall configuration.

FIG. 3 is a block diagram showing the CPU board.

FIG. 4 is a block diagram showing a graphic board.

FIG. 5 is a block diagram showing a video signal processing device.

FIG. 6 is a block diagram for explaining control of an image memory.

FIG. 7 is a block diagram showing an address generation circuit.

FIG. 8 is a schematic diagram for explaining a bank.

FIG. 9 is a schematic diagram for explaining switching of channels.

FIG. 10 is a schematic diagram showing a case where a display area extends over two banks.

FIG. 11 is a schematic diagram showing a case where a composite image is scrolled in the vertical direction.

FIG. 12 is a schematic diagram showing a case where a composite image is scrolled in the horizontal direction.

FIG. 13 is a schematic diagram showing a case in which a composite image is scrolled in an oblique direction.

FIG. 14 is a schematic diagram showing a case where a composite image spans four banks.

FIG. 15 is a signal waveform diagram showing a relationship between bank switching and a switching signal.

FIG. 16 is a schematic diagram showing a case where a composite image is scrolled vertically in one bank.

FIG. 17 is a schematic diagram showing a case where a composite image is scrolled horizontally in one bank.

FIG. 18 is a schematic diagram showing a case where a composite image is scrolled diagonally in one bank.

FIG. 19 is a block diagram for explaining the control of the look-up table.

FIG. 20 is a schematic diagram for explaining an Alpha 8 mode.

FIG. 21 is a schematic diagram for explaining an alpha 6 mode.

FIG. 22 is a schematic diagram used for explaining synthesis of a natural image.

FIG. 23 is a schematic diagram showing a general image data output method.

FIG. 24 is a schematic diagram for explaining a pallet animation.

FIG. 25 is a schematic diagram used for explaining a look-up table.

FIG. 26 is a characteristic curve diagram provided for explaining conversion of an alpha signal.

FIG. 27 is a block diagram showing an encoder.

FIG. 28 is a schematic diagram showing a display screen.

FIG. 29 is a flowchart for explaining switching of cursor display.

FIG. 30 is a schematic diagram for explaining a cursor jump button.

[Explanation of symbols]

1 ... Video graphic system, 2 ... Computer, 16 ... CPU board, 18 ... Graphic board, 20 ... Video signal processing device, 50 ... Image memory, 52 ... Memory controller, 54, 56, 58,
60, 62, 114 ... Selector, 61, 93, 94 ...
… Lookup table, 75 …… Encoder, 112
...... Conversion circuit.

Claims (1)

[Claims] 1. An image data processing device for processing image data in the selected processing format by selecting a processing format of red, blue, and green color signals or a processing format of luminance signals and color difference signals. The mode register that stores the mode of, the image memory that stores the image data of the color signals of red, blue, and green, or the image data of the luminance signal and the color difference signal corresponding to the above processing format, and the contents of the mode register. Accordingly, when the image data output from the image memory is the image data of the red, blue, and green color signals, the color signal of the image data is directly output, and the image data output from the image memory is An image data conversion circuit for converting image data of a luminance signal and a color difference signal into red, blue, and green color signals for output. Image data processing apparatus.