JPH052038A - Digital filter bank - Google Patents

Abstract

PURPOSE:To increase flexibility of a circuit and to meet various requests for performances with ease by combining a prefilter processor having a polyphase filter structure with a fast Fourier transform(FFT) processor executing an interstage pipeline operation. CONSTITUTION:A digital filter bank 10 is constructed of prefilters 30a to 30m (a polyphase filter) and FFT processors 40a to 40n formed to be a pipeline. The prefilters of a polyphase structure supply sequentially the data subjected to A/D conversion to be coefficients for computation set beforehand, so that an arithmetic processing be executed in proper amounts, and therefore no uselessness of hardware takes place. By increasing sets of the coefficients to be allocated, accordingly, the number of band-pass filters can be increased simply. An input analog signal X (f) is converted into a digital signal by an A/D converter 20 and then inputted to the filter bank 10, and the signal X (f) of a frequency axis is outputted as the result of filtering.

Description

Detailed Description of the Invention

[0001]

The present invention relates to digital filter banks used to measure the frequency spectrum of signals.

[0002]

2. Description of the Related Art As a general method of measuring a frequency spectrum, as shown in FIGS. 10 (a) and 10 (b), a plurality of analog bandpass filters are arranged in parallel and the power of the output signal of each filter is measured. There is a method (analog filter bank) or a method in which an analog signal is A / D converted and analyzed by an FFT (Fast Fourier Transform) processor as shown in FIG.

However, it is generally difficult to form an analog filter having good characteristics with a small amount of hardware, and since FFT is an analysis based on discrete data, high accuracy cannot be expected for a general waveform.

Therefore, in recent years, a digital filter bank having a structure in which a plurality of digital bandpass filters are arranged in parallel as shown in FIG. ..

In practice, this digital filter bank can be realized by using a pre-filter 50 and an FFT processor 60 as shown in FIG.

[0006]

The above-mentioned conventional digital filter bank has a problem that it is not flexible in structure. In other words, when you want to implement a filter bank according to cost or performance, such as when you need something that is expensive but has high performance (resolution or accuracy), or if you want low price and low performance, you can meet the individual requirements. Therefore, it is necessary to redesign the configurations of the prefilter and the FFT processor from the beginning. this is,
This is because the digital filter bank shown in FIG. 13 has one function in the entire configuration, and therefore it is necessary to review the entire configuration itself in order to change the characteristics. Such inflexibility is due to the fact that circuits are integrated into one chip, especially in ASICs.
It becomes a cause of hindering the application to the IC manufactured in response to the customer's demand such as.

Further, if an attempt is made to implement a high-performance prefilter and FFT processor on a single chip, there is a problem that the configuration becomes complicated and the cost becomes high.

The present invention has been made by paying attention to such a problem, and an object thereof is to enhance flexibility of a circuit (hardware) and to perform various performance (or The purpose of the present invention is to provide a digital filter bank that can easily meet the requirements of (cost) and that is suitable for IC implementation.

[0009]

The outline of the typical one of the present invention is as follows. That is, a digital filter bank is realized by combining a pre-filter processor having a polyphase filter structure and an FFT processor capable of performing pipeline operation between stages.

The polyphase digital filter structure has a structure in which coefficients for filtering operation are arranged in parallel, and a function is provided in which a common data input section sequentially and periodically distributes input data to each coefficient. .. Therefore, the A / D-converted input signal is distributed to each filter having a predetermined coefficient by the above-mentioned distribution function, sequentially multiplied by the coefficient, the result is accumulated, and the filtering output of the pre-filter processor is obtained. Is obtained.

The prefilter having such a polyphase structure is composed of, for example, a coefficient memory (RAM, ROM), a data memory, and an address counter (address control circuit), a multiplier, an accumulator, and a register group of these. ..

In this case, assuming that the number (resolution) of bandpass filters to be realized is n, the coefficient memory has n sets of coefficients necessary for producing each filter characteristic,
It is stored. In addition, the data memory is provided with a data storage area of n columns (or n rows) for accumulating data to be distributed to each coefficient set, and after input data is stored in this area in principle, It is output for calculation.

The address counter reads the coefficient and data from each memory by regularly changing the address so that each coefficient and data form a desired combination.

Such a structure is substantially a multiprocessor structure in which n prefilters (processors) arranged in parallel and m stages of pipelined FFT processors are combined.

[0015]

The pre-filter having a polyphase structure is for supplying the data, which has been A / D converted into a preset coefficient for calculation, sequentially to perform a calculation process without excess or deficiency, resulting in waste of hardware. Absent. Therefore, the number of bandpass filters can be easily increased by increasing the number of sets of coefficients to be distributed (or by preparing a plurality of such prefilters).

In response to the increase in the degree of parallelism of the pre-filter, the pre-filter and the FF are processed by pipelining the operation stage of the subsequent FFT to perform parallel processing.
Performance consistency with the T processor can also be ensured.

Therefore, if a plurality of prefilters (processors) having the same structure and an FFT processor are prepared,
You get performance that is commensurate with the number of processors you have. This makes it possible to easily realize filter banks according to various cost performances. Also, since it is only necessary to line up the same processors, it is relatively inexpensive.
A high performance digital filter bank can be realized.

Further, when considering the case where such a configuration is actually realized as an IC, the prefilter used in the filter bank of the present invention is a memory (ROM, RA).
M), a register, a multiplexer, an accumulator, and the like, the circuit elements that are generally used in the digital IC can be used for the configuration, so that the implementation is easy. Further, as described above, since the processors having the same configuration may be arranged, the layout design and the like are easy and are suitable for ASIC implementation. A programmable FFT processor that executes an arbitrary stage can also be easily realized by using a normal technique.

[0019]

Embodiments of the present invention will now be described with reference to the drawings. FIG. 1 is a diagram showing a basic configuration of a digital filter bank of the present invention.

The digital filter bank 10 of this embodiment is
Pre-filters 30a to 30n (constituting a polyphase filter PF) and a pipelined FFT processor
Input analog signal f (x)
Is converted into a digital signal by the A / D converter 20 and then input to the filter bank 10. As a result of the filtering, a signal X (f) on the frequency axis is output.

Consider a case where a bank having four bandpass filters as shown in FIG. 2A is realized by using such a configuration. Each bandpass filter has a characteristic as shown in FIG. 2B (BPF0 is substantially a lowpass filter).

The filter bank shown in FIG. 2 can be realized by the structure shown in FIG. 3, for example. In the prefilter of this example, h ₃ , h ₇ , and h ₁₁ are prepared as the BPF0 coefficients, h ₂ , h ₆ , and h ₁₀ are prepared as the BPF1 coefficients, and h ₁ and h are prepared as the BPF 2 coefficients. ₅ and h ₉ are prepared, and h ₀ , h ₄ and h ₈ are prepared as coefficients for the BPF ₃ . The data d0 to d11 and d1 are included in each coefficient.
2 ... are sequentially sorted and input.

[0023] For example, pre-filtering the output of the pre-filter for BPF0 (00), (04) _{is, (00) = h 11 ·} d0 + h 7 · d4 + h 3 · d8, (04) = h 11 · d4 + h 7 · d8 + h 3・ D12,
It is obtained by performing the operation.

In this example, the FFT processor (40a
~ 40n) are pipelined by sharing the processing for every two stages. FIG. 4 shows a specific configuration example (in particular, a specific configuration example of the polyphase filter PF) when the configuration of FIG. 3 is integrated into an IC. In this configuration example, the polyphase filter PF includes a coefficient RAM 300a (address circuits 100a, 200
read address is controlled by a), and data RA
M300b (a read address and a write address are controlled by the address circuits 100b and 200b), a register (I-Reg) for holding input data, a selector 500, registers MR1 and MR2, a multiplier 700, and a register
It has an 800, an accumulator 900, and a register 1000. The input data held in the register (I-Reg) is written in the data RAM 300b or sent to the secreter 500. Selector 500 is data RAM30
Data read from 0b or register (I-Reg)
The data sent from is selectively passed. Coefficient R
The coefficient output from the AM300a is temporarily stored in the register MR1.
Data held in the register MR2 and passed through the selector 500 is held in the register MR2, multiplied by the multiplier 700, and accumulated by the accumulator 900.

FIG. 5 shows the address control timing in the coefficient RAM 300a and the data RAM 300b and the data flow in the main part in the configuration of FIG. By thus regularly accessing the RAM, a pre-filter having a polyphase structure can be realized.

Next, pipelining between stages of the FFT processor 40 (FIG. 4) will be described with reference to FIGS. 6 (a) and 6 (b). For example, the two-stage pipeline processing as shown in FIG. 6A is performed in the FFT processor as shown in FIG.
It is realized by performing a butterfly operation as shown in (b).

The pre-filter having the polyphase structure is shown in FIG.
, Two pre-filter processors (A,
It can also be configured by combining B). The configuration of the coefficient RAM in the processors A and B is the same as that in the case of FIG. 4, and the data RAM is shown in FIGS. 8A and 8B, respectively.
Configure as follows. Address counter operation in processors A and B and R / W in data RAM
FIG. 9 shows (read / write) control and the flow of data in the main part. Such control can be easily realized by configuring an address generator using a counter and a gate.

[0028]

As described above, according to the present invention, the pre-filter has a polyphase filter structure, and this structure is realized as a structure suitable for multiprocessor by devising an address generation method in the coefficient RAM and the data RAM, In addition, the flexibility of the circuit (hardware) can be improved by using the pipelined FFT processor together.
There is an effect that various performance (or cost) requirements can be easily satisfied without completely modifying the circuit, and a digital filter bank suitable for IC implementation can be provided.

[Brief description of drawings]

FIG. 1 is a diagram showing a basic configuration of a digital filter bank of the present invention.

FIG. 2A shows a bank having four bandpass filters to be realized, and FIG. 2B shows characteristics of each bandpass filter (BPF0 is substantially a lowpass filter).

FIG. 3 is a diagram showing an implementation example of the digital filter bank of FIG.

FIG. 4 is a diagram showing a specific configuration example when the configuration of FIG. 3 is integrated into an IC.

5 is a diagram showing address control timings in a coefficient RAM 300a and a data RAM 300b and data flows in main parts in the configuration of FIG.

FIG. 6 is a diagram for explaining pipelining between stages of the FFT processor 40 (FIG. 4), (a)
FIG. 3 is a diagram showing a two-stage pipeline process, and FIG. 4B is a diagram showing the contents of butterfly operation for realizing the process of FIG.

FIG. 7 is a diagram showing an example in which a prefilter is configured by using two processors A and B.

8A and 8B are diagrams showing a configuration of a data RAM in processors A and B of FIG. 7, respectively.

9 is a diagram showing an operation of an address counter and R / W (read / write) control in a data RAM in processors A and B of FIG. 7, and a data flow in a main part.

[FIG. 10] (a) is a general frequency spectrum measurement method, in which a plurality of analog bandpass filters are arranged in parallel and the power of the output signal of each filter is measured (analog filter bank). It is a figure for explaining and (b) is a figure showing the characteristic of each bandpass filter.

FIG. 11 is a diagram for explaining a general method of measuring a frequency spectrum, which is a method of A / D converting an analog signal and analyzing the analog signal by an FFT (Fast Fourier Transform) processor.

FIG. 12 is a diagram for explaining a digital filter bank having a structure in which a plurality of digital bandpass filters are arranged in parallel.

13 is a diagram showing an example of an actual configuration of the digital filter bank of FIG.

[Explanation of symbols]

10 Digital filter bank 20 A / D converter 30a-30n Poly-phase filter (PF) pre-filter 40a-40n FFT processor 300a Coefficient RAM 300b Data RAM 500 Selector 700 Multiplier 900 Accumulator

Claims (1)

Claim: What is claimed is: 1. A digital filter bank comprising a pre-filter processor having a polyphase filter structure and an FFT processor capable of performing an inter-stage pipeline operation, the pre-filter processor. Is a data memory (300b) that stores input data
And the address control circuit of this data memory (100b, 200b)
And a coefficient memory (300a) for storing coefficients for digital filtering operation, an address control circuit (100a, 200a) of this coefficient memory, and data output from the data memory (300b) or newly input data. And a multiplier (700) for multiplying the coefficient output from the coefficient memory (300a), and an accumulator (900) for cumulatively adding the multiplication output of the multiplier (700). And a digital filter bank.