JP2009074922A - Signal analyzer and apd measuring device using the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a technology capable of rapidly filtering many desired frequency components and executing APD measurement while possessing a filter bank that can be constituted easily. <P>SOLUTION: A hardware constitution is clearly divided into a data storage section 230 for successively capturing data timewise, a filter coefficient memory 260 for generating filter coefficients, a filter operation section 240 for operation based on the storage section and the memory, and a timing generation section 280 for making the data storage section, the filter coefficient memory, and the filter operation section in timing. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention is a signal analysis device that analyzes and measures the frequency components of a received signal, and the probability that the size of each analyzed frequency component exceeds a predetermined threshold (amplitude probability distribution, or simply referred to as a time rate). (Hereinafter referred to as “APD”). In particular, the present invention relates to a technique in which a filter for analyzing a frequency component is configured by hardware.

  The APD measurement technique has conventionally been known. For example, there is a technique disclosed in Patent Document 1 that measures APD with high amplitude resolution and time resolution, and there is a technique disclosed in Patent Document 2 that is applied to a spectrum analyzer or the like.

  On the other hand, recently, there has been a demand for a communication system to simultaneously measure APDs of a plurality of predetermined frequency components in parallel. For example, as described in Non-Patent Document 1, a standard for digital terrestrial broadcasting is defined as an ARIB standard by the Radio Industries Association (ARIB), and a modulation method based on OFDM (Orthogonal Frequency Division Multiplex Operation Mode) is defined. In this OFDM system, transmission data is divided into thousands of low-speed data in a predetermined band, and digital modulation is performed. For example, the predetermined band is 5.6 MHz, and the transmission data is divided into 1 KHz carrier units, and is digitally modulated in a total of 5,600 lines.

Therefore, it is desirable for the APD measurement in the OFDM system to measure the APD of each frequency component by analyzing the frequency of the signal component every 1 KHz. Specifically, like the APD measuring apparatus shown in FIG. 9, the signal to be measured is sampled in analog signal input by the data converter 100 in units of a predetermined amplitude and converted into digital data, and the component detector 200A Are distributed by K band-pass filters (BPF1 to BPFK) constituting a filter bank, and square-detected by K detectors DET1 to DETK connected to the filter banks and output as amplitude values of respective components. The The output of each frequency component of the component detector 200A is logarithmically compressed by each converter LOG1 to LOGK of the LOG converter 300. That is, it is converted into dBm units. Then, the amplitude probability is obtained by each individual APD1 to individual APDK of the individual APD unit 400. Each of the individual APD1 to individual APDK can be configured by the APD described in Patent Documents 1 and 2.
Then, the individual APD display control unit 500 causes the display unit 600 to display the amplitude probability distribution in coordinates with the amplitude of each frequency component as the vertical axis and the probability as the horizontal axis. There are various display formats and the like, and Patent Document 2 also shows an example.

  FIG. 10 shows a typical example of filter bank characteristics (each bandpass filter) on the frequency axis. FIG. 10 partially shows frequency characteristics for 12 channels ch1 to ch12 in FIG.

  By the way, depending on the program broadcast by the modulation of the OFDM system adopted in the above terrestrial digital broadcasting, the frequency component of each carrier is not used with the same weight or with uniform weighting. , Center frequency, and bandwidth are used in various ways.

  For example, in FIG. 10, the program A uses ch3, 4, 5, 6 (the weights of other ch1, 2, 7, 8, 9,... Are 0), and the program B is ch2, ch6, ch13. .. (The frequency components and weights used so that the weights of the other channels 1, 3 to 5, 7 to 12... Are 0) have various modes.

Thus, for example, if the APD measurement of noise on the transmission line is performed according to each program, the filter bank becomes a large scale almost proportional to the number of programs. For example, if the number of programs is N, the following scale is required.
N × band × (filter bank configuration scale + detector DET configuration scale + APD configuration scale)
Therefore, even if the number of programs that can be handled is reduced and a filter bank corresponding to the programs is provided as an option whenever necessary, the work is difficult.

  On the other hand, although the field in which the filter bank is used is different, there is a technique disclosed in Patent Document 3 as a filter bank that is simple, has a fast processing time, and aims to detect a highly accurate frequency. This technique is theoretically achieved by performing convolution integration with the impulse response of the polyphase filter obtained by so-called polyphase decomposition and the signal distributed by the switch, and Fourier transforming the result. Specifically, in Patent Document 3, instantaneous data is captured by a serially connected shift register. The output of each shift register is multiplied by the transfer function of the filter that is also sent serially, and the result is accumulated for each even data and the result accumulated for each odd data is converted into a discrete Fourier transform (DFT) unit by the shift register. To acquire frequency domain data.

Japanese Patent No. 3156152 Japanese Patent No. 3374154 JP-A-11-160422 Toshiba Review VOL. 58 No. 12 (2003), p2-6.

  As described above, in the measurement of APD or the like, the frequency band required by a program differs depending on the modulation method, and particularly in the OFDM modulation method, and therefore the configuration of the filter bank is also different. Therefore, it is desirable to have a filter bank that can be configured with various combinations of frequency bands to be filtered easily and in various ways. Of course, since the number of filters is large, simplification and high-speed processing are desired.

  An object of the present invention is to provide a technique capable of quickly filtering and extracting many desired frequency components and performing APD measurement with a filter bank that can be easily configured.

  In order to achieve the object of the present invention, in the present invention, a data storage unit that sequentially captures data in time, a filter coefficient memory unit that generates filter coefficients, a calculation unit that calculates based on them, a twiddle factor memory, and a DFT calculation Each component, such as a timing generation unit that synchronizes timing with each other, has a hardware configuration that is as independent as possible.

  Here, terms are defined. The “amplitude probability distribution” (APD) is the rate at which an amplitude of a specific magnitude of a received signal occurs within a predetermined time. This APD measurement is useful for noise analysis. However, in the present invention, the input signal to be measured is not limited to noise. This is because a signal having a plurality of frequency components can be analyzed and the probability can be measured.

In order to achieve the above object, the invention of claim 1 is characterized in that an input signal is sampled and output as digital data, and a data converter (100) and data XQ output from the data converter are orthogonal to each other. , XI separating means (210) and the data XQ and XI are sequentially stored in time series as M data as one data period, and sequentially generated address signals (n = 0) ,..., N−1) every N times M / N = H pieces of data XQ _{(h, n)} , XI _{(h, n,)} {(h, n) is (h × N + n) H: 0 to H-1. } At the same time, and a number of filter coefficients F corresponding to each of the M pieces of data are stored in advance in order to limit the bandwidth to K frequency bands. A filter coefficient memory (260) for simultaneously outputting H filter coefficients F _{(h, n)} , a filter operation unit (240) for performing the next convolution operation,
_H-1
[YQ] _n = Σ XQ _{(h, n)} × F _{(h, n)}
^{h = 0}
_H-1
[YI] _n = Σ XI _{(h, n)} × F _{(h, n)}
^{h = 0}
Here, the subscript (h, n): (h × N + n) -th is shown.
A DFT operation unit (250) which receives data [YQ] _n and “YI] _n output from the filter operation unit and obtains frequency components orthogonal to each other for each of the K frequency bands;
And a detector (260) for determining the magnitude of each frequency component based on mutually orthogonal frequency components in each frequency band determined by the DFT operation unit.

According to a second aspect of the present invention, in the first aspect of the present invention, the rotation that stores in advance the values of the following twiddle factors Lc (n, k) and Ls (n, k) so as to be readable by the address signal. A factor memory (270);
Lc (n, k) = cos (2πj _n × j _k / N),
Ls (n, k) = sin (2πj _n × j _k / N)
However, a constant determined with respect to jn: n, a constant determined with respect to jk: k. The DFT operation unit receives the operation results [YQ] _n and [YI] _n from the filter operation unit, and receives the kth frequency. An arithmetic functional element that obtains frequency components SUM _kQ and SUM _kI orthogonal to the band (k: 1 to K) by the following DFT computation and obtains each component from k to 1 to N;
W _kQ (n) = [YQ] _n × Lc (n, k) + [YI] _n × Ls (n, k),
_N-1
SUM _kQ = Σ W _kQ (n)
^{n = 0}
W _kI (n) = [YI] _n × Lc (n, k) + [YQ] _n × Ls (n, k),
_N-1
SUM _kI = Σ W _kI (n)
^{n = 0}
The detection unit includes an addition function element that calculates a square sum of the frequency components SUM _kQ and SUM _kI obtained by the DFT operation unit for each frequency band k.

According to a third aspect of the present invention, in the second aspect of the present invention, the data storage unit includes H memories each having N addresses of address numbers n = 0 to N−1, The nth data at the address of each of H memories ((h × N + n), n when h = 0, N + n when h = 1,..., H × N + n when h = H are the same Reading is enabled by an address signal, and the data XQ and XI are sequentially stored from the first address of the first memory to the Hth Nth address,
The filter operation unit and the DFT operation unit obtain each value of the [YQ] _n , [YI] _n , W _kQ (n), and W _kI (n) for each address signal, and obtain the obtained W _kQ (n) and W _kI (n) are integrated to obtain the SUM _kQ and SUM _kI .

A data converter (100) that samples an input signal and outputs it as digital data, a separation means (210) that separates data XQ output from the data converter into orthogonal data XQ and XI, and the data XQ, Each of XI is sequentially stored as M data in time series as one data period, and every N address signals (n = 0, 1,..., N−1) sequentially generated. M / N = H pieces of data XQ _{(h, n)} , XI _{(h, n,)} {(h, n) represents (h × N + n), h: 0 to H−1. } At the same time, and a number of filter coefficients F corresponding to each of the M pieces of data are stored in advance in order to limit the band to K frequency bands, and every N pieces, M / A filter coefficient memory (260 ₎ for simultaneously outputting N = H filter coefficients F _{(h, n)} , a filter operation unit (240) for performing the next convolution operation from n = 0 to N−1,
_H-1
[YQ] _n = Σ XQ _{(h, n)} × F _{(h, n)}
^{h = 0}
_H-1
[YI] _n = Σ XI _{(h, n)} × F _{(h, n)}
^{h = 0}
Here, the subscript (h, n): (h × N + n) -th is shown.
The data [YQ] _n and “YI] _n output from the filter calculation unit are received, the calculation results [YQ] _n and [YI] _n from the filter calculation unit are received, and the kth frequency band (k : DFT operation unit (250) having operation functional elements for obtaining frequency components SUM _kQ and SUM _kI orthogonal to each other with respect to 1 to K) by the following DFT operation and obtaining each component of k from 1 to N;
W _kQ (n) = [YQ] _n × Lc (n, k) + [YI] _n × Ls (n, k),
_N-1
SUM _kQ = Σ W _kQ (n)
^{n = 0}
W _kI (n) = [YI] _n × Lc (n, k) + [YQ] _n × Ls (n, k),
_N-1
SUM _kI = Σ W _kI (n)
^{n = 0}
Where Lc (n, k) = cos (2πj _n × j _k / N),
Ls (n, k) = sin (2πj _n × j _k / N)
j _n : Constant determined for _n , j _k : Constant determined for k Detection unit (290 for determining the magnitude of each frequency component based on mutually orthogonal frequency components in each frequency band determined by the DFT operation unit (290) )When,
And an APD (400a) that synthesizes the magnitudes of the frequency components output from the detection unit and obtains a probability based on the frequency of occurrence of the synthesized amplitude after synthesis.

  According to the present invention, in response to the address signal, the reading from the data from the data storage unit, the reading of the filter coefficient from the filter coefficient storage unit, and the operation of the filter calculation unit are performed almost independently. In other words, the reading of the coefficient (factor) value for extracting the frequency from the twiddle factor memory and the operation of the DFT operation unit operate in parallel almost independently in response to the address signal. Therefore, a large number of frequency components can be filtered quickly with high resolution. In addition, the coefficient of each memory and each circuit can be easily changed according to a desired frequency channel and a desired frequency component in each frequency channel.

  Embodiments according to the present invention will be described with reference to the drawings. FIG. 1 is a diagram showing an embodiment of a signal analyzing apparatus of the present invention. FIG. 2 is a diagram for explaining details of the data storage unit, the filter calculation unit, and the filter coefficient memory of FIG. FIG. 3 is a diagram for explaining the details of the DFT operation unit and the twiddle factor memory of FIG. FIG. 4 shows a specific example of the separating means and detection unit of FIG. 1, and an equivalent circuit of a filter bank (bandpass filter group) composed of the data storage unit, the filter calculation unit, and the DFT calculation unit of FIG. FIG. FIG. 5 is a diagram for explaining the contents of each memory in FIG. 1 and the operation timing of each unit. FIG. 6 is a diagram for explaining an operation flow based on FIG. FIG. 7 is a diagram for explaining an embodiment of an APD measuring apparatus. FIG. 8 is a diagram for explaining the operation of the APD.

[Overall configuration / operation]
In FIG. 1, the data converter 100 is configured by an A / D converter for converting an analog signal into digital data. That is, the analog input signal f _IN (frequency band is ± B / 2) is received, and sampling is performed with fineness of the level width ΔL (there is a threshold corresponding to this fineness) with a clock having a period from the timing generation unit. (Sampling) and convert to digital data.

  The component detection unit 200B after the data conversion unit 100 in FIG. 1 is a technique that replaces the component detection unit 200A of FIG. 9 that is a conventional technique, and detects the frequency component of each frequency channel by the configuration of the filter according to the present invention. By doing so, the input signal is analyzed. This configuration will be described below.

The orthogonal separation unit 210 of FIG. 1, the data X of the digitized input signal f _IN is a component of the phase orthogonal to each other, is divided into data XI data XQ and the I component of the Q component. FIG. 4A shows the orthogonal separation unit 210 modeled in an analog manner. (In practice, it is equivalently implemented by digital processing). Although an analog explanation, the input signal _{f IN} is input mixer unit 201a, to 201b. On the other hand, the frequency generation unit 203 generates a frequency signal f _IF having substantially the same frequency as the input signal f _IN, and the phase shifter 202 that receives this generates two frequency signals f _IF whose phases are orthogonal to each other. Send to mixer means 201a, 201b. Mixer means 201a, from 201b, 2 two quadrature signals I and Q components, and Iαsin2πfb, Qαcos2πfb, however, the frequency _{fb = f} IN -f _IF (band B / 2) is output. In other words, into data XQ data XI corresponding to the two low-frequency (fb) signals that are orthogonal digital data corresponding to the input signal f _IN. The data XQ and the data XI are sequentially stored in the Q memory 230Q and the I memory 230I of the data storage unit 230, respectively, and input to the filter banks. In other words, the filter bank (FIG. 4A is an equivalent circuit of the bandpass filters BPF1 to BPFK group) including the data storage unit 230, the filter operation unit 240, and the DFT operation unit 250 of FIG. The Q component (SUM _kQ ) and the I component that have passed through the filter for each frequency channel (hereinafter sometimes referred to as “ch”. The k channel may also be referred to as “kch” or “chk”). (SUM _kI ) is output. Then, for example, when k = 1 (1ch) is described, as shown in FIG. 4B, each of the Q component (SUM _kQ ) and the I component (SUM _kI ) of the square means 291a and 291b of DET1 is used. Each of them squares and outputs, and the adder 292 receives and adds them (vector sum), and outputs the addition result as the magnitude of the frequency component of 1ch. The same applies to k = 2 to Kch.

[Configuration and operation of filter bank]
The filter bank includes the data storage unit 230, the filter operation unit 240, the DFT operation unit 250, the filter coefficient memory 260, the twiddle factor memory 270, and the timing of each control signal including an address signal in synchronization with the system clock in FIG. And a timing generation unit 280 that outputs them together. In particular, the data storage unit 230, the filter calculation unit 240, and the DFT calculation unit 250 have the same configuration in which two operations are performed for each of the Q component and the I component orthogonal components. Therefore, the following description will focus on the configuration and operation on one Q component side.

  FIG. 2 is a diagram showing internal functional configurations of the Q memory 230Q of the data storage unit 230, the Q calculation unit 240Q of the filter calculation unit 240, and the filter coefficient memory 260, and FIG. 5 shows data and operation timings handled by them. FIG. 2 and 5 will be described.

  In the following specific description, as an example, a case where the number of filter taps is four for data sampled by the data converter 100 with a clock of 100 MHz and a sampling frequency of 10 MHz will be described.

  As shown in FIG. 5, the Q memory 230Q stores 10 pieces of shifters h3 to h0 (corresponding to the number of taps: H) in order (corresponding to the ratio between the clock and the sampling frequency) as shown in FIG. . That is, as shown in FIG. 1, shifters h3 to h0 are serially provided, and shifter h3 has data x39 to x30 at 10 addresses (the numerical value following x indicates the order in which data XQ is stored. The larger numerical value is newer. The shifter h2 sequentially stores X29 to X20, the shifter h1 from x19 to x10, and the shifter h0 from x9 to x0. 40 pieces of data from X39 to x0 are stored as one cycle (referred to as “one data cycle”) for the following calculation processing. Each shifter has 10 consecutive identical addresses specified by the address counter shown in item number 1 (the number is the leftmost numerical value) in FIG. 5, and each shifter has an address counter value n (in FIG. 5). , N receives an address signal (hereinafter sometimes referred to as “address signal n”) corresponding to 1 to 10), and simultaneously outputs the data of the corresponding address in parallel.

If this is expressed in a generalized form, it can be said as follows. The Q memory 230Q sequentially stores time-sequential M data XQ as one data period, and M / N = every N address signals of n = 0, 1,..., N−1. H pieces of data XQ _{(h, n)} ((h, n) is an order (h × N + n), where h is an order in which each shifter is specified as a variable, and takes a value of 0 to H−1. .) At the same time. The address signal n is sequentially sent from the timing generator 280 in synchronization with the clock. In this example, M = 40 (x39 to x0), N = 10 (10 addresses), and n represents each address value from 0 to N−1 from the numerical examples of FIGS. 2 and 5. In other words, it has H shifters having N addresses, and stores in order from the first address of h = 1st shifter to the Nth address of h = Hth shifter. N-th ((h × N + n) data of the address value of each memory, that is, n of the address is shifter h0 (h = 0), N + n of shifter h1 (h = 1),..., Shifter hH (h = H) can be read by the same address signal.

  The twiddle factor memory 270 has coefficient memories 271 to 274 corresponding to four shifters as shown in FIG. 1, and each coefficient memory is divided into one data period as shown in item numbers 7 to 10 in FIG. The band pass filter coefficients (f39 to f0) corresponding to the minute data (XQ39 to XQ0) are stored. As the band pass filter coefficient, a coefficient having a frequency-amplitude characteristic of a desired band pass filter is stored in advance. In general, since the characteristics of the Gaussian distribution type are used for frequency analysis and APD, the Gaussian distribution type coefficients are stored in this example. Therefore, as shown in FIG. 5, filter coefficients f9 to f0 corresponding to the data XQ9 to XQ0 are stored in the coefficient memory 271 and filter coefficients f19 to f1 corresponding to the data XQ19 to XQ10 are stored in the coefficient memory 273. Are the filter coefficients f29 to f20 corresponding to the data x29 to x20, and the filter coefficients f39 to f30 corresponding to the data XQ39 to XQ30 are respectively in the coefficient memory 274, and the same address counter n = 9, 8,. , 0 are stored so as to be readable by an address signal corresponding to each value.

  The reading of the data XQ from the Q memory 230Q by the address signal n and the reading of the filter coefficient f value from the twiddle factor memory 270 are performed, for example, as indicated by a dotted line in FIG. For example, the data XQ0, XQ10, XQ20, and XQ30 of the shifters h0 to h3 and the coefficients f0, f10, f20, and f30 of the coefficient memories 271 to 274 are simultaneously read by the address signal of the address counter n = 0, and the Q calculation unit 240Q is input. Thereafter, the address counters n = 1, 2,... 9 are similarly read. That is, for the shifter number (order) h (h = 0, 1, 2, 3 in FIG. 1), data having a relationship of h × N + n and filter coefficients are simultaneously read.

  The Q calculation unit 240Q includes a Q multiplier 241 and a Q adder 242. The Q multiplier 241 has four adders 241a to 241d. The adder 241a multiplies the output of the shifter h0 read by the same address signal n and the output of the coefficient memory 271, and the adder 241b multiplies the output of the shifter h1 read by the same address signal n and the output of the coefficient memory 272. The adder 241c multiplies the output of the shifter h2 read by the same address signal n and the output of the coefficient memory 273, and the adder 241d multiplies the output of the shifter h3 read by the same address signal n and the output of the coefficient memory 274, The Q adder 242 includes adders 242a to 242c, adds all the outputs of the Q multiplier, and outputs a total value for each address signal n.

For example, as shown in the item numbers 11 to 15 of FIG. 5, the outputs XQ0, XQ10, XQ20, and XQ30 of each shifter output by the address signal 0 (address counter 0) and the filter coefficients f0, f10, f20, and f30 are as follows. Calculate as follows.
The output of the Q multiplier 241 is shown as follows for each shifter h = 0, 1, 2, 3.
[YQ] ₀ = XQ0 × f0,
[YQ] ₁ = XQ10 × f10
[YQ] ₂ = XQ20 × f30
[YQ] ₃ = XQ30 × f30
The output of the Q adder 242 outputs the following total value for the address signal n = 0.
[YQ] _{n = 0} = [YQ] ₀ + [YQ] ₁ + [YQ] ₂ + [YQ] ₃

When generalized, the output [YQ] _n of the Q calculation unit 240Q calculated for h = 0 to H-1 for each address signal n can be expressed as the following convolution calculation.
_H-1
[YQ] _n = Σ XQ _{(h, n)} × f _{(h, n)}
^{h = 0}
Here, the subscript (h, n): (h × N + n) -th is shown.
Similarly, the output [YI] _n of the I operation unit 240I is expressed as follows.
_H-1
[YI] _n = Σ XI _{(h, n)} × f _{(h, n)}
^{h = 0}

  Note that the cycle of the memory enable timing signal indicated by item number 2 in FIG. 5 indicates a calculation cycle for one data cycle. Therefore, one calculation cycle is formed by the address counters 0 to 9, and the next calculation cycle starts from the next address counter 0. At this time, the Q memory 230Q discards the data x0 which was the oldest data in the previous calculation cycle, puts the latest data x40, shifts the whole, and stores x40 to x1 (see items 3 to 6 in FIG. 5). ) Thereafter, the same calculation as the previous calculation cycle is performed, and thereafter this is repeated.

The twiddle factor memory 270 is a twiddle factor Ls (n, k) = sin (2πj _n × j as a frequency component extraction coefficient for each address signal n for the desired k = 1 to K frequency channels to be obtained. _k / N) and the twiddle factor Lc (n, k) = cos (2πj _n × j _k / N) are calculated and stored (i.e., k, in order to distinguish the former Ls as the “sine function value”, The latter Lc is sometimes referred to as a “cosine function value”.), And is stored so as to be readable by specifying (n, k). Here, j _k is a desired value that determines the frequency. In a simple example, j _k = k, that is, j ₁ = 1, j ₂ = 2 for k = 1, 2,... ... it may be a _j K = K. Similarly, the frequency element j _n may be j _n = n, that is, j ₁ = 1, j ₂ = 2... J _N = N. The set value can be set according to a desired frequency. In any case, a value (2πj _n × j _k / N) in sin and cos indicates N frequency components in the frequency band of the k channel (k = 1 to N). The frequency elements j _k and j _n are preferably set selectively from the desired frequency and a circuit configuration that is easy to configure. Further, the present invention is configured so as to easily meet the demand for such a selective setting (see FIG. 3 and its description below).

DFT calculation unit 250, a QDFT calculation unit 250Q1~250Qk performing _ch 1 operations to CH _k component of the Q component side, and IDFT calculation unit 250I1~250Ik performing _ch 1 operations to CH _k min of the I component side Have. FIG. 3 shows a detailed configuration example when obtaining the frequency components (K = 5) of 5ch. Each of the QDFT operation units 250Q1 to 250QK includes a multiplier 251, a multiplier 252, an adder 253, and an accumulator 254, as representatively shown in the QDFT operation unit 250Q1 of FIG. (However, 3ch does not have multipliers 251 and 252 and adder 253. The reason will be described later.)
Here, the calculation on the Q component side will be mainly described, and the difference from the calculation on the I component side will be described.

The multipliers 251 and 252 and the adder 253 in the QDFT operation units 250Q1 to 250QK are operated on the address signal n from the filter operation unit 240 at any time [YQ] _n , [YI] _n , and the twiddle factor memory 270. W _kQ (n) is obtained by receiving the twiddle factors Lc (n, k) and Ls (n, k) from the above and performing the next DFT (discrete Fourier transform) operation.
W _kQ (n) = [YQ] _n × Lc (n, k) + [YI] _n × Ls (n, k),
However, the twiddle factor Ls (n, k) = sin (2πj _n × j _k / N)
Rotation factor Lc (n, k) = cos (2πj _n × j _k / N)
Each accumulator 254 sets the value of W _kQ (n) from address signal n = 0 to N−1 for each chk (k = 1 to H, FIG. 3 H = 5) as follows: Accumulate and obtain SUM _kQ as a result.
_N-1
SUM _kQ = Σ W _kQ (n)
^{n = 0}
This SUM _kQ outputs one value for each channel in one calculation cycle.

Similarly, the IDFT arithmetic units 250I1 to 250Ik obtain the next W _kQ (n) and further obtain the accumulation result SUM _kI .
W _kI (n) = [YI] _n × Lc (n, k) + [YQ] _n × Ls (n, k),
_N-1
SUM _kI = Σ W _kI (n)
^{n = 0}
In the calculation of W _kI (n), the partner that multiplies Lc (n, k) and the partner that multiplies Ls (n, k) are changed compared to the calculation of W _kQ (n).

The process of _obtaining W _1Q (n), W _1I (n), SUM _1Q , and SUM _1I for ch1 (k = 1) is shown from item numbers 18 to 25 in FIG.

  In FIG. 5, the reset signal is shown in item number 26, and the data holding timing (data update timing) is shown in item number 27. The cycle of the reset signal is a so-called calculation cycle. An operation based on the data is performed. Then, with this reset signal, each accumulator 254 is reset, outputs an accumulation result for the previous period, and starts accumulation in a new period.

In the example of FIG. 3, in the example of the number of channels H = 5, the frequency extraction coefficients Ls (n, k) and Lc (n, k) corresponding to the channels ch1 to ch5 are _represented by j ₁ = − 2, j ₂ = −1, j ₃ = 0, j ₄ = 1, and j ₅ = 2. Therefore, in ch3, Ls (n, 3) = sin (0) = 0 and Lc (n, 3) = cos (0) = 1, so that W _3Q (n) = [YQ] _n , W _3I ( n) = [YI] It is obtained as _n . That is, in CH3, instead of the multipliers 251 and 252 and the adder 253, [YQ] _n and [YI] _n are passed through to simplify and effectively achieve the calculation. In this way, it is possible to set frequency elements j _k and j _n in consideration of a desired frequency and circuit configuration.

In FIG. 1, the detector 290 includes detectors DET1 to DETK in accordance with the number K of channels. Each detector DET squares and outputs each of the Q component (SUM _kQ ) and the I component (SUM _kI ) as shown in FIG. 4B by the square means 291a and 291b, and the adder 292 These are received and added (vector sum), and the addition result is output as the magnitude of the frequency component of each channel. The same detection operation is performed over each channel of k = 1 to K, and each ch component is output.

  FIG. 6 shows the calculation process of each part constituting the filter bank. Some of them overlap with the above, but will be described in the order of calculation.

Step S1: The timing generator 280 receives M pieces of data Xm (where m = T to T + M−1) input in the Tth data cycle, and a data storage unit having N common addresses for each of the H shifters. 230 is stored in a distributed manner. At this time, the address counter (address signal) n = 0, and the parameters SUM _kQ and SUM _kI indicating the total value are initially set to 0.

Step S2: The timing generator 280 sends the address signal n = 0, reads the data XQ0, XQ10, XQ20, XQ30 from the data storage 230, reads f0, f10, f20, f30 from the filter coefficient memory 60, and filters The calculation unit 240 performs the next convolution calculation.
General formula
_H-1
[YQ] _n = Σ XQ _{(h, n)} × f _{(h, n)}
^{h = 0}
Here, the subscript (h, n): (h × N + n) -th is shown.
[YQ] _{n = 0} is obtained as follows.
[YQ] _{n = 0} = XQ0 × f0 + XQ10 × f10 + XQ20 × f20 + XQ30 × f30
Similarly, [YI] _{n = 0} is obtained as follows.
[YI] _{n = 0} = XI0 × f0 + XI10 × f10 + XI20 × f20 + XI30 × f30

  Step S3: Steps S3-1 to S3-K are performed in parallel with step S3-1 and the channel value k being changed in parallel. Below, step S3-1 is demonstrated.

Step S3-1a: The timing generator 280 reads the twiddle factor corresponding to the address signals n = 0 and ch1 (k = 1) from the twiddle factor memory 270, and causes the DFT calculator 250Q1 to execute the next DFT operation.
W _1Q (0) = [YQ] ₀ × Lc (0, k) + [YI] ₀ × Ls (0, k),
However, the twiddle factor Ls (n, k) = sin (2πj ₁ × j _k / N)
Rotation factor Lc (n, k) = cos (2πj ₁ × j _k / N)
Similarly, the IDFT calculation unit 250I1 calculates the next W _1I (n).
W _1I (0) = [YI] ₀ × Lc (0, k) + [YQ] ₀ × Ls (0, k),

Step S3-1b: The accumulator 254 performs the following processing for each ch1 and stores it.
SUM _1Q = SUM _1Q + W _kQ (0)
SUM _1I = SUM _1I + W _kI (0)
However, each initial value of SUM _1Q and SUM _1I (when n = 0) is 0.
This is performed for all K channels up to step S3-K. And SUM _1Q ~
SUM _KQ and SUM _{1I to} SUM _KI are obtained.

Step S4: The next timing generator 280 receives the processing of the accumulator 254, determines whether n = N−1, and since n = 1, causes the processing of Step S2 and Step S3 to be performed. That is, hereinafter, calculation is performed for all channels from n = 2 to n = N−1.
Step S5:
Then, when n = N−1, the accumulator 254, for example, for ch = 1 (k = 1),
SUM _1Q = W _1Q (0) + ... + W _1Q (N)
SUM _1I = W _kI (0) + ... + W _1I (N)
And for each channel.

Step S6:
In step 5 above, accumulator 254
SUM _{1Q to} SUM _KQ, SUM _{1I to} SUM _KI
Is output, the timing generation unit 280 starts calculation of the next calculation cycle from step 1 with T = T + 1. The next calculation is performed on data of m = T + 1 to T + M.

[APD measurement apparatus embodiment]
FIG. 7 shows an embodiment of the APD measuring apparatus. This is obtained by replacing the component detection unit 200A having the configuration of FIG. 9 which is the conventional technology with the component detection unit 200B of FIG. 1 of the present invention. 7 and 9 are the same in the operation of the functional configuration blocks with the same reference numerals.

The individual APD unit 400 in FIG. 7 is also a conventional technique, but will be briefly described below. The individual APD unit 400 determines the amplitude probability of the digital data converted by the data conversion unit 100 by sampling (sampling) the input signal _fIN with a clock with a fineness of the level width ΔL and performing SPR (International Radio Interference Special Committee). ) Rounded to the accuracy specified in).

Specifically, the individual APD unit 400 is a measurement unit that measures the amplitude probability (distribution) from the logarithmically converted amplitude value, and includes individual APDs 1 to K. As a detailed example, the schematic configuration is shown in FIG. In Figure 7, represents logarithmically converted is input data, so that is easier data from each LOG1~K and D (i.e. amplitude), as this value corresponds to the address e of the memory 410, and the data D ^e To express. When the memory 410 is accessed by the data ^{D e,} the data converter 420 is data ^G r-1 have been stored in the address ^{e (e) (G r-} 1 (e) is up to the previous address (e) r- Data indicating that one access has been received), is converted into data G ^r (e) indicating that this access has been received, and is stored again (updated) at address k. Then, the frequency extraction unit 430 reads the data G ^r (e) from the memory 410 every predetermined period and extracts the number n (k) of times the address is accessed. r (e) represents the number of occurrences of an input signal of the magnitude (amplitude) in a predetermined time since the address e is the magnitude of the level (expressed in dB since it is an output of log conversion).

  The amplitude probability calculator 440 observes the number of occurrences every predetermined time (Δt) based on the time from the time control means 450 and calculates it as a probability. For example, the probability can be measured every Δt = 1 second for ch 1 to 2, whether it exceeds 1%, and the result can be displayed on the display unit 600 via the display control unit 500. The time control unit 450 generates a predetermined time that the operator wants to observe, for example, every second, but is not limited to this, and the measurement is performed by using the operation clock of an external device other than FIG. But it ’s okay.

  The details of APD measurement, that is, amplitude probability measurement, are described in JP-A-8-340643, and the technique can be used as it is. The data D corresponds to a polynomial expression described in Japanese Patent Application Laid-Open No. 8-34043.

  The display control unit 500 causes the display unit 600 to display data output from the individual APD unit 400 in a predetermined format.

It is a figure which shows embodiment of the signal analyzer of this invention. It is a figure for demonstrating the detail of the data storage part of FIG. 1, a filter calculating part, and a filter coefficient memory. It is a figure for demonstrating the detail of the DFT calculating part of FIG. 1, and a twiddle factor memory. 1 is a diagram illustrating a specific example of the separation unit and the detection unit in FIG. 1 and an equivalent circuit of a filter bank (bandpass filter group) including a data storage unit, a filter calculation unit, and a DFT calculation unit in FIG. is there. It is a figure for demonstrating the content of each memory of FIG. 1, and the operation timing of each part. It is a figure for demonstrating the operation | movement flow based on FIG. It is a figure for demonstrating embodiment of an APD measuring apparatus. It is a figure for demonstrating APD. It is a figure which shows the structure of a prior art. It is a figure for demonstrating the zone | band measured with a prior art.

Explanation of symbols

100 data conversion unit, 200A, 200B component detection unit, 210 orthogonal separation unit,
230 data storage unit, 240 filter calculation unit, 250 DFT calculation unit,
290 detection unit, 260 filter coefficient memory, 270 twiddle factor memory 280 timing generation unit, 300 LOG conversion unit, 400 individual APD unit,
500 display control unit, 600 display unit, 1000 APD measuring device,

Claims (4)

A data conversion unit (100) that samples an input signal and outputs it as digital data, a separation unit (210) that separates data X output from the data conversion unit into data XQ and XI orthogonal to each other, and the data XQ , XI are sequentially stored in a time series as M data in a time series, and every N address signals (n = 0, 1,..., N−1) are sequentially generated. M / N = H pieces of data XQ _{(h, n)} , XI _{(h, n,)} {(h, n) represents (h × N + n), h: 0 to H−1. } At the same time, and a number of filter coefficients F corresponding to each of the M pieces of data are stored in advance in order to limit the bandwidth to K frequency bands. A filter coefficient memory (260) for simultaneously outputting H filter coefficients F _{(h, n)} , a filter operation unit (240) for performing the next convolution operation,
_H-1
[YQ] _n = Σ XQ _{(h, n)} × F _{(h, n)}
^{h = 0}
_H-1
[YI] _n = Σ XI _{(h, n)} × F _{(h, n)}
^{h = 0}
Here, the subscript (h, n): (h × N + n) -th is shown.
A DFT operation unit (250) which receives data [YQ] _n and “YI] _n output from the filter operation unit and obtains frequency components orthogonal to each other for each of the K frequency bands;
A signal analysis apparatus comprising: a detection unit (260) that obtains the magnitude of each frequency component based on mutually orthogonal frequency components in each frequency band obtained by the DFT operation unit. It has a twiddle factor memory (270) for storing the values of the next twiddle factors Lc (n, k) and Ls (n, k) in advance so as to be readable by the address signal,
Lc (n, k) = cos (2πj _n × j _k / N),
Ls (n, k) = sin (2πj _n × j _k / N)
However, the constant determined with respect to jn: n, the constant determined with respect to jk: k The DFT operation unit receives the operation results [YQ] _n and [YI] _n from the filter operation unit, and receives the kth frequency. An arithmetic functional element that obtains frequency components SUM _kQ and SUM _kI orthogonal to the band (k: 1 to K) by the following DFT computation and obtains each component from k to 1 to N;
W _kQ (n) = [YQ] _n × Lc (n, k) + [YI] _n × Ls (n, k),
_N-1
SUM _kQ = Σ W _kQ (n)
^{n = 0}
W _kI (n) = [YI] _n × Lc (n, k) + [YQ] _n × Ls (n, k),
_N-1
SUM _kI = Σ W _kI (n)
^{n = 0}
2. The signal analysis according to claim 1, wherein the detection unit includes an addition function element that calculates a square sum of frequency components SUM _kQ and SUM _kI obtained by the DFT operation unit for each frequency band k. apparatus. The data storage unit includes H memories having N addresses each having an address number n = 0 to N−1, and the address nth data ((h × N + n)) of the H memories. , N when h = 0, N + n when h = 1,..., H × N + n when h = H can be read by the same address signal, and the data XQ and XI are read out. From the first address of the first memory to the Hth Nth address,
The filter operation unit and the DFT operation unit obtain each value of the [YQ] _n , [YI] _n , W _kQ (n), and W _kI (n) for each address signal, and obtain the obtained W The signal analysis apparatus according to claim 2, wherein the SUM _kQ and the SUM _kI are obtained by integrating _kQ (n) and W _kI (n). A data converter (100) that samples an input signal and outputs it as digital data, a separation means (210) that separates data XQ output from the data converter into orthogonal data XQ and XI, and the data XQ, Each of XI is sequentially stored as M data in time series as one data period, and every N address signals (n = 0, 1,..., N−1) sequentially generated. M / N = H pieces of data XQ _{(h, n)} , XI _{(h, n,)} {(h, n) represents (h × N + n), h: 0 to H−1. } At the same time, and a number of filter coefficients F corresponding to each of the M pieces of data are stored in advance in order to limit the band to K frequency bands, and every N pieces, M / A filter coefficient memory (260 ₎ for simultaneously outputting N = H filter coefficients F _{(h, n)} , a filter operation unit (240) for performing the next convolution operation from n = 0 to N−1,
_H-1
[YQ] _n = Σ XQ _{(h, n)} × F _{(h, n)}
^{h = 0}
_H-1
[YI] _n = Σ XI _{(h, n)} × F _{(h, n)}
^{h = 0}
Here, the subscript (h, n): (h × N + n) -th is shown.
The data [YQ] _n and “YI] _n output from the filter calculation unit are received, the calculation results [YQ] _n and [YI] _n from the filter calculation unit are received, and the kth frequency band (k : DFT operation unit (250) having operation functional elements for obtaining frequency components SUM _kQ and SUM _kI orthogonal to each other with respect to 1 to K) by the following DFT operation and obtaining each component of k from 1 to N;
W _kQ (n) = [YQ] _n × Lc (n, k) + [YI] _n × Ls (n, k),
_N-1
SUM _kQ = Σ W _kQ (n)
^{n = 0}
W _kI (n) = [YI] _n × Lc (n, k) + [YQ] _n × Ls (n, k),
_N-1
SUM _kI = Σ W _kI (n)
^{n = 0}
Where Lc (n, k) = cos (2πj _n × j _k / N),
Ls (n, k) = sin (2πj _n × j _k / N)
j _n : Constant determined for _n , j _k : Constant determined for k Detection unit (290 for determining the magnitude of each frequency component based on mutually orthogonal frequency components in each frequency band determined by the DFT operation unit (290) )When,
APD (400a) for synthesizing the magnitudes of the respective frequency components output from the detector and obtaining a probability based on the frequency of occurrence of the synthesized amplitude after synthesis;
An APD measuring apparatus comprising:

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